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targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h@147:30b64687e01f 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file rfAna_map.h
<> 144:ef7eb2e8f9f7 4 * @brief rfAna hw module register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 2953 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2014-09-15 18:13:01 +0530 (Mon, 15 Sep 2014) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup rfAna
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 * <p>
<> 144:ef7eb2e8f9f7 31 * Rf and Analog control and trimming hw module register map
<> 144:ef7eb2e8f9f7 32 * </p>
<> 144:ef7eb2e8f9f7 33 */
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #ifndef RFANA_MAP_H_
<> 144:ef7eb2e8f9f7 36 #define RFANA_MAP_H_
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 39 * *
<> 144:ef7eb2e8f9f7 40 * Header files *
<> 144:ef7eb2e8f9f7 41 * *
<> 144:ef7eb2e8f9f7 42 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #include "architecture.h"
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /**************************************************************************************************
<> 144:ef7eb2e8f9f7 47 * *
<> 144:ef7eb2e8f9f7 48 * Type definitions *
<> 144:ef7eb2e8f9f7 49 * *
<> 144:ef7eb2e8f9f7 50 **************************************************************************************************/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /** rfAna register map (control part) */
<> 144:ef7eb2e8f9f7 53 typedef struct {
<> 144:ef7eb2e8f9f7 54 union {
<> 144:ef7eb2e8f9f7 55 struct {
<> 144:ef7eb2e8f9f7 56 __IO uint32_t FRACT_WORD:24;
<> 144:ef7eb2e8f9f7 57 __IO uint32_t INT_WORD:8;
<> 144:ef7eb2e8f9f7 58 } BITS;
<> 144:ef7eb2e8f9f7 59 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 60 } TX_LO_CONTROL;
<> 144:ef7eb2e8f9f7 61 union {
<> 144:ef7eb2e8f9f7 62 struct {
<> 144:ef7eb2e8f9f7 63 __IO uint32_t FRACT_WORD:24;
<> 144:ef7eb2e8f9f7 64 __IO uint32_t INT_WORD:8;
<> 144:ef7eb2e8f9f7 65 } BITS;
<> 144:ef7eb2e8f9f7 66 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 67 } RX_LO_CONTROL;
<> 144:ef7eb2e8f9f7 68 union {
<> 144:ef7eb2e8f9f7 69 struct {
<> 144:ef7eb2e8f9f7 70 __IO uint32_t PLL_RESET_TIME:10;
<> 144:ef7eb2e8f9f7 71 __I uint32_t RESERVED:6;
<> 144:ef7eb2e8f9f7 72 __IO uint32_t PLL_LOCK_TIME:10;
<> 144:ef7eb2e8f9f7 73 } BITS;
<> 144:ef7eb2e8f9f7 74 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 75 } PLL_TIMING;
<> 144:ef7eb2e8f9f7 76 union {
<> 144:ef7eb2e8f9f7 77 struct {
<> 144:ef7eb2e8f9f7 78 __IO uint32_t LNA_GAIN_MODE:1;
<> 144:ef7eb2e8f9f7 79 __IO uint32_t ADC_DITHER_MODE:1;
<> 144:ef7eb2e8f9f7 80 } BITS;
<> 144:ef7eb2e8f9f7 81 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 82 } RX_CONTROL;
<> 144:ef7eb2e8f9f7 83 __IO uint32_t TX_POWER;
<> 144:ef7eb2e8f9f7 84 __I uint32_t RECEIVER_GAIN;
<> 144:ef7eb2e8f9f7 85 } RfAnaReg_t, *RfAnaReg_pt;
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** rfAna register map (trimming part) */
<> 144:ef7eb2e8f9f7 88 typedef struct {
<> 144:ef7eb2e8f9f7 89 __IO uint32_t PMU_TRIM;
<> 144:ef7eb2e8f9f7 90 __IO uint32_t RESERVED;
<> 144:ef7eb2e8f9f7 91 __IO uint32_t RX_CHAIN_TRIM;
<> 144:ef7eb2e8f9f7 92 union {
<> 144:ef7eb2e8f9f7 93 struct {
<> 144:ef7eb2e8f9f7 94 __I uint32_t BIAS_VCO_TRIM:4;
<> 144:ef7eb2e8f9f7 95 __I uint32_t MODULATION_TRIM:4;
<> 144:ef7eb2e8f9f7 96 __IO uint32_t TX_VCO_TRIM:4;
<> 144:ef7eb2e8f9f7 97 __IO uint32_t RX_VCO_TRIM:4;
<> 144:ef7eb2e8f9f7 98 __I uint32_t DIV_TRIM:3;
<> 144:ef7eb2e8f9f7 99 __I uint32_t REG_TRIM:2;
<> 144:ef7eb2e8f9f7 100 __I uint32_t LFR_TRIM:3;
<> 144:ef7eb2e8f9f7 101 __I uint32_t PAD0:4;
<> 144:ef7eb2e8f9f7 102 __I uint32_t CHARGE_PUMP_RANGE:4;
<> 144:ef7eb2e8f9f7 103 } BITS;
<> 144:ef7eb2e8f9f7 104 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 105 } PLL_TRIM;
<> 144:ef7eb2e8f9f7 106 __IO uint32_t PLL_VCO_TAP_LOCATION;
<> 144:ef7eb2e8f9f7 107 __IO uint32_t TX_CHAIN_TRIM;
<> 144:ef7eb2e8f9f7 108 #ifdef REVC
<> 144:ef7eb2e8f9f7 109 __IO uint32_t RX_VCO_TRIM_LUT2; /** 0x40019098 */
<> 144:ef7eb2e8f9f7 110 __IO uint32_t RX_VCO_TRIM_LUT1; /** 0x4001909C */
<> 144:ef7eb2e8f9f7 111 __IO uint32_t TX_VCO_TRIM_LUT2; /** 0x400190A0 */
<> 144:ef7eb2e8f9f7 112 __IO uint32_t TX_VCO_TRIM_LUT1; /** 0x400190A4 */
<> 144:ef7eb2e8f9f7 113 __IO uint32_t ADC_OFFSET_BUF; /** 0x400190A8 */
<> 144:ef7eb2e8f9f7 114 #endif
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 #ifdef REVD
<> 144:ef7eb2e8f9f7 117 __IO uint32_t RX_VCO_TRIM_LUT2; /** 0x40019098 */
<> 144:ef7eb2e8f9f7 118 __IO uint32_t RX_VCO_TRIM_LUT1; /** 0x4001909C */
<> 144:ef7eb2e8f9f7 119 __IO uint32_t TX_VCO_TRIM_LUT2; /** 0x400190A0 */
<> 144:ef7eb2e8f9f7 120 __IO uint32_t TX_VCO_TRIM_LUT1; /** 0x400190A4 */
<> 144:ef7eb2e8f9f7 121 __IO uint32_t ADC_OFFSET_BUF; /** 0x400190A8 */
<> 144:ef7eb2e8f9f7 122 #endif /* REVD */
<> 144:ef7eb2e8f9f7 123 } RfAnaTrimReg_t, *RfAnaTrimReg_pt;
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 #endif /* RFANA_MAP_H_ */