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targets/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

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<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file pmu_map.h
<> 149:156823d33999 4 * @brief PMU hw module register map
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 3372 $
<> 149:156823d33999 8 * $Date: 2015-04-22 12:18:18 +0530 (Wed, 22 Apr 2015) $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup pmu
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 */
<> 149:156823d33999 31
<> 149:156823d33999 32 #ifndef PMU_MAP_H_
<> 149:156823d33999 33 #define PMU_MAP_H_
<> 149:156823d33999 34
<> 149:156823d33999 35 /*************************************************************************************************
<> 149:156823d33999 36 * *
<> 149:156823d33999 37 * Header files *
<> 149:156823d33999 38 * *
<> 149:156823d33999 39 *************************************************************************************************/
<> 149:156823d33999 40
<> 149:156823d33999 41 #include "architecture.h"
<> 149:156823d33999 42
<> 149:156823d33999 43 /**************************************************************************************************
<> 149:156823d33999 44 * *
<> 149:156823d33999 45 * Type definitions *
<> 149:156823d33999 46 * *
<> 149:156823d33999 47 **************************************************************************************************/
<> 149:156823d33999 48
<> 149:156823d33999 49 /** PMU control
<> 149:156823d33999 50 * The Power Management Unit (PMU) is used to control the differing power modes.
<> 149:156823d33999 51 */
<> 149:156823d33999 52 typedef struct {
<> 149:156823d33999 53 union {
<> 149:156823d33999 54 struct {
<> 149:156823d33999 55 __IO uint32_t ENCOMA :1; /**< 0- Sleep or SleepDeep depending on System Control Register (see WFI and WFE instructions), 1 – Coma */
<> 149:156823d33999 56 __IO uint32_t SRAMA :1; /**< SRAMA Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
<> 149:156823d33999 57 __IO uint32_t SRAMB :1; /**< SRAMB Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
<> 149:156823d33999 58 __IO uint32_t EXT32K :1; /**< External 32.768kHz Enable: 0 – Disabled (off), 1 – Enabled (on), Hardware guarantees that this oscillator cannot be powered if the internal 32kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
<> 149:156823d33999 59 __IO uint32_t INT32K :1; /**< Internal 32kHz Enable: 0 – Enabled (on), 1 – Disabled (Off), Hardware guarantees that this oscillator cannot be powered down if the external 32.768kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
<> 149:156823d33999 60 __IO uint32_t INT32M :1; /**< Internal 32MHz Enable: 0 – Enabled (on), 1 – Disabled (off), This bit will automatically get cleared when exiting Coma, or SleepDeep modes of operation. This bit should be set by software after switching over to the external 32MHz oscillator using the Oscillator Select bit in the Clock Control register */
<> 149:156823d33999 61 __IO uint32_t C1V1:1; /**< Coma mode 1V1 regulator setting: 0 - Linear regulator, 1 - switching regulator */
<> 149:156823d33999 62 __IO uint32_t N1V1:1; /**< Regular mode (Run sleep and deepsleep) 1V1 regulator mode: 0 - Linear regulator, 1 - switching regulator */
<> 149:156823d33999 63 __IO uint32_t DBGPOW :1; /**< Debugger Power Behavior: 0 – Normal power behavior when the debugger is present, 1 – When debugger is present the ASIC can only enter SleepDeep mode and FVDDH and FVDDL always remain powered. The 32MHz oscillators can never be powered down in this mode either. */
<> 149:156823d33999 64 __IO uint32_t UVIC:1; /**< Under voltage indicator control: 0 - disabled, 1 - enabled */
<> 149:156823d33999 65 __IO uint32_t UVII:1; /**< Under voltage indicator input: 0 - 1V1 regulator, 1 - FVDDH regulator */
<> 149:156823d33999 66 __IO uint32_t UVIR:1; /**< Under voltage indicator reset: 0 - do not reset, 1 - reset */
<> 149:156823d33999 67 } BITS;
<> 149:156823d33999 68 __IO uint32_t WORD;
<> 149:156823d33999 69 } CONTROL; /* 0x4001D000 */
<> 149:156823d33999 70 union {
<> 149:156823d33999 71 struct {
<> 149:156823d33999 72 __I uint32_t BATTDET:1; /**< Detected battery: 0 - 1V, 1 - 3V */
<> 149:156823d33999 73 __I uint32_t UVIC:1; /**< Under voltage status: 0 - normal, 1 - low */
<> 149:156823d33999 74
<> 149:156823d33999 75 } BITS;
<> 149:156823d33999 76 __IO uint32_t WORD;
<> 149:156823d33999 77 } STATUS; /* 0x4001D004 */
<> 149:156823d33999 78
<> 149:156823d33999 79 __IO uint32_t PLACEHOLDER; /* 0x4001D008 */
<> 149:156823d33999 80 __IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */ /* 0x4001D00C */
<> 149:156823d33999 81 __IO uint32_t PLACEHOLDER1; /* 0x4001D010 */
<> 149:156823d33999 82 __IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */ /* 0x4001D014 */
<> 149:156823d33999 83 union {
<> 149:156823d33999 84 struct {
<> 149:156823d33999 85 __IO uint32_t TH:6; /**< Threshold */
<> 149:156823d33999 86 __I uint32_t PAD:2;
<> 149:156823d33999 87 __I uint32_t UVIVAL:6; /**< UVI value */
<> 149:156823d33999 88 } BITS;
<> 149:156823d33999 89 __IO uint32_t WORD;
<> 149:156823d33999 90 } UVI_TBASE; /* 0x4001D018 */
<> 149:156823d33999 91 __IO uint32_t SRAM_TRIM; /* 0x4001D01C */
<> 149:156823d33999 92
<> 149:156823d33999 93 } PmuReg_t, *PmuReg_pt;
<> 149:156823d33999 94
<> 149:156823d33999 95 #endif /* PMU_MAP_H_ */