FMF-ART / mbed-dev-lib

lib

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file W7500x.h
<> 144:ef7eb2e8f9f7 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
<> 144:ef7eb2e8f9f7 4 * Device W7500x
<> 144:ef7eb2e8f9f7 5 * @version V3.01
<> 144:ef7eb2e8f9f7 6 * @date 06. March 2012
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * @note
<> 144:ef7eb2e8f9f7 9 * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * @par
<> 144:ef7eb2e8f9f7 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
<> 144:ef7eb2e8f9f7 13 * processor based microcontrollers. This file can be freely distributed
<> 144:ef7eb2e8f9f7 14 * within development tools that are supporting such ARM based processors.
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * @par
<> 144:ef7eb2e8f9f7 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 144:ef7eb2e8f9f7 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 ******************************************************************************/
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #ifndef W7500x_H
<> 144:ef7eb2e8f9f7 27 #define W7500x_H
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 30 extern "C" {
<> 144:ef7eb2e8f9f7 31 #endif
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /** @addtogroup W7500x_Definitions W7500x Definitions
<> 144:ef7eb2e8f9f7 34 This file defines all structures and symbols for W7500x:
<> 144:ef7eb2e8f9f7 35 - registers and bitfields
<> 144:ef7eb2e8f9f7 36 - peripheral base address
<> 144:ef7eb2e8f9f7 37 - peripheral ID
<> 144:ef7eb2e8f9f7 38 - Peripheral definitions
<> 144:ef7eb2e8f9f7 39 @{
<> 144:ef7eb2e8f9f7 40 */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /******************************************************************************/
<> 144:ef7eb2e8f9f7 44 /* Processor and Core Peripherals */
<> 144:ef7eb2e8f9f7 45 /******************************************************************************/
<> 144:ef7eb2e8f9f7 46 /** @addtogroup W7500x_CMSIS Device CMSIS Definitions
<> 144:ef7eb2e8f9f7 47 Configuration of the Cortex-M0 Processor and Core Peripherals
<> 144:ef7eb2e8f9f7 48 @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /*
<> 144:ef7eb2e8f9f7 52 * ==========================================================================
<> 144:ef7eb2e8f9f7 53 * ---------- Interrupt Number Definition -----------------------------------
<> 144:ef7eb2e8f9f7 54 * ==========================================================================
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 typedef enum IRQn
<> 144:ef7eb2e8f9f7 58 {
<> 144:ef7eb2e8f9f7 59 /****** Cortex-M0 Processor Exceptions Numbers **************************************************/
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
<> 144:ef7eb2e8f9f7 62 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 63 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
<> 144:ef7eb2e8f9f7 64 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 65 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 66 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 67 /****** W7500x Specific Interrupt Numbers *********************************************************/
<> 144:ef7eb2e8f9f7 68 SSP0_IRQn = 0, /*!< SSP 0 Interrupt */
<> 144:ef7eb2e8f9f7 69 SSP1_IRQn = 1, /*!< SSP 1 Interrupt */
<> 144:ef7eb2e8f9f7 70 UART0_IRQn = 2, /*!< UART 0 Interrupt */
<> 144:ef7eb2e8f9f7 71 UART1_IRQn = 3, /*!< UART 1 Interrupt */
<> 144:ef7eb2e8f9f7 72 UART2_IRQn = 4, /*!< UART 2 Interrupt */
<> 144:ef7eb2e8f9f7 73 I2C0_IRQn = 5, /*!< I2C 0 Interrupt */
<> 144:ef7eb2e8f9f7 74 I2C1_IRQn = 6, /*!< I2C 1 Interrupt */
<> 144:ef7eb2e8f9f7 75 PORT0_IRQn = 7, /*!< Port 1 combined Interrupt */
<> 144:ef7eb2e8f9f7 76 PORT1_IRQn = 8, /*!< Port 2 combined Interrupt */
<> 144:ef7eb2e8f9f7 77 PORT2_IRQn = 9, /*!< Port 2 combined Interrupt */
<> 144:ef7eb2e8f9f7 78 PORT3_IRQn = 10, /*!< Port 2 combined Interrupt */
<> 144:ef7eb2e8f9f7 79 DMA_IRQn = 11, /*!< DMA combined Interrupt */
<> 144:ef7eb2e8f9f7 80 DUALTIMER0_IRQn = 12, /*!< Dual Timer 0 Interrupt */
<> 144:ef7eb2e8f9f7 81 DUALTIMER1_IRQn = 13, /*!< Dual Timer 1 Interrupt */
<> 144:ef7eb2e8f9f7 82 PWM0_IRQn = 14, /*!< PWM 0 Interrupt */
<> 144:ef7eb2e8f9f7 83 PWM1_IRQn = 15, /*!< PWM 1 Interrupt */
<> 144:ef7eb2e8f9f7 84 PWM2_IRQn = 16, /*!< PWM 2 Interrupt */
<> 144:ef7eb2e8f9f7 85 PWM3_IRQn = 17, /*!< PWM 3 Interrupt */
<> 144:ef7eb2e8f9f7 86 PWM4_IRQn = 18, /*!< PWM 4 Interrupt */
<> 144:ef7eb2e8f9f7 87 PWM5_IRQn = 19, /*!< PWM 5 Interrupt */
<> 144:ef7eb2e8f9f7 88 PWM6_IRQn = 20, /*!< PWM 6 Interrupt */
<> 144:ef7eb2e8f9f7 89 PWM7_IRQn = 21, /*!< PWM 7 Interrupt */
<> 144:ef7eb2e8f9f7 90 RTC_IRQn = 22, /*!< RTC Interrupt */
<> 144:ef7eb2e8f9f7 91 ADC_IRQn = 23, /*!< ADC Interrupt */
<> 144:ef7eb2e8f9f7 92 WZTOE_IRQn = 24, /*!< WZTOE Interrupt */
<> 144:ef7eb2e8f9f7 93 EXTI_IRQn = 25 /*!< EXTI Interrupt */
<> 144:ef7eb2e8f9f7 94 } IRQn_Type;
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /*
<> 144:ef7eb2e8f9f7 97 * ==========================================================================
<> 144:ef7eb2e8f9f7 98 * ----------- Processor and Core Peripheral Section ------------------------
<> 144:ef7eb2e8f9f7 99 * ==========================================================================
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
<> 144:ef7eb2e8f9f7 103 #define __CM0_REV 0x0000 /*!< Core Revision r0p0 */
<> 144:ef7eb2e8f9f7 104 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 105 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 106 #define __MPU_PRESENT 0 /*!< MPU present or not */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /*@}*/ /* end of group W7500x_CMSIS */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
<> 144:ef7eb2e8f9f7 112 #include "system_W7500x.h" /* W7500x System include file */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /** @addtogroup Exported_types
<> 144:ef7eb2e8f9f7 116 * @{
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
<> 144:ef7eb2e8f9f7 120 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
<> 144:ef7eb2e8f9f7 121 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /**
<> 144:ef7eb2e8f9f7 129 * @}
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @addtogroup Peripheral_registers_structures
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /**
<> 144:ef7eb2e8f9f7 140 * @brief Clock Reset Generator
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142 typedef struct
<> 144:ef7eb2e8f9f7 143 {
<> 144:ef7eb2e8f9f7 144 __IO uint32_t OSC_PDR; /*!< Oscillator power down register, Address offset : 0x00 */
<> 144:ef7eb2e8f9f7 145 uint32_t RESERVED0[3];
<> 144:ef7eb2e8f9f7 146 __IO uint32_t PLL_PDR; /*!< PLL power down register, Address offset : 0x10 */
<> 144:ef7eb2e8f9f7 147 __IO uint32_t PLL_FCR; /*!< PLL frequency calculating register, Address offset : 0x14 */
<> 144:ef7eb2e8f9f7 148 __IO uint32_t PLL_OER; /*!< PLL output enable register, Address offset : 0x18 */
<> 144:ef7eb2e8f9f7 149 __IO uint32_t PLL_BPR; /*!< PLL bypass register, Address offset : 0x1c */
<> 144:ef7eb2e8f9f7 150 __IO uint32_t PLL_IFSR; /*!< PLL input frequency select register, Address offset : 0x20 */
<> 144:ef7eb2e8f9f7 151 uint32_t RESERVED1[3];
<> 144:ef7eb2e8f9f7 152 __IO uint32_t FCLK_SSR; /*!< FCLK source select register, Address offset : 0x30 */
<> 144:ef7eb2e8f9f7 153 __IO uint32_t FCLK_PVSR; /*!< FCLK prescale value select register, Address offset : 0x34 */
<> 144:ef7eb2e8f9f7 154 uint32_t RESERVED2[2];
<> 144:ef7eb2e8f9f7 155 __IO uint32_t SSPCLK_SSR; /*!< SSPCLK source select register, Address offset : 0x40 */
<> 144:ef7eb2e8f9f7 156 __IO uint32_t SSPCLK_PVSR; /*!< SSPCLK prescale value select register, Address offset : 0x44 */
<> 144:ef7eb2e8f9f7 157 uint32_t RESERVED3[6];
<> 144:ef7eb2e8f9f7 158 __IO uint32_t ADCCLK_SSR; /*!< ADCCLK source select register, Address offset : 0x60 */
<> 144:ef7eb2e8f9f7 159 __IO uint32_t ADCCLK_PVSR; /*!< ADCCLK prescale value select register, Address offset : 0x64 */
<> 144:ef7eb2e8f9f7 160 uint32_t RESERVED4[2];
<> 144:ef7eb2e8f9f7 161 __IO uint32_t TIMER0CLK_SSR; /*!< TIMER0CLK source select register, Address offset : 0x70 */
<> 144:ef7eb2e8f9f7 162 __IO uint32_t TIMER0CLK_PVSR; /*!< TIMER0CLK prescale value select register, Address offset : 0x74 */
<> 144:ef7eb2e8f9f7 163 uint32_t RESERVED5[2];
<> 144:ef7eb2e8f9f7 164 __IO uint32_t TIMER1CLK_SSR; /*!< TIMER1CLK source select register, Address offset : 0x80 */
<> 144:ef7eb2e8f9f7 165 __IO uint32_t TIMER1CLK_PVSR; /*!< TIMER1CLK prescale value select register, Address offset : 0x84 */
<> 144:ef7eb2e8f9f7 166 uint32_t RESERVED6[10];
<> 144:ef7eb2e8f9f7 167 __IO uint32_t PWM0CLK_SSR; /*!< PWM0CLK source select register, Address offset : 0xb0 */
<> 144:ef7eb2e8f9f7 168 __IO uint32_t PWM0CLK_PVSR; /*!< PWM0CLK prescale value select register, Address offset : 0xb4 */
<> 144:ef7eb2e8f9f7 169 uint32_t RESERVED7[2];
<> 144:ef7eb2e8f9f7 170 __IO uint32_t PWM1CLK_SSR; /*!< PWM1CLK source select register, Address offset : 0xc0 */
<> 144:ef7eb2e8f9f7 171 __IO uint32_t PWM1CLK_PVSR; /*!< PWM1CLK prescale value select register, Address offset : 0xc4 */
<> 144:ef7eb2e8f9f7 172 uint32_t RESERVED8[2];
<> 144:ef7eb2e8f9f7 173 __IO uint32_t PWM2CLK_SSR; /*!< PWM2CLK source select register, Address offset : 0xd0 */
<> 144:ef7eb2e8f9f7 174 __IO uint32_t PWM2CLK_PVSR; /*!< PWM2CLK prescale value select register, Address offset : 0xd4 */
<> 144:ef7eb2e8f9f7 175 uint32_t RESERVED9[2];
<> 144:ef7eb2e8f9f7 176 __IO uint32_t PWM3CLK_SSR; /*!< PWM3CLK source select register, Address offset : 0xe0 */
<> 144:ef7eb2e8f9f7 177 __IO uint32_t PWM3CLK_PVSR; /*!< PWM3CLK prescale value select register, Address offset : 0xe4 */
<> 144:ef7eb2e8f9f7 178 uint32_t RESERVED10[2];
<> 144:ef7eb2e8f9f7 179 __IO uint32_t PWM4CLK_SSR; /*!< PWM4CLK source select register, Address offset : 0xf0 */
<> 144:ef7eb2e8f9f7 180 __IO uint32_t PWM4CLK_PVSR; /*!< PWM4CLK prescale value select register, Address offset : 0xf4 */
<> 144:ef7eb2e8f9f7 181 uint32_t RESERVED11[2];
<> 144:ef7eb2e8f9f7 182 __IO uint32_t PWM5CLK_SSR; /*!< PWM5CLK source select register, Address offset : 0x100 */
<> 144:ef7eb2e8f9f7 183 __IO uint32_t PWM5LK_PVSR; /*!< PWM5CLK prescale value select register, Address offset : 0x104 */
<> 144:ef7eb2e8f9f7 184 uint32_t RESERVED12[2];
<> 144:ef7eb2e8f9f7 185 __IO uint32_t PWM6CLK_SSR; /*!< PWM6CLK source select register, Address offset : 0x110 */
<> 144:ef7eb2e8f9f7 186 __IO uint32_t PWM6CLK_PVSR; /*!< PWM6CLK prescale value select register, Address offset : 0x114 */
<> 144:ef7eb2e8f9f7 187 uint32_t RESERVED13[2];
<> 144:ef7eb2e8f9f7 188 __IO uint32_t PWM7CLK_SSR; /*!< PWM7CLK source select register, Address offset : 0x120 */
<> 144:ef7eb2e8f9f7 189 __IO uint32_t PWM7CLK_PVSR; /*!< PWM7CLK prescale value select register, Address offset : 0x124 */
<> 144:ef7eb2e8f9f7 190 uint32_t RESERVED14[2];
<> 144:ef7eb2e8f9f7 191 __IO uint32_t RTC_HS_SSR; /*!< RTC High Speed source select register, Address offset : 0x130 */
<> 144:ef7eb2e8f9f7 192 __IO uint32_t RTC_HS_PVSR; /*!< RTC High Speed prescale value select register, Address offset : 0x134 */
<> 144:ef7eb2e8f9f7 193 uint32_t RESERVED15;
<> 144:ef7eb2e8f9f7 194 __IO uint32_t RTC_SSR; /*!< RTC source select register, Address offset : 0x13c */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 __IO uint32_t WDOGCLK_HS_SSR; /*!< WDOGCLK High Speed source select register, Address offset : 0x140 */
<> 144:ef7eb2e8f9f7 197 __IO uint32_t WDOGCLK_HS_PVSR; /*!< WDOGCLK High Speed prescale value select register, Address offset : 0x144 */
<> 144:ef7eb2e8f9f7 198 uint32_t RESERVED16;
<> 144:ef7eb2e8f9f7 199 __IO uint32_t WDOGCLK_SSR; /*!< WDOGCLK source select register, Address offset : 0x14c */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 __IO uint32_t UARTCLK_SSR; /*!< UARTCLK source select register, Address offset : 0x150 */
<> 144:ef7eb2e8f9f7 202 __IO uint32_t UARTCLK_PVSR; /*!< UARTCLK prescale value select register, Address offset : 0x154 */
<> 144:ef7eb2e8f9f7 203 uint32_t RESERVED17[2];
<> 144:ef7eb2e8f9f7 204 __IO uint32_t MIICLK_ECR; /*!< MII clock enable control register, Address offset : 0x160 */
<> 144:ef7eb2e8f9f7 205 uint32_t RESERVED18[3];
<> 144:ef7eb2e8f9f7 206 __IO uint32_t MONCLK_SSR; /*!< Monitoring clock source select I found Treasure was IoT Base Station in March.register, Address offset : 0x170 */
<> 144:ef7eb2e8f9f7 207 }CRG_TypeDef;
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /**
<> 144:ef7eb2e8f9f7 211 * @brief UART
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213 typedef struct
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 __IO uint32_t DR; /*!< Data, Address offset : 0x00 */
<> 144:ef7eb2e8f9f7 216 union {
<> 144:ef7eb2e8f9f7 217 __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */
<> 144:ef7eb2e8f9f7 218 __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */
<> 144:ef7eb2e8f9f7 219 } STATUS;
<> 144:ef7eb2e8f9f7 220 uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 221 __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */
<> 144:ef7eb2e8f9f7 222 uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 223 __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */
<> 144:ef7eb2e8f9f7 224 __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */
<> 144:ef7eb2e8f9f7 225 __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */
<> 144:ef7eb2e8f9f7 226 __IO uint32_t LCR_H; /*!< Line Control, Address offset : 0x2C */
<> 144:ef7eb2e8f9f7 227 __IO uint32_t CR; /*!< Control, Address offset : 0x30 */
<> 144:ef7eb2e8f9f7 228 __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */
<> 144:ef7eb2e8f9f7 229 __IO uint32_t IMSC; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */
<> 144:ef7eb2e8f9f7 230 __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */
<> 144:ef7eb2e8f9f7 231 __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */
<> 144:ef7eb2e8f9f7 232 __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */
<> 144:ef7eb2e8f9f7 233 __IO uint32_t DMACR; /*!< DMA Control, Address offset : 0x48 */
<> 144:ef7eb2e8f9f7 234 } UART_TypeDef;
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @brief Simple UART
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 typedef struct
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
<> 144:ef7eb2e8f9f7 243 __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
<> 144:ef7eb2e8f9f7 244 __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
<> 144:ef7eb2e8f9f7 245 union {
<> 144:ef7eb2e8f9f7 246 __I uint32_t STATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
<> 144:ef7eb2e8f9f7 247 __O uint32_t CLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
<> 144:ef7eb2e8f9f7 248 }INT;
<> 144:ef7eb2e8f9f7 249 __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 } S_UART_TypeDef;
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @brief Analog Digital Converter
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 typedef struct
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 __IO uint32_t ADC_CTR; /* ADC control register, Address offset : 0x000 */
<> 144:ef7eb2e8f9f7 260 __IO uint32_t ADC_CHSEL; /* ADC channel select register, Address offset : 0x004 */
<> 144:ef7eb2e8f9f7 261 __IO uint32_t ADC_START; /* ADC start register, Address offset : 0x008 */
<> 144:ef7eb2e8f9f7 262 __I uint32_t ADC_DATA; /* ADC conversion data register, Address offset : 0x00c */
<> 144:ef7eb2e8f9f7 263 __IO uint32_t ADC_INT; /* ADC interrupt register, Address offset : 0x010 */
<> 144:ef7eb2e8f9f7 264 uint32_t RESERVED0[2];
<> 144:ef7eb2e8f9f7 265 __IO uint32_t ADC_INTCLR; /* ADC interrupt clear register, Address offset : 0x01c */
<> 144:ef7eb2e8f9f7 266 }ADC_TypeDef;
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /**
<> 144:ef7eb2e8f9f7 269 * @brief dualtimer
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 typedef struct
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 __IO uint32_t TimerLoad; // <h> Timer Load </h>
<> 144:ef7eb2e8f9f7 274 __I uint32_t TimerValue; // <h> Timer Counter Current Value <r></h>
<> 144:ef7eb2e8f9f7 275 __IO uint32_t TimerControl; // <h> Timer Control
<> 144:ef7eb2e8f9f7 276 // <o.7> TimerEn: Timer Enable
<> 144:ef7eb2e8f9f7 277 // <o.6> TimerMode: Timer Mode
<> 144:ef7eb2e8f9f7 278 // <0=> Freerunning-mode
<> 144:ef7eb2e8f9f7 279 // <1=> Periodic mode
<> 144:ef7eb2e8f9f7 280 // <o.5> IntEnable: Interrupt Enable
<> 144:ef7eb2e8f9f7 281 // <o.2..3> TimerPre: Timer Prescale
<> 144:ef7eb2e8f9f7 282 // <0=> / 1
<> 144:ef7eb2e8f9f7 283 // <1=> / 16
<> 144:ef7eb2e8f9f7 284 // <2=> / 256
<> 144:ef7eb2e8f9f7 285 // <3=> Undefined!
<> 144:ef7eb2e8f9f7 286 // <o.1> TimerSize: Timer Size
<> 144:ef7eb2e8f9f7 287 // <0=> 16-bit counter
<> 144:ef7eb2e8f9f7 288 // <1=> 32-bit counter
<> 144:ef7eb2e8f9f7 289 // <o.0> OneShot: One-shoot mode
<> 144:ef7eb2e8f9f7 290 // <0=> Wrapping mode
<> 144:ef7eb2e8f9f7 291 // <1=> One-shot mode
<> 144:ef7eb2e8f9f7 292 // </h>
<> 144:ef7eb2e8f9f7 293 __O uint32_t TimerIntClr; // <h> Timer Interrupt Clear <w></h>
<> 144:ef7eb2e8f9f7 294 __I uint32_t TimerRIS; // <h> Timer Raw Interrupt Status <r></h>
<> 144:ef7eb2e8f9f7 295 __I uint32_t TimerMIS; // <h> Timer Masked Interrupt Status <r></h>
<> 144:ef7eb2e8f9f7 296 __IO uint32_t TimerBGLoad; // <h> Background Load Register </h>
<> 144:ef7eb2e8f9f7 297 } DUALTIMER_TypeDef;
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @brief GPIO
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302 typedef struct
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 __IO uint32_t DATA; /* DATA Register (R/W), offset : 0x000 */
<> 144:ef7eb2e8f9f7 305 __IO uint32_t DATAOUT; /* Data Output Latch Register (R/W), offset : 0x004 */
<> 144:ef7eb2e8f9f7 306 uint32_t RESERVED0[2];
<> 144:ef7eb2e8f9f7 307 __IO uint32_t OUTENSET; /* Output Enable Set Register (R/W) offset : 0x010 */
<> 144:ef7eb2e8f9f7 308 __IO uint32_t OUTENCLR; /* Output Enable Clear Register (R/W) offset : 0x014 */
<> 144:ef7eb2e8f9f7 309 __IO uint32_t RESERVED1; /* Alternate Function Set Register (R/W) offset : 0x018 */
<> 144:ef7eb2e8f9f7 310 __IO uint32_t RESERVED2; /* Alternate Function Clear Register (R/W) offset : 0x01C */
<> 144:ef7eb2e8f9f7 311 __IO uint32_t INTENSET; /* Interrupt Enable Set Register (R/W) offset : 0x020 */
<> 144:ef7eb2e8f9f7 312 __IO uint32_t INTENCLR; /* Interrupt Enable Clear Register (R/W) offset : 0x024 */
<> 144:ef7eb2e8f9f7 313 __IO uint32_t INTTYPESET; /* Interrupt Type Set Register (R/W) offset : 0x028 */
<> 144:ef7eb2e8f9f7 314 __IO uint32_t INTTYPECLR; /* Interrupt Type Clear Register (R/W) offset : 0x02C */
<> 144:ef7eb2e8f9f7 315 __IO uint32_t INTPOLSET; /* Interrupt Polarity Set Register (R/W) offset : 0x030 */
<> 144:ef7eb2e8f9f7 316 __IO uint32_t INTPOLCLR; /* Interrupt Polarity Clear Register (R/W) offset : 0x034 */
<> 144:ef7eb2e8f9f7 317 union {
<> 144:ef7eb2e8f9f7 318 __I uint32_t INTSTATUS; /* Interrupt Status Register (R/ ) offset : 0x038 */
<> 144:ef7eb2e8f9f7 319 __O uint32_t INTCLEAR; /* Interrupt Clear Register ( /W) offset : 0x038 */
<> 144:ef7eb2e8f9f7 320 }Interrupt;
<> 144:ef7eb2e8f9f7 321 uint32_t RESERVED3[241];
<> 144:ef7eb2e8f9f7 322 __IO uint32_t LB_MASKED[256]; /* Lower byte Masked Access Register (R/W) offset : 0x400 - 0x7FC */
<> 144:ef7eb2e8f9f7 323 __IO uint32_t UB_MASKED[256]; /* Upper byte Masked Access Register (R/W) offset : 0x800 - 0xBFC */
<> 144:ef7eb2e8f9f7 324 } GPIO_TypeDef;
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 typedef struct
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 __IO uint32_t Port[16]; /* Port_00, offset : 0x00 */
<> 144:ef7eb2e8f9f7 329 /* Port_01, offset : 0x04 */
<> 144:ef7eb2e8f9f7 330 /* Port_02, offset : 0x08 */
<> 144:ef7eb2e8f9f7 331 /* Port_03, offset : 0x0C */
<> 144:ef7eb2e8f9f7 332 /* Port_04, offset : 0x10 */
<> 144:ef7eb2e8f9f7 333 /* Port_05, offset : 0x14 */
<> 144:ef7eb2e8f9f7 334 /* Port_06, offset : 0x18 */
<> 144:ef7eb2e8f9f7 335 /* Port_07, offset : 0x1C */
<> 144:ef7eb2e8f9f7 336 /* Port_08, offset : 0x20 */
<> 144:ef7eb2e8f9f7 337 /* Port_09, offset : 0x24 */
<> 144:ef7eb2e8f9f7 338 /* Port_10, offset : 0x28 */
<> 144:ef7eb2e8f9f7 339 /* Port_11, offset : 0x2C */
<> 144:ef7eb2e8f9f7 340 /* Port_12, offset : 0x30 */
<> 144:ef7eb2e8f9f7 341 /* Port_13, offset : 0x34 */
<> 144:ef7eb2e8f9f7 342 /* Port_14, offset : 0x38 */
<> 144:ef7eb2e8f9f7 343 /* Port_15, offset : 0x3C */
<> 144:ef7eb2e8f9f7 344 } P_Port_Def;
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 typedef struct
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 __IO uint32_t Port[5]; /* Port_00, offset : 0x00 */
<> 144:ef7eb2e8f9f7 349 /* Port_01, offset : 0x04 */
<> 144:ef7eb2e8f9f7 350 /* Port_02, offset : 0x08 */
<> 144:ef7eb2e8f9f7 351 /* Port_03, offset : 0x0C */
<> 144:ef7eb2e8f9f7 352 /* Port_04, offset : 0x10 */
<> 144:ef7eb2e8f9f7 353 } P_Port_D_Def;
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /**
<> 144:ef7eb2e8f9f7 356 * @brief I2C Register structure definition
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 typedef struct
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 __IO uint32_t PRER; //0x00
<> 144:ef7eb2e8f9f7 361 __IO uint32_t CTR; //0x04
<> 144:ef7eb2e8f9f7 362 __IO uint32_t CMDR; //0x08
<> 144:ef7eb2e8f9f7 363 __I uint32_t SR; //0x0C
<> 144:ef7eb2e8f9f7 364 __IO uint32_t TSR; //0x10
<> 144:ef7eb2e8f9f7 365 __IO uint32_t SADDR; //0x14
<> 144:ef7eb2e8f9f7 366 __IO uint32_t TXR; //0x18
<> 144:ef7eb2e8f9f7 367 __I uint32_t RXR; //0x1C
<> 144:ef7eb2e8f9f7 368 __I uint32_t ISR; //0x20
<> 144:ef7eb2e8f9f7 369 __IO uint32_t ISCR; //0x24
<> 144:ef7eb2e8f9f7 370 __IO uint32_t ISMR; //0x28
<> 144:ef7eb2e8f9f7 371 }I2C_TypeDef;
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @brief PWM Register structure definition
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376 typedef struct
<> 144:ef7eb2e8f9f7 377 {
<> 144:ef7eb2e8f9f7 378 __IO uint32_t IER; //Interrupt enable register
<> 144:ef7eb2e8f9f7 379 // <7> IE7 : Channel 7 interrupt enable <R/W>
<> 144:ef7eb2e8f9f7 380 // <6> IE6 : Channel 6 interrupt enable <R/W>
<> 144:ef7eb2e8f9f7 381 // <5> IE5 : Channel 5 interrupt enable <R/W>
<> 144:ef7eb2e8f9f7 382 // <4> IE4 : Channel 4 interrupt enable <R/W>
<> 144:ef7eb2e8f9f7 383 // <3> IE3 : Channel 3 interrupt enable <R/W>
<> 144:ef7eb2e8f9f7 384 // <2> IE2 : Channel 2 interrupt enable <R/W>
<> 144:ef7eb2e8f9f7 385 // <1> IE1 : Channel 1 interrupt enable <R/W>
<> 144:ef7eb2e8f9f7 386 // <0> IE0 : Channel 0 interrupt enable <R/W>
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 __IO uint32_t SSR; //Start Stop register
<> 144:ef7eb2e8f9f7 389 // <7> SS7 : Channel 7 TC start or stop <R/W>
<> 144:ef7eb2e8f9f7 390 // <6> SS6 : Channel 6 TC start or stop <R/W>
<> 144:ef7eb2e8f9f7 391 // <5> SS5 : Channel 5 TC start or stop <R/W>
<> 144:ef7eb2e8f9f7 392 // <4> SS4 : Channel 4 TC start or stop <R/W>
<> 144:ef7eb2e8f9f7 393 // <3> SS3 : Channel 3 TC start or stop <R/W>
<> 144:ef7eb2e8f9f7 394 // <2> SS2 : Channel 2 TC start or stop <R/W>
<> 144:ef7eb2e8f9f7 395 // <1> SS1 : Channel 1 TC start or stop <R/W>
<> 144:ef7eb2e8f9f7 396 // <0> SS0 : Channel 0 TC start or stop <R/W>
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 __IO uint32_t PSR; //Pause register
<> 144:ef7eb2e8f9f7 399 // <7> PS7 : Channel 7 TC pasue <R/W>
<> 144:ef7eb2e8f9f7 400 // <6> PS6 : Channel 6 TC pasue <R/W>
<> 144:ef7eb2e8f9f7 401 // <5> PS5 : Channel 5 TC pasue <R/W>
<> 144:ef7eb2e8f9f7 402 // <4> PS4 : Channel 4 TC pasue <R/W>
<> 144:ef7eb2e8f9f7 403 // <3> PS3 : Channel 3 TC pasue <R/W>
<> 144:ef7eb2e8f9f7 404 // <2> PS2 : Channel 2 TC pasue <R/W>
<> 144:ef7eb2e8f9f7 405 // <1> PS1 : Channel 1 TC pasue <R/W>
<> 144:ef7eb2e8f9f7 406 // <0> PS0 : Channel 0 TC pasue <R/W>
<> 144:ef7eb2e8f9f7 407 } PWM_TypeDef;
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 typedef struct
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 __I uint32_t IR; //Interrupt register
<> 144:ef7eb2e8f9f7 412 // <2> CI : Capture interrupt <R>
<> 144:ef7eb2e8f9f7 413 // <1> OI : Overflow interrupt <R>
<> 144:ef7eb2e8f9f7 414 // <0> MI : Match interrupt <R>
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 __IO uint32_t IER; //Interrupt enable register
<> 144:ef7eb2e8f9f7 417 // <2> CIE : Capture interrupt enable <R/W>
<> 144:ef7eb2e8f9f7 418 // <1> OIE : Overflow interrupt enable <R/W>
<> 144:ef7eb2e8f9f7 419 // <0> MIE : Match interrupt enable <R/W>
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 __O uint32_t ICR; //Interrupt clear register
<> 144:ef7eb2e8f9f7 422 // <2> CIC : Capture interrupt clear <W>
<> 144:ef7eb2e8f9f7 423 // <1> OIC : Overflow interrupt clear <W>
<> 144:ef7eb2e8f9f7 424 // <0> MIC : Match interrupt clear <W>
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 __I uint32_t TCR; //Timer/Counter register
<> 144:ef7eb2e8f9f7 427 // <0..31> TCR : Timer/Counter register <R>
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 __I uint32_t PCR; //Prescale counter register
<> 144:ef7eb2e8f9f7 430 // <0..5> PCR : Prescale Counter register <R>
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 __IO uint32_t PR; //Prescale register
<> 144:ef7eb2e8f9f7 433 // <0..5> PR : prescale register <R/W>
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 __IO uint32_t MR; //Match register
<> 144:ef7eb2e8f9f7 436 // <0..31> MR : Match register <R/W>
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 __IO uint32_t LR; //Limit register
<> 144:ef7eb2e8f9f7 439 // <0..31> LR : Limit register <R/W>
<> 144:ef7eb2e8f9f7 440 __IO uint32_t UDMR; //Up-Down mode register
<> 144:ef7eb2e8f9f7 441 // <0> UDM : Up-down mode <R/W>
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 __IO uint32_t TCMR; //Timer/Counter mode register
<> 144:ef7eb2e8f9f7 444 // <0> TCM : Timer/Counter mode <R/W>
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 __IO uint32_t PEEER; //PWM output enable and external input enable register
<> 144:ef7eb2e8f9f7 447 // <0..1> PEEE : PWM output enable and external input enable <R/W>
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 __IO uint32_t CMR; //Capture mode register
<> 144:ef7eb2e8f9f7 450 // <0> CM : Capture mode <R/W>
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 __IO uint32_t CR; //Capture register
<> 144:ef7eb2e8f9f7 453 // <0..31> CR : Capture register <R>
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 __IO uint32_t PDMR; //Periodic mode register
<> 144:ef7eb2e8f9f7 456 // <0> PDM : Periodic mode <R/W>
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 __IO uint32_t DZER; //Dead-zone enable register
<> 144:ef7eb2e8f9f7 459 // <0> DZE : Dead-zone enable <R/W>
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 __IO uint32_t DZCR; //Dead-zone counter register
<> 144:ef7eb2e8f9f7 462 // <0..9> DZC : Dead-zone counter <R/W>
<> 144:ef7eb2e8f9f7 463 } PWM_CHn_TypeDef;
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 typedef struct
<> 144:ef7eb2e8f9f7 466 {
<> 144:ef7eb2e8f9f7 467 __IO uint32_t PWM_CHn_PR; //Prescale register
<> 144:ef7eb2e8f9f7 468 // <0..5> PR : prescale register <R/W>
<> 144:ef7eb2e8f9f7 469 __IO uint32_t PWM_CHn_MR; //Match register
<> 144:ef7eb2e8f9f7 470 // <0..31> MR : Match register <R/W>
<> 144:ef7eb2e8f9f7 471 __IO uint32_t PWM_CHn_LR; //Limit register
<> 144:ef7eb2e8f9f7 472 // <0..31> LR : Limit register <R/W>
<> 144:ef7eb2e8f9f7 473 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
<> 144:ef7eb2e8f9f7 474 // <0> UDM : Up-down mode <R/W>
<> 144:ef7eb2e8f9f7 475 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
<> 144:ef7eb2e8f9f7 476 // <0> PDM : Periodic mode <R/W>
<> 144:ef7eb2e8f9f7 477 }PWM_TimerModeInitTypeDef;
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 typedef struct
<> 144:ef7eb2e8f9f7 480 {
<> 144:ef7eb2e8f9f7 481 __IO uint32_t PWM_CHn_PR; //Prescale register
<> 144:ef7eb2e8f9f7 482 // <0..5> PR : prescale register <R/W>
<> 144:ef7eb2e8f9f7 483 __IO uint32_t PWM_CHn_MR; //Match register
<> 144:ef7eb2e8f9f7 484 // <0..31> MR : Match register <R/W>
<> 144:ef7eb2e8f9f7 485 __IO uint32_t PWM_CHn_LR; //Limit register
<> 144:ef7eb2e8f9f7 486 // <0..31> LR : Limit register <R/W>
<> 144:ef7eb2e8f9f7 487 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
<> 144:ef7eb2e8f9f7 488 // <0> UDM : Up-down mode <R/W>
<> 144:ef7eb2e8f9f7 489 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
<> 144:ef7eb2e8f9f7 490 // <0> PDM : Peiodic mode <R/W>
<> 144:ef7eb2e8f9f7 491 __IO uint32_t PWM_CHn_CMR; //Capture mode register
<> 144:ef7eb2e8f9f7 492 // <0> CM : Capture mode <R/W>
<> 144:ef7eb2e8f9f7 493 }PWM_CaptureModeInitTypeDef;
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 typedef struct
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 __IO uint32_t PWM_CHn_MR;
<> 144:ef7eb2e8f9f7 498 __IO uint32_t PWM_CHn_LR;
<> 144:ef7eb2e8f9f7 499 __IO uint32_t PWM_CHn_UDMR;
<> 144:ef7eb2e8f9f7 500 __IO uint32_t PWM_CHn_PDMR;
<> 144:ef7eb2e8f9f7 501 __IO uint32_t PWM_CHn_TCMR;
<> 144:ef7eb2e8f9f7 502 }PWM_CounterModeInitTypeDef;
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /**
<> 144:ef7eb2e8f9f7 506 * @brief Random Number generator
<> 144:ef7eb2e8f9f7 507 */
<> 144:ef7eb2e8f9f7 508 typedef struct
<> 144:ef7eb2e8f9f7 509 {
<> 144:ef7eb2e8f9f7 510 __IO uint32_t RNG_RUN; /* RNG run register, Address offset : 0x000 */
<> 144:ef7eb2e8f9f7 511 __IO uint32_t RNG_SEED; /* RNG seed value register, Address offset : 0x004 */
<> 144:ef7eb2e8f9f7 512 __IO uint32_t RNG_CLKSEL; /* RNG Clock source select register, Address offset : 0x008 */
<> 144:ef7eb2e8f9f7 513 __IO uint32_t RNG_MODE; /* RNG MODE select register, Address offset : 0x00c */
<> 144:ef7eb2e8f9f7 514 __I uint32_t RNG_RN; /* RNG random number value register, Address offset : 0x010 */
<> 144:ef7eb2e8f9f7 515 __IO uint32_t RNG_POLY; /* RNG polynomial register, Address offset : 0x014 */
<> 144:ef7eb2e8f9f7 516 }RNG_TypeDef;
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /**
<> 144:ef7eb2e8f9f7 519 * @brief Serial Peripheral Interface
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 typedef struct
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 __IO uint32_t CR0;
<> 144:ef7eb2e8f9f7 524 __IO uint32_t CR1;
<> 144:ef7eb2e8f9f7 525 __IO uint32_t DR;
<> 144:ef7eb2e8f9f7 526 __IO uint32_t SR;
<> 144:ef7eb2e8f9f7 527 __IO uint32_t CPSR;
<> 144:ef7eb2e8f9f7 528 __IO uint32_t IMSC;
<> 144:ef7eb2e8f9f7 529 __IO uint32_t RIS;
<> 144:ef7eb2e8f9f7 530 __IO uint32_t MIS;
<> 144:ef7eb2e8f9f7 531 __IO uint32_t ICR;
<> 144:ef7eb2e8f9f7 532 __IO uint32_t DMACR;
<> 144:ef7eb2e8f9f7 533 } SSP_TypeDef;
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 typedef struct
<> 144:ef7eb2e8f9f7 536 {
<> 144:ef7eb2e8f9f7 537 __IO uint32_t WatchdogLoad; // <h> Watchdog Load Register </h>
<> 144:ef7eb2e8f9f7 538 __I uint32_t WatchdogValue; // <h> Watchdog Value Register </h>
<> 144:ef7eb2e8f9f7 539 __IO uint32_t WatchdogControl; // <h> Watchdog Control Register
<> 144:ef7eb2e8f9f7 540 // <o.1> RESEN: Reset enable
<> 144:ef7eb2e8f9f7 541 // <o.0> INTEN: Interrupt enable
<> 144:ef7eb2e8f9f7 542 // </h>
<> 144:ef7eb2e8f9f7 543 __O uint32_t WatchdogIntClr; // <h> Watchdog Clear Interrupt Register </h>
<> 144:ef7eb2e8f9f7 544 __I uint32_t WatchdogRIS; // <h> Watchdog Raw Interrupt Status Register </h>
<> 144:ef7eb2e8f9f7 545 __I uint32_t WatchdogMIS; // <h> Watchdog Interrupt Status Register </h>
<> 144:ef7eb2e8f9f7 546 uint32_t RESERVED[762];
<> 144:ef7eb2e8f9f7 547 __IO uint32_t WatchdogLock; // <h> Watchdog Lock Register </h>
<> 144:ef7eb2e8f9f7 548 }WATCHDOG_TypeDef;
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /** @addtogroup Peripheral_memory_map
<> 144:ef7eb2e8f9f7 551 * @{
<> 144:ef7eb2e8f9f7 552 */
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /* Peripheral and SRAM base address */
<> 144:ef7eb2e8f9f7 555 #define W7500x_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
<> 144:ef7eb2e8f9f7 556 #define W7500x_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
<> 144:ef7eb2e8f9f7 557 #define W7500x_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 #define W7500x_RAM_BASE (0x20000000UL)
<> 144:ef7eb2e8f9f7 560 #define W7500x_APB1_BASE (0x40000000UL)
<> 144:ef7eb2e8f9f7 561 #define W7500x_APB2_BASE (0x41000000UL)
<> 144:ef7eb2e8f9f7 562 #define W7500x_AHB_BASE (0x42000000UL)
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 #define W7500x_UART0_BASE (W7500x_APB1_BASE + 0x0000C000UL)
<> 144:ef7eb2e8f9f7 565 #define W7500x_UART1_BASE (W7500x_APB1_BASE + 0x0000D000UL)
<> 144:ef7eb2e8f9f7 566 #define W7500x_UART2_BASE (W7500x_APB1_BASE + 0x00006000UL)
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 #define W7500x_CRG_BASE (W7500x_APB2_BASE + 0x00001000UL)
<> 144:ef7eb2e8f9f7 569 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 #define W7500x_INFO_BGT (0x0003FDB8)
<> 144:ef7eb2e8f9f7 572 #define W7500x_INFO_OSC (0x0003FDBC)
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 #define W7500x_TRIM_BGT (0x41001210)
<> 144:ef7eb2e8f9f7 575 #define W7500x_TRIM_OSC (0x41001004)
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 #define W7500x_DUALTIMER0_BASE (W7500x_APB1_BASE + 0x00001000ul)
<> 144:ef7eb2e8f9f7 578 #define W7500x_DUALTIMER1_BASE (W7500x_APB1_BASE + 0x00002000ul)
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 #define EXTI_Px_BASE (W7500x_APB2_BASE + 0x00002200UL)
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 #define GPIOA_BASE (W7500x_AHB_BASE + 0x00000000UL) // W7500x_AHB_BASE : 0x42000000UL
<> 144:ef7eb2e8f9f7 583 #define GPIOB_BASE (W7500x_AHB_BASE + 0x01000000UL)
<> 144:ef7eb2e8f9f7 584 #define GPIOC_BASE (W7500x_AHB_BASE + 0x02000000UL)
<> 144:ef7eb2e8f9f7 585 #define GPIOD_BASE (W7500x_AHB_BASE + 0x03000000UL)
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 #define P_AFSR_BASE (W7500x_APB2_BASE + 0x00002000UL)
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 #define P_PCR_BASE (W7500x_APB2_BASE + 0x00003000UL)
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 #define I2C0_BASE (W7500x_APB1_BASE + 0x8000)
<> 144:ef7eb2e8f9f7 592 #define I2C1_BASE (W7500x_APB1_BASE + 0x9000)
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 #define W7500x_PWM_BASE (W7500x_APB1_BASE + 0x00005000UL)
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 #define W7500x_RNG_BASE (W7500x_APB1_BASE + 0x00007000UL)
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 #define SSP0_BASE (0x4000A000)
<> 144:ef7eb2e8f9f7 599 #define SSP1_BASE (0x4000B000)
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 #define W7500x_WATCHDOG_BASE (W7500x_APB1_BASE + 0x0000UL)
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /**
<> 144:ef7eb2e8f9f7 604 * @}
<> 144:ef7eb2e8f9f7 605 */
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /** @addtogroup Peripheral_declaration
<> 144:ef7eb2e8f9f7 609 * @{
<> 144:ef7eb2e8f9f7 610 */
<> 144:ef7eb2e8f9f7 611 #define CRG ((CRG_TypeDef *) W7500x_CRG_BASE)
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 #define UART0 ((UART_TypeDef *) W7500x_UART0_BASE)
<> 144:ef7eb2e8f9f7 614 #define UART1 ((UART_TypeDef *) W7500x_UART1_BASE)
<> 144:ef7eb2e8f9f7 615 #define UART2 ((S_UART_TypeDef *) W7500x_UART2_BASE)
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 #define DUALTIMER0_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE) )
<> 144:ef7eb2e8f9f7 620 #define DUALTIMER0_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE + 0x20ul))
<> 144:ef7eb2e8f9f7 621 #define DUALTIMER1_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE) )
<> 144:ef7eb2e8f9f7 622 #define DUALTIMER1_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE + 0x20ul))
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 #define EXTI_PA ((P_Port_Def *) (EXTI_Px_BASE + 0x00000000UL)) /* PA_XX External interrupt Enable Register */
<> 144:ef7eb2e8f9f7 625 #define EXTI_PB ((P_Port_Def *) (EXTI_Px_BASE + 0x00000040UL)) /* PB_XX External interrupt Enable Register */
<> 144:ef7eb2e8f9f7 626 #define EXTI_PC ((P_Port_Def *) (EXTI_Px_BASE + 0x00000080UL)) /* PC_XX External interrupt Enable Register */
<> 144:ef7eb2e8f9f7 627 #define EXTI_PD ((P_Port_D_Def *) (EXTI_Px_BASE + 0x000000C0UL)) /* PD_XX External interrupt Enable Register */
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 #define GPIOA ((GPIO_TypeDef *) (GPIOA_BASE) )
<> 144:ef7eb2e8f9f7 630 #define GPIOB ((GPIO_TypeDef *) (GPIOB_BASE) )
<> 144:ef7eb2e8f9f7 631 #define GPIOC ((GPIO_TypeDef *) (GPIOC_BASE) )
<> 144:ef7eb2e8f9f7 632 #define GPIOD ((GPIO_TypeDef *) (GPIOD_BASE) )
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 #define PA_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000000UL)) /* PA_XX Pad Alternate Function Select Register */
<> 144:ef7eb2e8f9f7 635 #define PB_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000040UL)) /* PB_XX Pad Alternate Function Select Register */
<> 144:ef7eb2e8f9f7 636 #define PC_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000080UL)) /* PC_XX Pad Alternate Function Select Register */
<> 144:ef7eb2e8f9f7 637 #define PD_AFSR ((P_Port_D_Def *) (P_AFSR_BASE + 0x000000C0UL)) /* PD_XX Pad Alternate Function Select Register */
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 #define PA_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000000UL)) /* PA_XX Pad Control Register */
<> 144:ef7eb2e8f9f7 640 #define PB_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000040UL)) /* PB_XX Pad Control Register */
<> 144:ef7eb2e8f9f7 641 #define PC_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000080UL)) /* PC_XX Pad Control Register */
<> 144:ef7eb2e8f9f7 642 #define PD_PCR ((P_Port_D_Def *) (P_PCR_BASE + 0x000000C0UL)) /* PD_XX Pad Control Register */
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
<> 144:ef7eb2e8f9f7 645 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 #define TIMCLKEN0_0 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0x80ul)
<> 144:ef7eb2e8f9f7 649 #define TIMCLKEN0_1 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0xA0ul)
<> 144:ef7eb2e8f9f7 650 #define TIMCLKEN1_0 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0x80ul)
<> 144:ef7eb2e8f9f7 651 #define TIMCLKEN1_1 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0xA0ul)
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 #define PWM ((PWM_TypeDef *) (W7500x_PWM_BASE + 0x800UL ))
<> 144:ef7eb2e8f9f7 654 #define PWM_CH0 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE))
<> 144:ef7eb2e8f9f7 655 #define PWM_CH1 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x100UL))
<> 144:ef7eb2e8f9f7 656 #define PWM_CH2 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x200UL))
<> 144:ef7eb2e8f9f7 657 #define PWM_CH3 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x300UL))
<> 144:ef7eb2e8f9f7 658 #define PWM_CH4 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x400UL))
<> 144:ef7eb2e8f9f7 659 #define PWM_CH5 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x500UL))
<> 144:ef7eb2e8f9f7 660 #define PWM_CH6 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x600UL))
<> 144:ef7eb2e8f9f7 661 #define PWM_CH7 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x700UL))
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 #define PWM_CH0_BASE (W7500x_PWM_BASE)
<> 144:ef7eb2e8f9f7 664 #define PWM_CH1_BASE (W7500x_PWM_BASE + 0x100UL)
<> 144:ef7eb2e8f9f7 665 #define PWM_CH2_BASE (W7500x_PWM_BASE + 0x200UL)
<> 144:ef7eb2e8f9f7 666 #define PWM_CH3_BASE (W7500x_PWM_BASE + 0x300UL)
<> 144:ef7eb2e8f9f7 667 #define PWM_CH4_BASE (W7500x_PWM_BASE + 0x400UL)
<> 144:ef7eb2e8f9f7 668 #define PWM_CH5_BASE (W7500x_PWM_BASE + 0x500UL)
<> 144:ef7eb2e8f9f7 669 #define PWM_CH6_BASE (W7500x_PWM_BASE + 0x600UL)
<> 144:ef7eb2e8f9f7 670 #define PWM_CH7_BASE (W7500x_PWM_BASE + 0x700UL)
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 #define RNG ((RNG_TypeDef *) W7500x_RNG_BASE)
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 #define SSP0 ((SSP_TypeDef*) (SSP0_BASE))
<> 144:ef7eb2e8f9f7 675 #define SSP1 ((SSP_TypeDef*) (SSP1_BASE))
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 #define WATCHDOG ((WATCHDOG_TypeDef *) W7500x_WATCHDOG_BASE)
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @}
<> 144:ef7eb2e8f9f7 681 */
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /******************************************************************************/
<> 144:ef7eb2e8f9f7 686 /* */
<> 144:ef7eb2e8f9f7 687 /* Clock Reset Generator */
<> 144:ef7eb2e8f9f7 688 /* */
<> 144:ef7eb2e8f9f7 689 /******************************************************************************/
<> 144:ef7eb2e8f9f7 690 /**************** Bit definition for CRG_OSC_PDR **************************/
<> 144:ef7eb2e8f9f7 691 #define CRG_OSC_PDR_NRMLOP (0x0ul) // Normal Operation
<> 144:ef7eb2e8f9f7 692 #define CRG_OSC_PDR_PD (0x1ul) // Power Down
<> 144:ef7eb2e8f9f7 693 /**************** Bit definition for CRG_PLL_PDR **************************/
<> 144:ef7eb2e8f9f7 694 #define CRG_PLL_PDR_PD (0x0ul) // Power Down
<> 144:ef7eb2e8f9f7 695 #define CRG_PLL_PDR_NRMLOP (0x1ul) // Normal Operation
<> 144:ef7eb2e8f9f7 696 /**************** Bit definition for CRG_PLL_FCR **************************/
<> 144:ef7eb2e8f9f7 697 //ToDo
<> 144:ef7eb2e8f9f7 698 /**************** Bit definition for CRG_PLL_OER **************************/
<> 144:ef7eb2e8f9f7 699 #define CRG_PLL_OER_DIS (0x0ul) // Clock out is disable
<> 144:ef7eb2e8f9f7 700 #define CRG_PLL_OER_EN (0x1ul) // Clock out is enable
<> 144:ef7eb2e8f9f7 701 /**************** Bit definition for CRG_PLL_BPR **************************/
<> 144:ef7eb2e8f9f7 702 #define CRG_PLL_BPR_DIS (0x0ul) // Bypass disable. Normal operation
<> 144:ef7eb2e8f9f7 703 #define CRG_PLL_BPR_EN (0x1ul) // Bypass enable. Clock will be set to external clock
<> 144:ef7eb2e8f9f7 704 /**************** Bit definition for CRG_PLL_IFSR **************************/
<> 144:ef7eb2e8f9f7 705 #define CRG_PLL_IFSR_RCLK (0x0ul) // Internal 8MHz RC oscillator clock(RCLK)
<> 144:ef7eb2e8f9f7 706 #define CRG_PLL_IFSR_OCLK (0x1ul) // External oscillator clock (OCLK, 8MHz ~ 24MHz)
<> 144:ef7eb2e8f9f7 707 /**************** Bit definition for CRG_FCLK_SSR **************************/
<> 144:ef7eb2e8f9f7 708 #define CRG_FCLK_SSR_MCLK (0x01ul) // 00,01 Output clock of PLL(MCLK)
<> 144:ef7eb2e8f9f7 709 #define CRG_FCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
<> 144:ef7eb2e8f9f7 710 #define CRG_FCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
<> 144:ef7eb2e8f9f7 711 /**************** Bit definition for CRG_FCLK_PVSR **************************/
<> 144:ef7eb2e8f9f7 712 #define CRG_FCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
<> 144:ef7eb2e8f9f7 713 #define CRG_FCLK_PVSR_DIV2 (0x01ul) // 1/2
<> 144:ef7eb2e8f9f7 714 #define CRG_FCLK_PVSR_DIV4 (0x02ul) // 1/4
<> 144:ef7eb2e8f9f7 715 #define CRG_FCLK_PVSR_DIV8 (0x03ul) // 1/8
<> 144:ef7eb2e8f9f7 716 /**************** Bit definition for CRG_SSPCLK_SSR **************************/
<> 144:ef7eb2e8f9f7 717 #define CRG_SSPCLK_SSR_DIS (0x00ul) // Disable clock
<> 144:ef7eb2e8f9f7 718 #define CRG_SSPCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
<> 144:ef7eb2e8f9f7 719 #define CRG_SSPCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
<> 144:ef7eb2e8f9f7 720 #define CRG_SSPCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
<> 144:ef7eb2e8f9f7 721 /**************** Bit definition for CRG_SSPCLK_PVSR **************************/
<> 144:ef7eb2e8f9f7 722 #define CRG_SSPCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
<> 144:ef7eb2e8f9f7 723 #define CRG_SSPCLK_PVSR_DIV2 (0x01ul) // 1/2
<> 144:ef7eb2e8f9f7 724 #define CRG_SSPCLK_PVSR_DIV4 (0x02ul) // 1/4
<> 144:ef7eb2e8f9f7 725 #define CRG_SSPCLK_PVSR_DIV8 (0x03ul) // 1/8
<> 144:ef7eb2e8f9f7 726 /**************** Bit definition for CRG_ADCCLK_SSR **************************/
<> 144:ef7eb2e8f9f7 727 #define CRG_ADCCLK_SSR_DIS (0x00ul) // Disable clock
<> 144:ef7eb2e8f9f7 728 #define CRG_ADCCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
<> 144:ef7eb2e8f9f7 729 #define CRG_ADCCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
<> 144:ef7eb2e8f9f7 730 #define CRG_ADCCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
<> 144:ef7eb2e8f9f7 731 /**************** Bit definition for CRG_ADCCLK_PVSR **************************/
<> 144:ef7eb2e8f9f7 732 #define CRG_ADCCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
<> 144:ef7eb2e8f9f7 733 #define CRG_ADCCLK_PVSR_DIV2 (0x01ul) // 1/2
<> 144:ef7eb2e8f9f7 734 #define CRG_ADCCLK_PVSR_DIV4 (0x02ul) // 1/4
<> 144:ef7eb2e8f9f7 735 #define CRG_ADCCLK_PVSR_DIV8 (0x03ul) // 1/8
<> 144:ef7eb2e8f9f7 736 /**************** Bit definition for CRG_TIMER0/1CLK_SSR **************************/
<> 144:ef7eb2e8f9f7 737 #define CRG_TIMERCLK_SSR_DIS (0x00ul) // Disable clock
<> 144:ef7eb2e8f9f7 738 #define CRG_TIMERCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
<> 144:ef7eb2e8f9f7 739 #define CRG_TIMERCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
<> 144:ef7eb2e8f9f7 740 #define CRG_TIMERCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
<> 144:ef7eb2e8f9f7 741 /**************** Bit definition for CRG_TIMER0/1CLK_PVSR **************************/
<> 144:ef7eb2e8f9f7 742 #define CRG_TIMERCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
<> 144:ef7eb2e8f9f7 743 #define CRG_TIMERCLK_PVSR_DIV2 (0x01ul) // 1/2
<> 144:ef7eb2e8f9f7 744 #define CRG_TIMERCLK_PVSR_DIV4 (0x02ul) // 1/4
<> 144:ef7eb2e8f9f7 745 #define CRG_TIMERCLK_PVSR_DIV8 (0x03ul) // 1/8
<> 144:ef7eb2e8f9f7 746 #define CRG_TIMERCLK_PVSR_DIV16 (0x04ul) // 1/16
<> 144:ef7eb2e8f9f7 747 #define CRG_TIMERCLK_PVSR_DIV32 (0x05ul) // 1/32
<> 144:ef7eb2e8f9f7 748 #define CRG_TIMERCLK_PVSR_DIV64 (0x06ul) // 1/64
<> 144:ef7eb2e8f9f7 749 #define CRG_TIMERCLK_PVSR_DIV128 (0x07ul) // 1/128
<> 144:ef7eb2e8f9f7 750 /**************** Bit definition for CRG_PWMnCLK_SSR **************************/
<> 144:ef7eb2e8f9f7 751 #define CRG_PWMCLK_SSR_DIS (0x00ul) // Disable clock
<> 144:ef7eb2e8f9f7 752 #define CRG_PWMCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
<> 144:ef7eb2e8f9f7 753 #define CRG_PWMCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
<> 144:ef7eb2e8f9f7 754 #define CRG_PWMCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
<> 144:ef7eb2e8f9f7 755 /**************** Bit definition for CRG_PWMnCLK_PVSR **************************/
<> 144:ef7eb2e8f9f7 756 #define CRG_PWMCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
<> 144:ef7eb2e8f9f7 757 #define CRG_PWMCLK_PVSR_DIV2 (0x01ul) // 1/2
<> 144:ef7eb2e8f9f7 758 #define CRG_PWMCLK_PVSR_DIV4 (0x02ul) // 1/4
<> 144:ef7eb2e8f9f7 759 #define CRG_PWMCLK_PVSR_DIV8 (0x03ul) // 1/8
<> 144:ef7eb2e8f9f7 760 #define CRG_PWMCLK_PVSR_DIV16 (0x04ul) // 1/16
<> 144:ef7eb2e8f9f7 761 #define CRG_PWMCLK_PVSR_DIV32 (0x05ul) // 1/32
<> 144:ef7eb2e8f9f7 762 #define CRG_PWMCLK_PVSR_DIV64 (0x06ul) // 1/64
<> 144:ef7eb2e8f9f7 763 #define CRG_PWMCLK_PVSR_DIV128 (0x07ul) // 1/128
<> 144:ef7eb2e8f9f7 764 /**************** Bit definition for CRG_RTC_HS_SSR **************************/
<> 144:ef7eb2e8f9f7 765 #define CRG_RTC_HS_SSR_DIS (0x00ul) // Disable clock
<> 144:ef7eb2e8f9f7 766 #define CRG_RTC_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
<> 144:ef7eb2e8f9f7 767 #define CRG_RTC_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
<> 144:ef7eb2e8f9f7 768 #define CRG_RTC_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
<> 144:ef7eb2e8f9f7 769 /**************** Bit definition for CRG_RTC_HS_PVSR **************************/
<> 144:ef7eb2e8f9f7 770 #define CRG_RTC_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
<> 144:ef7eb2e8f9f7 771 #define CRG_RTC_HS_PVSR_DIV2 (0x01ul) // 1/2
<> 144:ef7eb2e8f9f7 772 #define CRG_RTC_HS_PVSR_DIV4 (0x02ul) // 1/4
<> 144:ef7eb2e8f9f7 773 #define CRG_RTC_HS_PVSR_DIV8 (0x03ul) // 1/8
<> 144:ef7eb2e8f9f7 774 #define CRG_RTC_HS_PVSR_DIV16 (0x04ul) // 1/16
<> 144:ef7eb2e8f9f7 775 #define CRG_RTC_HS_PVSR_DIV32 (0x05ul) // 1/32
<> 144:ef7eb2e8f9f7 776 #define CRG_RTC_HS_PVSR_DIV64 (0x06ul) // 1/64
<> 144:ef7eb2e8f9f7 777 #define CRG_RTC_HS_PVSR_DIV128 (0x07ul) // 1/128
<> 144:ef7eb2e8f9f7 778 /**************** Bit definition for CRG_RTC_SSR **************************/
<> 144:ef7eb2e8f9f7 779 #define CRG_RTC_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
<> 144:ef7eb2e8f9f7 780 #define CRG_RTC_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
<> 144:ef7eb2e8f9f7 781 /**************** Bit definition for CRG_WDOGCLK_HS_SSR **************************/
<> 144:ef7eb2e8f9f7 782 #define CRG_WDOGCLK_HS_SSR_DIS (0x00ul) // Disable clock
<> 144:ef7eb2e8f9f7 783 #define CRG_WDOGCLK_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
<> 144:ef7eb2e8f9f7 784 #define CRG_WDOGCLK_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
<> 144:ef7eb2e8f9f7 785 #define CRG_WDOGCLK_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
<> 144:ef7eb2e8f9f7 786 /**************** Bit definition for CRG_WDOGCLK_HS_PVSR **************************/
<> 144:ef7eb2e8f9f7 787 #define CRG_WDOGCLK_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
<> 144:ef7eb2e8f9f7 788 #define CRG_WDOGCLK_HS_PVSR_DIV2 (0x01ul) // 1/2
<> 144:ef7eb2e8f9f7 789 #define CRG_WDOGCLK_HS_PVSR_DIV4 (0x02ul) // 1/4
<> 144:ef7eb2e8f9f7 790 #define CRG_WDOGCLK_HS_PVSR_DIV8 (0x03ul) // 1/8
<> 144:ef7eb2e8f9f7 791 #define CRG_WDOGCLK_HS_PVSR_DIV16 (0x04ul) // 1/16
<> 144:ef7eb2e8f9f7 792 #define CRG_WDOGCLK_HS_PVSR_DIV32 (0x05ul) // 1/32
<> 144:ef7eb2e8f9f7 793 #define CRG_WDOGCLK_HS_PVSR_DIV64 (0x06ul) // 1/64
<> 144:ef7eb2e8f9f7 794 #define CRG_WDOGCLK_HS_PVSR_DIV128 (0x07ul) // 1/128
<> 144:ef7eb2e8f9f7 795 /**************** Bit definition for CRG_WDOGCLK_SSR **************************/
<> 144:ef7eb2e8f9f7 796 #define CRG_WDOGCLK_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
<> 144:ef7eb2e8f9f7 797 #define CRG_WDOGCLK_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
<> 144:ef7eb2e8f9f7 798 /**************** Bit definition for CRG_UARTCLK_SSR **************************/
<> 144:ef7eb2e8f9f7 799 #define CRG_UARTCLK_SSR_DIS (0x00ul) // Disable clock
<> 144:ef7eb2e8f9f7 800 #define CRG_UARTCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
<> 144:ef7eb2e8f9f7 801 #define CRG_UARTCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
<> 144:ef7eb2e8f9f7 802 #define CRG_UARTCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
<> 144:ef7eb2e8f9f7 803 /**************** Bit definition for CRG_UARTCLK_PVSR **************************/
<> 144:ef7eb2e8f9f7 804 #define CRG_UARTCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
<> 144:ef7eb2e8f9f7 805 #define CRG_UARTCLK_PVSR_DIV2 (0x01ul) // 1/2
<> 144:ef7eb2e8f9f7 806 #define CRG_UARTCLK_PVSR_DIV4 (0x02ul) // 1/4
<> 144:ef7eb2e8f9f7 807 #define CRG_UARTCLK_PVSR_DIV8 (0x03ul) // 1/8
<> 144:ef7eb2e8f9f7 808 /**************** Bit definition for CRG_MIICLK_ECR **************************/
<> 144:ef7eb2e8f9f7 809 #define CRG_MIICLK_ECR_EN_RXCLK (0x01ul << 0) // Enable MII_RCK and MII_RCK_N
<> 144:ef7eb2e8f9f7 810 #define CRG_MIICLK_ECR_EN_TXCLK (0x01ul << 1) // Enable MII_TCK and MII_TCK_N
<> 144:ef7eb2e8f9f7 811 /**************** Bit definition for CRG_MONCLK_SSR **************************/
<> 144:ef7eb2e8f9f7 812 #define CRG_MONCLK_SSR_MCLK (0x00ul) // PLL output clock (MCLK)
<> 144:ef7eb2e8f9f7 813 #define CRG_MONCLK_SSR_FCLK (0x01ul) // FCLK
<> 144:ef7eb2e8f9f7 814 #define CRG_MONCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
<> 144:ef7eb2e8f9f7 815 #define CRG_MONCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
<> 144:ef7eb2e8f9f7 816 #define CRG_MONCLK_SSR_ADCCLK (0x04ul) // ADCCLK
<> 144:ef7eb2e8f9f7 817 #define CRG_MONCLK_SSR_SSPCLK (0x05ul) // SSPCLK
<> 144:ef7eb2e8f9f7 818 #define CRG_MONCLK_SSR_TIMCLK0 (0x06ul) // TIMCLK0
<> 144:ef7eb2e8f9f7 819 #define CRG_MONCLK_SSR_TIMCLK1 (0x07ul) // TIMCLK1
<> 144:ef7eb2e8f9f7 820 #define CRG_MONCLK_SSR_PWMCLK0 (0x08ul) // PWMCLK0
<> 144:ef7eb2e8f9f7 821 #define CRG_MONCLK_SSR_PWMCLK1 (0x09ul) // PWMCLK1
<> 144:ef7eb2e8f9f7 822 #define CRG_MONCLK_SSR_PWMCLK2 (0x0Aul) // PWMCLK2
<> 144:ef7eb2e8f9f7 823 #define CRG_MONCLK_SSR_PWMCLK3 (0x0Bul) // PWMCLK3
<> 144:ef7eb2e8f9f7 824 #define CRG_MONCLK_SSR_PWMCLK4 (0x0Cul) // PWMCLK4
<> 144:ef7eb2e8f9f7 825 #define CRG_MONCLK_SSR_PWMCLK5 (0x0Dul) // PWMCLK5
<> 144:ef7eb2e8f9f7 826 #define CRG_MONCLK_SSR_PWMCLK6 (0x0Eul) // PWMCLK6
<> 144:ef7eb2e8f9f7 827 #define CRG_MONCLK_SSR_PWMCLK7 (0x0Ful) // PWMCLK7
<> 144:ef7eb2e8f9f7 828 #define CRG_MONCLK_SSR_UARTCLK (0x10ul) // UARTCLK
<> 144:ef7eb2e8f9f7 829 #define CRG_MONCLK_SSR_MII_RXCLK (0x11ul) // MII_RXCLK
<> 144:ef7eb2e8f9f7 830 #define CRG_MONCLK_SSR_MII_TXCLK (0x12ul) // MII_TXCLK
<> 144:ef7eb2e8f9f7 831 #define CRG_MONCLK_SSR_RTCCLK (0x13ul) // RTCCLK
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 /******************************************************************************/
<> 144:ef7eb2e8f9f7 834 /* */
<> 144:ef7eb2e8f9f7 835 /* UART */
<> 144:ef7eb2e8f9f7 836 /* */
<> 144:ef7eb2e8f9f7 837 /******************************************************************************/
<> 144:ef7eb2e8f9f7 838 /****************** Bit definition for UART Data(UARTDR) register *************************/
<> 144:ef7eb2e8f9f7 839 #define UART_DR_OE (0x01ul << 11) // Overrun Error
<> 144:ef7eb2e8f9f7 840 #define UART_DR_BE (0x01ul << 10) // Break Error
<> 144:ef7eb2e8f9f7 841 #define UART_DR_PE (0x01ul << 9) // Parity Error
<> 144:ef7eb2e8f9f7 842 #define UART_DR_FE (0x01ul << 8) // Framing Error
<> 144:ef7eb2e8f9f7 843 //#define UART_DR_DR // ToDo
<> 144:ef7eb2e8f9f7 844 /***************** Bit definition for UART Receive Status(UARTRSR) register ***************/
<> 144:ef7eb2e8f9f7 845 #define UARTR_SR_OE (0x01ul << 3) // Overrun Error
<> 144:ef7eb2e8f9f7 846 #define UARTR_SR_BE (0x01ul << 2) // Break Error
<> 144:ef7eb2e8f9f7 847 #define UARTR_SR_PE (0x01ul << 1) // Parity Error
<> 144:ef7eb2e8f9f7 848 #define UARTR_SR_FE (0x01ul << 0) // Framing Error
<> 144:ef7eb2e8f9f7 849 /***************** Bit definition for UART Error Clear(UARTECR) register ******************/
<> 144:ef7eb2e8f9f7 850 #define UARTE_CR_OE (0x01ul << 3) // Overrun Error
<> 144:ef7eb2e8f9f7 851 #define UARTE_CR_BE (0x01ul << 2) // Break Error
<> 144:ef7eb2e8f9f7 852 #define UARTE_CR_PE (0x01ul << 1) // Parity Error
<> 144:ef7eb2e8f9f7 853 #define UARTE_CR_FE (0x01ul << 0) // Framing Error
<> 144:ef7eb2e8f9f7 854 /****************** Bit definition for UART Flags(UARTFR) register ************************/
<> 144:ef7eb2e8f9f7 855 #define UART_FR_RI (0x01ul << 8) // Ring indicator
<> 144:ef7eb2e8f9f7 856 #define UART_FR_TXFE (0x01ul << 7) // Transmit FIFO empty
<> 144:ef7eb2e8f9f7 857 #define UART_FR_RXFF (0x01ul << 6) // Receive FIFO full
<> 144:ef7eb2e8f9f7 858 #define UART_FR_TXFF (0x01ul << 5) // Transmit FIFO full
<> 144:ef7eb2e8f9f7 859 #define UART_FR_RXFE (0x01ul << 4) // Receive FIFO empty
<> 144:ef7eb2e8f9f7 860 #define UART_FR_BUSY (0x01ul << 3) // UART busy
<> 144:ef7eb2e8f9f7 861 #define UART_FR_DCD (0x01ul << 2) // Data carrier detect
<> 144:ef7eb2e8f9f7 862 #define UART_FR_DSR (0x01ul << 1) // Data set ready
<> 144:ef7eb2e8f9f7 863 #define UART_FR_CTS (0x01ul << 0) // Clear to send
<> 144:ef7eb2e8f9f7 864 /********** Bit definition for UART Low-power Counter(UARTILPR) register *******************/
<> 144:ef7eb2e8f9f7 865 #define UARTILPR_COUNTER (0xFFul << 0) // 8-bit low-power divisor value (0..255)
<> 144:ef7eb2e8f9f7 866 /********************* Bit definition for Line Control(UARTLCR_H) register *****************/
<> 144:ef7eb2e8f9f7 867 #define UART_LCR_H_SPS (0x1ul << 7) // Stick parity select
<> 144:ef7eb2e8f9f7 868 #define UART_LCR_H_WLEN(n) ((n & 0x3ul) << 5) // Word length ( 0=5bits, 1=6bits, 2=7bits, 3=8bits )
<> 144:ef7eb2e8f9f7 869 #define UART_LCR_H_FEN (0x1ul << 4) // Enable FIFOs
<> 144:ef7eb2e8f9f7 870 #define UART_LCR_H_STP2 (0x1ul << 3) // Two stop bits select
<> 144:ef7eb2e8f9f7 871 #define UART_LCR_H_EPS (0x1ul << 2) // Even parity select
<> 144:ef7eb2e8f9f7 872 #define UART_LCR_H_PEN (0x1ul << 1) // Parity enable
<> 144:ef7eb2e8f9f7 873 #define UART_LCR_H_BRK (0x1ul << 0) // Send break
<> 144:ef7eb2e8f9f7 874 /********************* Bit definition for Contro(UARTCR) register *************************/
<> 144:ef7eb2e8f9f7 875 #define UART_CR_CTSEn (0x1ul << 15) // CTS hardware flow control enable
<> 144:ef7eb2e8f9f7 876 #define UART_CR_RTSEn (0x1ul << 14) // RTS hardware flow control enable
<> 144:ef7eb2e8f9f7 877 #define UART_CR_Out2 (0x1ul << 13) // Complement of Out2 modem status output
<> 144:ef7eb2e8f9f7 878 #define UART_CR_Out1 (0x1ul << 12) // Complement of Out1 modem status output
<> 144:ef7eb2e8f9f7 879 #define UART_CR_RTS (0x1ul << 11) // Request to send
<> 144:ef7eb2e8f9f7 880 #define UART_CR_DTR (0x1ul << 10) // Data transmit ready
<> 144:ef7eb2e8f9f7 881 #define UART_CR_RXE (0x1ul << 9) // Receive enable
<> 144:ef7eb2e8f9f7 882 #define UART_CR_TXE (0x1ul << 8) // Transmit enable
<> 144:ef7eb2e8f9f7 883 #define UART_CR_LBE (0x1ul << 7) // Loop-back enable
<> 144:ef7eb2e8f9f7 884 #define UART_CR_SIRLP (0x1ul << 2) // IrDA SIR low power mode
<> 144:ef7eb2e8f9f7 885 #define UART_CR_SIREN (0x1ul << 1) // SIR enable
<> 144:ef7eb2e8f9f7 886 #define UART_CR_UARTEN (0x1ul << 0) // UART enable
<> 144:ef7eb2e8f9f7 887 /******* Bit definition for Interrupt FIFO Level Select(UARTIFLS) register *****************/
<> 144:ef7eb2e8f9f7 888 #define UART_IFLS_RXIFLSEL(n) ((n & 0x7ul) << 3) // Receive interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
<> 144:ef7eb2e8f9f7 889 #define UART_IFLS_TXIFLSEL(n) ((n & 0x7ul) << 0) // Transmit interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
<> 144:ef7eb2e8f9f7 890 /******* Bit definition for Interrupt Mask Set/Clear(UARTIMSC) register ********************/
<> 144:ef7eb2e8f9f7 891 #define UART_IMSC_OEIM (0x1ul << 10) // Overrun error interrupt mask
<> 144:ef7eb2e8f9f7 892 #define UART_IMSC_BEIM (0x1ul << 9) // Break error interrupt mask
<> 144:ef7eb2e8f9f7 893 #define UART_IMSC_PEIM (0x1ul << 8) // Parity error interrupt mask
<> 144:ef7eb2e8f9f7 894 #define UART_IMSC_FEIM (0x1ul << 7) // Framing error interrupt mask
<> 144:ef7eb2e8f9f7 895 #define UART_IMSC_RTIM (0x1ul << 6) // Receive interrupt mask
<> 144:ef7eb2e8f9f7 896 #define UART_IMSC_TXIM (0x1ul << 5) // Transmit interrupt mask
<> 144:ef7eb2e8f9f7 897 #define UART_IMSC_RXIM (0x1ul << 4) // Receive interrupt mask
<> 144:ef7eb2e8f9f7 898 #define UART_IMSC_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt mask
<> 144:ef7eb2e8f9f7 899 #define UART_IMSC_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt mask
<> 144:ef7eb2e8f9f7 900 #define UART_IMSC_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt mask
<> 144:ef7eb2e8f9f7 901 #define UART_IMSC_RIMIM (0x1ul << 0) // nUARTRI modem interrupt mask
<> 144:ef7eb2e8f9f7 902 /*************** Bit definition for Raw Interrupt Status(UARTRIS) register *****************/
<> 144:ef7eb2e8f9f7 903 #define UART_RIS_OEIM (0x1ul << 10) // Overrun error interrupt status
<> 144:ef7eb2e8f9f7 904 #define UART_RIS_BEIM (0x1ul << 9) // Break error interrupt status
<> 144:ef7eb2e8f9f7 905 #define UART_RIS_PEIM (0x1ul << 8) // Parity error interrupt status
<> 144:ef7eb2e8f9f7 906 #define UART_RIS_FEIM (0x1ul << 7) // Framing error interrupt status
<> 144:ef7eb2e8f9f7 907 #define UART_RIS_RTIM (0x1ul << 6) // Receive interrupt status
<> 144:ef7eb2e8f9f7 908 #define UART_RIS_TXIM (0x1ul << 5) // Transmit interrupt status
<> 144:ef7eb2e8f9f7 909 #define UART_RIS_RXIM (0x1ul << 4) // Receive interrupt status
<> 144:ef7eb2e8f9f7 910 #define UART_RIS_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt status
<> 144:ef7eb2e8f9f7 911 #define UART_RIS_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt status
<> 144:ef7eb2e8f9f7 912 #define UART_RIS_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt status
<> 144:ef7eb2e8f9f7 913 #define UART_RIS_RIMIM (0x1ul << 0) // nUARTRI modem interrupt status
<> 144:ef7eb2e8f9f7 914 /************** Bit definition for Masked Interrupt Status(UARTMIS) register ****************/
<> 144:ef7eb2e8f9f7 915 #define UART_MIS_OEIM (0x1ul << 10) // Overrun error masked interrupt status
<> 144:ef7eb2e8f9f7 916 #define UART_MIS_BEIM (0x1ul << 9) // Break error masked interrupt status
<> 144:ef7eb2e8f9f7 917 #define UART_MIS_PEIM (0x1ul << 8) // Parity error masked interrupt status
<> 144:ef7eb2e8f9f7 918 #define UART_MIS_FEIM (0x1ul << 7) // Framing error masked interrupt status
<> 144:ef7eb2e8f9f7 919 #define UART_MIS_RTIM (0x1ul << 6) // Receive masked interrupt status
<> 144:ef7eb2e8f9f7 920 #define UART_MIS_TXIM (0x1ul << 5) // Transmit masked interrupt status
<> 144:ef7eb2e8f9f7 921 #define UART_MIS_RXIM (0x1ul << 4) // Receive masked interrupt status
<> 144:ef7eb2e8f9f7 922 #define UART_MIS_DSRMIM (0x1ul << 3) // nUARTDSR modem masked interrupt status
<> 144:ef7eb2e8f9f7 923 #define UART_MIS_DCDMIM (0x1ul << 2) // nUARTDCD modem masked interrupt status
<> 144:ef7eb2e8f9f7 924 #define UART_MIS_CTSMIM (0x1ul << 1) // nUARTCTS modem masked interrupt status
<> 144:ef7eb2e8f9f7 925 #define UART_MIS_RIMIM (0x1ul << 0) // nUARTRI modem masked interrupt status
<> 144:ef7eb2e8f9f7 926 /*************** Bit definition for Interrupt Clear(UARTICR) register ************************/
<> 144:ef7eb2e8f9f7 927 #define UART_ICR_OEIM (0x1ul << 10) // Overrun error interrupt clear
<> 144:ef7eb2e8f9f7 928 #define UART_ICR_BEIM (0x1ul << 9) // Break error interrupt clear
<> 144:ef7eb2e8f9f7 929 #define UART_ICR_PEIM (0x1ul << 8) // Parity error interrupt clear
<> 144:ef7eb2e8f9f7 930 #define UART_ICR_FEIM (0x1ul << 7) // Framing error interrupt clear
<> 144:ef7eb2e8f9f7 931 #define UART_ICR_RTIM (0x1ul << 6) // Receive interrupt clear
<> 144:ef7eb2e8f9f7 932 #define UART_ICR_TXIM (0x1ul << 5) // Transmit interrupt clear
<> 144:ef7eb2e8f9f7 933 #define UART_ICR_RXIM (0x1ul << 4) // Receive interrupt clear
<> 144:ef7eb2e8f9f7 934 #define UART_ICR_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt clear
<> 144:ef7eb2e8f9f7 935 #define UART_ICR_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt clear
<> 144:ef7eb2e8f9f7 936 #define UART_ICR_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt clear
<> 144:ef7eb2e8f9f7 937 #define UART_ICR_RIMIM (0x1ul << 0) // nUARTRI modem interrupt clear
<> 144:ef7eb2e8f9f7 938 /***************** Bit definition for DMA Control(UARTDMACR) register ************************/
<> 144:ef7eb2e8f9f7 939 #define UART_DMACR_DMAONERR (0x1ul << 2) // DMA on error
<> 144:ef7eb2e8f9f7 940 #define UART_DMACR_TXDMAE (0x1ul << 1) // Transmit DMA enable
<> 144:ef7eb2e8f9f7 941 #define UART_DMACR_RXDMAE (0x1ul << 0) // Receive DMA enable
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 /******************************************************************************/
<> 144:ef7eb2e8f9f7 944 /* */
<> 144:ef7eb2e8f9f7 945 /* Simple UART */
<> 144:ef7eb2e8f9f7 946 /* */
<> 144:ef7eb2e8f9f7 947 /******************************************************************************/
<> 144:ef7eb2e8f9f7 948 /***************** Bit definition for S_UART Data () register ************************/
<> 144:ef7eb2e8f9f7 949 #define S_UART_DATA (0xFFul << 0)
<> 144:ef7eb2e8f9f7 950 /***************** Bit definition for S_UART State() register ************************/
<> 144:ef7eb2e8f9f7 951 #define S_UART_STATE_TX_BUF_OVERRUN (0x01ul << 2) // TX buffer overrun, wirte 1 to clear.
<> 144:ef7eb2e8f9f7 952 #define S_UART_STATE_RX_BUF_FULL (0x01ul << 1) // RX buffer full, read only.
<> 144:ef7eb2e8f9f7 953 #define S_UART_STATE_TX_BUF_FULL (0x01ul << 0) // TX buffer full, read only.
<> 144:ef7eb2e8f9f7 954 /***************** Bit definition for S_UART Control() register ************************/
<> 144:ef7eb2e8f9f7 955 #define S_UART_CTRL_HIGH_SPEED_TEST (0x01ul << 6) // High-speed test mode for TX only.
<> 144:ef7eb2e8f9f7 956 #define S_UART_CTRL_RX_OVERRUN_EN (0x01ul << 5) // RX overrun interrupt enable.
<> 144:ef7eb2e8f9f7 957 #define S_UART_CTRL_TX_OVERRUN_EN (0x01ul << 4) // TX overrun interrupt enable.
<> 144:ef7eb2e8f9f7 958 #define S_UART_CTRL_RX_INT_EN (0x01ul << 3) // RX interrupt enable.
<> 144:ef7eb2e8f9f7 959 #define S_UART_CTRL_TX_INT_EN (0x01ul << 2) // TX interrupt enable.
<> 144:ef7eb2e8f9f7 960 #define S_UART_CTRL_RX_EN (0x01ul << 1) // RX enable.
<> 144:ef7eb2e8f9f7 961 #define S_UART_CTRL_TX_EN (0x01ul << 0) // TX enable.
<> 144:ef7eb2e8f9f7 962 /***************** Bit definition for S_UART Interrupt() register ************************/
<> 144:ef7eb2e8f9f7 963 #define S_UART_INT_RX_OVERRUN (0x01ul << 3) // RX overrun interrupt. Wirte 1 to clear
<> 144:ef7eb2e8f9f7 964 #define S_UART_INT_TX_OVERRUN (0x01ul << 2) // TX overrun interrupt. Write 1 to clear
<> 144:ef7eb2e8f9f7 965 #define S_UART_INT_RX (0x01ul << 1) // RX interrupt. Write 1 to clear
<> 144:ef7eb2e8f9f7 966 #define S_UART_INT_TX (0x01ul << 0) // TX interrupt. Write 1 to clear
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /******************************************************************************/
<> 144:ef7eb2e8f9f7 969 /* */
<> 144:ef7eb2e8f9f7 970 /* Analog Digital Register */
<> 144:ef7eb2e8f9f7 971 /* */
<> 144:ef7eb2e8f9f7 972 /******************************************************************************/
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 /*********************** Bit definition for ADC_CTR ***********************/
<> 144:ef7eb2e8f9f7 975 //#define ADC_CTR_SAMSEL_ABNORMAL (0x0ul) // Abnormal Operation
<> 144:ef7eb2e8f9f7 976 //#define ADC_CTR_SAMSEL_NORMAL (0x1ul) // Normal Operation
<> 144:ef7eb2e8f9f7 977 #define ADC_CTR_PWD_NRMOP (0x1ul) // Active Operation
<> 144:ef7eb2e8f9f7 978 #define ADC_CTR_PWD_PD (0x3ul) // Power down
<> 144:ef7eb2e8f9f7 979 /*********************** Bit definition for ADC_CHSEL ***********************/
<> 144:ef7eb2e8f9f7 980 #define ADC_CHSEL_CH0 (0x0ul) // Channel 0
<> 144:ef7eb2e8f9f7 981 #define ADC_CHSEL_CH1 (0x1ul) // Channel 1
<> 144:ef7eb2e8f9f7 982 #define ADC_CHSEL_CH2 (0x2ul) // Channel 2
<> 144:ef7eb2e8f9f7 983 #define ADC_CHSEL_CH3 (0x3ul) // Channel 3
<> 144:ef7eb2e8f9f7 984 #define ADC_CHSEL_CH4 (0x4ul) // Channel 4
<> 144:ef7eb2e8f9f7 985 #define ADC_CHSEL_CH5 (0x5ul) // Channel 5
<> 144:ef7eb2e8f9f7 986 #define ADC_CHSEL_CH6 (0x6ul) // Channel 6
<> 144:ef7eb2e8f9f7 987 #define ADC_CHSEL_CH7 (0x7ul) // Channel 7
<> 144:ef7eb2e8f9f7 988 #define ADC_CHSEL_CH15 (0xful) // LDO output(1.5V)
<> 144:ef7eb2e8f9f7 989 /*********************** Bit definition for ADC_START ***********************/
<> 144:ef7eb2e8f9f7 990 #define ADC_START_START (0x1ul) // ADC conversion start
<> 144:ef7eb2e8f9f7 991 /*********************** Bit definition for ADC_DATA ***********************/
<> 144:ef7eb2e8f9f7 992 //ToDo (Readonly)
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994 /*********************** Bit definition for ADC_INT ***********************/
<> 144:ef7eb2e8f9f7 995 #define ADC_INT_MASK_DIS (0x0ul << 1) // Interrupt disable
<> 144:ef7eb2e8f9f7 996 #define ADC_INT_MASK_ENA (0x1ul << 1) // Interrupt enable
<> 144:ef7eb2e8f9f7 997 //ToDo (Readonly)
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 /*********************** Bit definition for ADC_INTCLR ***********************/
<> 144:ef7eb2e8f9f7 1000 #define ADC_INTCLEAR (0x1ul) // ADC Interrupt clear
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
<> 144:ef7eb2e8f9f7 1003 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1006 /* */
<> 144:ef7eb2e8f9f7 1007 /* Dual Timer */
<> 144:ef7eb2e8f9f7 1008 /* */
<> 144:ef7eb2e8f9f7 1009 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 /*********************** Bit definition for dualtimer ***********************/
<> 144:ef7eb2e8f9f7 1012 #define DUALTIMER_TimerControl_TimerDIsable 0x0ul
<> 144:ef7eb2e8f9f7 1013 #define DUALTIMER_TimerControl_TimerEnable 0x1ul
<> 144:ef7eb2e8f9f7 1014 #define DUALTIMER_TimerControl_TimerEnable_Pos 7
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 #define DUALTIMER_TimerControl_FreeRunning 0x0ul
<> 144:ef7eb2e8f9f7 1017 #define DUALTIMER_TimerControl_Periodic 0x1ul
<> 144:ef7eb2e8f9f7 1018 #define DUALTIMER_TimerControl_TimerMode_Pos 6
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 #define DUALTIMER_TimerControl_IntDisable 0x0ul
<> 144:ef7eb2e8f9f7 1021 #define DUALTIMER_TimerControl_IntEnable 0x1ul
<> 144:ef7eb2e8f9f7 1022 #define DUALTIMER_TimerControl_IntEnable_Pos 5
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 #define DUALTIMER_TimerControl_Pre_1 0x0ul
<> 144:ef7eb2e8f9f7 1025 #define DUALTIMER_TimerControl_Pre_16 0x1ul
<> 144:ef7eb2e8f9f7 1026 #define DUALTIMER_TimerControl_Pre_256 0x2ul
<> 144:ef7eb2e8f9f7 1027 #define DUALTIMER_TimerControl_Pre_Pos 2
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 #define DUALTIMER_TimerControl_Size_16 0x0ul
<> 144:ef7eb2e8f9f7 1030 #define DUALTIMER_TimerControl_Size_32 0x1ul
<> 144:ef7eb2e8f9f7 1031 #define DUALTIMER_TimerControl_Size_Pos 1
<> 144:ef7eb2e8f9f7 1032
<> 144:ef7eb2e8f9f7 1033 #define DUALTIMER_TimerControl_Wrapping 0x0ul
<> 144:ef7eb2e8f9f7 1034 #define DUALTIMER_TimerControl_OneShot 0x1ul
<> 144:ef7eb2e8f9f7 1035 #define DUALTIMER_TimerControl_OneShot_Pos 0
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1038 /* */
<> 144:ef7eb2e8f9f7 1039 /* External Interrupt */
<> 144:ef7eb2e8f9f7 1040 /* */
<> 144:ef7eb2e8f9f7 1041 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /**************** Bit definition for Px_IER **************************/
<> 144:ef7eb2e8f9f7 1044 #define EXTI_Px_INTPOR_RISING_EDGE (0x00ul << 0)
<> 144:ef7eb2e8f9f7 1045 #define EXTI_Px_INTPOR_FALLING_EDGE (0x01ul << 0)
<> 144:ef7eb2e8f9f7 1046 #define EXTI_Px_INTEN_DISABLE (0x00ul << 1)
<> 144:ef7eb2e8f9f7 1047 #define EXTI_Px_INTEN_ENABLE (0x01ul << 1)
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1050 /* */
<> 144:ef7eb2e8f9f7 1051 /* GPIO */
<> 144:ef7eb2e8f9f7 1052 /* */
<> 144:ef7eb2e8f9f7 1053 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 /**************** Bit definition for Px_AFSR **************************/
<> 144:ef7eb2e8f9f7 1056 #define Px_AFSR_AF0 (0x00ul)
<> 144:ef7eb2e8f9f7 1057 #define Px_AFSR_AF1 (0x01ul)
<> 144:ef7eb2e8f9f7 1058 #define Px_AFSR_AF2 (0x02ul)
<> 144:ef7eb2e8f9f7 1059 #define Px_AFSR_AF3 (0x03ul)
<> 144:ef7eb2e8f9f7 1060 /**************** Bit definition for Px_PCR **************************/
<> 144:ef7eb2e8f9f7 1061 #define Px_PCR_PUPD_DOWN (0x01ul << 0) // Pull Down
<> 144:ef7eb2e8f9f7 1062 #define Px_PCR_PUPD_UP (0x01ul << 1) // Pull Up
<> 144:ef7eb2e8f9f7 1063 #define Px_PCR_DS_HIGH (0x01ul << 2) // High Driving
<> 144:ef7eb2e8f9f7 1064 #define Px_PCR_OD (0x01ul << 3) // Open Drain
<> 144:ef7eb2e8f9f7 1065 #define Px_PCR_IE (0x01ul << 5) // Input Buffer Enable
<> 144:ef7eb2e8f9f7 1066 #define Px_PCR_CS_SUMMIT (0x01ul << 6) // Use Summit Trigger Input Buffer
<> 144:ef7eb2e8f9f7 1067
<> 144:ef7eb2e8f9f7 1068 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1069 /* */
<> 144:ef7eb2e8f9f7 1070 /* I2C */
<> 144:ef7eb2e8f9f7 1071 /* */
<> 144:ef7eb2e8f9f7 1072 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 /**************** Bit definition for I2C_CTR **************************/
<> 144:ef7eb2e8f9f7 1075 #define I2C_CTR_COREEN (0x01ul << 7 ) // 0x80
<> 144:ef7eb2e8f9f7 1076 #define I2C_CTR_INTEREN (0x01ul << 6 ) // 0x40
<> 144:ef7eb2e8f9f7 1077 #define I2C_CTR_MODE (0x01ul << 5 ) // 0x20
<> 144:ef7eb2e8f9f7 1078 #define I2C_CTR_ADDR10 (0x01ul << 4 ) // 0x10
<> 144:ef7eb2e8f9f7 1079 #define I2C_CTR_CTRRWN (0x01ul << 3 ) // 0x08
<> 144:ef7eb2e8f9f7 1080 #define I2C_CTR_CTEN (0x01ul << 2 ) // 0x04
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 /**************** Bit definition for I2C_CMDR **************************/
<> 144:ef7eb2e8f9f7 1083 #define I2C_CMDR_STA (0x01ul << 7 ) // 0x80
<> 144:ef7eb2e8f9f7 1084 #define I2C_CMDR_STO (0x01ul << 6 ) // 0x40
<> 144:ef7eb2e8f9f7 1085 #define I2C_CMDR_ACK (0x01ul << 5 ) // 0x20
<> 144:ef7eb2e8f9f7 1086 #define I2C_CMDR_RESTA (0x01ul << 4 ) // 0x10
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 /**************** Bit definition for I2C_ISCR **************************/
<> 144:ef7eb2e8f9f7 1089 #define I2C_ISCR_RST (0x01ul << 1) // 0x01
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 /**************** Bit definition for I2C_SR **************************/
<> 144:ef7eb2e8f9f7 1092 #define I2C_SR_TX (0x01ul << 9 ) // 0x200
<> 144:ef7eb2e8f9f7 1093 #define I2C_SR_RX (0x01ul << 8 ) // 0x100
<> 144:ef7eb2e8f9f7 1094 #define I2C_SR_ACKT (0x01ul << 7 ) // 0x080
<> 144:ef7eb2e8f9f7 1095 #define I2C_SR_BT (0x01ul << 6 ) // 0x040
<> 144:ef7eb2e8f9f7 1096 #define I2C_SR_SA (0x01ul << 5 ) // 0x020
<> 144:ef7eb2e8f9f7 1097 #define I2C_SR_SB (0x01ul << 4 ) // 0x010
<> 144:ef7eb2e8f9f7 1098 #define I2C_SR_AL (0x01ul << 3 ) // 0x008
<> 144:ef7eb2e8f9f7 1099 #define I2C_SR_TO (0x01ul << 2 ) // 0x004
<> 144:ef7eb2e8f9f7 1100 #define I2C_SR_SRW (0x01ul << 1 ) // 0x002
<> 144:ef7eb2e8f9f7 1101 #define I2C_SR_ACKR (0x01ul << 0 ) // 0x001
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /**************** Bit definition for I2C_ISR **************************/
<> 144:ef7eb2e8f9f7 1104 #define I2C_ISR_STAE (0x01ul << 4 ) // 0x010
<> 144:ef7eb2e8f9f7 1105 #define I2C_ISR_STOE (0x01ul << 3 ) // 0x008
<> 144:ef7eb2e8f9f7 1106 #define I2C_ISR_TOE (0x01ul << 2 ) // 0x004
<> 144:ef7eb2e8f9f7 1107 #define I2C_ISR_ACK_RXE (0x01ul << 1 ) // 0x002
<> 144:ef7eb2e8f9f7 1108 #define I2C_ISR_ACK_TXE (0x01ul << 0 ) // 0x001
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 /**************** Bit definition for I2C_ISMR **************************/
<> 144:ef7eb2e8f9f7 1111 #define I2C_ISR_STAEM (0x01ul << 4 ) // 0x010
<> 144:ef7eb2e8f9f7 1112 #define I2C_ISR_STOEM (0x01ul << 3 ) // 0x008
<> 144:ef7eb2e8f9f7 1113 #define I2C_ISR_TOEM (0x01ul << 2 ) // 0x004
<> 144:ef7eb2e8f9f7 1114 #define I2C_ISR_ACK_RXEM (0x01ul << 1 ) // 0x002
<> 144:ef7eb2e8f9f7 1115 #define I2C_ISR_ACK_TXEM (0x01ul << 0 ) // 0x001
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1118 /* */
<> 144:ef7eb2e8f9f7 1119 /* PWM */
<> 144:ef7eb2e8f9f7 1120 /* */
<> 144:ef7eb2e8f9f7 1121 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1122
<> 144:ef7eb2e8f9f7 1123 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1124 /* */
<> 144:ef7eb2e8f9f7 1125 /* Random number generator Register */
<> 144:ef7eb2e8f9f7 1126 /* */
<> 144:ef7eb2e8f9f7 1127 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 /*********************** Bit definition for RNG_RUN ***********************/
<> 144:ef7eb2e8f9f7 1130 #define RNG_RUN_STOP (0x0ul) // STOP RNG shift register
<> 144:ef7eb2e8f9f7 1131 #define RNG_RUN_RUN (0x1ul) // RUN RNG shift register
<> 144:ef7eb2e8f9f7 1132 /*********************** Bit definition for RNG_SEED ***********************/
<> 144:ef7eb2e8f9f7 1133 //ToDo
<> 144:ef7eb2e8f9f7 1134
<> 144:ef7eb2e8f9f7 1135 /*********************** Bit definition for RNG_CLKSEL ***********************/
<> 144:ef7eb2e8f9f7 1136 #define RNG_CLKSEL_RNGCLK (0x0ul) // RNGCLK is source clock for rng shift register
<> 144:ef7eb2e8f9f7 1137 #define RNG_CLKSEL_APBCLK (0x1ul) // APBCLK is source clock for rng shift register
<> 144:ef7eb2e8f9f7 1138 /*********************** Bit definition for RNG_ENABLE ***********************/
<> 144:ef7eb2e8f9f7 1139 #define RNG_MANUAL_DISABLE (0x0ul) // RNG disble
<> 144:ef7eb2e8f9f7 1140 #define RNG_MANUAL_ENABLE (0x1ul) // RNG enable
<> 144:ef7eb2e8f9f7 1141 /*********************** Bit definition for RNG_RN ***********************/
<> 144:ef7eb2e8f9f7 1142 //ToDo
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 /*********************** Bit definition for RNG_POLY ***********************/
<> 144:ef7eb2e8f9f7 1145 //ToDo
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 typedef enum
<> 144:ef7eb2e8f9f7 1150 {
<> 144:ef7eb2e8f9f7 1151 PAD_PA = 0,
<> 144:ef7eb2e8f9f7 1152 PAD_PB,
<> 144:ef7eb2e8f9f7 1153 PAD_PC,
<> 144:ef7eb2e8f9f7 1154 PAD_PD
<> 144:ef7eb2e8f9f7 1155 }PAD_Type;
<> 144:ef7eb2e8f9f7 1156
<> 144:ef7eb2e8f9f7 1157 typedef enum
<> 144:ef7eb2e8f9f7 1158 {
<> 144:ef7eb2e8f9f7 1159 PAD_AF0 = Px_AFSR_AF0,
<> 144:ef7eb2e8f9f7 1160 PAD_AF1 = Px_AFSR_AF1,
<> 144:ef7eb2e8f9f7 1161 PAD_AF2 = Px_AFSR_AF2,
<> 144:ef7eb2e8f9f7 1162 PAD_AF3 = Px_AFSR_AF3
<> 144:ef7eb2e8f9f7 1163 }PAD_AF_TypeDef;
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 #if !defined (USE_HAL_DRIVER)
<> 144:ef7eb2e8f9f7 1167 #define USE_HAL_DRIVER
<> 144:ef7eb2e8f9f7 1168 #endif /* USE_HAL_DRIVER */
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172 #if defined (USE_HAL_DRIVER)
<> 144:ef7eb2e8f9f7 1173 // #include "system_W7500x.h"
<> 144:ef7eb2e8f9f7 1174 // #include "W7500x_conf.h"
<> 144:ef7eb2e8f9f7 1175 #endif
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 #ifdef USE_FULL_ASSERT
<> 144:ef7eb2e8f9f7 1178 #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__))
<> 144:ef7eb2e8f9f7 1179 #else
<> 144:ef7eb2e8f9f7 1180 #define assert_param(expr) ((void)0)
<> 144:ef7eb2e8f9f7 1181 #endif /* USE_FULL_ASSERT */
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1184 }
<> 144:ef7eb2e8f9f7 1185 #endif
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 #endif /* W7500x_H */
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190
<> 144:ef7eb2e8f9f7 1191 /************************ (C) COPYRIGHT Wiznet *****END OF FILE****/