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targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

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<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file gpio_map.h
<> 149:156823d33999 4 * @brief GPIO HW register map
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 2115 $
<> 149:156823d33999 8 * $Date: 2013-07-17 18:08:17 +0530 (Wed, 17 Jul 2013) $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup gpio
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 * <p>
<> 149:156823d33999 31 * GPIO HW register map description
<> 149:156823d33999 32 * </p>
<> 149:156823d33999 33 *
<> 149:156823d33999 34 * <h1> Reference document(s) </h1>
<> 149:156823d33999 35 * <p>
<> 149:156823d33999 36 * <a href="../pdf/IPC7203_GPIO_APB_DS_v1P1.pdf" target="_blank">
<> 149:156823d33999 37 * Reference document: IPC7203 APB GPIO Design Specification v1.2</a>
<> 149:156823d33999 38 * </p>
<> 149:156823d33999 39 */
<> 149:156823d33999 40
<> 149:156823d33999 41 #ifndef GPIO_MAP_H_
<> 149:156823d33999 42 #define GPIO_MAP_H_
<> 149:156823d33999 43
<> 149:156823d33999 44 #include "architecture.h"
<> 149:156823d33999 45
<> 149:156823d33999 46 /** Structure overlay for GPIO control registers, see memory_map.h
<> 149:156823d33999 47 * For most registers, bit lockations match GPIO numbers.*/
<> 149:156823d33999 48 typedef struct {
<> 149:156823d33999 49 __IO uint32_t R_STATE_W_SET; /**< Read synchronized input / Write ones to bits to set corresponding output IO's*/
<> 149:156823d33999 50 __IO uint32_t R_IRQ_W_CLEAR; /**< Read state of irq / Write ones to bits to clear corresponging output IO's */
<> 149:156823d33999 51 __IO uint32_t W_OUT; /**< Write ones to set direction to output */
<> 149:156823d33999 52 __IO uint32_t W_IN; /**< Write ones to set direction to input */
<> 149:156823d33999 53 __IO uint32_t IRQ_ENABLE_SET; /**< Read active high irq enable / Write ones to enable irq */
<> 149:156823d33999 54 __IO uint32_t IRQ_ENABLE_CLEAR; /**< Read active high irq enable / Write ones to disable irq */
<> 149:156823d33999 55 __IO uint32_t IRQ_EDGE; /**< Read irq configuration (edge or level) / Write ones to set irq to edge-sensitive */
<> 149:156823d33999 56 __IO uint32_t IRQ_LEVEL; /**< Read irq configuration (edge or level) / Write ones to set irq to level-sensitive */
<> 149:156823d33999 57 __IO uint32_t IRQ_POLARITY_SET; /**< Read irq polarity / Write ones to set irq to active high or rising edge */
<> 149:156823d33999 58 __IO uint32_t IRQ_POLARITY_CLEAR; /**< Read irq polarity / Write ones to set interrupts to active low or falling edge */
<> 149:156823d33999 59 __IO uint32_t ANYEDGE_SET; /**< Read irq anyedge configuration / Write ones to override irq edge selection & irq on any edge */
<> 149:156823d33999 60 __IO uint32_t ANYEDGE_CLEAR; /**< Read irq anyedge configuration / Write ones to clear edge selection override */
<> 149:156823d33999 61 __IO uint32_t IRQ_CLEAR; /**< Write ones to clear edge-sensitive irq */
<> 149:156823d33999 62 __IO uint32_t CONTROL; /**< Controls loopback/normal mode selection */
<> 149:156823d33999 63 } GpioReg_t, *GpioReg_pt;
<> 149:156823d33999 64
<> 149:156823d33999 65 #endif /* GPIO_MAP_H_ */