ethmac.h

00001 /******************************************************************
00002  *****                                                        *****
00003  *****  Name: cs8900.h                                        *****
00004  *****  Ver.: 1.0                                             *****
00005  *****  Date: 07/05/2001                                      *****
00006  *****  Auth: Andreas Dannenberg                              *****
00007  *****        HTWK Leipzig                                    *****
00008  *****        university of applied sciences                  *****
00009  *****        Germany                                         *****
00010  *****        adannenb@et.htwk-leipzig.de                     *****
00011  *****  Func: header-file for cs8900.c                        *****
00012  *****                                                        *****
00013  ******************************************************************/
00014 
00015 // Modifications by Code Red Technologies for NXP LPC1768
00016 // Filename changed to ethmac.h as no longer for cs8900
00017 
00018 // CodeRed - update for new header filename
00019 //#ifndef __CS8900_H
00020 //#define __CS8900_H
00021 #ifndef __ETHMAC_H
00022 #define __ETHMAC_H
00023 
00024 #define MYMAC_1              1                   // our ethernet (MAC) address
00025 #define MYMAC_2              2                   // (MUST be unique in LAN!)
00026 #define MYMAC_3              3
00027 #define MYMAC_4              4
00028 #define MYMAC_5              5
00029 #define MYMAC_6              6
00030 
00031 
00032 // CodeRed - commented out original CS8900 defines
00033 /*
00034 #define IOR                  BIT6                // CS8900's ISA-bus interface pins
00035 #define IOW                  BIT7
00036 
00037 // definitions for Crystal CS8900 ethernet-controller
00038 // based on linux-header by Russel Nelson
00039 
00040 #define PP_ChipID            0x0000              // offset 0h -> Corp-ID
00041                                                  // offset 2h -> Model/Product Number
00042                                                  // offset 3h -> Chip Revision Number
00043 
00044 #define PP_ISAIOB            0x0020              // IO base address
00045 #define PP_CS8900_ISAINT     0x0022              // ISA interrupt select
00046 #define PP_CS8900_ISADMA     0x0024              // ISA Rec DMA channel
00047 #define PP_ISASOF            0x0026              // ISA DMA offset
00048 #define PP_DmaFrameCnt       0x0028              // ISA DMA Frame count
00049 #define PP_DmaByteCnt        0x002A              // ISA DMA Byte count
00050 #define PP_CS8900_ISAMemB    0x002C              // Memory base
00051 #define PP_ISABootBase       0x0030              // Boot Prom base
00052 #define PP_ISABootMask       0x0034              // Boot Prom Mask
00053 
00054 // EEPROM data and command registers
00055 #define PP_EECMD             0x0040              // NVR Interface Command register
00056 #define PP_EEData            0x0042              // NVR Interface Data Register
00057 
00058 // Configuration and control registers
00059 #define PP_RxCFG             0x0102              // Rx Bus config
00060 #define PP_RxCTL             0x0104              // Receive Control Register
00061 #define PP_TxCFG             0x0106              // Transmit Config Register
00062 #define PP_TxCMD             0x0108              // Transmit Command Register
00063 #define PP_BufCFG            0x010A              // Bus configuration Register
00064 #define PP_LineCTL           0x0112              // Line Config Register
00065 #define PP_SelfCTL           0x0114              // Self Command Register
00066 #define PP_BusCTL            0x0116              // ISA bus control Register
00067 #define PP_TestCTL           0x0118              // Test Register
00068 
00069 // Status and Event Registers
00070 #define PP_ISQ               0x0120              // Interrupt Status
00071 #define PP_RxEvent           0x0124              // Rx Event Register
00072 #define PP_TxEvent           0x0128              // Tx Event Register
00073 #define PP_BufEvent          0x012C              // Bus Event Register
00074 #define PP_RxMiss            0x0130              // Receive Miss Count
00075 #define PP_TxCol             0x0132              // Transmit Collision Count
00076 #define PP_LineST            0x0134              // Line State Register
00077 #define PP_SelfST            0x0136              // Self State register
00078 #define PP_BusST             0x0138              // Bus Status
00079 #define PP_TDR               0x013C              // Time Domain Reflectometry
00080 
00081 // Initiate Transmit Registers
00082 #define PP_TxCommand         0x0144              // Tx Command
00083 #define PP_TxLength          0x0146              // Tx Length
00084 
00085 // Adress Filter Registers
00086 #define PP_LAF               0x0150              // Hash Table
00087 #define PP_IA                0x0158              // Physical Address Register
00088 
00089 // Frame Location
00090 #define PP_RxStatus          0x0400              // Receive start of frame
00091 #define PP_RxLength          0x0402              // Receive Length of frame
00092 #define PP_RxFrame           0x0404              // Receive frame pointer
00093 #define PP_TxFrame           0x0A00              // Transmit frame pointer
00094 
00095 // Primary I/O Base Address. If no I/O base is supplied by the user, then this
00096 // can be used as the default I/O base to access the PacketPage Area.
00097 #define DEFAULTIOBASE        0x0300
00098 
00099 // PP_RxCFG - Receive  Configuration and Interrupt Mask bit definition - Read/write
00100 #define SKIP_1               0x0040
00101 #define RX_STREAM_ENBL       0x0080
00102 #define RX_OK_ENBL           0x0100
00103 #define RX_DMA_ONLY          0x0200
00104 #define AUTO_RX_DMA          0x0400
00105 #define BUFFER_CRC           0x0800
00106 #define RX_CRC_ERROR_ENBL    0x1000
00107 #define RX_RUNT_ENBL         0x2000
00108 #define RX_EXTRA_DATA_ENBL   0x4000
00109 
00110 // PP_RxCTL - Receive Control bit definition - Read/write
00111 #define RX_IA_HASH_ACCEPT    0x0040
00112 #define RX_PROM_ACCEPT       0x0080
00113 #define RX_OK_ACCEPT         0x0100
00114 #define RX_MULTCAST_ACCEPT   0x0200
00115 #define RX_IA_ACCEPT         0x0400
00116 #define RX_BROADCAST_ACCEPT  0x0800
00117 #define RX_BAD_CRC_ACCEPT    0x1000
00118 #define RX_RUNT_ACCEPT       0x2000
00119 #define RX_EXTRA_DATA_ACCEPT 0x4000
00120 
00121 // PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write
00122 #define TX_LOST_CRS_ENBL     0x0040
00123 #define TX_SQE_ERROR_ENBL    0x0080
00124 #define TX_OK_ENBL           0x0100
00125 #define TX_LATE_COL_ENBL     0x0200
00126 #define TX_JBR_ENBL          0x0400
00127 #define TX_ANY_COL_ENBL      0x0800
00128 #define TX_16_COL_ENBL       0x8000
00129 
00130 // PP_TxCMD - Transmit Command bit definition - Read-only and
00131 // PP_TxCommand - Write-only
00132 #define TX_START_5_BYTES     0x0000
00133 #define TX_START_381_BYTES   0x0040
00134 #define TX_START_1021_BYTES  0x0080
00135 #define TX_START_ALL_BYTES   0x00C0
00136 #define TX_FORCE             0x0100
00137 #define TX_ONE_COL           0x0200
00138 #define TX_NO_CRC            0x1000
00139 #define TX_RUNT              0x2000
00140 
00141 // PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write
00142 #define GENERATE_SW_INTERRUPT      0x0040
00143 #define RX_DMA_ENBL                0x0080
00144 #define READY_FOR_TX_ENBL          0x0100
00145 #define TX_UNDERRUN_ENBL           0x0200
00146 #define RX_MISS_ENBL               0x0400
00147 #define RX_128_BYTE_ENBL           0x0800
00148 #define TX_COL_COUNT_OVRFLOW_ENBL  0x1000
00149 #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
00150 #define RX_DEST_MATCH_ENBL         0x8000
00151 
00152 // PP_LineCTL - Line Control bit definition - Read/write
00153 #define SERIAL_RX_ON         0x0040
00154 #define SERIAL_TX_ON         0x0080
00155 #define AUI_ONLY             0x0100
00156 #define AUTO_AUI_10BASET     0x0200
00157 #define MODIFIED_BACKOFF     0x0800
00158 #define NO_AUTO_POLARITY     0x1000
00159 #define TWO_PART_DEFDIS      0x2000
00160 #define LOW_RX_SQUELCH       0x4000
00161 
00162 // PP_SelfCTL - Software Self Control bit definition - Read/write
00163 #define POWER_ON_RESET       0x0040
00164 #define SW_STOP              0x0100
00165 #define SLEEP_ON             0x0200
00166 #define AUTO_WAKEUP          0x0400
00167 #define HCB0_ENBL            0x1000
00168 #define HCB1_ENBL            0x2000
00169 #define HCB0                 0x4000
00170 #define HCB1                 0x8000
00171 
00172 // PP_BusCTL - ISA Bus Control bit definition - Read/write
00173 #define RESET_RX_DMA         0x0040
00174 #define MEMORY_ON            0x0400
00175 #define DMA_BURST_MODE       0x0800
00176 #define IO_CHANNEL_READY_ON  0x1000
00177 #define RX_DMA_SIZE_64K      0x2000
00178 #define ENABLE_IRQ           0x8000
00179 
00180 // PP_TestCTL - Test Control bit definition - Read/write
00181 #define LINK_OFF             0x0080
00182 #define ENDEC_LOOPBACK       0x0200
00183 #define AUI_LOOPBACK         0x0400
00184 #define BACKOFF_OFF          0x0800
00185 #define FDX_8900             0x4000
00186 
00187 // PP_RxEvent - Receive Event Bit definition - Read-only
00188 #define RX_IA_HASHED         0x0040
00189 #define RX_DRIBBLE           0x0080
00190 #define RX_OK                0x0100
00191 #define RX_HASHED            0x0200
00192 #define RX_IA                0x0400
00193 #define RX_BROADCAST         0x0800
00194 #define RX_CRC_ERROR         0x1000
00195 #define RX_RUNT              0x2000
00196 #define RX_EXTRA_DATA        0x4000
00197 #define HASH_INDEX_MASK      0xFC00              // Hash-Table Index Mask (6 Bit)
00198 
00199 // PP_TxEvent - Transmit Event Bit definition - Read-only
00200 #define TX_LOST_CRS          0x0040
00201 #define TX_SQE_ERROR         0x0080
00202 #define TX_OK                0x0100
00203 #define TX_LATE_COL          0x0200
00204 #define TX_JBR               0x0400
00205 #define TX_16_COL            0x8000
00206 #define TX_COL_COUNT_MASK    0x7800
00207 
00208 // PP_BufEvent - Buffer Event Bit definition - Read-only
00209 #define SW_INTERRUPT         0x0040
00210 #define RX_DMA               0x0080
00211 #define READY_FOR_TX         0x0100
00212 #define TX_UNDERRUN          0x0200
00213 #define RX_MISS              0x0400
00214 #define RX_128_BYTE          0x0800
00215 #define TX_COL_OVRFLW        0x1000
00216 #define RX_MISS_OVRFLW       0x2000
00217 #define RX_DEST_MATCH        0x8000
00218 
00219 // PP_LineST - Ethernet Line Status bit definition - Read-only
00220 #define LINK_OK              0x0080
00221 #define AUI_ON               0x0100
00222 #define TENBASET_ON          0x0200
00223 #define POLARITY_OK          0x1000
00224 #define CRS_OK               0x4000
00225 
00226 // PP_SelfST - Chip Software Status bit definition
00227 #define ACTIVE_33V           0x0040
00228 #define INIT_DONE            0x0080
00229 #define SI_BUSY              0x0100
00230 #define EEPROM_PRESENT       0x0200
00231 #define EEPROM_OK            0x0400
00232 #define EL_PRESENT           0x0800
00233 #define EE_SIZE_64           0x1000
00234 
00235 // PP_BusST - ISA Bus Status bit definition
00236 #define TX_BID_ERROR         0x0080
00237 #define READY_FOR_TX_NOW     0x0100
00238 
00239 // The following block defines the ISQ event types
00240 #define ISQ_RX_EVENT         0x0004
00241 #define ISQ_TX_EVENT         0x0008
00242 #define ISQ_BUFFER_EVENT     0x000C
00243 #define ISQ_RX_MISS_EVENT    0x0010
00244 #define ISQ_TX_COL_EVENT     0x0012
00245 
00246 #define ISQ_EVENT_MASK       0x003F              // ISQ mask to find out type of event
00247 
00248 // Ports for I/O-Mode
00249 #define RX_FRAME_PORT        0x0000
00250 #define TX_FRAME_PORT        0x0000
00251 #define TX_CMD_PORT          0x0004
00252 #define TX_LEN_PORT          0x0006
00253 #define ISQ_PORT             0x0008
00254 #define ADD_PORT             0x000A
00255 #define DATA_PORT            0x000C
00256 
00257 #define AUTOINCREMENT        0x8000              // Bit mask to set Bit-15 for autoincrement
00258 
00259 // EEProm Commands
00260 #define EEPROM_WRITE_EN      0x00F0
00261 #define EEPROM_WRITE_DIS     0x0000
00262 #define EEPROM_WRITE_CMD     0x0100
00263 #define EEPROM_READ_CMD      0x0200
00264 
00265 // Receive Header of each packet in receive area of memory for DMA-Mode
00266 #define RBUF_EVENT_LOW       0x0000              // Low byte of RxEvent
00267 #define RBUF_EVENT_HIGH      0x0001              // High byte of RxEvent
00268 #define RBUF_LEN_LOW         0x0002              // Length of received data - low byte
00269 #define RBUF_LEN_HI          0x0003              // Length of received data - high byte
00270 #define RBUF_HEAD_LEN        0x0004              // Length of this header
00271 
00272 // CodeRed - end of original CS8900 defines
00273 */
00274 
00275 // *******
00276 // CodeRed -  defines for LPC1768 ethernet
00277 // *******
00278 
00279 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
00280 #define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */
00281 #define NUM_TX_FRAG         2           /* Num.of TX Fragments 3*1536= 4.6kB */
00282 #define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
00283 
00284 #define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
00285 
00286 /* EMAC variables located in AHB SRAM bank 1*/
00287 // Below is base address for first silicon
00288 //#define RX_DESC_BASE        0x20004000
00289 // Below is base address for production silicon
00290 #define RX_DESC_BASE        0x2007c000
00291 #define RX_STAT_BASE        (RX_DESC_BASE + NUM_RX_FRAG*8)
00292 #define TX_DESC_BASE        (RX_STAT_BASE + NUM_RX_FRAG*8)
00293 #define TX_STAT_BASE        (TX_DESC_BASE + NUM_TX_FRAG*8)
00294 #define RX_BUF_BASE         (TX_STAT_BASE + NUM_TX_FRAG*4)
00295 #define TX_BUF_BASE         (RX_BUF_BASE  + NUM_RX_FRAG*ETH_FRAG_SIZE)
00296 
00297 /* RX and TX descriptor and status definitions. */
00298 #define RX_DESC_PACKET(i)   (*(unsigned int *)(RX_DESC_BASE   + 8*i))
00299 #define RX_DESC_CTRL(i)     (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
00300 #define RX_STAT_INFO(i)     (*(unsigned int *)(RX_STAT_BASE   + 8*i))
00301 #define RX_STAT_HASHCRC(i)  (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
00302 #define TX_DESC_PACKET(i)   (*(unsigned int *)(TX_DESC_BASE   + 8*i))
00303 #define TX_DESC_CTRL(i)     (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
00304 #define TX_STAT_INFO(i)     (*(unsigned int *)(TX_STAT_BASE   + 4*i))
00305 #define RX_BUF(i)           (RX_BUF_BASE + ETH_FRAG_SIZE*i)
00306 #define TX_BUF(i)           (TX_BUF_BASE + ETH_FRAG_SIZE*i)
00307 
00308 /* MAC Configuration Register 1 */
00309 #define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
00310 #define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
00311 #define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
00312 #define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
00313 #define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
00314 #define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
00315 #define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
00316 #define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
00317 #define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
00318 #define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
00319 #define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
00320 
00321 /* MAC Configuration Register 2 */
00322 #define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
00323 #define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
00324 #define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
00325 #define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
00326 #define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
00327 #define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
00328 #define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
00329 #define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
00330 #define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
00331 #define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
00332 #define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
00333 #define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
00334 #define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
00335 
00336 /* Back-to-Back Inter-Packet-Gap Register */
00337 #define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
00338 #define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
00339 
00340 /* Non Back-to-Back Inter-Packet-Gap Register */
00341 #define IPGR_DEF            0x00000012  /* Recommended value                 */
00342 
00343 /* Collision Window/Retry Register */
00344 #define CLRT_DEF            0x0000370F  /* Default value                     */
00345 
00346 /* PHY Support Register */
00347 #define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
00348 
00349 /* Test Register */
00350 #define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
00351 #define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
00352 #define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
00353 
00354 /* MII Management Configuration Register */
00355 #define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
00356 #define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
00357 #define MCFG_CLK_SEL        0x0000001C  /* Clock Select Mask                 */
00358 #define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
00359 
00360 /* MII Management Command Register */
00361 #define MCMD_READ           0x00000001  /* MII Read                          */
00362 #define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
00363 
00364 #define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
00365 #define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
00366 
00367 /* MII Management Address Register */
00368 #define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
00369 #define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
00370 
00371 /* MII Management Indicators Register */
00372 #define MIND_BUSY           0x00000001  /* MII is Busy                       */
00373 #define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
00374 #define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
00375 #define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
00376 
00377 /* Command Register */
00378 #define CR_RX_EN            0x00000001  /* Enable Receive                    */
00379 #define CR_TX_EN            0x00000002  /* Enable Transmit                   */
00380 #define CR_REG_RES          0x00000008  /* Reset Host Registers              */
00381 #define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
00382 #define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
00383 #define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
00384 #define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
00385 #define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
00386 #define CR_RMII             0x00000200  /* Reduced MII Interface             */
00387 #define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
00388 
00389 /* Status Register */
00390 #define SR_RX_EN            0x00000001  /* Enable Receive                    */
00391 #define SR_TX_EN            0x00000002  /* Enable Transmit                   */
00392 
00393 /* Transmit Status Vector 0 Register */
00394 #define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
00395 #define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
00396 #define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
00397 #define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
00398 #define TSV0_MCAST          0x00000010  /* Multicast Destination             */
00399 #define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
00400 #define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
00401 #define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
00402 #define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
00403 #define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
00404 #define TSV0_GIANT          0x00000400  /* Giant Frame                       */
00405 #define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
00406 #define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
00407 #define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
00408 #define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
00409 #define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
00410 #define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
00411 
00412 /* Transmit Status Vector 1 Register */
00413 #define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
00414 #define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
00415 
00416 /* Receive Status Vector Register */
00417 #define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
00418 #define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
00419 #define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
00420 #define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
00421 #define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
00422 #define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
00423 #define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
00424 #define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
00425 #define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
00426 #define RSV_MCAST           0x01000000  /* Multicast Frame                   */
00427 #define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
00428 #define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
00429 #define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
00430 #define RSV_PAUSE           0x10000000  /* Pause Frame                       */
00431 #define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
00432 #define RSV_VLAN            0x40000000  /* VLAN Frame                        */
00433 
00434 /* Flow Control Counter Register */
00435 #define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
00436 #define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
00437 
00438 /* Flow Control Status Register */
00439 #define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
00440 
00441 /* Receive Filter Control Register */
00442 #define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
00443 #define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
00444 #define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
00445 #define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
00446 #define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
00447 #define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
00448 #define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
00449 #define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
00450 
00451 /* Receive Filter WoL Status/Clear Registers */
00452 #define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
00453 #define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
00454 #define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
00455 #define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
00456 #define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
00457 #define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
00458 #define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
00459 #define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
00460 
00461 /* Interrupt Status/Enable/Clear/Set Registers */
00462 #define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
00463 #define INT_RX_ERR          0x00000002  /* Receive Error                     */
00464 #define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
00465 #define INT_RX_DONE         0x00000008  /* Receive Done                      */
00466 #define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
00467 #define INT_TX_ERR          0x00000020  /* Transmit Error                    */
00468 #define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
00469 #define INT_TX_DONE         0x00000080  /* Transmit Done                     */
00470 #define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
00471 #define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
00472 
00473 /* Power Down Register */
00474 #define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
00475 
00476 /* RX Descriptor Control Word */
00477 #define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
00478 #define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
00479 
00480 /* RX Status Hash CRC Word */
00481 #define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
00482 #define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
00483 
00484 /* RX Status Information Word */
00485 #define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
00486 #define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
00487 #define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
00488 #define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
00489 #define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
00490 #define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
00491 #define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
00492 #define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
00493 #define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
00494 #define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
00495 #define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
00496 #define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
00497 #define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
00498 #define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
00499 #define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
00500 
00501 #define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | \
00502                             RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
00503 
00504 /* TX Descriptor Control Word */
00505 #define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
00506 #define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
00507 #define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
00508 #define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
00509 #define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
00510 #define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
00511 #define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
00512 
00513 /* TX Status Information Word */
00514 #define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
00515 #define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
00516 #define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
00517 #define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
00518 #define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
00519 #define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
00520 #define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
00521 #define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
00522 
00523 /* ENET Device Revision ID */
00524 #define OLD_EMAC_MODULE_ID  0x39022000  /* Rev. ID for first rev '-'         */
00525 
00526 /* DP83848C PHY Registers */
00527 #define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
00528 #define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
00529 #define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
00530 #define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
00531 #define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
00532 #define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
00533 #define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
00534 #define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
00535 
00536 /* PHY Extended Registers */
00537 #define PHY_REG_STS         0x10        /* Status Register                   */
00538 #define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */
00539 #define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */
00540 #define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */
00541 #define PHY_REG_RECR        0x15        /* Receive Error Counter             */
00542 #define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */
00543 #define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */
00544 #define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */
00545 #define PHY_REG_PHYCR       0x19        /* PHY Control Register              */
00546 #define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */
00547 #define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */
00548 #define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */
00549 
00550 #define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
00551 #define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
00552 #define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
00553 #define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
00554 #define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */
00555 
00556 #define DP83848C_DEF_ADR    0x0100      /* Default PHY device address        */
00557 #define DP83848C_ID         0x20005C90  /* PHY Identifier                    */
00558 
00559 
00560 /*************************************************
00561  * CodeRed - PHY definitions for RDB1768 rev 2
00562  * which uses SMSC LAN8720 PHY instead of DP83848C
00563  *************************************************/
00564 #define LAN8720_ID          0x000730F0  /* PHY Identifier                    */
00565 
00566 
00567 
00568 
00569 // Code Red - not required for RDB1768 port
00570 /*
00571 // typedefs
00572 typedef struct {                                 // struct to store CS8900's
00573   unsigned int Addr;                             // init-sequence
00574   unsigned int Data;
00575 } TInitSeq;
00576 */
00577 
00578 // Code Red - moved into tcpip.c
00579 /*
00580 // constants
00581 const unsigned char MyMAC[] =                    // "M1-M2-M3-M4-M5-M6"
00582 {
00583   MYMAC_1, MYMAC_2, MYMAC_3,
00584   MYMAC_4, MYMAC_5, MYMAC_6
00585 };
00586 */
00587 
00588 // Code Red - not required for RDB1768 port
00589 /*
00590 const TInitSeq InitSeq[] =
00591 {
00592   PP_IA, MYMAC_1 + (MYMAC_2 << 8),               // set our MAC as Individual Address
00593   PP_IA + 2, MYMAC_3 + (MYMAC_4 << 8),
00594   PP_IA + 4, MYMAC_5 + (MYMAC_6 << 8),
00595   PP_LineCTL, SERIAL_RX_ON | SERIAL_TX_ON,       // configure the Physical Interface
00596   PP_RxCTL, RX_OK_ACCEPT | RX_IA_ACCEPT | RX_BROADCAST_ACCEPT
00597 };
00598 */
00599 
00600 // prototypes
00601 
00602 // CodeRed - updated for LPC1768 port
00603 /*
00604 void Init8900(void);
00605 void Write8900(unsigned char Address, unsigned int Data);
00606 void WriteFrame8900(unsigned int Data);
00607 unsigned int Read8900(unsigned char Address);
00608 unsigned int ReadFrame8900(void);
00609 unsigned int ReadHB1ST8900(unsigned char Address);
00610 unsigned int ReadFrameBE8900(void);
00611 void CopyToFrame8900(void *Source, unsigned int Size);
00612 void CopyFromFrame8900(void *Dest, unsigned int Size);
00613 void DummyReadFrame8900(unsigned int Size);
00614 void RequestSend(unsigned int FrameSize);
00615 unsigned int Rdy4Tx(void);
00616 */
00617 
00618 void Init_EthMAC(void);
00619 unsigned short ReadFrameBE_EthMAC(void);
00620 void CopyToFrame_EthMAC(void *Source, unsigned int Size);
00621 void CopyFromFrame_EthMAC(void *Dest, unsigned short Size);
00622 void DummyReadFrame_EthMAC(unsigned short Size);
00623 void RequestSend(unsigned short FrameSize);
00624 unsigned int Rdy4Tx(void);
00625 unsigned short StartReadingFrame(void);
00626 void StopReadingFrame(void);
00627 unsigned int CheckIfFrameReceived(void); 
00628 
00629 #endif
00630