EL4121 Embedded System / mbed-os

mbed-os

Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_STM/gpio_api.c@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /* mbed Microcontroller Library
be_bryan 0:b74591d5ab33 2 *******************************************************************************
be_bryan 0:b74591d5ab33 3 * Copyright (c) 2015, STMicroelectronics
be_bryan 0:b74591d5ab33 4 * All rights reserved.
be_bryan 0:b74591d5ab33 5 *
be_bryan 0:b74591d5ab33 6 * Redistribution and use in source and binary forms, with or without
be_bryan 0:b74591d5ab33 7 * modification, are permitted provided that the following conditions are met:
be_bryan 0:b74591d5ab33 8 *
be_bryan 0:b74591d5ab33 9 * 1. Redistributions of source code must retain the above copyright notice,
be_bryan 0:b74591d5ab33 10 * this list of conditions and the following disclaimer.
be_bryan 0:b74591d5ab33 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
be_bryan 0:b74591d5ab33 12 * this list of conditions and the following disclaimer in the documentation
be_bryan 0:b74591d5ab33 13 * and/or other materials provided with the distribution.
be_bryan 0:b74591d5ab33 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
be_bryan 0:b74591d5ab33 15 * may be used to endorse or promote products derived from this software
be_bryan 0:b74591d5ab33 16 * without specific prior written permission.
be_bryan 0:b74591d5ab33 17 *
be_bryan 0:b74591d5ab33 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
be_bryan 0:b74591d5ab33 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
be_bryan 0:b74591d5ab33 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
be_bryan 0:b74591d5ab33 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
be_bryan 0:b74591d5ab33 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
be_bryan 0:b74591d5ab33 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
be_bryan 0:b74591d5ab33 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
be_bryan 0:b74591d5ab33 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
be_bryan 0:b74591d5ab33 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
be_bryan 0:b74591d5ab33 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
be_bryan 0:b74591d5ab33 28 *******************************************************************************
be_bryan 0:b74591d5ab33 29 */
be_bryan 0:b74591d5ab33 30 #include "mbed_assert.h"
be_bryan 0:b74591d5ab33 31 #include "gpio_api.h"
be_bryan 0:b74591d5ab33 32 #include "pinmap.h"
be_bryan 0:b74591d5ab33 33 #include "mbed_error.h"
be_bryan 0:b74591d5ab33 34 #include "pin_device.h"
be_bryan 0:b74591d5ab33 35
be_bryan 0:b74591d5ab33 36 extern const uint32_t ll_pin_defines[16];
be_bryan 0:b74591d5ab33 37
be_bryan 0:b74591d5ab33 38 // Enable GPIO clock and return GPIO base address
be_bryan 0:b74591d5ab33 39 GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx) {
be_bryan 0:b74591d5ab33 40 uint32_t gpio_add = 0;
be_bryan 0:b74591d5ab33 41 switch (port_idx) {
be_bryan 0:b74591d5ab33 42 case PortA:
be_bryan 0:b74591d5ab33 43 gpio_add = GPIOA_BASE;
be_bryan 0:b74591d5ab33 44 __HAL_RCC_GPIOA_CLK_ENABLE();
be_bryan 0:b74591d5ab33 45 break;
be_bryan 0:b74591d5ab33 46 case PortB:
be_bryan 0:b74591d5ab33 47 gpio_add = GPIOB_BASE;
be_bryan 0:b74591d5ab33 48 __HAL_RCC_GPIOB_CLK_ENABLE();
be_bryan 0:b74591d5ab33 49 break;
be_bryan 0:b74591d5ab33 50 #if defined(GPIOC_BASE)
be_bryan 0:b74591d5ab33 51 case PortC:
be_bryan 0:b74591d5ab33 52 gpio_add = GPIOC_BASE;
be_bryan 0:b74591d5ab33 53 __HAL_RCC_GPIOC_CLK_ENABLE();
be_bryan 0:b74591d5ab33 54 break;
be_bryan 0:b74591d5ab33 55 #endif
be_bryan 0:b74591d5ab33 56 #if defined GPIOD_BASE
be_bryan 0:b74591d5ab33 57 case PortD:
be_bryan 0:b74591d5ab33 58 gpio_add = GPIOD_BASE;
be_bryan 0:b74591d5ab33 59 __HAL_RCC_GPIOD_CLK_ENABLE();
be_bryan 0:b74591d5ab33 60 break;
be_bryan 0:b74591d5ab33 61 #endif
be_bryan 0:b74591d5ab33 62 #if defined GPIOE_BASE
be_bryan 0:b74591d5ab33 63 case PortE:
be_bryan 0:b74591d5ab33 64 gpio_add = GPIOE_BASE;
be_bryan 0:b74591d5ab33 65 __HAL_RCC_GPIOE_CLK_ENABLE();
be_bryan 0:b74591d5ab33 66 break;
be_bryan 0:b74591d5ab33 67 #endif
be_bryan 0:b74591d5ab33 68 #if defined GPIOF_BASE
be_bryan 0:b74591d5ab33 69 case PortF:
be_bryan 0:b74591d5ab33 70 gpio_add = GPIOF_BASE;
be_bryan 0:b74591d5ab33 71 __HAL_RCC_GPIOF_CLK_ENABLE();
be_bryan 0:b74591d5ab33 72 break;
be_bryan 0:b74591d5ab33 73 #endif
be_bryan 0:b74591d5ab33 74 #if defined GPIOG_BASE
be_bryan 0:b74591d5ab33 75 case PortG:
be_bryan 0:b74591d5ab33 76 #if defined TARGET_STM32L4
be_bryan 0:b74591d5ab33 77 __HAL_RCC_PWR_CLK_ENABLE();
be_bryan 0:b74591d5ab33 78 HAL_PWREx_EnableVddIO2();
be_bryan 0:b74591d5ab33 79 #endif
be_bryan 0:b74591d5ab33 80 gpio_add = GPIOG_BASE;
be_bryan 0:b74591d5ab33 81 __HAL_RCC_GPIOG_CLK_ENABLE();
be_bryan 0:b74591d5ab33 82 break;
be_bryan 0:b74591d5ab33 83 #endif
be_bryan 0:b74591d5ab33 84 #if defined GPIOH_BASE
be_bryan 0:b74591d5ab33 85 case PortH:
be_bryan 0:b74591d5ab33 86 gpio_add = GPIOH_BASE;
be_bryan 0:b74591d5ab33 87 __HAL_RCC_GPIOH_CLK_ENABLE();
be_bryan 0:b74591d5ab33 88 break;
be_bryan 0:b74591d5ab33 89 #endif
be_bryan 0:b74591d5ab33 90 #if defined GPIOI_BASE
be_bryan 0:b74591d5ab33 91 case PortI:
be_bryan 0:b74591d5ab33 92 gpio_add = GPIOI_BASE;
be_bryan 0:b74591d5ab33 93 __HAL_RCC_GPIOI_CLK_ENABLE();
be_bryan 0:b74591d5ab33 94 break;
be_bryan 0:b74591d5ab33 95 #endif
be_bryan 0:b74591d5ab33 96 #if defined GPIOJ_BASE
be_bryan 0:b74591d5ab33 97 case PortJ:
be_bryan 0:b74591d5ab33 98 gpio_add = GPIOJ_BASE;
be_bryan 0:b74591d5ab33 99 __HAL_RCC_GPIOJ_CLK_ENABLE();
be_bryan 0:b74591d5ab33 100 break;
be_bryan 0:b74591d5ab33 101 #endif
be_bryan 0:b74591d5ab33 102 #if defined GPIOK_BASE
be_bryan 0:b74591d5ab33 103 case PortK:
be_bryan 0:b74591d5ab33 104 gpio_add = GPIOK_BASE;
be_bryan 0:b74591d5ab33 105 __HAL_RCC_GPIOK_CLK_ENABLE();
be_bryan 0:b74591d5ab33 106 break;
be_bryan 0:b74591d5ab33 107 #endif
be_bryan 0:b74591d5ab33 108 default:
be_bryan 0:b74591d5ab33 109 error("Pinmap error: wrong port number.");
be_bryan 0:b74591d5ab33 110 break;
be_bryan 0:b74591d5ab33 111 }
be_bryan 0:b74591d5ab33 112 return (GPIO_TypeDef *) gpio_add;
be_bryan 0:b74591d5ab33 113 }
be_bryan 0:b74591d5ab33 114
be_bryan 0:b74591d5ab33 115 uint32_t gpio_set(PinName pin) {
be_bryan 0:b74591d5ab33 116 MBED_ASSERT(pin != (PinName)NC);
be_bryan 0:b74591d5ab33 117
be_bryan 0:b74591d5ab33 118 pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
be_bryan 0:b74591d5ab33 119
be_bryan 0:b74591d5ab33 120 return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
be_bryan 0:b74591d5ab33 121 }
be_bryan 0:b74591d5ab33 122
be_bryan 0:b74591d5ab33 123
be_bryan 0:b74591d5ab33 124 void gpio_init(gpio_t *obj, PinName pin) {
be_bryan 0:b74591d5ab33 125 obj->pin = pin;
be_bryan 0:b74591d5ab33 126 if (pin == (PinName)NC) {
be_bryan 0:b74591d5ab33 127 return;
be_bryan 0:b74591d5ab33 128 }
be_bryan 0:b74591d5ab33 129
be_bryan 0:b74591d5ab33 130 uint32_t port_index = STM_PORT(pin);
be_bryan 0:b74591d5ab33 131
be_bryan 0:b74591d5ab33 132 // Enable GPIO clock
be_bryan 0:b74591d5ab33 133 GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
be_bryan 0:b74591d5ab33 134
be_bryan 0:b74591d5ab33 135 // Fill GPIO object structure for future use
be_bryan 0:b74591d5ab33 136 obj->mask = gpio_set(pin);
be_bryan 0:b74591d5ab33 137 obj->gpio = gpio;
be_bryan 0:b74591d5ab33 138 obj->ll_pin = ll_pin_defines[STM_PIN(obj->pin)];
be_bryan 0:b74591d5ab33 139 obj->reg_in = &gpio->IDR;
be_bryan 0:b74591d5ab33 140 obj->reg_set = &gpio->BSRR;
be_bryan 0:b74591d5ab33 141 #ifdef GPIO_IP_WITHOUT_BRR
be_bryan 0:b74591d5ab33 142 obj->reg_clr = &gpio->BSRR;
be_bryan 0:b74591d5ab33 143 #else
be_bryan 0:b74591d5ab33 144 obj->reg_clr = &gpio->BRR;
be_bryan 0:b74591d5ab33 145 #endif
be_bryan 0:b74591d5ab33 146 }
be_bryan 0:b74591d5ab33 147
be_bryan 0:b74591d5ab33 148 void gpio_mode(gpio_t *obj, PinMode mode) {
be_bryan 0:b74591d5ab33 149 pin_mode(obj->pin, mode);
be_bryan 0:b74591d5ab33 150 }
be_bryan 0:b74591d5ab33 151
be_bryan 0:b74591d5ab33 152 inline void gpio_dir(gpio_t *obj, PinDirection direction) {
be_bryan 0:b74591d5ab33 153 if (direction == PIN_INPUT) {
be_bryan 0:b74591d5ab33 154 LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_INPUT);
be_bryan 0:b74591d5ab33 155 } else {
be_bryan 0:b74591d5ab33 156 LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_OUTPUT);
be_bryan 0:b74591d5ab33 157 }
be_bryan 0:b74591d5ab33 158 }
be_bryan 0:b74591d5ab33 159