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targets/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /**
be_bryan 0:b74591d5ab33 2 ******************************************************************************
be_bryan 0:b74591d5ab33 3 * @file macHw_map.h
be_bryan 0:b74591d5ab33 4 * @brief MACHW hw module register map
be_bryan 0:b74591d5ab33 5 * @internal
be_bryan 0:b74591d5ab33 6 * @author ON Semiconductor
be_bryan 0:b74591d5ab33 7 * $Rev: 3390 $
be_bryan 0:b74591d5ab33 8 * $Date: 2015-05-13 17:21:05 +0530 (Wed, 13 May 2015) $
be_bryan 0:b74591d5ab33 9 ******************************************************************************
be_bryan 0:b74591d5ab33 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
be_bryan 0:b74591d5ab33 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
be_bryan 0:b74591d5ab33 12 * under limited terms and conditions. The terms and conditions pertaining to the software
be_bryan 0:b74591d5ab33 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
be_bryan 0:b74591d5ab33 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
be_bryan 0:b74591d5ab33 15 * if applicable the software license agreement. Do not use this software and/or
be_bryan 0:b74591d5ab33 16 * documentation unless you have carefully read and you agree to the limited terms and
be_bryan 0:b74591d5ab33 17 * conditions. By using this software and/or documentation, you agree to the limited
be_bryan 0:b74591d5ab33 18 * terms and conditions.
be_bryan 0:b74591d5ab33 19 *
be_bryan 0:b74591d5ab33 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
be_bryan 0:b74591d5ab33 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
be_bryan 0:b74591d5ab33 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
be_bryan 0:b74591d5ab33 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
be_bryan 0:b74591d5ab33 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
be_bryan 0:b74591d5ab33 25 * @endinternal
be_bryan 0:b74591d5ab33 26 *
be_bryan 0:b74591d5ab33 27 * @ingroup macHw
be_bryan 0:b74591d5ab33 28 *
be_bryan 0:b74591d5ab33 29 * @details
be_bryan 0:b74591d5ab33 30 */
be_bryan 0:b74591d5ab33 31
be_bryan 0:b74591d5ab33 32 #ifndef MACHW_MAP_H_
be_bryan 0:b74591d5ab33 33 #define MACHW_MAP_H_
be_bryan 0:b74591d5ab33 34
be_bryan 0:b74591d5ab33 35 /*************************************************************************************************
be_bryan 0:b74591d5ab33 36 * *
be_bryan 0:b74591d5ab33 37 * Header files *
be_bryan 0:b74591d5ab33 38 * *
be_bryan 0:b74591d5ab33 39 *************************************************************************************************/
be_bryan 0:b74591d5ab33 40
be_bryan 0:b74591d5ab33 41 #include "architecture.h"
be_bryan 0:b74591d5ab33 42
be_bryan 0:b74591d5ab33 43 /**************************************************************************************************
be_bryan 0:b74591d5ab33 44 * *
be_bryan 0:b74591d5ab33 45 * Type definitions *
be_bryan 0:b74591d5ab33 46 * *
be_bryan 0:b74591d5ab33 47 **************************************************************************************************/
be_bryan 0:b74591d5ab33 48
be_bryan 0:b74591d5ab33 49 /** macHw register map (phy, mac and agc parts) */
be_bryan 0:b74591d5ab33 50 typedef struct {
be_bryan 0:b74591d5ab33 51 __O uint32_t SEQUENCER; /**< 0x40014000 */
be_bryan 0:b74591d5ab33 52 union {
be_bryan 0:b74591d5ab33 53 struct {
be_bryan 0:b74591d5ab33 54 __IO uint32_t MODE:2;
be_bryan 0:b74591d5ab33 55 __IO uint32_t NOACK:1;
be_bryan 0:b74591d5ab33 56 __IO uint32_t FT:1;
be_bryan 0:b74591d5ab33 57 __IO uint32_t PAD0:3;
be_bryan 0:b74591d5ab33 58 __IO uint32_t AUTO:1;
be_bryan 0:b74591d5ab33 59 __IO uint32_t PAD1:1;
be_bryan 0:b74591d5ab33 60 __IO uint32_t NOW:1;
be_bryan 0:b74591d5ab33 61 __IO uint32_t PAD2:1;
be_bryan 0:b74591d5ab33 62 __IO uint32_t PRM:1;
be_bryan 0:b74591d5ab33 63 __IO uint32_t NFCS:1;
be_bryan 0:b74591d5ab33 64 __IO uint32_t PAN:1;
be_bryan 0:b74591d5ab33 65 __IO uint32_t RSTT:1;
be_bryan 0:b74591d5ab33 66 __IO uint32_t RSTR:1;
be_bryan 0:b74591d5ab33 67 __IO uint32_t ACK_ENABLE:1;
be_bryan 0:b74591d5ab33 68 __IO uint32_t BEA_ENABLE:1;
be_bryan 0:b74591d5ab33 69 __IO uint32_t CMD_ENABLE:1;
be_bryan 0:b74591d5ab33 70 __IO uint32_t DATA_ENABLE:1;
be_bryan 0:b74591d5ab33 71 __IO uint32_t RES_ENABLE:1;
be_bryan 0:b74591d5ab33 72 } BITS;
be_bryan 0:b74591d5ab33 73 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 74 } SEQ_OPTIONS; /**< 0x40014004 */
be_bryan 0:b74591d5ab33 75 union {
be_bryan 0:b74591d5ab33 76 struct {
be_bryan 0:b74591d5ab33 77 __IO uint32_t SRST:1;
be_bryan 0:b74591d5ab33 78 __IO uint32_t ON:1;
be_bryan 0:b74591d5ab33 79 __IO uint32_t CLKDIV:1;
be_bryan 0:b74591d5ab33 80 } BITS;
be_bryan 0:b74591d5ab33 81 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 82 } CONTROL; /**< 0x40014008 */
be_bryan 0:b74591d5ab33 83 __O uint32_t PAD0; /**< 0x4001400C */
be_bryan 0:b74591d5ab33 84 union {
be_bryan 0:b74591d5ab33 85 struct {
be_bryan 0:b74591d5ab33 86 __I uint32_t CODE:4;
be_bryan 0:b74591d5ab33 87 __I uint32_t PAD0:8;
be_bryan 0:b74591d5ab33 88 __I uint32_t MSO:1;
be_bryan 0:b74591d5ab33 89 __I uint32_t CB:1;
be_bryan 0:b74591d5ab33 90 __I uint32_t PAD1:1;
be_bryan 0:b74591d5ab33 91 __I uint32_t MST:1;
be_bryan 0:b74591d5ab33 92 } BITS;
be_bryan 0:b74591d5ab33 93 __I uint32_t WORD;
be_bryan 0:b74591d5ab33 94 } STATUS; /**< 0x40014010 */
be_bryan 0:b74591d5ab33 95 union {
be_bryan 0:b74591d5ab33 96 struct {
be_bryan 0:b74591d5ab33 97 __IO uint32_t TFP:1;
be_bryan 0:b74591d5ab33 98 __IO uint32_t SDC:1;
be_bryan 0:b74591d5ab33 99 __IO uint32_t IC:1;
be_bryan 0:b74591d5ab33 100 __IO uint32_t SDB:1;
be_bryan 0:b74591d5ab33 101 __IO uint32_t SSP:1;
be_bryan 0:b74591d5ab33 102 __IO uint32_t TFPO:1;
be_bryan 0:b74591d5ab33 103 } BITS;
be_bryan 0:b74591d5ab33 104 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 105 } OPTIONS; /**< 0x40014014 */
be_bryan 0:b74591d5ab33 106 __IO uint32_t PANID; /**< 0x40014018 */
be_bryan 0:b74591d5ab33 107 __IO uint32_t SHORT_ADDRESS; /**< 0x4001401C */
be_bryan 0:b74591d5ab33 108 __IO uint32_t LONG_ADDRESS_HIGH; /**< 0x40014020 */
be_bryan 0:b74591d5ab33 109 __IO uint32_t LONG_ADDRESS_LOW; /**< 0x40014024 */
be_bryan 0:b74591d5ab33 110 union {
be_bryan 0:b74591d5ab33 111 struct {
be_bryan 0:b74591d5ab33 112 __IO uint32_t BIT_CLOCK_DIVIDER:8;
be_bryan 0:b74591d5ab33 113 __IO uint32_t SYSTEM_CLOCK_DIVIDER:8;
be_bryan 0:b74591d5ab33 114 __IO uint32_t CHIP_CLOCK_DIVIDER:8;
be_bryan 0:b74591d5ab33 115 } BITS;
be_bryan 0:b74591d5ab33 116 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 117 } DIVIDER; /**< 0x40014028 */
be_bryan 0:b74591d5ab33 118 union {
be_bryan 0:b74591d5ab33 119 struct {
be_bryan 0:b74591d5ab33 120 __IO uint32_t RECEIVE_WARMPUP:12;
be_bryan 0:b74591d5ab33 121 __IO uint32_t PAD0:4;
be_bryan 0:b74591d5ab33 122 __IO uint32_t TRANSMIT_WARMPUP:12;
be_bryan 0:b74591d5ab33 123 } BITS;
be_bryan 0:b74591d5ab33 124 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 125 } RX_TX_WARMPUPS; /**< 0x4001402c */
be_bryan 0:b74591d5ab33 126 union {
be_bryan 0:b74591d5ab33 127 struct {
be_bryan 0:b74591d5ab33 128 __O uint32_t EC:1;
be_bryan 0:b74591d5ab33 129 __O uint32_t ES:1;
be_bryan 0:b74591d5ab33 130 __O uint32_t DATA:1;
be_bryan 0:b74591d5ab33 131 __O uint32_t FS:1;
be_bryan 0:b74591d5ab33 132 __O uint32_t FP:1;
be_bryan 0:b74591d5ab33 133 __O uint32_t FMD:1;
be_bryan 0:b74591d5ab33 134 __I uint32_t PC:1;
be_bryan 0:b74591d5ab33 135 } BITS;
be_bryan 0:b74591d5ab33 136 __O uint32_t WORD;
be_bryan 0:b74591d5ab33 137 } CLEAR_IRQ; /**< 0x40014030 */
be_bryan 0:b74591d5ab33 138 union {
be_bryan 0:b74591d5ab33 139 struct {
be_bryan 0:b74591d5ab33 140 __IO uint32_t EC:1;
be_bryan 0:b74591d5ab33 141 __IO uint32_t ES:1;
be_bryan 0:b74591d5ab33 142 __IO uint32_t DATA:1;
be_bryan 0:b74591d5ab33 143 __IO uint32_t FS:1;
be_bryan 0:b74591d5ab33 144 __IO uint32_t FP:1;
be_bryan 0:b74591d5ab33 145 __IO uint32_t FM:1;
be_bryan 0:b74591d5ab33 146 __I uint32_t PC:1;
be_bryan 0:b74591d5ab33 147 } BITS;
be_bryan 0:b74591d5ab33 148 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 149 } MASK_IRQ; /**< 0x40014034 */
be_bryan 0:b74591d5ab33 150 union {
be_bryan 0:b74591d5ab33 151 struct {
be_bryan 0:b74591d5ab33 152 __I uint32_t EC:1;
be_bryan 0:b74591d5ab33 153 __I uint32_t ES:1;
be_bryan 0:b74591d5ab33 154 __I uint32_t DATA:1;
be_bryan 0:b74591d5ab33 155 __I uint32_t FS:1;
be_bryan 0:b74591d5ab33 156 __I uint32_t FP:1;
be_bryan 0:b74591d5ab33 157 __I uint32_t FM:1;
be_bryan 0:b74591d5ab33 158 __I uint32_t PC:1;
be_bryan 0:b74591d5ab33 159 } BITS;
be_bryan 0:b74591d5ab33 160 __I uint32_t WORD;
be_bryan 0:b74591d5ab33 161 } IRQ_STATUS; /**< 0x40014038 */
be_bryan 0:b74591d5ab33 162 __O uint32_t PAD1; /**< 0x4001403C */
be_bryan 0:b74591d5ab33 163 union {
be_bryan 0:b74591d5ab33 164 struct {
be_bryan 0:b74591d5ab33 165 __IO uint32_t START:1;
be_bryan 0:b74591d5ab33 166 __IO uint32_t STOP:1;
be_bryan 0:b74591d5ab33 167 } BITS;
be_bryan 0:b74591d5ab33 168 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 169 } TIMER_ENABLE; /**< 0x40014040 */
be_bryan 0:b74591d5ab33 170 union {
be_bryan 0:b74591d5ab33 171 struct {
be_bryan 0:b74591d5ab33 172 __IO uint32_t START:1;
be_bryan 0:b74591d5ab33 173 __IO uint32_t STOP:1;
be_bryan 0:b74591d5ab33 174 } BITS;
be_bryan 0:b74591d5ab33 175 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 176 } TIMER_DISABLE; /**< 0x40014044 */
be_bryan 0:b74591d5ab33 177 __IO uint32_t TIMER; /**< 0x40014048 */
be_bryan 0:b74591d5ab33 178 __IO uint32_t START_TIME; /**< 0x4001404C */
be_bryan 0:b74591d5ab33 179 __IO uint32_t STOP_TIME; /**< 0x40014050 */
be_bryan 0:b74591d5ab33 180 union {
be_bryan 0:b74591d5ab33 181 struct {
be_bryan 0:b74591d5ab33 182 __I uint32_t START:1;
be_bryan 0:b74591d5ab33 183 __I uint32_t STOP:1;
be_bryan 0:b74591d5ab33 184 } BITS;
be_bryan 0:b74591d5ab33 185 __I uint32_t WORD;
be_bryan 0:b74591d5ab33 186 } TIMER_STATUS; /**< 0x40014054 */
be_bryan 0:b74591d5ab33 187 __I uint32_t PROTOCOL_TIMER; /**< 0x40014058 */
be_bryan 0:b74591d5ab33 188 __O uint32_t PAD4; /**< 0x4001405C */
be_bryan 0:b74591d5ab33 189 __I uint32_t FINISH_TIME; /**< 0x40014060 */
be_bryan 0:b74591d5ab33 190 union {
be_bryan 0:b74591d5ab33 191 struct {
be_bryan 0:b74591d5ab33 192 __IO uint32_t TX_SLOT_OFFSET:12;
be_bryan 0:b74591d5ab33 193 __IO uint32_t PAD0:4;
be_bryan 0:b74591d5ab33 194 __IO uint32_t RX_SLOT_OFFSET:12;
be_bryan 0:b74591d5ab33 195 } BITS;
be_bryan 0:b74591d5ab33 196 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 197 } SLOT_OFFSET; /**< 0x40014064 */
be_bryan 0:b74591d5ab33 198 __I uint32_t TIME_STAMP; /**< 0x40014068 */
be_bryan 0:b74591d5ab33 199 union {
be_bryan 0:b74591d5ab33 200 struct {
be_bryan 0:b74591d5ab33 201 __IO uint32_t CRD_SHORT_ADDRESS:16;
be_bryan 0:b74591d5ab33 202 __IO uint32_t PAD0:13;
be_bryan 0:b74591d5ab33 203 __IO uint32_t ASSOC_PAN_COORD:1;
be_bryan 0:b74591d5ab33 204 __IO uint32_t PAN_COORD_ADDR_L:1;
be_bryan 0:b74591d5ab33 205 __IO uint32_t PAN_COORD_ADDR_S:1;
be_bryan 0:b74591d5ab33 206 } BITS;
be_bryan 0:b74591d5ab33 207 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 208 } CRD_SHORT_ADDR; /**< 0x4001406C */
be_bryan 0:b74591d5ab33 209 __IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014070 */
be_bryan 0:b74591d5ab33 210 __IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014074 */
be_bryan 0:b74591d5ab33 211 __O uint32_t PAD5; /**< 0x40014078 */
be_bryan 0:b74591d5ab33 212 __O uint32_t PAD9; /**< 0x4001407C */
be_bryan 0:b74591d5ab33 213 __O uint32_t PAD10; /**< 0x40014080 */
be_bryan 0:b74591d5ab33 214 __O uint32_t PAD11; /**< 0x40014084 */
be_bryan 0:b74591d5ab33 215 __IO uint32_t RX_LENGTH; /**< 0x40014088 */
be_bryan 0:b74591d5ab33 216 union {
be_bryan 0:b74591d5ab33 217 struct {
be_bryan 0:b74591d5ab33 218 __IO uint32_t TXLENGTH:7;
be_bryan 0:b74591d5ab33 219 __O uint32_t PAD0:1;
be_bryan 0:b74591d5ab33 220 __IO uint32_t TX_PRE_CHIPS:4;
be_bryan 0:b74591d5ab33 221 } BITS;
be_bryan 0:b74591d5ab33 222 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 223 } TX_LENGTH; /**< 0x4001408C */
be_bryan 0:b74591d5ab33 224 __IO uint32_t TX_SEQ_NUMBER; /**< 0x40014090 */
be_bryan 0:b74591d5ab33 225 __IO uint32_t TX_ACK_DELAY; /**< 0x40014094 */
be_bryan 0:b74591d5ab33 226 union {
be_bryan 0:b74591d5ab33 227 struct {
be_bryan 0:b74591d5ab33 228 __IO uint32_t RXACKDELAY:12;
be_bryan 0:b74591d5ab33 229 __IO uint32_t PAD0:4;
be_bryan 0:b74591d5ab33 230 __IO uint32_t RXAUTODELAY:12;
be_bryan 0:b74591d5ab33 231 } BITS;
be_bryan 0:b74591d5ab33 232 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 233 } RX_ACK_DELAY; /**< 0x40014098 */
be_bryan 0:b74591d5ab33 234 __IO uint32_t TX_FLUSH; /**< 0x4001409C */
be_bryan 0:b74591d5ab33 235 union {
be_bryan 0:b74591d5ab33 236 struct {
be_bryan 0:b74591d5ab33 237 __IO uint32_t CCA_DELAY:12;
be_bryan 0:b74591d5ab33 238 __IO uint32_t PAD0:4;
be_bryan 0:b74591d5ab33 239 __IO uint32_t CCA_LENGTH:12;
be_bryan 0:b74591d5ab33 240 } BITS;
be_bryan 0:b74591d5ab33 241 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 242 } CCA; /**< 0x400140A0 */
be_bryan 0:b74591d5ab33 243 union {
be_bryan 0:b74591d5ab33 244 struct {
be_bryan 0:b74591d5ab33 245 __IO uint32_t RXACK_END:12;
be_bryan 0:b74591d5ab33 246 __IO uint32_t PAD0:4;
be_bryan 0:b74591d5ab33 247 __IO uint32_t RXSLOTTED_END:12;
be_bryan 0:b74591d5ab33 248 } BITS;
be_bryan 0:b74591d5ab33 249 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 250 } ACK_STOP; /**< 0x400140A4 */
be_bryan 0:b74591d5ab33 251 __IO uint32_t TXCCA; /**< 0x400140A8 */
be_bryan 0:b74591d5ab33 252 __IO uint32_t ADDR_L_LOC; /**< 0x400140AC */
be_bryan 0:b74591d5ab33 253 __IO uint32_t ADDR_S_LOC; /**< 0x400140B0 */
be_bryan 0:b74591d5ab33 254 __IO uint32_t FRAME_MATCH_RESULT; /**< 0x400140B4 */
be_bryan 0:b74591d5ab33 255 __IO uint32_t FRAME_MATCH_ADDR_L; /**< 0x400140B8 */
be_bryan 0:b74591d5ab33 256 __IO uint32_t FRAME_MATCH_ADDR_S; /**< 0x400140BC */
be_bryan 0:b74591d5ab33 257 union {
be_bryan 0:b74591d5ab33 258 struct {
be_bryan 0:b74591d5ab33 259 __IO uint32_t AA:1;
be_bryan 0:b74591d5ab33 260 __IO uint32_t AFA:1;
be_bryan 0:b74591d5ab33 261 __IO uint32_t PRE:1;
be_bryan 0:b74591d5ab33 262 __IO uint32_t PAD0:25;
be_bryan 0:b74591d5ab33 263 __IO uint32_t GAIN_START:4;
be_bryan 0:b74591d5ab33 264 } BITS;
be_bryan 0:b74591d5ab33 265 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 266 } AGC_CONTROL; /**< 0x400140C0 */
be_bryan 0:b74591d5ab33 267 union {
be_bryan 0:b74591d5ab33 268 struct {
be_bryan 0:b74591d5ab33 269 __IO uint32_t SETTLE_DELAY:8;
be_bryan 0:b74591d5ab33 270 __IO uint32_t MEASURE_DELAY:8;
be_bryan 0:b74591d5ab33 271 __IO uint32_t DIVIDER:8;
be_bryan 0:b74591d5ab33 272 __IO uint32_t HIGH_THRESHOLD:4;
be_bryan 0:b74591d5ab33 273 __IO uint32_t LOW_THRESHOLD:4;
be_bryan 0:b74591d5ab33 274 } BITS;
be_bryan 0:b74591d5ab33 275 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 276 } AGC_SETTINGS; /**< 0x400140C4 */
be_bryan 0:b74591d5ab33 277 union {
be_bryan 0:b74591d5ab33 278 struct {
be_bryan 0:b74591d5ab33 279 __IO uint32_t GC1:3;
be_bryan 0:b74591d5ab33 280 __IO uint32_t GC2:3;
be_bryan 0:b74591d5ab33 281 __IO uint32_t GC3:1;
be_bryan 0:b74591d5ab33 282 __IO uint32_t PAD:1;
be_bryan 0:b74591d5ab33 283 __IO uint32_t AGC_STATE:4;
be_bryan 0:b74591d5ab33 284 } BITS;
be_bryan 0:b74591d5ab33 285 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 286 } AGC_STATUS; /**< 0x400140C8 */
be_bryan 0:b74591d5ab33 287 union {
be_bryan 0:b74591d5ab33 288 struct {
be_bryan 0:b74591d5ab33 289 __IO uint32_t GAIN3:7;
be_bryan 0:b74591d5ab33 290 __IO uint32_t PAD0:1;
be_bryan 0:b74591d5ab33 291 __IO uint32_t GAIN2:7;
be_bryan 0:b74591d5ab33 292 __IO uint32_t PAD1:1;
be_bryan 0:b74591d5ab33 293 __IO uint32_t GAIN1:7;
be_bryan 0:b74591d5ab33 294 __IO uint32_t PAD2:1;
be_bryan 0:b74591d5ab33 295 __IO uint32_t GAIN0:7;
be_bryan 0:b74591d5ab33 296 __IO uint32_t PAD3:1;
be_bryan 0:b74591d5ab33 297 } BITS;
be_bryan 0:b74591d5ab33 298 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 299 } AGC_GAIN_TABLE0; /**< 0x400140CC */
be_bryan 0:b74591d5ab33 300 union {
be_bryan 0:b74591d5ab33 301 struct {
be_bryan 0:b74591d5ab33 302 __IO uint32_t GAIN7:7;
be_bryan 0:b74591d5ab33 303 __IO uint32_t PAD0:1;
be_bryan 0:b74591d5ab33 304 __IO uint32_t GAIN6:7;
be_bryan 0:b74591d5ab33 305 __IO uint32_t PAD1:1;
be_bryan 0:b74591d5ab33 306 __IO uint32_t GAIN5:7;
be_bryan 0:b74591d5ab33 307 __IO uint32_t PAD2:1;
be_bryan 0:b74591d5ab33 308 __IO uint32_t GAIN4:7;
be_bryan 0:b74591d5ab33 309 __IO uint32_t PAD3:1;
be_bryan 0:b74591d5ab33 310 } BITS;
be_bryan 0:b74591d5ab33 311 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 312 } AGC_GAIN_TABLE1; /**< 0x400140D0 */
be_bryan 0:b74591d5ab33 313 union {
be_bryan 0:b74591d5ab33 314 struct {
be_bryan 0:b74591d5ab33 315 __IO uint32_t GAIN11:7;
be_bryan 0:b74591d5ab33 316 __IO uint32_t PAD0:1;
be_bryan 0:b74591d5ab33 317 __IO uint32_t GAIN10:7;
be_bryan 0:b74591d5ab33 318 __IO uint32_t PAD1:1;
be_bryan 0:b74591d5ab33 319 __IO uint32_t GAIN9:7;
be_bryan 0:b74591d5ab33 320 __IO uint32_t PAD2:1;
be_bryan 0:b74591d5ab33 321 __IO uint32_t GAIN8:7;
be_bryan 0:b74591d5ab33 322 __IO uint32_t PAD3:1;
be_bryan 0:b74591d5ab33 323 } BITS;
be_bryan 0:b74591d5ab33 324 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 325 } AGC_GAIN_TABLE2; /**< 0x400140D4 */
be_bryan 0:b74591d5ab33 326 union {
be_bryan 0:b74591d5ab33 327 struct {
be_bryan 0:b74591d5ab33 328 __IO uint32_t GAIN15:7;
be_bryan 0:b74591d5ab33 329 __IO uint32_t PAD0:1;
be_bryan 0:b74591d5ab33 330 __IO uint32_t GAIN14:7;
be_bryan 0:b74591d5ab33 331 __IO uint32_t PAD1:1;
be_bryan 0:b74591d5ab33 332 __IO uint32_t GAIN13:7;
be_bryan 0:b74591d5ab33 333 __IO uint32_t PAD2:1;
be_bryan 0:b74591d5ab33 334 __IO uint32_t GAIN12:7;
be_bryan 0:b74591d5ab33 335 __IO uint32_t PAD3:1;
be_bryan 0:b74591d5ab33 336 } BITS;
be_bryan 0:b74591d5ab33 337 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 338 } AGC_GAIN_TABLE3; /**< 0x400140D8 */
be_bryan 0:b74591d5ab33 339 } MacHwReg_t, *MacHwReg_pt;
be_bryan 0:b74591d5ab33 340
be_bryan 0:b74591d5ab33 341 /** macHw register map (demodulator part) */
be_bryan 0:b74591d5ab33 342 typedef struct {
be_bryan 0:b74591d5ab33 343 union {
be_bryan 0:b74591d5ab33 344 struct {
be_bryan 0:b74591d5ab33 345 __IO uint32_t DRC:1; /**< Reserved */
be_bryan 0:b74591d5ab33 346 __IO uint32_t SWIQ:1; /**< Compensation for quadrature polarity. (set to 1 for RevB) */
be_bryan 0:b74591d5ab33 347 __IO uint32_t LIF:1; /**< Allows the receiver to use a low-IF frequency of +1.23 MHz (0) or -1.23 MHz (1). */
be_bryan 0:b74591d5ab33 348 __IO uint32_t PM:1; /**< Preamble Mode: Mode 0 (high sensitivity) – Preamble detection is based on observation of a regular pattern of correlation peaks over a span of 5 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If 4 out of 5 symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode improves preamble detection rate by tolerating one corrupt correlation result in the span of 5 symbols. However, the relaxed detection rule allows a higher rate of false preamble detection when no signal is present. Mode 1 (low false detection) – Preamble detection is based on a span of 4 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If all four symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode enforces a more strict detection rule and therefore offers lower rate of false preamble detection at the expense of higher missed detection. */
be_bryan 0:b74591d5ab33 349 __IO uint32_t ASM:1; /**< This bit determines whether antenna selection is automatic (1) or manual (0). For applications that do not use antenna diversity, this bit should be set to 0. */
be_bryan 0:b74591d5ab33 350 __IO uint32_t AS:1; /**< If automatic antenna selection mode is used, this bit determines the initial antenna selection. If manual antenna selection mode is used, this bit determines the antenna selection, 0 or 1. */
be_bryan 0:b74591d5ab33 351 __IO uint32_t DTC:1; /**< Sets the decay time constant used in the RSSI calculation and Digital Gain Control functions. 0: Time constant set to 1 symbol period. This produces a slower response time but more stable RSSI values. Not recommended for use with antenna diversity. 1: Time constant set to 1/4th of a symbol period. This produces a faster response with slightly more variance in the RSSI calculation. Recommended for most cases. */
be_bryan 0:b74591d5ab33 352 __IO uint32_t PAD1:9;
be_bryan 0:b74591d5ab33 353 __IO uint32_t DFR:16; /**<Selectively enables individual frequency offsets used during preamble search. Each of the 15 bits in this field corresponds to one of 15 different frequency offsets. A bit value of 0 removes a specific frequency offset from the search, while a bit value of 1 includes the frequency offset in the search. */
be_bryan 0:b74591d5ab33 354 } BITS;
be_bryan 0:b74591d5ab33 355 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 356 } DMD_CONTROL0; /**< 0x40014100 */
be_bryan 0:b74591d5ab33 357 union {
be_bryan 0:b74591d5ab33 358 struct {
be_bryan 0:b74591d5ab33 359 __IO uint32_t DST:4; /**< This value specifies the SFD search period in symbols. After preamble detection, the demodulator begins symbol recovery and searches for the start-of-frame delimiter (SFD). If the SFD is not found within the number of symbols specified, the preamble detection flag is cleared and a new preamble search is initiated. The default value of 8 symbols should be sufficient for 802.15.4 compliant applications. Default 8 */
be_bryan 0:b74591d5ab33 360 __IO uint32_t PAD0:4;
be_bryan 0:b74591d5ab33 361 __IO uint32_t DPT:6; /**< The similarity criteria used for preamble detection includes a rule that all time index values must occupy a span equal to or less than this value. The default span of 0011 means that the correlation peaks must span a range of 3Ts, where Ts is the sample period = 0.25 µs. This value is recommended for typical multipath conditions. Very long-range applications may benefit from a higher value. Default 3 */
be_bryan 0:b74591d5ab33 362 __IO uint32_t PAD1:2;
be_bryan 0:b74591d5ab33 363 __IO uint32_t DPF:4; /**< The similarity criteria used for preamble detection includes a rule that all frequency index values must occupy a span equal to or less than this value. The default span of 0001 means that the difference between largest frequency index and smallest frequency index must be less than or equal to 1. Default 1 */
be_bryan 0:b74591d5ab33 364 __IO uint32_t PAD2:4;
be_bryan 0:b74591d5ab33 365 __IO uint32_t DCT:4; /**< In order for preamble detection to be declared, the correlation peaks must exceed a threshold. The threshold is computed dynamically and includes a programmable scale factor: 1 + bit[27]/2 + bit[26]/4 + bit[25]/8 + bit[24]/16 The default value of 1.5 is recommended for manual-antenna selection, while a value of 1.75 is recommended for automatic antenna selection. */
be_bryan 0:b74591d5ab33 366
be_bryan 0:b74591d5ab33 367 } BITS;
be_bryan 0:b74591d5ab33 368 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 369 } DMD_CONTROL1; /**< 0x40014104 */
be_bryan 0:b74591d5ab33 370 union {
be_bryan 0:b74591d5ab33 371 struct {
be_bryan 0:b74591d5ab33 372 __IO uint32_t RSSI_THRESHOLD:8; /**< Threshold value used to determine clear channel assessment (CCA) result. The channel is declared busy if RSSI > threshold. Default 0xFF */
be_bryan 0:b74591d5ab33 373 __IO uint32_t RSSI_OFFSET:6; /**< Calibration constant added to the RSSI calculation. The 6-bit field is treated as a signed value in two’s complement format with values from -32 to +31 dB. */
be_bryan 0:b74591d5ab33 374 } BITS;
be_bryan 0:b74591d5ab33 375 __IO uint32_t WORD;
be_bryan 0:b74591d5ab33 376 } DMD_CONTROL2; /**< 0x40014108 */
be_bryan 0:b74591d5ab33 377 union {
be_bryan 0:b74591d5ab33 378 struct {
be_bryan 0:b74591d5ab33 379 __I uint32_t RSSI_VALUE:8; /**< The value is captured at the end of packet reception or at the end of ED/CCA measurements and is interpreted in dBm as follows: 00000000 -> 0127dBm (or below) ... 01111111 -> 0dBm (or above) */
be_bryan 0:b74591d5ab33 380 __I uint32_t FREQUENCY_OFFSET:4; /**< Frequency correction applied to the received packet. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
be_bryan 0:b74591d5ab33 381 __I uint32_t ANT:1; /**< Antenna used for reception. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
be_bryan 0:b74591d5ab33 382 __I uint32_t PAD0:3;
be_bryan 0:b74591d5ab33 383 __I uint32_t RSSI_COMPONENT:4; /**< Magnitude of the baseband digital signal (units are dB relative to A/D saturation). The value is updated until AGC is frozen. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
be_bryan 0:b74591d5ab33 384 } BITS;
be_bryan 0:b74591d5ab33 385 __I uint32_t WORD;
be_bryan 0:b74591d5ab33 386 } DMD_STATUS; /**< 0x4001410C */
be_bryan 0:b74591d5ab33 387 } DmdReg_t, *DmdReg_pt;
be_bryan 0:b74591d5ab33 388
be_bryan 0:b74591d5ab33 389 #endif /* MACHW_MAP_H_ */