EL4121 Embedded System / mbed-os

mbed-os

Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_NXP/TARGET_LPC81X/serial_api.c@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /* mbed Microcontroller Library
be_bryan 0:b74591d5ab33 2 * Copyright (c) 2006-2013 ARM Limited
be_bryan 0:b74591d5ab33 3 *
be_bryan 0:b74591d5ab33 4 * Licensed under the Apache License, Version 2.0 (the "License");
be_bryan 0:b74591d5ab33 5 * you may not use this file except in compliance with the License.
be_bryan 0:b74591d5ab33 6 * You may obtain a copy of the License at
be_bryan 0:b74591d5ab33 7 *
be_bryan 0:b74591d5ab33 8 * http://www.apache.org/licenses/LICENSE-2.0
be_bryan 0:b74591d5ab33 9 *
be_bryan 0:b74591d5ab33 10 * Unless required by applicable law or agreed to in writing, software
be_bryan 0:b74591d5ab33 11 * distributed under the License is distributed on an "AS IS" BASIS,
be_bryan 0:b74591d5ab33 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan 0:b74591d5ab33 13 * See the License for the specific language governing permissions and
be_bryan 0:b74591d5ab33 14 * limitations under the License.
be_bryan 0:b74591d5ab33 15 */
be_bryan 0:b74591d5ab33 16 // math.h required for floating point operations for baud rate calculation
be_bryan 0:b74591d5ab33 17 #include "mbed_assert.h"
be_bryan 0:b74591d5ab33 18 #include <math.h>
be_bryan 0:b74591d5ab33 19 #include <string.h>
be_bryan 0:b74591d5ab33 20
be_bryan 0:b74591d5ab33 21 #include "serial_api.h"
be_bryan 0:b74591d5ab33 22 #include "cmsis.h"
be_bryan 0:b74591d5ab33 23 #include "pinmap.h"
be_bryan 0:b74591d5ab33 24 #include "mbed_error.h"
be_bryan 0:b74591d5ab33 25
be_bryan 0:b74591d5ab33 26 /******************************************************************************
be_bryan 0:b74591d5ab33 27 * INITIALIZATION
be_bryan 0:b74591d5ab33 28 ******************************************************************************/
be_bryan 0:b74591d5ab33 29 #define UART_NUM 3
be_bryan 0:b74591d5ab33 30
be_bryan 0:b74591d5ab33 31 static const SWM_Map SWM_UART_TX[] = {
be_bryan 0:b74591d5ab33 32 {0, 0},
be_bryan 0:b74591d5ab33 33 {1, 8},
be_bryan 0:b74591d5ab33 34 {2, 16},
be_bryan 0:b74591d5ab33 35 };
be_bryan 0:b74591d5ab33 36
be_bryan 0:b74591d5ab33 37 static const SWM_Map SWM_UART_RX[] = {
be_bryan 0:b74591d5ab33 38 {0, 8},
be_bryan 0:b74591d5ab33 39 {1, 16},
be_bryan 0:b74591d5ab33 40 {2, 24},
be_bryan 0:b74591d5ab33 41 };
be_bryan 0:b74591d5ab33 42
be_bryan 0:b74591d5ab33 43 static const SWM_Map SWM_UART_RTS[] = {
be_bryan 0:b74591d5ab33 44 {0, 16},
be_bryan 0:b74591d5ab33 45 {1, 24},
be_bryan 0:b74591d5ab33 46 {3, 0},
be_bryan 0:b74591d5ab33 47 };
be_bryan 0:b74591d5ab33 48
be_bryan 0:b74591d5ab33 49 static const SWM_Map SWM_UART_CTS[] = {
be_bryan 0:b74591d5ab33 50 {0, 24},
be_bryan 0:b74591d5ab33 51 {2, 0},
be_bryan 0:b74591d5ab33 52 {3, 8}
be_bryan 0:b74591d5ab33 53 };
be_bryan 0:b74591d5ab33 54
be_bryan 0:b74591d5ab33 55 // bit flags for used UARTs
be_bryan 0:b74591d5ab33 56 static unsigned char uart_used = 0;
be_bryan 0:b74591d5ab33 57 static int get_available_uart(void) {
be_bryan 0:b74591d5ab33 58 int i;
be_bryan 0:b74591d5ab33 59 for (i=0; i<3; i++) {
be_bryan 0:b74591d5ab33 60 if ((uart_used & (1 << i)) == 0)
be_bryan 0:b74591d5ab33 61 return i;
be_bryan 0:b74591d5ab33 62 }
be_bryan 0:b74591d5ab33 63 return -1;
be_bryan 0:b74591d5ab33 64 }
be_bryan 0:b74591d5ab33 65
be_bryan 0:b74591d5ab33 66 #define UART_EN (0x01<<0)
be_bryan 0:b74591d5ab33 67
be_bryan 0:b74591d5ab33 68 #define CTS_DELTA (0x01<<5)
be_bryan 0:b74591d5ab33 69 #define RXBRK (0x01<<10)
be_bryan 0:b74591d5ab33 70 #define DELTA_RXBRK (0x01<<11)
be_bryan 0:b74591d5ab33 71
be_bryan 0:b74591d5ab33 72 #define RXRDY (0x01<<0)
be_bryan 0:b74591d5ab33 73 #define TXRDY (0x01<<2)
be_bryan 0:b74591d5ab33 74
be_bryan 0:b74591d5ab33 75 #define TXBRKEN (0x01<<1)
be_bryan 0:b74591d5ab33 76 #define CTSEN (0x01<<9)
be_bryan 0:b74591d5ab33 77
be_bryan 0:b74591d5ab33 78 static uint32_t UARTSysClk;
be_bryan 0:b74591d5ab33 79
be_bryan 0:b74591d5ab33 80 static uint32_t serial_irq_ids[UART_NUM] = {0};
be_bryan 0:b74591d5ab33 81 static uart_irq_handler irq_handler;
be_bryan 0:b74591d5ab33 82
be_bryan 0:b74591d5ab33 83 int stdio_uart_inited = 0;
be_bryan 0:b74591d5ab33 84 serial_t stdio_uart;
be_bryan 0:b74591d5ab33 85
be_bryan 0:b74591d5ab33 86 void serial_init(serial_t *obj, PinName tx, PinName rx) {
be_bryan 0:b74591d5ab33 87 int is_stdio_uart = 0;
be_bryan 0:b74591d5ab33 88
be_bryan 0:b74591d5ab33 89 int uart_n = get_available_uart();
be_bryan 0:b74591d5ab33 90 if (uart_n == -1) {
be_bryan 0:b74591d5ab33 91 error("No available UART");
be_bryan 0:b74591d5ab33 92 }
be_bryan 0:b74591d5ab33 93 obj->index = uart_n;
be_bryan 0:b74591d5ab33 94 obj->uart = (LPC_USART_TypeDef *)(LPC_USART0_BASE + (0x4000 * uart_n));
be_bryan 0:b74591d5ab33 95 uart_used |= (1 << uart_n);
be_bryan 0:b74591d5ab33 96
be_bryan 0:b74591d5ab33 97 const SWM_Map *swm;
be_bryan 0:b74591d5ab33 98 uint32_t regVal;
be_bryan 0:b74591d5ab33 99
be_bryan 0:b74591d5ab33 100 swm = &SWM_UART_TX[uart_n];
be_bryan 0:b74591d5ab33 101 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
be_bryan 0:b74591d5ab33 102 LPC_SWM->PINASSIGN[swm->n] = regVal | (tx << swm->offset);
be_bryan 0:b74591d5ab33 103
be_bryan 0:b74591d5ab33 104 swm = &SWM_UART_RX[uart_n];
be_bryan 0:b74591d5ab33 105 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
be_bryan 0:b74591d5ab33 106 LPC_SWM->PINASSIGN[swm->n] = regVal | (rx << swm->offset);
be_bryan 0:b74591d5ab33 107
be_bryan 0:b74591d5ab33 108 /* uart clock divided by 1 */
be_bryan 0:b74591d5ab33 109 LPC_SYSCON->UARTCLKDIV = 1;
be_bryan 0:b74591d5ab33 110
be_bryan 0:b74591d5ab33 111 /* disable uart interrupts */
be_bryan 0:b74591d5ab33 112 NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
be_bryan 0:b74591d5ab33 113
be_bryan 0:b74591d5ab33 114 /* Enable UART clock */
be_bryan 0:b74591d5ab33 115 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (14 + uart_n));
be_bryan 0:b74591d5ab33 116
be_bryan 0:b74591d5ab33 117 /* Peripheral reset control to UART, a "1" bring it out of reset. */
be_bryan 0:b74591d5ab33 118 LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n));
be_bryan 0:b74591d5ab33 119 LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n));
be_bryan 0:b74591d5ab33 120
be_bryan 0:b74591d5ab33 121 // Derive UART Clock from MainClock
be_bryan 0:b74591d5ab33 122 UARTSysClk = MainClock / LPC_SYSCON->UARTCLKDIV;
be_bryan 0:b74591d5ab33 123
be_bryan 0:b74591d5ab33 124 // set default baud rate and format
be_bryan 0:b74591d5ab33 125 serial_baud (obj, 9600);
be_bryan 0:b74591d5ab33 126 serial_format(obj, 8, ParityNone, 1);
be_bryan 0:b74591d5ab33 127
be_bryan 0:b74591d5ab33 128 /* Clear all status bits. */
be_bryan 0:b74591d5ab33 129 obj->uart->STAT = CTS_DELTA | DELTA_RXBRK;
be_bryan 0:b74591d5ab33 130
be_bryan 0:b74591d5ab33 131 /* enable uart interrupts */
be_bryan 0:b74591d5ab33 132 NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
be_bryan 0:b74591d5ab33 133
be_bryan 0:b74591d5ab33 134 /* Enable UART interrupt */
be_bryan 0:b74591d5ab33 135 // obj->uart->INTENSET = RXRDY | TXRDY | DELTA_RXBRK;
be_bryan 0:b74591d5ab33 136
be_bryan 0:b74591d5ab33 137 /* Enable UART */
be_bryan 0:b74591d5ab33 138 obj->uart->CFG |= UART_EN;
be_bryan 0:b74591d5ab33 139
be_bryan 0:b74591d5ab33 140 is_stdio_uart = ((tx == USBTX) && (rx == USBRX));
be_bryan 0:b74591d5ab33 141
be_bryan 0:b74591d5ab33 142 if (is_stdio_uart) {
be_bryan 0:b74591d5ab33 143 stdio_uart_inited = 1;
be_bryan 0:b74591d5ab33 144 memcpy(&stdio_uart, obj, sizeof(serial_t));
be_bryan 0:b74591d5ab33 145 }
be_bryan 0:b74591d5ab33 146 }
be_bryan 0:b74591d5ab33 147
be_bryan 0:b74591d5ab33 148 void serial_free(serial_t *obj) {
be_bryan 0:b74591d5ab33 149 uart_used &= ~(1 << obj->index);
be_bryan 0:b74591d5ab33 150 serial_irq_ids[obj->index] = 0;
be_bryan 0:b74591d5ab33 151 }
be_bryan 0:b74591d5ab33 152
be_bryan 0:b74591d5ab33 153 // serial_baud
be_bryan 0:b74591d5ab33 154 // set the baud rate, taking in to account the current SystemFrequency
be_bryan 0:b74591d5ab33 155 void serial_baud(serial_t *obj, int baudrate) {
be_bryan 0:b74591d5ab33 156 /* Integer divider:
be_bryan 0:b74591d5ab33 157 BRG = UARTSysClk/(Baudrate * 16) - 1
be_bryan 0:b74591d5ab33 158
be_bryan 0:b74591d5ab33 159 Frational divider:
be_bryan 0:b74591d5ab33 160 FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1)
be_bryan 0:b74591d5ab33 161
be_bryan 0:b74591d5ab33 162 where
be_bryan 0:b74591d5ab33 163 FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1)
be_bryan 0:b74591d5ab33 164
be_bryan 0:b74591d5ab33 165 (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB
be_bryan 0:b74591d5ab33 166 register is 0xFF.
be_bryan 0:b74591d5ab33 167 (2) In ADD register value, depending on the value of UartSysClk,
be_bryan 0:b74591d5ab33 168 baudrate, BRG register value, and SUB register value, be careful
be_bryan 0:b74591d5ab33 169 about the order of multiplier and divider and make sure any
be_bryan 0:b74591d5ab33 170 multiplier doesn't exceed 32-bit boundary and any divider doesn't get
be_bryan 0:b74591d5ab33 171 down below one(integer 0).
be_bryan 0:b74591d5ab33 172 (3) ADD should be always less than SUB.
be_bryan 0:b74591d5ab33 173 */
be_bryan 0:b74591d5ab33 174 obj->uart->BRG = UARTSysClk / 16 / baudrate - 1;
be_bryan 0:b74591d5ab33 175
be_bryan 0:b74591d5ab33 176 LPC_SYSCON->UARTFRGDIV = 0xFF;
be_bryan 0:b74591d5ab33 177 LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) /
be_bryan 0:b74591d5ab33 178 (baudrate * (obj->uart->BRG + 1))
be_bryan 0:b74591d5ab33 179 ) - (LPC_SYSCON->UARTFRGDIV + 1);
be_bryan 0:b74591d5ab33 180
be_bryan 0:b74591d5ab33 181 }
be_bryan 0:b74591d5ab33 182
be_bryan 0:b74591d5ab33 183 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
be_bryan 0:b74591d5ab33 184 // 0: 1 stop bits, 1: 2 stop bits
be_bryan 0:b74591d5ab33 185 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
be_bryan 0:b74591d5ab33 186 MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
be_bryan 0:b74591d5ab33 187 MBED_ASSERT((parity == ParityNone) || (parity == ParityEven) || (parity == ParityOdd));
be_bryan 0:b74591d5ab33 188 stop_bits -= 1;
be_bryan 0:b74591d5ab33 189 data_bits -= 7;
be_bryan 0:b74591d5ab33 190
be_bryan 0:b74591d5ab33 191 int paritysel;
be_bryan 0:b74591d5ab33 192 switch (parity) {
be_bryan 0:b74591d5ab33 193 case ParityNone: paritysel = 0; break;
be_bryan 0:b74591d5ab33 194 case ParityEven: paritysel = 2; break;
be_bryan 0:b74591d5ab33 195 case ParityOdd : paritysel = 3; break;
be_bryan 0:b74591d5ab33 196 default:
be_bryan 0:b74591d5ab33 197 break;
be_bryan 0:b74591d5ab33 198 }
be_bryan 0:b74591d5ab33 199
be_bryan 0:b74591d5ab33 200 // First disable the the usart as described in documentation and then enable while updating CFG
be_bryan 0:b74591d5ab33 201
be_bryan 0:b74591d5ab33 202 // 24.6.1 USART Configuration register
be_bryan 0:b74591d5ab33 203 // Remark: If software needs to change configuration values, the following sequence should
be_bryan 0:b74591d5ab33 204 // be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable
be_bryan 0:b74591d5ab33 205 // the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3)
be_bryan 0:b74591d5ab33 206 // Write the new configuration value, with the ENABLE bit set to 1.
be_bryan 0:b74591d5ab33 207 obj->uart->CFG &= ~(1 << 0);
be_bryan 0:b74591d5ab33 208
be_bryan 0:b74591d5ab33 209 obj->uart->CFG = (1 << 0) // this will enable the usart
be_bryan 0:b74591d5ab33 210 | (data_bits << 2)
be_bryan 0:b74591d5ab33 211 | (paritysel << 4)
be_bryan 0:b74591d5ab33 212 | (stop_bits << 6);
be_bryan 0:b74591d5ab33 213 }
be_bryan 0:b74591d5ab33 214
be_bryan 0:b74591d5ab33 215 /******************************************************************************
be_bryan 0:b74591d5ab33 216 * INTERRUPTS HANDLING
be_bryan 0:b74591d5ab33 217 ******************************************************************************/
be_bryan 0:b74591d5ab33 218 static inline void uart_irq(uint32_t iir, uint32_t index) {
be_bryan 0:b74591d5ab33 219 // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
be_bryan 0:b74591d5ab33 220 SerialIrq irq_type;
be_bryan 0:b74591d5ab33 221 switch (iir) {
be_bryan 0:b74591d5ab33 222 case 1: irq_type = TxIrq; break;
be_bryan 0:b74591d5ab33 223 case 2: irq_type = RxIrq; break;
be_bryan 0:b74591d5ab33 224 default: return;
be_bryan 0:b74591d5ab33 225 }
be_bryan 0:b74591d5ab33 226
be_bryan 0:b74591d5ab33 227 if (serial_irq_ids[index] != 0)
be_bryan 0:b74591d5ab33 228 irq_handler(serial_irq_ids[index], irq_type);
be_bryan 0:b74591d5ab33 229 }
be_bryan 0:b74591d5ab33 230
be_bryan 0:b74591d5ab33 231 void uart0_irq() {uart_irq((LPC_USART0->STAT & (1 << 2)) ? 2 : 1, 0);}
be_bryan 0:b74591d5ab33 232 void uart1_irq() {uart_irq((LPC_USART1->STAT & (1 << 2)) ? 2 : 1, 1);}
be_bryan 0:b74591d5ab33 233 void uart2_irq() {uart_irq((LPC_USART2->STAT & (1 << 2)) ? 2 : 1, 2);}
be_bryan 0:b74591d5ab33 234
be_bryan 0:b74591d5ab33 235 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
be_bryan 0:b74591d5ab33 236 irq_handler = handler;
be_bryan 0:b74591d5ab33 237 serial_irq_ids[obj->index] = id;
be_bryan 0:b74591d5ab33 238 }
be_bryan 0:b74591d5ab33 239
be_bryan 0:b74591d5ab33 240 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
be_bryan 0:b74591d5ab33 241 IRQn_Type irq_n = (IRQn_Type)0;
be_bryan 0:b74591d5ab33 242 uint32_t vector = 0;
be_bryan 0:b74591d5ab33 243 switch ((int)obj->uart) {
be_bryan 0:b74591d5ab33 244 case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
be_bryan 0:b74591d5ab33 245 case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
be_bryan 0:b74591d5ab33 246 case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
be_bryan 0:b74591d5ab33 247 }
be_bryan 0:b74591d5ab33 248
be_bryan 0:b74591d5ab33 249 if (enable) {
be_bryan 0:b74591d5ab33 250 obj->uart->INTENSET = (1 << ((irq == RxIrq) ? 0 : 2));
be_bryan 0:b74591d5ab33 251 NVIC_SetVector(irq_n, vector);
be_bryan 0:b74591d5ab33 252 NVIC_EnableIRQ(irq_n);
be_bryan 0:b74591d5ab33 253 } else { // disable
be_bryan 0:b74591d5ab33 254 int all_disabled = 0;
be_bryan 0:b74591d5ab33 255 SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
be_bryan 0:b74591d5ab33 256 obj->uart->INTENSET &= ~(1 << ((irq == RxIrq) ? 0 : 2));
be_bryan 0:b74591d5ab33 257 all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0;
be_bryan 0:b74591d5ab33 258 if (all_disabled)
be_bryan 0:b74591d5ab33 259 NVIC_DisableIRQ(irq_n);
be_bryan 0:b74591d5ab33 260 }
be_bryan 0:b74591d5ab33 261 }
be_bryan 0:b74591d5ab33 262
be_bryan 0:b74591d5ab33 263 /******************************************************************************
be_bryan 0:b74591d5ab33 264 * READ/WRITE
be_bryan 0:b74591d5ab33 265 ******************************************************************************/
be_bryan 0:b74591d5ab33 266 int serial_getc(serial_t *obj) {
be_bryan 0:b74591d5ab33 267 while (!serial_readable(obj));
be_bryan 0:b74591d5ab33 268 return obj->uart->RXDATA;
be_bryan 0:b74591d5ab33 269 }
be_bryan 0:b74591d5ab33 270
be_bryan 0:b74591d5ab33 271 void serial_putc(serial_t *obj, int c) {
be_bryan 0:b74591d5ab33 272 while (!serial_writable(obj));
be_bryan 0:b74591d5ab33 273 obj->uart->TXDATA = c;
be_bryan 0:b74591d5ab33 274 }
be_bryan 0:b74591d5ab33 275
be_bryan 0:b74591d5ab33 276 int serial_readable(serial_t *obj) {
be_bryan 0:b74591d5ab33 277 return obj->uart->STAT & RXRDY;
be_bryan 0:b74591d5ab33 278 }
be_bryan 0:b74591d5ab33 279
be_bryan 0:b74591d5ab33 280 int serial_writable(serial_t *obj) {
be_bryan 0:b74591d5ab33 281 return obj->uart->STAT & TXRDY;
be_bryan 0:b74591d5ab33 282 }
be_bryan 0:b74591d5ab33 283
be_bryan 0:b74591d5ab33 284 void serial_clear(serial_t *obj) {
be_bryan 0:b74591d5ab33 285 // [TODO]
be_bryan 0:b74591d5ab33 286 }
be_bryan 0:b74591d5ab33 287
be_bryan 0:b74591d5ab33 288 void serial_pinout_tx(PinName tx) {
be_bryan 0:b74591d5ab33 289
be_bryan 0:b74591d5ab33 290 }
be_bryan 0:b74591d5ab33 291
be_bryan 0:b74591d5ab33 292 void serial_break_set(serial_t *obj) {
be_bryan 0:b74591d5ab33 293 obj->uart->CTRL |= TXBRKEN;
be_bryan 0:b74591d5ab33 294 }
be_bryan 0:b74591d5ab33 295
be_bryan 0:b74591d5ab33 296 void serial_break_clear(serial_t *obj) {
be_bryan 0:b74591d5ab33 297 obj->uart->CTRL &= ~TXBRKEN;
be_bryan 0:b74591d5ab33 298 }
be_bryan 0:b74591d5ab33 299
be_bryan 0:b74591d5ab33 300 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
be_bryan 0:b74591d5ab33 301 const SWM_Map *swm_rts, *swm_cts;
be_bryan 0:b74591d5ab33 302 uint32_t regVal_rts, regVal_cts;
be_bryan 0:b74591d5ab33 303
be_bryan 0:b74591d5ab33 304 swm_rts = &SWM_UART_RTS[obj->index];
be_bryan 0:b74591d5ab33 305 swm_cts = &SWM_UART_CTS[obj->index];
be_bryan 0:b74591d5ab33 306 regVal_rts = LPC_SWM->PINASSIGN[swm_rts->n] & ~(0xFF << swm_rts->offset);
be_bryan 0:b74591d5ab33 307 regVal_cts = LPC_SWM->PINASSIGN[swm_cts->n] & ~(0xFF << swm_cts->offset);
be_bryan 0:b74591d5ab33 308
be_bryan 0:b74591d5ab33 309 if (FlowControlNone == type) {
be_bryan 0:b74591d5ab33 310 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
be_bryan 0:b74591d5ab33 311 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
be_bryan 0:b74591d5ab33 312 obj->uart->CFG &= ~CTSEN;
be_bryan 0:b74591d5ab33 313 return;
be_bryan 0:b74591d5ab33 314 }
be_bryan 0:b74591d5ab33 315 if ((FlowControlRTS == type || FlowControlRTSCTS == type) && (rxflow != NC)) {
be_bryan 0:b74591d5ab33 316 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (rxflow << swm_rts->offset);
be_bryan 0:b74591d5ab33 317 if (FlowControlRTS == type) {
be_bryan 0:b74591d5ab33 318 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
be_bryan 0:b74591d5ab33 319 obj->uart->CFG &= ~CTSEN;
be_bryan 0:b74591d5ab33 320 }
be_bryan 0:b74591d5ab33 321 }
be_bryan 0:b74591d5ab33 322 if ((FlowControlCTS == type || FlowControlRTSCTS == type) && (txflow != NC)) {
be_bryan 0:b74591d5ab33 323 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (txflow << swm_cts->offset);
be_bryan 0:b74591d5ab33 324 obj->uart->CFG |= CTSEN;
be_bryan 0:b74591d5ab33 325 if (FlowControlCTS == type) {
be_bryan 0:b74591d5ab33 326 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
be_bryan 0:b74591d5ab33 327 }
be_bryan 0:b74591d5ab33 328 }
be_bryan 0:b74591d5ab33 329 }
be_bryan 0:b74591d5ab33 330