EL4121 Embedded System / mbed-os

mbed-os

Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_NXP/TARGET_LPC81X/pwmout_api.c@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /* mbed Microcontroller Library
be_bryan 0:b74591d5ab33 2 * Copyright (c) 2006-2013 ARM Limited
be_bryan 0:b74591d5ab33 3 *
be_bryan 0:b74591d5ab33 4 * Licensed under the Apache License, Version 2.0 (the "License");
be_bryan 0:b74591d5ab33 5 * you may not use this file except in compliance with the License.
be_bryan 0:b74591d5ab33 6 * You may obtain a copy of the License at
be_bryan 0:b74591d5ab33 7 *
be_bryan 0:b74591d5ab33 8 * http://www.apache.org/licenses/LICENSE-2.0
be_bryan 0:b74591d5ab33 9 *
be_bryan 0:b74591d5ab33 10 * Unless required by applicable law or agreed to in writing, software
be_bryan 0:b74591d5ab33 11 * distributed under the License is distributed on an "AS IS" BASIS,
be_bryan 0:b74591d5ab33 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan 0:b74591d5ab33 13 * See the License for the specific language governing permissions and
be_bryan 0:b74591d5ab33 14 * limitations under the License.
be_bryan 0:b74591d5ab33 15 */
be_bryan 0:b74591d5ab33 16 #include "mbed_assert.h"
be_bryan 0:b74591d5ab33 17 #include "pwmout_api.h"
be_bryan 0:b74591d5ab33 18 #include "cmsis.h"
be_bryan 0:b74591d5ab33 19 #include "pinmap.h"
be_bryan 0:b74591d5ab33 20 #include "mbed_error.h"
be_bryan 0:b74591d5ab33 21
be_bryan 0:b74591d5ab33 22 // Ported from LPC824 and adapted.
be_bryan 0:b74591d5ab33 23
be_bryan 0:b74591d5ab33 24 #if DEVICE_PWMOUT
be_bryan 0:b74591d5ab33 25
be_bryan 0:b74591d5ab33 26 #define PWM_IRQn SCT_IRQn
be_bryan 0:b74591d5ab33 27
be_bryan 0:b74591d5ab33 28 // Bit flags for used SCT Outputs
be_bryan 0:b74591d5ab33 29 static unsigned char sct_used = 0;
be_bryan 0:b74591d5ab33 30 static int sct_inited = 0;
be_bryan 0:b74591d5ab33 31
be_bryan 0:b74591d5ab33 32 // Find available output channel
be_bryan 0:b74591d5ab33 33 // Max number of PWM outputs is 4 on LPC812
be_bryan 0:b74591d5ab33 34 static int get_available_sct() {
be_bryan 0:b74591d5ab33 35 int i;
be_bryan 0:b74591d5ab33 36
be_bryan 0:b74591d5ab33 37 // Find available output channel 0..3
be_bryan 0:b74591d5ab33 38 // Also need one Match register per channel
be_bryan 0:b74591d5ab33 39 for (i = 0; i < CONFIG_SCT_nOU; i++) {
be_bryan 0:b74591d5ab33 40 if ((sct_used & (1 << i)) == 0)
be_bryan 0:b74591d5ab33 41 return i;
be_bryan 0:b74591d5ab33 42 }
be_bryan 0:b74591d5ab33 43 return -1;
be_bryan 0:b74591d5ab33 44 }
be_bryan 0:b74591d5ab33 45
be_bryan 0:b74591d5ab33 46 // Any Port pin may be used for PWM.
be_bryan 0:b74591d5ab33 47 // Max number of PWM outputs is 4
be_bryan 0:b74591d5ab33 48 void pwmout_init(pwmout_t* obj, PinName pin) {
be_bryan 0:b74591d5ab33 49 MBED_ASSERT(pin != (PinName)NC);
be_bryan 0:b74591d5ab33 50
be_bryan 0:b74591d5ab33 51 int sct_n = get_available_sct();
be_bryan 0:b74591d5ab33 52 if (sct_n == -1) {
be_bryan 0:b74591d5ab33 53 error("No available SCT Output");
be_bryan 0:b74591d5ab33 54 }
be_bryan 0:b74591d5ab33 55
be_bryan 0:b74591d5ab33 56 sct_used |= (1 << sct_n);
be_bryan 0:b74591d5ab33 57
be_bryan 0:b74591d5ab33 58 obj->pwm = (LPC_SCT_TypeDef*)LPC_SCT;
be_bryan 0:b74591d5ab33 59 obj->pwm_ch = sct_n;
be_bryan 0:b74591d5ab33 60
be_bryan 0:b74591d5ab33 61 LPC_SCT_TypeDef* pwm = obj->pwm;
be_bryan 0:b74591d5ab33 62
be_bryan 0:b74591d5ab33 63 // Init SCT on first use
be_bryan 0:b74591d5ab33 64 if (! sct_inited) {
be_bryan 0:b74591d5ab33 65 sct_inited = 1;
be_bryan 0:b74591d5ab33 66
be_bryan 0:b74591d5ab33 67 // Enable the SCT clock
be_bryan 0:b74591d5ab33 68 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
be_bryan 0:b74591d5ab33 69
be_bryan 0:b74591d5ab33 70 // Clear peripheral reset the SCT:
be_bryan 0:b74591d5ab33 71 LPC_SYSCON->PRESETCTRL |= (1 << 8);
be_bryan 0:b74591d5ab33 72
be_bryan 0:b74591d5ab33 73 // Two 16-bit counters, autolimit (ie reset on Match_0)
be_bryan 0:b74591d5ab33 74 pwm->CONFIG |= ((0x3 << 17) | 0x01);
be_bryan 0:b74591d5ab33 75
be_bryan 0:b74591d5ab33 76 // halt and clear the counter
be_bryan 0:b74591d5ab33 77 pwm->CTRL_U |= (1 << 2) | (1 << 3);
be_bryan 0:b74591d5ab33 78
be_bryan 0:b74591d5ab33 79 // System Clock (30 Mhz) -> Prescaler -> us_ticker (1 MHz)
be_bryan 0:b74591d5ab33 80 pwm->CTRL_U &= ~(0x7F << 5);
be_bryan 0:b74591d5ab33 81 pwm->CTRL_U |= (((SystemCoreClock/1000000 - 1) & 0x7F) << 5);
be_bryan 0:b74591d5ab33 82
be_bryan 0:b74591d5ab33 83 pwm->EVENT[0].CTRL = (1 << 12) | 0; // Event_0 on Match_0
be_bryan 0:b74591d5ab33 84 pwm->EVENT[0].STATE = 0xFFFFFFFF; // All states
be_bryan 0:b74591d5ab33 85
be_bryan 0:b74591d5ab33 86 // unhalt the counter:
be_bryan 0:b74591d5ab33 87 // - clearing bit 2 of the CTRL register
be_bryan 0:b74591d5ab33 88 pwm->CTRL_U &= ~(1 << 2);
be_bryan 0:b74591d5ab33 89
be_bryan 0:b74591d5ab33 90 }
be_bryan 0:b74591d5ab33 91
be_bryan 0:b74591d5ab33 92 // LPC81x has only one SCT and 4 Outputs
be_bryan 0:b74591d5ab33 93 // LPC82x has only one SCT and 6 Outputs
be_bryan 0:b74591d5ab33 94 // LPC1549 has 4 SCTs and 16 Outputs
be_bryan 0:b74591d5ab33 95 switch(sct_n) {
be_bryan 0:b74591d5ab33 96 case 0:
be_bryan 0:b74591d5ab33 97 // SCTx_OUT0
be_bryan 0:b74591d5ab33 98 LPC_SWM->PINASSIGN[6] &= ~0xFF000000;
be_bryan 0:b74591d5ab33 99 LPC_SWM->PINASSIGN[6] |= (pin << 24);
be_bryan 0:b74591d5ab33 100 break;
be_bryan 0:b74591d5ab33 101 case 1:
be_bryan 0:b74591d5ab33 102 // SCTx_OUT1
be_bryan 0:b74591d5ab33 103 LPC_SWM->PINASSIGN[7] &= ~0x000000FF;
be_bryan 0:b74591d5ab33 104 LPC_SWM->PINASSIGN[7] |= (pin);
be_bryan 0:b74591d5ab33 105 break;
be_bryan 0:b74591d5ab33 106 case 2:
be_bryan 0:b74591d5ab33 107 // SCTx_OUT2
be_bryan 0:b74591d5ab33 108 LPC_SWM->PINASSIGN[7] &= ~0x0000FF00;
be_bryan 0:b74591d5ab33 109 LPC_SWM->PINASSIGN[7] |= (pin << 8);
be_bryan 0:b74591d5ab33 110 break;
be_bryan 0:b74591d5ab33 111 case 3:
be_bryan 0:b74591d5ab33 112 // SCTx_OUT3
be_bryan 0:b74591d5ab33 113 LPC_SWM->PINASSIGN[7] &= ~0x00FF0000;
be_bryan 0:b74591d5ab33 114 LPC_SWM->PINASSIGN[7] |= (pin << 16);
be_bryan 0:b74591d5ab33 115 break;
be_bryan 0:b74591d5ab33 116 default:
be_bryan 0:b74591d5ab33 117 break;
be_bryan 0:b74591d5ab33 118 }
be_bryan 0:b74591d5ab33 119
be_bryan 0:b74591d5ab33 120 pwm->EVENT[sct_n + 1].CTRL = (1 << 12) | (sct_n + 1); // Event_n on Match_n
be_bryan 0:b74591d5ab33 121 pwm->EVENT[sct_n + 1].STATE = 0xFFFFFFFF; // All states
be_bryan 0:b74591d5ab33 122
be_bryan 0:b74591d5ab33 123 pwm->OUT[sct_n].SET = (1 << 0); // All PWM channels are SET on Event_0
be_bryan 0:b74591d5ab33 124 pwm->OUT[sct_n].CLR = (1 << (sct_n + 1)); // PWM ch is CLRed on Event_(ch+1)
be_bryan 0:b74591d5ab33 125
be_bryan 0:b74591d5ab33 126 // default to 20ms: standard for servos, and fine for e.g. brightness control
be_bryan 0:b74591d5ab33 127 pwmout_period_ms(obj, 20); // 20ms period
be_bryan 0:b74591d5ab33 128 pwmout_write (obj, 0.0); // 0ms pulsewidth, dutycycle 0
be_bryan 0:b74591d5ab33 129 }
be_bryan 0:b74591d5ab33 130
be_bryan 0:b74591d5ab33 131 void pwmout_free(pwmout_t* obj) {
be_bryan 0:b74591d5ab33 132 // PWM channel is now free
be_bryan 0:b74591d5ab33 133 sct_used &= ~(1 << obj->pwm_ch);
be_bryan 0:b74591d5ab33 134
be_bryan 0:b74591d5ab33 135 // Disable the SCT clock when all channels free
be_bryan 0:b74591d5ab33 136 if (sct_used == 0) {
be_bryan 0:b74591d5ab33 137 LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8);
be_bryan 0:b74591d5ab33 138 sct_inited = 0;
be_bryan 0:b74591d5ab33 139 };
be_bryan 0:b74591d5ab33 140 }
be_bryan 0:b74591d5ab33 141
be_bryan 0:b74591d5ab33 142 // Set new dutycycle (0.0 .. 1.0)
be_bryan 0:b74591d5ab33 143 void pwmout_write(pwmout_t* obj, float value) {
be_bryan 0:b74591d5ab33 144 //value is new dutycycle
be_bryan 0:b74591d5ab33 145 if (value < 0.0f) {
be_bryan 0:b74591d5ab33 146 value = 0.0;
be_bryan 0:b74591d5ab33 147 } else if (value > 1.0f) {
be_bryan 0:b74591d5ab33 148 value = 1.0;
be_bryan 0:b74591d5ab33 149 }
be_bryan 0:b74591d5ab33 150
be_bryan 0:b74591d5ab33 151 // Match_0 is PWM period. Compute new endtime of pulse for current channel
be_bryan 0:b74591d5ab33 152 uint32_t t_off = (uint32_t)((float)(obj->pwm->MATCHREL[0].U) * value);
be_bryan 0:b74591d5ab33 153 obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U = t_off; // New endtime
be_bryan 0:b74591d5ab33 154
be_bryan 0:b74591d5ab33 155 // Clear OxRES (conflict resolution register) bit first, effect of simultaneous set and clear on output x
be_bryan 0:b74591d5ab33 156 int offset = (obj->pwm_ch * 2);
be_bryan 0:b74591d5ab33 157 obj->pwm->RES &= ~(0x3 << offset);
be_bryan 0:b74591d5ab33 158
be_bryan 0:b74591d5ab33 159 if (value == 0.0f) { // duty is 0%
be_bryan 0:b74591d5ab33 160 // Clear output
be_bryan 0:b74591d5ab33 161 obj->pwm->RES |= (0x2 << offset);
be_bryan 0:b74591d5ab33 162 // Set CLR event to be same as SET event, makes output to be 0 (low)
be_bryan 0:b74591d5ab33 163 obj->pwm->OUT[(obj->pwm_ch)].CLR = (1 << 0);
be_bryan 0:b74591d5ab33 164 } else {
be_bryan 0:b74591d5ab33 165 // Set output
be_bryan 0:b74591d5ab33 166 obj->pwm->RES |= (0x1 << offset);
be_bryan 0:b74591d5ab33 167 // Use normal CLR event (current SCT ch + 1)
be_bryan 0:b74591d5ab33 168 obj->pwm->OUT[(obj->pwm_ch)].CLR = (1 << ((obj->pwm_ch) + 1));
be_bryan 0:b74591d5ab33 169 }
be_bryan 0:b74591d5ab33 170 }
be_bryan 0:b74591d5ab33 171
be_bryan 0:b74591d5ab33 172 // Get dutycycle (0.0 .. 1.0)
be_bryan 0:b74591d5ab33 173 float pwmout_read(pwmout_t* obj) {
be_bryan 0:b74591d5ab33 174 uint32_t t_period = obj->pwm->MATCHREL[0].U;
be_bryan 0:b74591d5ab33 175
be_bryan 0:b74591d5ab33 176 //Sanity check
be_bryan 0:b74591d5ab33 177 if (t_period == 0) {
be_bryan 0:b74591d5ab33 178 return 0.0;
be_bryan 0:b74591d5ab33 179 };
be_bryan 0:b74591d5ab33 180
be_bryan 0:b74591d5ab33 181 uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U;
be_bryan 0:b74591d5ab33 182 float v = (float)t_off/(float)t_period;
be_bryan 0:b74591d5ab33 183 //Sanity check
be_bryan 0:b74591d5ab33 184 return (v > 1.0f) ? (1.0f) : (v);
be_bryan 0:b74591d5ab33 185 }
be_bryan 0:b74591d5ab33 186
be_bryan 0:b74591d5ab33 187 // Set the PWM period, keeping the duty cycle the same (for this channel only!).
be_bryan 0:b74591d5ab33 188 void pwmout_period(pwmout_t* obj, float seconds){
be_bryan 0:b74591d5ab33 189 pwmout_period_us(obj, seconds * 1000000.0f);
be_bryan 0:b74591d5ab33 190 }
be_bryan 0:b74591d5ab33 191
be_bryan 0:b74591d5ab33 192 // Set the PWM period, keeping the duty cycle the same (for this channel only!).
be_bryan 0:b74591d5ab33 193 void pwmout_period_ms(pwmout_t* obj, int ms) {
be_bryan 0:b74591d5ab33 194 pwmout_period_us(obj, ms * 1000);
be_bryan 0:b74591d5ab33 195 }
be_bryan 0:b74591d5ab33 196
be_bryan 0:b74591d5ab33 197 // Set the PWM period, keeping the duty cycle the same (for this channel only!).
be_bryan 0:b74591d5ab33 198 void pwmout_period_us(pwmout_t* obj, int us) {
be_bryan 0:b74591d5ab33 199
be_bryan 0:b74591d5ab33 200 uint32_t t_period = obj->pwm->MATCHREL[0].U; // Current PWM period
be_bryan 0:b74591d5ab33 201 obj->pwm->MATCHREL[0].U = (uint32_t)us; // New PWM period
be_bryan 0:b74591d5ab33 202
be_bryan 0:b74591d5ab33 203 // Sanity check
be_bryan 0:b74591d5ab33 204 if (t_period == 0) {
be_bryan 0:b74591d5ab33 205 return;
be_bryan 0:b74591d5ab33 206 }
be_bryan 0:b74591d5ab33 207 else {
be_bryan 0:b74591d5ab33 208 int cnt = sct_used;
be_bryan 0:b74591d5ab33 209 int ch = 0;
be_bryan 0:b74591d5ab33 210 // Update match period for exising PWM channels
be_bryan 0:b74591d5ab33 211 do {
be_bryan 0:b74591d5ab33 212 // Get current pulse width
be_bryan 0:b74591d5ab33 213 uint32_t t_off = obj->pwm->MATCHREL[ch + 1].U;
be_bryan 0:b74591d5ab33 214 // Get the duty
be_bryan 0:b74591d5ab33 215 float v = (float)t_off/(float)t_period;
be_bryan 0:b74591d5ab33 216 // Update pulse width for this channel
be_bryan 0:b74591d5ab33 217 obj->pwm->MATCHREL[ch + 1].U = (uint32_t)((float)us * (float)v);
be_bryan 0:b74591d5ab33 218 // Get next used SCT channel
be_bryan 0:b74591d5ab33 219 cnt = cnt >> 1;
be_bryan 0:b74591d5ab33 220 ch++;
be_bryan 0:b74591d5ab33 221 } while (cnt != 0);
be_bryan 0:b74591d5ab33 222 }
be_bryan 0:b74591d5ab33 223 }
be_bryan 0:b74591d5ab33 224
be_bryan 0:b74591d5ab33 225
be_bryan 0:b74591d5ab33 226 //Set pulsewidth
be_bryan 0:b74591d5ab33 227 void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
be_bryan 0:b74591d5ab33 228 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
be_bryan 0:b74591d5ab33 229 }
be_bryan 0:b74591d5ab33 230
be_bryan 0:b74591d5ab33 231 //Set pulsewidth
be_bryan 0:b74591d5ab33 232 void pwmout_pulsewidth_ms(pwmout_t* obj, int ms){
be_bryan 0:b74591d5ab33 233 pwmout_pulsewidth_us(obj, ms * 1000);
be_bryan 0:b74591d5ab33 234 }
be_bryan 0:b74591d5ab33 235
be_bryan 0:b74591d5ab33 236 //Set pulsewidth
be_bryan 0:b74591d5ab33 237 void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
be_bryan 0:b74591d5ab33 238 if (us == 0) { // pulse width is 0
be_bryan 0:b74591d5ab33 239 // Set CLR event to be same as SET event, makes output to be 0 (low)
be_bryan 0:b74591d5ab33 240 obj->pwm->OUT[(obj->pwm_ch)].CLR = (1 << 0);
be_bryan 0:b74591d5ab33 241 } else {
be_bryan 0:b74591d5ab33 242 // Use normal CLR event (current SCT ch + 1)
be_bryan 0:b74591d5ab33 243 obj->pwm->OUT[(obj->pwm_ch)].CLR = (1 << ((obj->pwm_ch) + 1));
be_bryan 0:b74591d5ab33 244 }
be_bryan 0:b74591d5ab33 245 //Should add Sanity check to make sure pulsewidth < period!
be_bryan 0:b74591d5ab33 246 obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U = (uint32_t)us; // New endtime for this channel
be_bryan 0:b74591d5ab33 247 }
be_bryan 0:b74591d5ab33 248
be_bryan 0:b74591d5ab33 249 #endif