EL4121 Embedded System / mbed-os

mbed-os

Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /* mbed Microcontroller Library
be_bryan 0:b74591d5ab33 2 * Copyright (c) 2006-2013 ARM Limited
be_bryan 0:b74591d5ab33 3 *
be_bryan 0:b74591d5ab33 4 * Licensed under the Apache License, Version 2.0 (the "License");
be_bryan 0:b74591d5ab33 5 * you may not use this file except in compliance with the License.
be_bryan 0:b74591d5ab33 6 * You may obtain a copy of the License at
be_bryan 0:b74591d5ab33 7 *
be_bryan 0:b74591d5ab33 8 * http://www.apache.org/licenses/LICENSE-2.0
be_bryan 0:b74591d5ab33 9 *
be_bryan 0:b74591d5ab33 10 * Unless required by applicable law or agreed to in writing, software
be_bryan 0:b74591d5ab33 11 * distributed under the License is distributed on an "AS IS" BASIS,
be_bryan 0:b74591d5ab33 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan 0:b74591d5ab33 13 * See the License for the specific language governing permissions and
be_bryan 0:b74591d5ab33 14 * limitations under the License.
be_bryan 0:b74591d5ab33 15 */
be_bryan 0:b74591d5ab33 16 #include "i2c_api.h"
be_bryan 0:b74591d5ab33 17 #include "cmsis.h"
be_bryan 0:b74591d5ab33 18 #include "pinmap.h"
be_bryan 0:b74591d5ab33 19
be_bryan 0:b74591d5ab33 20 #if DEVICE_I2C
be_bryan 0:b74591d5ab33 21
be_bryan 0:b74591d5ab33 22 static const SWM_Map SWM_I2C_SDA[] = {
be_bryan 0:b74591d5ab33 23 {7, 24},
be_bryan 0:b74591d5ab33 24 };
be_bryan 0:b74591d5ab33 25
be_bryan 0:b74591d5ab33 26 static const SWM_Map SWM_I2C_SCL[] = {
be_bryan 0:b74591d5ab33 27 {8, 0},
be_bryan 0:b74591d5ab33 28 };
be_bryan 0:b74591d5ab33 29
be_bryan 0:b74591d5ab33 30 static uint8_t repeated_start = 0;
be_bryan 0:b74591d5ab33 31
be_bryan 0:b74591d5ab33 32 #define I2C_DAT(x) (x->i2c->MSTDAT)
be_bryan 0:b74591d5ab33 33 #define I2C_STAT(x) ((x->i2c->STAT >> 1) & (0x07))
be_bryan 0:b74591d5ab33 34
be_bryan 0:b74591d5ab33 35 static inline int i2c_status(i2c_t *obj) {
be_bryan 0:b74591d5ab33 36 return I2C_STAT(obj);
be_bryan 0:b74591d5ab33 37 }
be_bryan 0:b74591d5ab33 38
be_bryan 0:b74591d5ab33 39 // Wait until the Serial Interrupt (SI) is set
be_bryan 0:b74591d5ab33 40 static int i2c_wait_SI(i2c_t *obj) {
be_bryan 0:b74591d5ab33 41 int timeout = 0;
be_bryan 0:b74591d5ab33 42 while (!(obj->i2c->STAT & (1 << 0))) {
be_bryan 0:b74591d5ab33 43 timeout++;
be_bryan 0:b74591d5ab33 44 if (timeout > 100000) return -1;
be_bryan 0:b74591d5ab33 45 }
be_bryan 0:b74591d5ab33 46 return 0;
be_bryan 0:b74591d5ab33 47 }
be_bryan 0:b74591d5ab33 48
be_bryan 0:b74591d5ab33 49 static inline void i2c_interface_enable(i2c_t *obj) {
be_bryan 0:b74591d5ab33 50 obj->i2c->CFG |= (1 << 0);
be_bryan 0:b74591d5ab33 51 }
be_bryan 0:b74591d5ab33 52
be_bryan 0:b74591d5ab33 53 static inline void i2c_power_enable(i2c_t *obj) {
be_bryan 0:b74591d5ab33 54 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<5);
be_bryan 0:b74591d5ab33 55 LPC_SYSCON->PRESETCTRL &= ~(0x1<<6);
be_bryan 0:b74591d5ab33 56 LPC_SYSCON->PRESETCTRL |= (0x1<<6);
be_bryan 0:b74591d5ab33 57 }
be_bryan 0:b74591d5ab33 58
be_bryan 0:b74591d5ab33 59 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
be_bryan 0:b74591d5ab33 60 obj->i2c = (LPC_I2C_TypeDef *)LPC_I2C;
be_bryan 0:b74591d5ab33 61
be_bryan 0:b74591d5ab33 62 const SWM_Map *swm;
be_bryan 0:b74591d5ab33 63 uint32_t regVal;
be_bryan 0:b74591d5ab33 64
be_bryan 0:b74591d5ab33 65 swm = &SWM_I2C_SDA[0];
be_bryan 0:b74591d5ab33 66 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
be_bryan 0:b74591d5ab33 67 LPC_SWM->PINASSIGN[swm->n] = regVal | (sda << swm->offset);
be_bryan 0:b74591d5ab33 68
be_bryan 0:b74591d5ab33 69 swm = &SWM_I2C_SCL[0];
be_bryan 0:b74591d5ab33 70 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
be_bryan 0:b74591d5ab33 71 LPC_SWM->PINASSIGN[swm->n] = regVal | (scl << swm->offset);
be_bryan 0:b74591d5ab33 72
be_bryan 0:b74591d5ab33 73 // enable power
be_bryan 0:b74591d5ab33 74 i2c_power_enable(obj);
be_bryan 0:b74591d5ab33 75 // set default frequency at 100k
be_bryan 0:b74591d5ab33 76 i2c_frequency(obj, 100000);
be_bryan 0:b74591d5ab33 77 i2c_interface_enable(obj);
be_bryan 0:b74591d5ab33 78 }
be_bryan 0:b74591d5ab33 79
be_bryan 0:b74591d5ab33 80 //Actually Wrong. Spec says: First store Address in DAT before setting STA !
be_bryan 0:b74591d5ab33 81 //Undefined state when using single byte I2C operations and too much delay
be_bryan 0:b74591d5ab33 82 //between i2c_start and do_i2c_write(Address).
be_bryan 0:b74591d5ab33 83 //Also note that lpc812 will immediately continue reading a byte when Address b0 == 1
be_bryan 0:b74591d5ab33 84 inline int i2c_start(i2c_t *obj) {
be_bryan 0:b74591d5ab33 85 int status = 0;
be_bryan 0:b74591d5ab33 86 if (repeated_start) {
be_bryan 0:b74591d5ab33 87 obj->i2c->MSTCTL = (1 << 1) | (1 << 0);
be_bryan 0:b74591d5ab33 88 repeated_start = 0;
be_bryan 0:b74591d5ab33 89 } else {
be_bryan 0:b74591d5ab33 90 obj->i2c->MSTCTL = (1 << 1);
be_bryan 0:b74591d5ab33 91 }
be_bryan 0:b74591d5ab33 92 return status;
be_bryan 0:b74591d5ab33 93 }
be_bryan 0:b74591d5ab33 94
be_bryan 0:b74591d5ab33 95 //Generate Stop condition and wait until bus is Idle
be_bryan 0:b74591d5ab33 96 //Will also send NAK for previous RD
be_bryan 0:b74591d5ab33 97 inline int i2c_stop(i2c_t *obj) {
be_bryan 0:b74591d5ab33 98 int timeout = 0;
be_bryan 0:b74591d5ab33 99
be_bryan 0:b74591d5ab33 100 obj->i2c->MSTCTL = (1 << 2) | (1 << 0); // STP bit and Continue bit. Sends NAK to complete previous RD
be_bryan 0:b74591d5ab33 101
be_bryan 0:b74591d5ab33 102 //Spin until Ready (b0 == 1)and Status is Idle (b3..b1 == 000)
be_bryan 0:b74591d5ab33 103 while ((obj->i2c->STAT & ((7 << 1) | (1 << 0))) != ((0 << 1) | (1 << 0))) {
be_bryan 0:b74591d5ab33 104 timeout ++;
be_bryan 0:b74591d5ab33 105 if (timeout > 100000) return 1;
be_bryan 0:b74591d5ab33 106 }
be_bryan 0:b74591d5ab33 107
be_bryan 0:b74591d5ab33 108 return 0;
be_bryan 0:b74591d5ab33 109 }
be_bryan 0:b74591d5ab33 110
be_bryan 0:b74591d5ab33 111 static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
be_bryan 0:b74591d5ab33 112 // write the data
be_bryan 0:b74591d5ab33 113 I2C_DAT(obj) = value;
be_bryan 0:b74591d5ab33 114
be_bryan 0:b74591d5ab33 115 if (!addr)
be_bryan 0:b74591d5ab33 116 obj->i2c->MSTCTL = (1 << 0);
be_bryan 0:b74591d5ab33 117
be_bryan 0:b74591d5ab33 118 // wait and return status
be_bryan 0:b74591d5ab33 119 i2c_wait_SI(obj);
be_bryan 0:b74591d5ab33 120 return i2c_status(obj);
be_bryan 0:b74591d5ab33 121 }
be_bryan 0:b74591d5ab33 122
be_bryan 0:b74591d5ab33 123 static inline int i2c_do_read(i2c_t *obj, int last) {
be_bryan 0:b74591d5ab33 124 // wait for it to arrive
be_bryan 0:b74591d5ab33 125 i2c_wait_SI(obj);
be_bryan 0:b74591d5ab33 126 if (!last)
be_bryan 0:b74591d5ab33 127 obj->i2c->MSTCTL = (1 << 0);
be_bryan 0:b74591d5ab33 128
be_bryan 0:b74591d5ab33 129 // return the data
be_bryan 0:b74591d5ab33 130 return (I2C_DAT(obj) & 0xFF);
be_bryan 0:b74591d5ab33 131 }
be_bryan 0:b74591d5ab33 132
be_bryan 0:b74591d5ab33 133 void i2c_frequency(i2c_t *obj, int hz) {
be_bryan 0:b74591d5ab33 134 // No peripheral clock divider on the M0
be_bryan 0:b74591d5ab33 135 uint32_t PCLK = SystemCoreClock;
be_bryan 0:b74591d5ab33 136
be_bryan 0:b74591d5ab33 137 uint32_t clkdiv = PCLK / (hz * 4) - 1;
be_bryan 0:b74591d5ab33 138
be_bryan 0:b74591d5ab33 139 obj->i2c->DIV = clkdiv;
be_bryan 0:b74591d5ab33 140 obj->i2c->MSTTIME = 0;
be_bryan 0:b74591d5ab33 141 }
be_bryan 0:b74591d5ab33 142
be_bryan 0:b74591d5ab33 143 // The I2C does a read or a write as a whole operation
be_bryan 0:b74591d5ab33 144 // There are two types of error conditions it can encounter
be_bryan 0:b74591d5ab33 145 // 1) it can not obtain the bus
be_bryan 0:b74591d5ab33 146 // 2) it gets error responses at part of the transmission
be_bryan 0:b74591d5ab33 147 //
be_bryan 0:b74591d5ab33 148 // We tackle them as follows:
be_bryan 0:b74591d5ab33 149 // 1) we retry until we get the bus. we could have a "timeout" if we can not get it
be_bryan 0:b74591d5ab33 150 // which basically turns it in to a 2)
be_bryan 0:b74591d5ab33 151 // 2) on error, we use the standard error mechanisms to report/debug
be_bryan 0:b74591d5ab33 152 //
be_bryan 0:b74591d5ab33 153 // Therefore an I2C transaction should always complete. If it doesn't it is usually
be_bryan 0:b74591d5ab33 154 // because something is setup wrong (e.g. wiring), and we don't need to programatically
be_bryan 0:b74591d5ab33 155 // check for that
be_bryan 0:b74591d5ab33 156
be_bryan 0:b74591d5ab33 157 //New version WH, Tested OK for Start and Repeated Start
be_bryan 0:b74591d5ab33 158 //Old version was Wrong: Calls i2c_start without setting address, i2c_do_read continues before checking status, status check for wrong value
be_bryan 0:b74591d5ab33 159 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
be_bryan 0:b74591d5ab33 160 int count, status;
be_bryan 0:b74591d5ab33 161
be_bryan 0:b74591d5ab33 162 //Store the address+RD and then generate STA
be_bryan 0:b74591d5ab33 163 I2C_DAT(obj) = address | 0x01;
be_bryan 0:b74591d5ab33 164 i2c_start(obj);
be_bryan 0:b74591d5ab33 165
be_bryan 0:b74591d5ab33 166 // Wait for completion of STA and Sending of SlaveAddress+RD and first Read byte
be_bryan 0:b74591d5ab33 167 i2c_wait_SI(obj);
be_bryan 0:b74591d5ab33 168 status = i2c_status(obj);
be_bryan 0:b74591d5ab33 169 if (status == 0x03) { // NAK on SlaveAddress
be_bryan 0:b74591d5ab33 170 i2c_stop(obj);
be_bryan 0:b74591d5ab33 171 return I2C_ERROR_NO_SLAVE;
be_bryan 0:b74591d5ab33 172 }
be_bryan 0:b74591d5ab33 173
be_bryan 0:b74591d5ab33 174 // Read in all except last byte
be_bryan 0:b74591d5ab33 175 for (count = 0; count < (length-1); count++) {
be_bryan 0:b74591d5ab33 176
be_bryan 0:b74591d5ab33 177 // Wait for it to arrive, note that first byte read after address+RD is already waiting
be_bryan 0:b74591d5ab33 178 i2c_wait_SI(obj);
be_bryan 0:b74591d5ab33 179 status = i2c_status(obj);
be_bryan 0:b74591d5ab33 180 if (status != 0x01) { // RX RDY
be_bryan 0:b74591d5ab33 181 i2c_stop(obj);
be_bryan 0:b74591d5ab33 182 return count;
be_bryan 0:b74591d5ab33 183 }
be_bryan 0:b74591d5ab33 184 data[count] = I2C_DAT(obj) & 0xFF; // Store read byte
be_bryan 0:b74591d5ab33 185
be_bryan 0:b74591d5ab33 186 obj->i2c->MSTCTL = (1 << 0); // Send ACK and Continue to read
be_bryan 0:b74591d5ab33 187 }
be_bryan 0:b74591d5ab33 188
be_bryan 0:b74591d5ab33 189 // Read final byte
be_bryan 0:b74591d5ab33 190 // Wait for it to arrive
be_bryan 0:b74591d5ab33 191 i2c_wait_SI(obj);
be_bryan 0:b74591d5ab33 192
be_bryan 0:b74591d5ab33 193 status = i2c_status(obj);
be_bryan 0:b74591d5ab33 194 if (status != 0x01) { // RX RDY
be_bryan 0:b74591d5ab33 195 i2c_stop(obj);
be_bryan 0:b74591d5ab33 196 return count;
be_bryan 0:b74591d5ab33 197 }
be_bryan 0:b74591d5ab33 198 data[count] = I2C_DAT(obj) & 0xFF; // Store final read byte
be_bryan 0:b74591d5ab33 199
be_bryan 0:b74591d5ab33 200 // If not repeated start, send stop.
be_bryan 0:b74591d5ab33 201 if (stop) {
be_bryan 0:b74591d5ab33 202 i2c_stop(obj); // Also sends NAK for last read byte
be_bryan 0:b74591d5ab33 203 } else {
be_bryan 0:b74591d5ab33 204 repeated_start = 1;
be_bryan 0:b74591d5ab33 205 }
be_bryan 0:b74591d5ab33 206
be_bryan 0:b74591d5ab33 207 return length;
be_bryan 0:b74591d5ab33 208 }
be_bryan 0:b74591d5ab33 209
be_bryan 0:b74591d5ab33 210
be_bryan 0:b74591d5ab33 211
be_bryan 0:b74591d5ab33 212 //New version WH, Tested OK for Start and Repeated Start
be_bryan 0:b74591d5ab33 213 //Old version was Wrong: Calls i2c_start without setting address first
be_bryan 0:b74591d5ab33 214 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
be_bryan 0:b74591d5ab33 215 int i, status;
be_bryan 0:b74591d5ab33 216
be_bryan 0:b74591d5ab33 217 //Store the address+/WR and then generate STA
be_bryan 0:b74591d5ab33 218 I2C_DAT(obj) = address & 0xFE;
be_bryan 0:b74591d5ab33 219 i2c_start(obj);
be_bryan 0:b74591d5ab33 220
be_bryan 0:b74591d5ab33 221 // Wait for completion of STA and Sending of SlaveAddress+/WR
be_bryan 0:b74591d5ab33 222 i2c_wait_SI(obj);
be_bryan 0:b74591d5ab33 223 status = i2c_status(obj);
be_bryan 0:b74591d5ab33 224 if (status == 0x03) { // NAK SlaveAddress
be_bryan 0:b74591d5ab33 225 i2c_stop(obj);
be_bryan 0:b74591d5ab33 226 return I2C_ERROR_NO_SLAVE;
be_bryan 0:b74591d5ab33 227 }
be_bryan 0:b74591d5ab33 228
be_bryan 0:b74591d5ab33 229 //Write all bytes
be_bryan 0:b74591d5ab33 230 for (i=0; i<length; i++) {
be_bryan 0:b74591d5ab33 231 status = i2c_do_write(obj, data[i], 0);
be_bryan 0:b74591d5ab33 232 if (status != 0x02) { // TX RDY. Handles a Slave NAK on datawrite
be_bryan 0:b74591d5ab33 233 i2c_stop(obj);
be_bryan 0:b74591d5ab33 234 return i;
be_bryan 0:b74591d5ab33 235 }
be_bryan 0:b74591d5ab33 236 }
be_bryan 0:b74591d5ab33 237
be_bryan 0:b74591d5ab33 238 // If not repeated start, send stop.
be_bryan 0:b74591d5ab33 239 if (stop) {
be_bryan 0:b74591d5ab33 240 i2c_stop(obj);
be_bryan 0:b74591d5ab33 241 } else {
be_bryan 0:b74591d5ab33 242 repeated_start = 1;
be_bryan 0:b74591d5ab33 243 }
be_bryan 0:b74591d5ab33 244
be_bryan 0:b74591d5ab33 245 return length;
be_bryan 0:b74591d5ab33 246 }
be_bryan 0:b74591d5ab33 247
be_bryan 0:b74591d5ab33 248
be_bryan 0:b74591d5ab33 249
be_bryan 0:b74591d5ab33 250 void i2c_reset(i2c_t *obj) {
be_bryan 0:b74591d5ab33 251 i2c_stop(obj);
be_bryan 0:b74591d5ab33 252 }
be_bryan 0:b74591d5ab33 253
be_bryan 0:b74591d5ab33 254 int i2c_byte_read(i2c_t *obj, int last) {
be_bryan 0:b74591d5ab33 255 return (i2c_do_read(obj, last) & 0xFF);
be_bryan 0:b74591d5ab33 256 }
be_bryan 0:b74591d5ab33 257
be_bryan 0:b74591d5ab33 258 int i2c_byte_write(i2c_t *obj, int data) {
be_bryan 0:b74591d5ab33 259 int ack;
be_bryan 0:b74591d5ab33 260 int status = i2c_do_write(obj, (data & 0xFF), 0);
be_bryan 0:b74591d5ab33 261
be_bryan 0:b74591d5ab33 262 switch(status) {
be_bryan 0:b74591d5ab33 263 case 2:
be_bryan 0:b74591d5ab33 264 ack = 1;
be_bryan 0:b74591d5ab33 265 break;
be_bryan 0:b74591d5ab33 266 default:
be_bryan 0:b74591d5ab33 267 ack = 0;
be_bryan 0:b74591d5ab33 268 break;
be_bryan 0:b74591d5ab33 269 }
be_bryan 0:b74591d5ab33 270
be_bryan 0:b74591d5ab33 271 return ack;
be_bryan 0:b74591d5ab33 272 }
be_bryan 0:b74591d5ab33 273
be_bryan 0:b74591d5ab33 274 #if DEVICE_I2CSLAVE
be_bryan 0:b74591d5ab33 275
be_bryan 0:b74591d5ab33 276 #define I2C_SLVDAT(x) (x->i2c->SLVDAT)
be_bryan 0:b74591d5ab33 277 #define I2C_SLVSTAT(x) ((x->i2c->STAT >> 9) & (0x03))
be_bryan 0:b74591d5ab33 278 #define I2C_SLVSI(x) ((x->i2c->STAT >> 8) & (0x01))
be_bryan 0:b74591d5ab33 279 //#define I2C_SLVCNT(x) (x->i2c->SLVCTL = (1 << 0))
be_bryan 0:b74591d5ab33 280 //#define I2C_SLVNAK(x) (x->i2c->SLVCTL = (1 << 1))
be_bryan 0:b74591d5ab33 281
be_bryan 0:b74591d5ab33 282 #if(0)
be_bryan 0:b74591d5ab33 283 // Wait until the Slave Serial Interrupt (SI) is set
be_bryan 0:b74591d5ab33 284 // Timeout when it takes too long.
be_bryan 0:b74591d5ab33 285 static int i2c_wait_slave_SI(i2c_t *obj) {
be_bryan 0:b74591d5ab33 286 int timeout = 0;
be_bryan 0:b74591d5ab33 287 while (!(obj->i2c->STAT & (1 << 8))) {
be_bryan 0:b74591d5ab33 288 timeout++;
be_bryan 0:b74591d5ab33 289 if (timeout > 100000) return -1;
be_bryan 0:b74591d5ab33 290 }
be_bryan 0:b74591d5ab33 291 return 0;
be_bryan 0:b74591d5ab33 292 }
be_bryan 0:b74591d5ab33 293 #endif
be_bryan 0:b74591d5ab33 294
be_bryan 0:b74591d5ab33 295 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
be_bryan 0:b74591d5ab33 296
be_bryan 0:b74591d5ab33 297 if (enable_slave) {
be_bryan 0:b74591d5ab33 298 // obj->i2c->CFG &= ~(1 << 0); //Disable Master mode
be_bryan 0:b74591d5ab33 299 obj->i2c->CFG |= (1 << 1); //Enable Slave mode
be_bryan 0:b74591d5ab33 300 }
be_bryan 0:b74591d5ab33 301 else {
be_bryan 0:b74591d5ab33 302 // obj->i2c->CFG |= (1 << 0); //Enable Master mode
be_bryan 0:b74591d5ab33 303 obj->i2c->CFG &= ~(1 << 1); //Disable Slave mode
be_bryan 0:b74591d5ab33 304 }
be_bryan 0:b74591d5ab33 305 }
be_bryan 0:b74591d5ab33 306
be_bryan 0:b74591d5ab33 307 // Wait for next I2C event and find out what is going on
be_bryan 0:b74591d5ab33 308 //
be_bryan 0:b74591d5ab33 309 int i2c_slave_receive(i2c_t *obj) {
be_bryan 0:b74591d5ab33 310 int addr;
be_bryan 0:b74591d5ab33 311
be_bryan 0:b74591d5ab33 312 // Check if there is any data pending
be_bryan 0:b74591d5ab33 313 if (! I2C_SLVSI(obj)) {
be_bryan 0:b74591d5ab33 314 return 0; //NoData
be_bryan 0:b74591d5ab33 315 };
be_bryan 0:b74591d5ab33 316
be_bryan 0:b74591d5ab33 317 // Check State
be_bryan 0:b74591d5ab33 318 switch(I2C_SLVSTAT(obj)) {
be_bryan 0:b74591d5ab33 319 case 0x0: // Slave address plus R/W received
be_bryan 0:b74591d5ab33 320 // At least one of the four slave addresses has been matched by hardware.
be_bryan 0:b74591d5ab33 321 // You can figure out which address by checking Slave address match Index in STAT register.
be_bryan 0:b74591d5ab33 322
be_bryan 0:b74591d5ab33 323 // Get the received address
be_bryan 0:b74591d5ab33 324 addr = I2C_SLVDAT(obj) & 0xFF;
be_bryan 0:b74591d5ab33 325 // Send ACK on address and Continue
be_bryan 0:b74591d5ab33 326 obj->i2c->SLVCTL = (1 << 0);
be_bryan 0:b74591d5ab33 327
be_bryan 0:b74591d5ab33 328 if (addr == 0x00) {
be_bryan 0:b74591d5ab33 329 return 2; //WriteGeneral
be_bryan 0:b74591d5ab33 330 }
be_bryan 0:b74591d5ab33 331 //check the RW bit
be_bryan 0:b74591d5ab33 332 if ((addr & 0x01) == 0x01) {
be_bryan 0:b74591d5ab33 333 return 1; //ReadAddressed
be_bryan 0:b74591d5ab33 334 }
be_bryan 0:b74591d5ab33 335 else {
be_bryan 0:b74591d5ab33 336 return 3; //WriteAddressed
be_bryan 0:b74591d5ab33 337 }
be_bryan 0:b74591d5ab33 338 //break;
be_bryan 0:b74591d5ab33 339
be_bryan 0:b74591d5ab33 340 case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
be_bryan 0:b74591d5ab33 341 // Oops, should never get here...
be_bryan 0:b74591d5ab33 342 obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data, try to recover...
be_bryan 0:b74591d5ab33 343 return 0; //NoData
be_bryan 0:b74591d5ab33 344
be_bryan 0:b74591d5ab33 345 case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
be_bryan 0:b74591d5ab33 346 // Oops, should never get here...
be_bryan 0:b74591d5ab33 347 I2C_SLVDAT(obj) = 0xFF; // Send dummy data for transmission
be_bryan 0:b74591d5ab33 348 obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover...
be_bryan 0:b74591d5ab33 349 return 0; //NoData
be_bryan 0:b74591d5ab33 350
be_bryan 0:b74591d5ab33 351 case 0x3: // Reserved.
be_bryan 0:b74591d5ab33 352 default: // Oops, should never get here...
be_bryan 0:b74591d5ab33 353 obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover...
be_bryan 0:b74591d5ab33 354 return 0; //NoData
be_bryan 0:b74591d5ab33 355 //break;
be_bryan 0:b74591d5ab33 356 } //switch status
be_bryan 0:b74591d5ab33 357 }
be_bryan 0:b74591d5ab33 358
be_bryan 0:b74591d5ab33 359 // The dedicated I2C Slave byte read and byte write functions need to be called
be_bryan 0:b74591d5ab33 360 // from 'common' mbed I2CSlave API for devices that have separate Master and
be_bryan 0:b74591d5ab33 361 // Slave engines such as the lpc812 and lpc1549.
be_bryan 0:b74591d5ab33 362
be_bryan 0:b74591d5ab33 363 //Called when Slave is addressed for Write, Slave will receive Data in polling mode
be_bryan 0:b74591d5ab33 364 //Parameter last=1 means received byte will be NACKed.
be_bryan 0:b74591d5ab33 365 int i2c_slave_byte_read(i2c_t *obj, int last) {
be_bryan 0:b74591d5ab33 366 int data;
be_bryan 0:b74591d5ab33 367
be_bryan 0:b74591d5ab33 368 // Wait for data
be_bryan 0:b74591d5ab33 369 while (!I2C_SLVSI(obj)); // Wait forever
be_bryan 0:b74591d5ab33 370 //if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
be_bryan 0:b74591d5ab33 371
be_bryan 0:b74591d5ab33 372 // Dont bother to check State, were not returning it anyhow..
be_bryan 0:b74591d5ab33 373 //if (I2C_SLVSTAT(obj)) == 0x01) {
be_bryan 0:b74591d5ab33 374 // Slave receive. Received data is available (Slave Receiver mode).
be_bryan 0:b74591d5ab33 375 //};
be_bryan 0:b74591d5ab33 376
be_bryan 0:b74591d5ab33 377 data = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data
be_bryan 0:b74591d5ab33 378 if (last) {
be_bryan 0:b74591d5ab33 379 obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data and Continue
be_bryan 0:b74591d5ab33 380 }
be_bryan 0:b74591d5ab33 381 else {
be_bryan 0:b74591d5ab33 382 obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read
be_bryan 0:b74591d5ab33 383 }
be_bryan 0:b74591d5ab33 384
be_bryan 0:b74591d5ab33 385 return data;
be_bryan 0:b74591d5ab33 386 }
be_bryan 0:b74591d5ab33 387
be_bryan 0:b74591d5ab33 388
be_bryan 0:b74591d5ab33 389 //Called when Slave is addressed for Read, Slave will send Data in polling mode
be_bryan 0:b74591d5ab33 390 //
be_bryan 0:b74591d5ab33 391 int i2c_slave_byte_write(i2c_t *obj, int data) {
be_bryan 0:b74591d5ab33 392
be_bryan 0:b74591d5ab33 393 // Wait until Ready
be_bryan 0:b74591d5ab33 394 while (!I2C_SLVSI(obj)); // Wait forever
be_bryan 0:b74591d5ab33 395 // if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
be_bryan 0:b74591d5ab33 396
be_bryan 0:b74591d5ab33 397 // Check State
be_bryan 0:b74591d5ab33 398 switch(I2C_SLVSTAT(obj)) {
be_bryan 0:b74591d5ab33 399 case 0x0: // Slave address plus R/W received
be_bryan 0:b74591d5ab33 400 // At least one of the four slave addresses has been matched by hardware.
be_bryan 0:b74591d5ab33 401 // You can figure out which address by checking Slave address match Index in STAT register.
be_bryan 0:b74591d5ab33 402 // I2C Restart occurred
be_bryan 0:b74591d5ab33 403 return -1;
be_bryan 0:b74591d5ab33 404 //break;
be_bryan 0:b74591d5ab33 405 case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
be_bryan 0:b74591d5ab33 406 // Should not get here...
be_bryan 0:b74591d5ab33 407 return -2;
be_bryan 0:b74591d5ab33 408 //break;
be_bryan 0:b74591d5ab33 409 case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
be_bryan 0:b74591d5ab33 410 I2C_SLVDAT(obj) = data & 0xFF; // Store the data for transmission
be_bryan 0:b74591d5ab33 411 obj->i2c->SLVCTL = (1 << 0); // Continue to send
be_bryan 0:b74591d5ab33 412
be_bryan 0:b74591d5ab33 413 return 1;
be_bryan 0:b74591d5ab33 414 //break;
be_bryan 0:b74591d5ab33 415 case 0x3: // Reserved.
be_bryan 0:b74591d5ab33 416 default:
be_bryan 0:b74591d5ab33 417 // Should not get here...
be_bryan 0:b74591d5ab33 418 return -3;
be_bryan 0:b74591d5ab33 419 //break;
be_bryan 0:b74591d5ab33 420 } // switch status
be_bryan 0:b74591d5ab33 421 }
be_bryan 0:b74591d5ab33 422
be_bryan 0:b74591d5ab33 423
be_bryan 0:b74591d5ab33 424 //Called when Slave is addressed for Write, Slave will receive Data in polling mode
be_bryan 0:b74591d5ab33 425 //Parameter length (>=1) is the maximum allowable number of bytes. All bytes will be ACKed.
be_bryan 0:b74591d5ab33 426 int i2c_slave_read(i2c_t *obj, char *data, int length) {
be_bryan 0:b74591d5ab33 427 int count=0;
be_bryan 0:b74591d5ab33 428
be_bryan 0:b74591d5ab33 429 // Read and ACK all expected bytes
be_bryan 0:b74591d5ab33 430 while (count < length) {
be_bryan 0:b74591d5ab33 431 // Wait for data
be_bryan 0:b74591d5ab33 432 while (!I2C_SLVSI(obj)); // Wait forever
be_bryan 0:b74591d5ab33 433 // if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
be_bryan 0:b74591d5ab33 434
be_bryan 0:b74591d5ab33 435 // Check State
be_bryan 0:b74591d5ab33 436 switch(I2C_SLVSTAT(obj)) {
be_bryan 0:b74591d5ab33 437 case 0x0: // Slave address plus R/W received
be_bryan 0:b74591d5ab33 438 // At least one of the four slave addresses has been matched by hardware.
be_bryan 0:b74591d5ab33 439 // You can figure out which address by checking Slave address match Index in STAT register.
be_bryan 0:b74591d5ab33 440 // I2C Restart occurred
be_bryan 0:b74591d5ab33 441 return -1;
be_bryan 0:b74591d5ab33 442 //break;
be_bryan 0:b74591d5ab33 443
be_bryan 0:b74591d5ab33 444 case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
be_bryan 0:b74591d5ab33 445 data[count] = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data
be_bryan 0:b74591d5ab33 446 obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read
be_bryan 0:b74591d5ab33 447 break;
be_bryan 0:b74591d5ab33 448
be_bryan 0:b74591d5ab33 449 case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
be_bryan 0:b74591d5ab33 450 case 0x3: // Reserved.
be_bryan 0:b74591d5ab33 451 default: // Should never get here...
be_bryan 0:b74591d5ab33 452 return -2;
be_bryan 0:b74591d5ab33 453 //break;
be_bryan 0:b74591d5ab33 454 } // switch status
be_bryan 0:b74591d5ab33 455
be_bryan 0:b74591d5ab33 456 count++;
be_bryan 0:b74591d5ab33 457 } // for all bytes
be_bryan 0:b74591d5ab33 458
be_bryan 0:b74591d5ab33 459 return count; // Received the expected number of bytes
be_bryan 0:b74591d5ab33 460 }
be_bryan 0:b74591d5ab33 461
be_bryan 0:b74591d5ab33 462
be_bryan 0:b74591d5ab33 463 //Called when Slave is addressed for Read, Slave will send Data in polling mode
be_bryan 0:b74591d5ab33 464 //Parameter length (>=1) is the maximum number of bytes. Exit when Slave byte is NACKed.
be_bryan 0:b74591d5ab33 465 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
be_bryan 0:b74591d5ab33 466 int count;
be_bryan 0:b74591d5ab33 467
be_bryan 0:b74591d5ab33 468 // Send and all bytes or Exit on NAK
be_bryan 0:b74591d5ab33 469 for (count=0; count < length; count++) {
be_bryan 0:b74591d5ab33 470 // Wait until Ready for data
be_bryan 0:b74591d5ab33 471 while (!I2C_SLVSI(obj)); // Wait forever
be_bryan 0:b74591d5ab33 472 // if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
be_bryan 0:b74591d5ab33 473
be_bryan 0:b74591d5ab33 474 // Check State
be_bryan 0:b74591d5ab33 475 switch(I2C_SLVSTAT(obj)) {
be_bryan 0:b74591d5ab33 476 case 0x0: // Slave address plus R/W received
be_bryan 0:b74591d5ab33 477 // At least one of the four slave addresses has been matched by hardware.
be_bryan 0:b74591d5ab33 478 // You can figure out which address by checking Slave address match Index in STAT register.
be_bryan 0:b74591d5ab33 479 // I2C Restart occurred
be_bryan 0:b74591d5ab33 480 return -1;
be_bryan 0:b74591d5ab33 481 //break;
be_bryan 0:b74591d5ab33 482 case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
be_bryan 0:b74591d5ab33 483 // Should not get here...
be_bryan 0:b74591d5ab33 484 return -2;
be_bryan 0:b74591d5ab33 485 //break;
be_bryan 0:b74591d5ab33 486 case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
be_bryan 0:b74591d5ab33 487 I2C_SLVDAT(obj) = data[count] & 0xFF; // Store the data for transmission
be_bryan 0:b74591d5ab33 488 obj->i2c->SLVCTL = (1 << 0); // Continue to send
be_bryan 0:b74591d5ab33 489 break;
be_bryan 0:b74591d5ab33 490 case 0x3: // Reserved.
be_bryan 0:b74591d5ab33 491 default:
be_bryan 0:b74591d5ab33 492 // Should not get here...
be_bryan 0:b74591d5ab33 493 return -3;
be_bryan 0:b74591d5ab33 494 //break;
be_bryan 0:b74591d5ab33 495 } // switch status
be_bryan 0:b74591d5ab33 496 } // for all bytes
be_bryan 0:b74591d5ab33 497
be_bryan 0:b74591d5ab33 498 return length; // Transmitted the max number of bytes
be_bryan 0:b74591d5ab33 499 }
be_bryan 0:b74591d5ab33 500
be_bryan 0:b74591d5ab33 501
be_bryan 0:b74591d5ab33 502 // Set the four slave addresses.
be_bryan 0:b74591d5ab33 503 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
be_bryan 0:b74591d5ab33 504 obj->i2c->SLVADR0 = (address & 0xFE); // Store address in address 0 register
be_bryan 0:b74591d5ab33 505 obj->i2c->SLVADR1 = (0x00 & 0xFE); // Store general call write address in address 1 register
be_bryan 0:b74591d5ab33 506 obj->i2c->SLVADR2 = (0x01); // Disable address 2 register
be_bryan 0:b74591d5ab33 507 obj->i2c->SLVADR3 = (0x01); // Disable address 3 register
be_bryan 0:b74591d5ab33 508 obj->i2c->SLVQUAL0 = (mask & 0xFE); // Qualifier mask for address 0 register. Any maskbit that is 1 will always be a match
be_bryan 0:b74591d5ab33 509 }
be_bryan 0:b74591d5ab33 510
be_bryan 0:b74591d5ab33 511 #endif
be_bryan 0:b74591d5ab33 512
be_bryan 0:b74591d5ab33 513 #endif