EL4121 Embedded System / mbed-os

mbed-os

Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /* mbed Microcontroller Library
be_bryan 0:b74591d5ab33 2 * Copyright (c) 2006-2013 ARM Limited
be_bryan 0:b74591d5ab33 3 *
be_bryan 0:b74591d5ab33 4 * Licensed under the Apache License, Version 2.0 (the "License");
be_bryan 0:b74591d5ab33 5 * you may not use this file except in compliance with the License.
be_bryan 0:b74591d5ab33 6 * You may obtain a copy of the License at
be_bryan 0:b74591d5ab33 7 *
be_bryan 0:b74591d5ab33 8 * http://www.apache.org/licenses/LICENSE-2.0
be_bryan 0:b74591d5ab33 9 *
be_bryan 0:b74591d5ab33 10 * Unless required by applicable law or agreed to in writing, software
be_bryan 0:b74591d5ab33 11 * distributed under the License is distributed on an "AS IS" BASIS,
be_bryan 0:b74591d5ab33 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan 0:b74591d5ab33 13 * See the License for the specific language governing permissions and
be_bryan 0:b74591d5ab33 14 * limitations under the License.
be_bryan 0:b74591d5ab33 15 *
be_bryan 0:b74591d5ab33 16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
be_bryan 0:b74591d5ab33 17 */
be_bryan 0:b74591d5ab33 18 #include <stddef.h>
be_bryan 0:b74591d5ab33 19 #include "gpio_irq_api.h"
be_bryan 0:b74591d5ab33 20 #include "mbed_error.h"
be_bryan 0:b74591d5ab33 21 #include "cmsis.h"
be_bryan 0:b74591d5ab33 22
be_bryan 0:b74591d5ab33 23 /* The LPC43xx implements GPIO pin and group interrupts. Any pin in the
be_bryan 0:b74591d5ab33 24 * 8 32-bit GPIO ports can interrupt. On group interrupts a pin can
be_bryan 0:b74591d5ab33 25 * only interrupt on the rising or falling edge, not both as required
be_bryan 0:b74591d5ab33 26 * by mbed. Also, group interrupts can't be cleared individually.
be_bryan 0:b74591d5ab33 27 * This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
be_bryan 0:b74591d5ab33 28 * A future implementation may provide group interrupt support.
be_bryan 0:b74591d5ab33 29 */
be_bryan 0:b74591d5ab33 30 #if !defined(CORE_M0)
be_bryan 0:b74591d5ab33 31 #define CHANNEL_MAX 8
be_bryan 0:b74591d5ab33 32 #else
be_bryan 0:b74591d5ab33 33 #define CHANNEL_MAX 1
be_bryan 0:b74591d5ab33 34 #endif
be_bryan 0:b74591d5ab33 35
be_bryan 0:b74591d5ab33 36 static uint32_t channel_ids[CHANNEL_MAX] = {0};
be_bryan 0:b74591d5ab33 37 static uint8_t channel = 0;
be_bryan 0:b74591d5ab33 38 static gpio_irq_handler irq_handler;
be_bryan 0:b74591d5ab33 39
be_bryan 0:b74591d5ab33 40 static void handle_interrupt_in(void) {
be_bryan 0:b74591d5ab33 41 uint32_t rise = LPC_GPIO_PIN_INT->RISE;
be_bryan 0:b74591d5ab33 42 uint32_t fall = LPC_GPIO_PIN_INT->FALL;
be_bryan 0:b74591d5ab33 43 uint32_t pmask;
be_bryan 0:b74591d5ab33 44 int i;
be_bryan 0:b74591d5ab33 45
be_bryan 0:b74591d5ab33 46 for (i = 0; i < CHANNEL_MAX; i++) {
be_bryan 0:b74591d5ab33 47 pmask = (1 << i);
be_bryan 0:b74591d5ab33 48 if (rise & pmask) {
be_bryan 0:b74591d5ab33 49 /* Rising edge interrupts */
be_bryan 0:b74591d5ab33 50 if (channel_ids[i] != 0) {
be_bryan 0:b74591d5ab33 51 irq_handler(channel_ids[i], IRQ_RISE);
be_bryan 0:b74591d5ab33 52 }
be_bryan 0:b74591d5ab33 53 /* Clear rising edge detected */
be_bryan 0:b74591d5ab33 54 LPC_GPIO_PIN_INT->RISE = pmask;
be_bryan 0:b74591d5ab33 55 }
be_bryan 0:b74591d5ab33 56 if (fall & pmask) {
be_bryan 0:b74591d5ab33 57 /* Falling edge interrupts */
be_bryan 0:b74591d5ab33 58 if (channel_ids[i] != 0) {
be_bryan 0:b74591d5ab33 59 irq_handler(channel_ids[i], IRQ_FALL);
be_bryan 0:b74591d5ab33 60 }
be_bryan 0:b74591d5ab33 61 /* Clear falling edge detected */
be_bryan 0:b74591d5ab33 62 LPC_GPIO_PIN_INT->FALL = pmask;
be_bryan 0:b74591d5ab33 63 }
be_bryan 0:b74591d5ab33 64 }
be_bryan 0:b74591d5ab33 65 }
be_bryan 0:b74591d5ab33 66
be_bryan 0:b74591d5ab33 67 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
be_bryan 0:b74591d5ab33 68 uint32_t portnum, pinnum; //, pmask;
be_bryan 0:b74591d5ab33 69
be_bryan 0:b74591d5ab33 70 if (pin == NC) return -1;
be_bryan 0:b74591d5ab33 71
be_bryan 0:b74591d5ab33 72 irq_handler = handler;
be_bryan 0:b74591d5ab33 73
be_bryan 0:b74591d5ab33 74 /* Set port and pin numbers */
be_bryan 0:b74591d5ab33 75 obj->port = portnum = MBED_GPIO_PORT(pin);
be_bryan 0:b74591d5ab33 76 obj->pin = pinnum = MBED_GPIO_PIN(pin);
be_bryan 0:b74591d5ab33 77
be_bryan 0:b74591d5ab33 78 /* Add to channel table */
be_bryan 0:b74591d5ab33 79 channel_ids[channel] = id;
be_bryan 0:b74591d5ab33 80 obj->ch = channel;
be_bryan 0:b74591d5ab33 81
be_bryan 0:b74591d5ab33 82 /* Clear rising and falling edge detection */
be_bryan 0:b74591d5ab33 83 //pmask = (1 << channel);
be_bryan 0:b74591d5ab33 84 //LPC_GPIO_PIN_INT->IST = pmask;
be_bryan 0:b74591d5ab33 85
be_bryan 0:b74591d5ab33 86 /* Set SCU */
be_bryan 0:b74591d5ab33 87 if (channel < 4) {
be_bryan 0:b74591d5ab33 88 LPC_SCU->PINTSEL0 &= ~(0xFF << (portnum << 3));
be_bryan 0:b74591d5ab33 89 LPC_SCU->PINTSEL0 |= (((portnum << 5) | pinnum) << (channel << 3));
be_bryan 0:b74591d5ab33 90 } else {
be_bryan 0:b74591d5ab33 91 LPC_SCU->PINTSEL1 &= ~(0xFF << ((portnum - 4) << 3));
be_bryan 0:b74591d5ab33 92 LPC_SCU->PINTSEL1 |= (((portnum << 5) | pinnum) << ((channel - 4) << 3));
be_bryan 0:b74591d5ab33 93 }
be_bryan 0:b74591d5ab33 94
be_bryan 0:b74591d5ab33 95 #if !defined(CORE_M0)
be_bryan 0:b74591d5ab33 96 NVIC_SetVector((IRQn_Type)(PIN_INT0_IRQn + channel), (uint32_t)handle_interrupt_in);
be_bryan 0:b74591d5ab33 97 NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + channel));
be_bryan 0:b74591d5ab33 98 #else
be_bryan 0:b74591d5ab33 99 NVIC_SetVector((IRQn_Type)PIN_INT4_IRQn, (uint32_t)handle_interrupt_in);
be_bryan 0:b74591d5ab33 100 NVIC_EnableIRQ((IRQn_Type)PIN_INT4_IRQn);
be_bryan 0:b74591d5ab33 101 #endif
be_bryan 0:b74591d5ab33 102
be_bryan 0:b74591d5ab33 103 // Increment channel number
be_bryan 0:b74591d5ab33 104 channel++;
be_bryan 0:b74591d5ab33 105 channel %= CHANNEL_MAX;
be_bryan 0:b74591d5ab33 106
be_bryan 0:b74591d5ab33 107 return 0;
be_bryan 0:b74591d5ab33 108 }
be_bryan 0:b74591d5ab33 109
be_bryan 0:b74591d5ab33 110 void gpio_irq_free(gpio_irq_t *obj) {
be_bryan 0:b74591d5ab33 111 channel_ids[obj->ch] = 0;
be_bryan 0:b74591d5ab33 112 }
be_bryan 0:b74591d5ab33 113
be_bryan 0:b74591d5ab33 114 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
be_bryan 0:b74591d5ab33 115 uint32_t pmask;
be_bryan 0:b74591d5ab33 116
be_bryan 0:b74591d5ab33 117 /* Clear pending interrupts */
be_bryan 0:b74591d5ab33 118 pmask = (1 << obj->ch);
be_bryan 0:b74591d5ab33 119 LPC_GPIO_PIN_INT->IST = pmask;
be_bryan 0:b74591d5ab33 120
be_bryan 0:b74591d5ab33 121 /* Configure pin interrupt */
be_bryan 0:b74591d5ab33 122 LPC_GPIO_PIN_INT->ISEL &= ~pmask;
be_bryan 0:b74591d5ab33 123 if (event == IRQ_RISE) {
be_bryan 0:b74591d5ab33 124 /* Rising edge interrupts */
be_bryan 0:b74591d5ab33 125 if (enable) {
be_bryan 0:b74591d5ab33 126 LPC_GPIO_PIN_INT->SIENR |= pmask;
be_bryan 0:b74591d5ab33 127 } else {
be_bryan 0:b74591d5ab33 128 LPC_GPIO_PIN_INT->CIENR |= pmask;
be_bryan 0:b74591d5ab33 129 }
be_bryan 0:b74591d5ab33 130 } else {
be_bryan 0:b74591d5ab33 131 /* Falling edge interrupts */
be_bryan 0:b74591d5ab33 132 if (enable) {
be_bryan 0:b74591d5ab33 133 LPC_GPIO_PIN_INT->SIENF |= pmask;
be_bryan 0:b74591d5ab33 134 } else {
be_bryan 0:b74591d5ab33 135 LPC_GPIO_PIN_INT->CIENF |= pmask;
be_bryan 0:b74591d5ab33 136 }
be_bryan 0:b74591d5ab33 137 }
be_bryan 0:b74591d5ab33 138 }
be_bryan 0:b74591d5ab33 139
be_bryan 0:b74591d5ab33 140 void gpio_irq_enable(gpio_irq_t *obj) {
be_bryan 0:b74591d5ab33 141 #if !defined(CORE_M0)
be_bryan 0:b74591d5ab33 142 NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch));
be_bryan 0:b74591d5ab33 143 #else
be_bryan 0:b74591d5ab33 144 NVIC_EnableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch));
be_bryan 0:b74591d5ab33 145 #endif
be_bryan 0:b74591d5ab33 146 }
be_bryan 0:b74591d5ab33 147
be_bryan 0:b74591d5ab33 148 void gpio_irq_disable(gpio_irq_t *obj) {
be_bryan 0:b74591d5ab33 149 #if !defined(CORE_M0)
be_bryan 0:b74591d5ab33 150 NVIC_DisableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch));
be_bryan 0:b74591d5ab33 151 #else
be_bryan 0:b74591d5ab33 152 NVIC_DisableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch));
be_bryan 0:b74591d5ab33 153 #endif
be_bryan 0:b74591d5ab33 154 }