EL4121 Embedded System / mbed-os

mbed-os

Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /* mbed Microcontroller Library
be_bryan 0:b74591d5ab33 2 * Copyright (c) 2006-2015 ARM Limited
be_bryan 0:b74591d5ab33 3 *
be_bryan 0:b74591d5ab33 4 * Licensed under the Apache License, Version 2.0 (the "License");
be_bryan 0:b74591d5ab33 5 * you may not use this file except in compliance with the License.
be_bryan 0:b74591d5ab33 6 * You may obtain a copy of the License at
be_bryan 0:b74591d5ab33 7 *
be_bryan 0:b74591d5ab33 8 * http://www.apache.org/licenses/LICENSE-2.0
be_bryan 0:b74591d5ab33 9 *
be_bryan 0:b74591d5ab33 10 * Unless required by applicable law or agreed to in writing, software
be_bryan 0:b74591d5ab33 11 * distributed under the License is distributed on an "AS IS" BASIS,
be_bryan 0:b74591d5ab33 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan 0:b74591d5ab33 13 * See the License for the specific language governing permissions and
be_bryan 0:b74591d5ab33 14 * limitations under the License.
be_bryan 0:b74591d5ab33 15 *
be_bryan 0:b74591d5ab33 16 * Contribution by Nitin Bhaskar(nitin.bhaskar.27.09@gmail.com)
be_bryan 0:b74591d5ab33 17 */
be_bryan 0:b74591d5ab33 18 #include "ethernet_api.h"
be_bryan 0:b74591d5ab33 19
be_bryan 0:b74591d5ab33 20 #include <string.h>
be_bryan 0:b74591d5ab33 21 #include "cmsis.h"
be_bryan 0:b74591d5ab33 22 #include "mbed_interface.h"
be_bryan 0:b74591d5ab33 23 #include "mbed_toolchain.h"
be_bryan 0:b74591d5ab33 24 #include "mbed_error.h"
be_bryan 0:b74591d5ab33 25 #include "pinmap.h"
be_bryan 0:b74591d5ab33 26
be_bryan 0:b74591d5ab33 27 #define NEW_LOGIC 0
be_bryan 0:b74591d5ab33 28 #define NEW_ETH_BUFFER 0
be_bryan 0:b74591d5ab33 29
be_bryan 0:b74591d5ab33 30 #if NEW_ETH_BUFFER
be_bryan 0:b74591d5ab33 31
be_bryan 0:b74591d5ab33 32 #define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets)
be_bryan 0:b74591d5ab33 33 #define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets)
be_bryan 0:b74591d5ab33 34
be_bryan 0:b74591d5ab33 35 #define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size
be_bryan 0:b74591d5ab33 36 #define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length)
be_bryan 0:b74591d5ab33 37
be_bryan 0:b74591d5ab33 38 #else
be_bryan 0:b74591d5ab33 39
be_bryan 0:b74591d5ab33 40 // Memfree calculation:
be_bryan 0:b74591d5ab33 41 // (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
be_bryan 0:b74591d5ab33 42 // (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
be_bryan 0:b74591d5ab33 43 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
be_bryan 0:b74591d5ab33 44 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
be_bryan 0:b74591d5ab33 45 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
be_bryan 0:b74591d5ab33 46 //#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
be_bryan 0:b74591d5ab33 47
be_bryan 0:b74591d5ab33 48 //#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
be_bryan 0:b74591d5ab33 49 #define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */
be_bryan 0:b74591d5ab33 50 #define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */
be_bryan 0:b74591d5ab33 51
be_bryan 0:b74591d5ab33 52 const int ethernet_MTU_SIZE = 0x300;
be_bryan 0:b74591d5ab33 53
be_bryan 0:b74591d5ab33 54 #endif
be_bryan 0:b74591d5ab33 55
be_bryan 0:b74591d5ab33 56 #define ETHERNET_ADDR_SIZE 6
be_bryan 0:b74591d5ab33 57
be_bryan 0:b74591d5ab33 58 /* Descriptors Fields bits */
be_bryan 0:b74591d5ab33 59 #define TRDES_OWN_BIT (1U<<31) /* Own bit in RDES0 & TDES0 */
be_bryan 0:b74591d5ab33 60 #define RX_END_RING (1<<15) /* Receive End of Ring bit in RDES1 */
be_bryan 0:b74591d5ab33 61 #define RX_NXTDESC_FLAG (1<<14) /* Second Address Chained bit in RDES1 */
be_bryan 0:b74591d5ab33 62 #define TX_LAST_SEGM (1<<29) /* Last Segment bit in TDES0 */
be_bryan 0:b74591d5ab33 63 #define TX_FIRST_SEGM (1<<28) /* First Segment bit in TDES0 */
be_bryan 0:b74591d5ab33 64 #define TX_END_RING (1<<21) /* Transmit End of Ring bit in TDES0 */
be_bryan 0:b74591d5ab33 65 #define TX_NXTDESC_FLAG (1<<20) /* Second Address Chained bit in TDES0 */
be_bryan 0:b74591d5ab33 66
be_bryan 0:b74591d5ab33 67 PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */
be_bryan 0:b74591d5ab33 68 unsigned int Status;
be_bryan 0:b74591d5ab33 69 unsigned int Ctrl;
be_bryan 0:b74591d5ab33 70 unsigned int BufAddr1;
be_bryan 0:b74591d5ab33 71 unsigned int NextDescAddr;
be_bryan 0:b74591d5ab33 72 };
be_bryan 0:b74591d5ab33 73 typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
be_bryan 0:b74591d5ab33 74
be_bryan 0:b74591d5ab33 75 PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */
be_bryan 0:b74591d5ab33 76 unsigned int Status;
be_bryan 0:b74591d5ab33 77 unsigned int Ctrl;
be_bryan 0:b74591d5ab33 78 unsigned int BufAddr1;
be_bryan 0:b74591d5ab33 79 unsigned int NextDescAddr;
be_bryan 0:b74591d5ab33 80 };
be_bryan 0:b74591d5ab33 81 typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
be_bryan 0:b74591d5ab33 82
be_bryan 0:b74591d5ab33 83 /* ETHMODE RMII SELECT */
be_bryan 0:b74591d5ab33 84 #define RMII_SELECT 0x04
be_bryan 0:b74591d5ab33 85 /* define to tell PHY about write operation */
be_bryan 0:b74591d5ab33 86 #define MII_WRITE (1 << 1)
be_bryan 0:b74591d5ab33 87 /* define to tell PHY about read operation */
be_bryan 0:b74591d5ab33 88 #define MII_READ (0 << 1)
be_bryan 0:b74591d5ab33 89 /* define to enable duplex mode */
be_bryan 0:b74591d5ab33 90 #define MAC_DUPLEX_MODE (1 << 11)
be_bryan 0:b74591d5ab33 91
be_bryan 0:b74591d5ab33 92 /* MAC_FRAME_FILTER register bit defines */
be_bryan 0:b74591d5ab33 93 #define MAC_FRAME_FILTER_PR (1 << 0) /* Promiscuous Mode */
be_bryan 0:b74591d5ab33 94 #define MAC_FRAME_FILTER_RA (1UL << 31) /* Receive all */
be_bryan 0:b74591d5ab33 95
be_bryan 0:b74591d5ab33 96 /* MAC_CONFIG register bit defines */
be_bryan 0:b74591d5ab33 97 #define MAC_CONFIG_RE (1 << 2) /* Receiver enable */
be_bryan 0:b74591d5ab33 98 #define MAC_CONFIG_TE (1 << 3) /* Transmitter Enable */
be_bryan 0:b74591d5ab33 99
be_bryan 0:b74591d5ab33 100 /* DMA_OP_MODE register bit defines */
be_bryan 0:b74591d5ab33 101 #define DMA_OP_MODE_SSR (1 << 1) /* Start/stop receive */
be_bryan 0:b74591d5ab33 102 #define DMA_OP_MODE_SST (1 << 13) /* Start/Stop Transmission Command */
be_bryan 0:b74591d5ab33 103
be_bryan 0:b74591d5ab33 104 /* DMA_INT_EN register bit defines */
be_bryan 0:b74591d5ab33 105 #define DMA_INT_EN_TIE (1 << 0) /* Transmit interrupt enable */
be_bryan 0:b74591d5ab33 106 #define DMA_INT_EN_TSE (1 << 1) /* Transmit stopped enable */
be_bryan 0:b74591d5ab33 107 #define DMA_INT_EN_TUE (1 << 2) /* Transmit buffer unavailable enable */
be_bryan 0:b74591d5ab33 108 #define DMA_INT_EN_TJE (1 << 3) /* Transmit jabber timeout enable */
be_bryan 0:b74591d5ab33 109 #define DMA_INT_EN_OVE (1 << 4) /* Overflow interrupt enable */
be_bryan 0:b74591d5ab33 110 #define DMA_INT_EN_UNE (1 << 5) /* Underflow interrupt enable */
be_bryan 0:b74591d5ab33 111 #define DMA_INT_EN_RIE (1 << 6) /* Receive interrupt enable */
be_bryan 0:b74591d5ab33 112 #define DMA_INT_EN_RUE (1 << 7) /* Receive buffer unavailable enable */
be_bryan 0:b74591d5ab33 113 #define DMA_INT_EN_RSE (1 << 8) /* Received stopped enable */
be_bryan 0:b74591d5ab33 114 #define DMA_INT_EN_RWE (1 << 9) /* Receive watchdog timeout enable */
be_bryan 0:b74591d5ab33 115 #define DMA_INT_EN_ETE (1 << 10) /* Early transmit interrupt enable */
be_bryan 0:b74591d5ab33 116 #define DMA_INT_EN_FBE (1 << 13) /* Fatal bus error enable */
be_bryan 0:b74591d5ab33 117 #define DMA_INT_EN_ERE (1 << 14) /* Early receive interrupt enable */
be_bryan 0:b74591d5ab33 118 #define DMA_INT_EN_AIE (1 << 15) /* Abnormal interrupt summary enable */
be_bryan 0:b74591d5ab33 119 #define DMA_INT_EN_NIE (1 << 16) /* Normal interrupt summary enable */
be_bryan 0:b74591d5ab33 120
be_bryan 0:b74591d5ab33 121
be_bryan 0:b74591d5ab33 122
be_bryan 0:b74591d5ab33 123 /* PHY Support Register */
be_bryan 0:b74591d5ab33 124 #define SUPP_SPEED 0x00004000 /* Reduced MII Logic Current Speed */
be_bryan 0:b74591d5ab33 125 //#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
be_bryan 0:b74591d5ab33 126 #define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
be_bryan 0:b74591d5ab33 127
be_bryan 0:b74591d5ab33 128 /* MII Management Command Register */
be_bryan 0:b74591d5ab33 129 #define MCMD_READ 0x00000001 /* MII Read */
be_bryan 0:b74591d5ab33 130 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
be_bryan 0:b74591d5ab33 131
be_bryan 0:b74591d5ab33 132 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
be_bryan 0:b74591d5ab33 133 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
be_bryan 0:b74591d5ab33 134
be_bryan 0:b74591d5ab33 135 /* MII Management Address Register */
be_bryan 0:b74591d5ab33 136 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
be_bryan 0:b74591d5ab33 137 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
be_bryan 0:b74591d5ab33 138
be_bryan 0:b74591d5ab33 139 /* MII Management Indicators Register */
be_bryan 0:b74591d5ab33 140 #define MIND_BUSY 0x00000001 /* MII is Busy */
be_bryan 0:b74591d5ab33 141 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
be_bryan 0:b74591d5ab33 142 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
be_bryan 0:b74591d5ab33 143 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
be_bryan 0:b74591d5ab33 144
be_bryan 0:b74591d5ab33 145 /* DP83848C PHY Registers */
be_bryan 0:b74591d5ab33 146 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
be_bryan 0:b74591d5ab33 147 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
be_bryan 0:b74591d5ab33 148 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
be_bryan 0:b74591d5ab33 149 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
be_bryan 0:b74591d5ab33 150 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
be_bryan 0:b74591d5ab33 151 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
be_bryan 0:b74591d5ab33 152 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
be_bryan 0:b74591d5ab33 153 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
be_bryan 0:b74591d5ab33 154
be_bryan 0:b74591d5ab33 155 /* PHY Extended Registers */
be_bryan 0:b74591d5ab33 156 #define PHY_REG_STS 0x10 /* Status Register */
be_bryan 0:b74591d5ab33 157 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
be_bryan 0:b74591d5ab33 158 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
be_bryan 0:b74591d5ab33 159 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
be_bryan 0:b74591d5ab33 160 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
be_bryan 0:b74591d5ab33 161 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
be_bryan 0:b74591d5ab33 162 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
be_bryan 0:b74591d5ab33 163 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
be_bryan 0:b74591d5ab33 164 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
be_bryan 0:b74591d5ab33 165 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
be_bryan 0:b74591d5ab33 166 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
be_bryan 0:b74591d5ab33 167 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
be_bryan 0:b74591d5ab33 168
be_bryan 0:b74591d5ab33 169 #define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
be_bryan 0:b74591d5ab33 170
be_bryan 0:b74591d5ab33 171 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
be_bryan 0:b74591d5ab33 172 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
be_bryan 0:b74591d5ab33 173 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
be_bryan 0:b74591d5ab33 174 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
be_bryan 0:b74591d5ab33 175 #define PHY_AUTO_NEG 0x1000 /* Select Auto Negotiation */
be_bryan 0:b74591d5ab33 176
be_bryan 0:b74591d5ab33 177 #define DP83848C_DEF_ADR 0x01 /* Default PHY device address */
be_bryan 0:b74591d5ab33 178 #define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
be_bryan 0:b74591d5ab33 179
be_bryan 0:b74591d5ab33 180 #define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
be_bryan 0:b74591d5ab33 181
be_bryan 0:b74591d5ab33 182 #define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
be_bryan 0:b74591d5ab33 183 #define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
be_bryan 0:b74591d5ab33 184 #define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
be_bryan 0:b74591d5ab33 185
be_bryan 0:b74591d5ab33 186 #define PHY_BMCR_RESET 0x8000 /* PHY Reset */
be_bryan 0:b74591d5ab33 187
be_bryan 0:b74591d5ab33 188 #define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
be_bryan 0:b74591d5ab33 189
be_bryan 0:b74591d5ab33 190 #define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
be_bryan 0:b74591d5ab33 191 #define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
be_bryan 0:b74591d5ab33 192
be_bryan 0:b74591d5ab33 193 static int phy_read(unsigned int PhyReg);
be_bryan 0:b74591d5ab33 194 static int phy_write(unsigned int PhyReg, unsigned short Data);
be_bryan 0:b74591d5ab33 195
be_bryan 0:b74591d5ab33 196 static void txdscr_init(void);
be_bryan 0:b74591d5ab33 197 static void rxdscr_init(void);
be_bryan 0:b74591d5ab33 198
be_bryan 0:b74591d5ab33 199 #if defined (__ICCARM__)
be_bryan 0:b74591d5ab33 200 # define AHBSRAM1
be_bryan 0:b74591d5ab33 201 #elif defined(TOOLCHAIN_GCC_CR)
be_bryan 0:b74591d5ab33 202 # define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
be_bryan 0:b74591d5ab33 203 #else
be_bryan 0:b74591d5ab33 204 # define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned))
be_bryan 0:b74591d5ab33 205 #endif
be_bryan 0:b74591d5ab33 206
be_bryan 0:b74591d5ab33 207 AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
be_bryan 0:b74591d5ab33 208 AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
be_bryan 0:b74591d5ab33 209 AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
be_bryan 0:b74591d5ab33 210 AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
be_bryan 0:b74591d5ab33 211
be_bryan 0:b74591d5ab33 212 #ifndef min
be_bryan 0:b74591d5ab33 213 #define min(x, y) (((x)<(y))?(x):(y))
be_bryan 0:b74591d5ab33 214 #endif
be_bryan 0:b74591d5ab33 215
be_bryan 0:b74591d5ab33 216 static uint32_t phy_id = 0;
be_bryan 0:b74591d5ab33 217 static uint32_t TxDescIndex = 0;
be_bryan 0:b74591d5ab33 218 static uint32_t RxDescIndex = 0;
be_bryan 0:b74591d5ab33 219 static uint32_t RxOffset = 0;
be_bryan 0:b74591d5ab33 220
be_bryan 0:b74591d5ab33 221 /*----------------------------------------------------------------------------
be_bryan 0:b74591d5ab33 222 Ethernet Device initialize
be_bryan 0:b74591d5ab33 223 *----------------------------------------------------------------------------*/
be_bryan 0:b74591d5ab33 224 int ethernet_init()
be_bryan 0:b74591d5ab33 225 {
be_bryan 0:b74591d5ab33 226 int regv, tout;
be_bryan 0:b74591d5ab33 227 char mac[ETHERNET_ADDR_SIZE];
be_bryan 0:b74591d5ab33 228
be_bryan 0:b74591d5ab33 229 pin_function(PC_0, (SCU_MODE_INACT | FUNC3)); /* Enable ENET RX CLK */
be_bryan 0:b74591d5ab33 230 pin_function(P1_19, (SCU_MODE_INACT | FUNC0)); /* Enable ENET TX CLK */
be_bryan 0:b74591d5ab33 231
be_bryan 0:b74591d5ab33 232 /* Ethernet pinmuxing */
be_bryan 0:b74591d5ab33 233 pin_function(P2_0, SCU_PINIO_FAST | FUNC7); /* ENET_MDC */
be_bryan 0:b74591d5ab33 234 pin_function(P1_17, SCU_PINIO_FAST | FUNC3); /* ENET_MDIO */
be_bryan 0:b74591d5ab33 235 pin_function(P1_18, SCU_PINIO_FAST | FUNC3); /* ENET_TXD0 */
be_bryan 0:b74591d5ab33 236 pin_function(P1_20, SCU_PINIO_FAST | FUNC3); /* ENET_TXD1 */
be_bryan 0:b74591d5ab33 237 pin_function(P1_19, SCU_PINIO_FAST | FUNC0); /* ENET_REF */
be_bryan 0:b74591d5ab33 238 pin_function(P0_1, SCU_PINIO_FAST | FUNC6); /* ENET_TX_EN */
be_bryan 0:b74591d5ab33 239 pin_function(P1_15, SCU_PINIO_FAST | FUNC3); /* ENET_RXD0 */
be_bryan 0:b74591d5ab33 240 pin_function(P0_0, SCU_PINIO_FAST | FUNC2); /* ENET_RXD1 */
be_bryan 0:b74591d5ab33 241 pin_function(P1_16, SCU_PINIO_FAST | FUNC3); /* ENET_CRS */
be_bryan 0:b74591d5ab33 242 pin_function(PC_9, SCU_PINIO_FAST | FUNC3); /* ENET_RX_ER */
be_bryan 0:b74591d5ab33 243 pin_function(P1_16, SCU_PINIO_FAST | FUNC7); /* ENET_RXDV */
be_bryan 0:b74591d5ab33 244
be_bryan 0:b74591d5ab33 245 LPC_CREG->CREG6 |= RMII_SELECT;
be_bryan 0:b74591d5ab33 246
be_bryan 0:b74591d5ab33 247 /* perform RGU soft reset */
be_bryan 0:b74591d5ab33 248 LPC_RGU->RESET_CTRL0 = 1 << 22;
be_bryan 0:b74591d5ab33 249 LPC_RGU->RESET_CTRL0 = 0;
be_bryan 0:b74591d5ab33 250
be_bryan 0:b74591d5ab33 251 /* Wait until reset is performed */
be_bryan 0:b74591d5ab33 252 while(1) {
be_bryan 0:b74591d5ab33 253 if (LPC_RGU->RESET_ACTIVE_STATUS0 & (1 << 22))
be_bryan 0:b74591d5ab33 254 break;
be_bryan 0:b74591d5ab33 255 }
be_bryan 0:b74591d5ab33 256
be_bryan 0:b74591d5ab33 257 /* Reset MAC DMA Controller */
be_bryan 0:b74591d5ab33 258 LPC_ETHERNET->DMA_BUS_MODE |= 0x01;
be_bryan 0:b74591d5ab33 259 while(LPC_ETHERNET->DMA_BUS_MODE & 0x01);
be_bryan 0:b74591d5ab33 260
be_bryan 0:b74591d5ab33 261 phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */
be_bryan 0:b74591d5ab33 262
be_bryan 0:b74591d5ab33 263 for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */
be_bryan 0:b74591d5ab33 264 regv = phy_read(PHY_REG_BMCR);
be_bryan 0:b74591d5ab33 265 if(regv < 0 || tout == 0) {
be_bryan 0:b74591d5ab33 266 return -1; /* Error */
be_bryan 0:b74591d5ab33 267 }
be_bryan 0:b74591d5ab33 268 if(!(regv & PHY_BMCR_RESET)) {
be_bryan 0:b74591d5ab33 269 break; /* Reset complete. */
be_bryan 0:b74591d5ab33 270 }
be_bryan 0:b74591d5ab33 271 }
be_bryan 0:b74591d5ab33 272
be_bryan 0:b74591d5ab33 273 phy_id = (phy_read(PHY_REG_IDR1) << 16);
be_bryan 0:b74591d5ab33 274 phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
be_bryan 0:b74591d5ab33 275
be_bryan 0:b74591d5ab33 276 if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
be_bryan 0:b74591d5ab33 277 error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
be_bryan 0:b74591d5ab33 278 }
be_bryan 0:b74591d5ab33 279
be_bryan 0:b74591d5ab33 280 ethernet_set_link(-1, 0);
be_bryan 0:b74591d5ab33 281
be_bryan 0:b74591d5ab33 282 /* Set the Ethernet MAC Address registers */
be_bryan 0:b74591d5ab33 283 ethernet_address(mac);
be_bryan 0:b74591d5ab33 284 LPC_ETHERNET->MAC_ADDR0_HIGH = (mac[5] << 8) | mac[4];
be_bryan 0:b74591d5ab33 285 LPC_ETHERNET->MAC_ADDR0_LOW = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0];
be_bryan 0:b74591d5ab33 286
be_bryan 0:b74591d5ab33 287 txdscr_init(); /* initialize DMA TX Descriptor */
be_bryan 0:b74591d5ab33 288 rxdscr_init(); /* initialize DMA RX Descriptor */
be_bryan 0:b74591d5ab33 289
be_bryan 0:b74591d5ab33 290 /* Configure Filter */
be_bryan 0:b74591d5ab33 291 LPC_ETHERNET->MAC_FRAME_FILTER = MAC_FRAME_FILTER_PR | MAC_FRAME_FILTER_RA;
be_bryan 0:b74591d5ab33 292
be_bryan 0:b74591d5ab33 293 /* Enable Receiver and Transmitter */
be_bryan 0:b74591d5ab33 294 LPC_ETHERNET->MAC_CONFIG |= (MAC_CONFIG_RE | MAC_CONFIG_TE);
be_bryan 0:b74591d5ab33 295
be_bryan 0:b74591d5ab33 296 //LPC_ETHERNET->DMA_INT_EN = DMA_INT_EN_NIE | DMA_INT_EN_RIE | DMA_INT_EN_TJE; /* Enable EMAC interrupts. */
be_bryan 0:b74591d5ab33 297
be_bryan 0:b74591d5ab33 298 /* Start Transmission & Receive processes */
be_bryan 0:b74591d5ab33 299 LPC_ETHERNET->DMA_OP_MODE |= (DMA_OP_MODE_SST | DMA_OP_MODE_SSR);
be_bryan 0:b74591d5ab33 300
be_bryan 0:b74591d5ab33 301 return 0;
be_bryan 0:b74591d5ab33 302 }
be_bryan 0:b74591d5ab33 303
be_bryan 0:b74591d5ab33 304 /*----------------------------------------------------------------------------
be_bryan 0:b74591d5ab33 305 Ethernet Device Uninitialize
be_bryan 0:b74591d5ab33 306 *----------------------------------------------------------------------------*/
be_bryan 0:b74591d5ab33 307 void ethernet_free()
be_bryan 0:b74591d5ab33 308 {
be_bryan 0:b74591d5ab33 309 }
be_bryan 0:b74591d5ab33 310
be_bryan 0:b74591d5ab33 311 /*----------------------------------------------------------------------------
be_bryan 0:b74591d5ab33 312 Ethernet write
be_bryan 0:b74591d5ab33 313 *----------------------------------------------------------------------------*/
be_bryan 0:b74591d5ab33 314 int ethernet_write(const char *data, int slen)
be_bryan 0:b74591d5ab33 315 {
be_bryan 0:b74591d5ab33 316 if (slen > ETH_FRAG_SIZE)
be_bryan 0:b74591d5ab33 317 return -1;
be_bryan 0:b74591d5ab33 318
be_bryan 0:b74591d5ab33 319 txdesc[TxDescIndex].Ctrl = slen;
be_bryan 0:b74591d5ab33 320 memcpy((void *)txdesc[TxDescIndex].BufAddr1, data, slen);
be_bryan 0:b74591d5ab33 321 return slen;
be_bryan 0:b74591d5ab33 322 }
be_bryan 0:b74591d5ab33 323
be_bryan 0:b74591d5ab33 324 /*----------------------------------------------------------------------------
be_bryan 0:b74591d5ab33 325 Ethernet Send
be_bryan 0:b74591d5ab33 326 *----------------------------------------------------------------------------*/
be_bryan 0:b74591d5ab33 327 int ethernet_send()
be_bryan 0:b74591d5ab33 328 {
be_bryan 0:b74591d5ab33 329 int s = txdesc[TxDescIndex].Ctrl;
be_bryan 0:b74591d5ab33 330 txdesc[TxDescIndex].Status |= TRDES_OWN_BIT;
be_bryan 0:b74591d5ab33 331 LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 1; // Wake Up the DMA if it's in Suspended Mode
be_bryan 0:b74591d5ab33 332 TxDescIndex++;
be_bryan 0:b74591d5ab33 333 if (TxDescIndex == NUM_TX_FRAG)
be_bryan 0:b74591d5ab33 334 TxDescIndex = 0;
be_bryan 0:b74591d5ab33 335
be_bryan 0:b74591d5ab33 336 return s;
be_bryan 0:b74591d5ab33 337 }
be_bryan 0:b74591d5ab33 338
be_bryan 0:b74591d5ab33 339 /*----------------------------------------------------------------------------
be_bryan 0:b74591d5ab33 340 Ethernet receive
be_bryan 0:b74591d5ab33 341 *----------------------------------------------------------------------------*/
be_bryan 0:b74591d5ab33 342 int ethernet_receive()
be_bryan 0:b74591d5ab33 343 {
be_bryan 0:b74591d5ab33 344 int i, slen = 0;
be_bryan 0:b74591d5ab33 345 for (i = RxDescIndex;; i++) {
be_bryan 0:b74591d5ab33 346 if (rxdesc[i].Status & TRDES_OWN_BIT)
be_bryan 0:b74591d5ab33 347 return (slen - RxOffset);
be_bryan 0:b74591d5ab33 348 else
be_bryan 0:b74591d5ab33 349 slen += (rxdesc[i].Status >> 16) & 0x03FFF;
be_bryan 0:b74591d5ab33 350 }
be_bryan 0:b74591d5ab33 351 return 0;
be_bryan 0:b74591d5ab33 352 }
be_bryan 0:b74591d5ab33 353
be_bryan 0:b74591d5ab33 354
be_bryan 0:b74591d5ab33 355 /*----------------------------------------------------------------------------
be_bryan 0:b74591d5ab33 356 Ethernet read
be_bryan 0:b74591d5ab33 357 *----------------------------------------------------------------------------*/
be_bryan 0:b74591d5ab33 358 int ethernet_read(char *data, int dlen)
be_bryan 0:b74591d5ab33 359 {
be_bryan 0:b74591d5ab33 360 int copylen;
be_bryan 0:b74591d5ab33 361 uint32_t *pSrc = (uint32_t *)rxdesc[RxDescIndex].BufAddr1;
be_bryan 0:b74591d5ab33 362 copylen = (rxdesc[RxDescIndex].Status >> 16) & 0x03FFF;
be_bryan 0:b74591d5ab33 363 if (rxdesc[RxDescIndex].Status & TRDES_OWN_BIT || (dlen + RxOffset) > copylen)
be_bryan 0:b74591d5ab33 364 return -1;
be_bryan 0:b74591d5ab33 365
be_bryan 0:b74591d5ab33 366 if ((dlen + RxOffset) == copylen) {
be_bryan 0:b74591d5ab33 367 memcpy(&pSrc[RxOffset], data, copylen);
be_bryan 0:b74591d5ab33 368 rxdesc[RxDescIndex].Status = TRDES_OWN_BIT;
be_bryan 0:b74591d5ab33 369 RxDescIndex++;
be_bryan 0:b74591d5ab33 370 RxOffset = 0;
be_bryan 0:b74591d5ab33 371 if (RxDescIndex == NUM_RX_FRAG)
be_bryan 0:b74591d5ab33 372 RxDescIndex = 0;
be_bryan 0:b74591d5ab33 373 } else if ((dlen + RxOffset) < copylen) {
be_bryan 0:b74591d5ab33 374 copylen = dlen;
be_bryan 0:b74591d5ab33 375 memcpy(&pSrc[RxOffset], data, copylen);
be_bryan 0:b74591d5ab33 376 RxOffset += dlen;
be_bryan 0:b74591d5ab33 377 }
be_bryan 0:b74591d5ab33 378 return copylen;
be_bryan 0:b74591d5ab33 379 }
be_bryan 0:b74591d5ab33 380
be_bryan 0:b74591d5ab33 381 int ethernet_link(void)
be_bryan 0:b74591d5ab33 382 {
be_bryan 0:b74591d5ab33 383
be_bryan 0:b74591d5ab33 384 if (phy_id == DP83848C_ID) {
be_bryan 0:b74591d5ab33 385 return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
be_bryan 0:b74591d5ab33 386 } else { // LAN8720_ID
be_bryan 0:b74591d5ab33 387 return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
be_bryan 0:b74591d5ab33 388 }
be_bryan 0:b74591d5ab33 389 }
be_bryan 0:b74591d5ab33 390
be_bryan 0:b74591d5ab33 391 static int phy_write(unsigned int PhyReg, unsigned short Data)
be_bryan 0:b74591d5ab33 392 {
be_bryan 0:b74591d5ab33 393 unsigned int timeOut;
be_bryan 0:b74591d5ab33 394
be_bryan 0:b74591d5ab33 395 while(LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY);
be_bryan 0:b74591d5ab33 396 LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | MII_WRITE;
be_bryan 0:b74591d5ab33 397 LPC_ETHERNET->MAC_MII_DATA = Data;
be_bryan 0:b74591d5ab33 398 LPC_ETHERNET->MAC_MII_ADDR |= MIND_BUSY; // Start PHY Write Cycle
be_bryan 0:b74591d5ab33 399
be_bryan 0:b74591d5ab33 400 /* Wait utill operation completed */
be_bryan 0:b74591d5ab33 401 for (timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) {
be_bryan 0:b74591d5ab33 402 if ((LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY) == 0) {
be_bryan 0:b74591d5ab33 403 break;
be_bryan 0:b74591d5ab33 404 }
be_bryan 0:b74591d5ab33 405 }
be_bryan 0:b74591d5ab33 406
be_bryan 0:b74591d5ab33 407 return -1;
be_bryan 0:b74591d5ab33 408 }
be_bryan 0:b74591d5ab33 409
be_bryan 0:b74591d5ab33 410 static int phy_read(unsigned int PhyReg)
be_bryan 0:b74591d5ab33 411 {
be_bryan 0:b74591d5ab33 412 unsigned int timeOut;
be_bryan 0:b74591d5ab33 413
be_bryan 0:b74591d5ab33 414 while(LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY);
be_bryan 0:b74591d5ab33 415 LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | MII_READ;
be_bryan 0:b74591d5ab33 416 LPC_ETHERNET->MAC_MII_ADDR |= MIND_BUSY;
be_bryan 0:b74591d5ab33 417
be_bryan 0:b74591d5ab33 418 for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */
be_bryan 0:b74591d5ab33 419 if((LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY) == 0) {
be_bryan 0:b74591d5ab33 420 return LPC_ETHERNET->MAC_MII_DATA; /* Return a 16-bit value. */
be_bryan 0:b74591d5ab33 421 }
be_bryan 0:b74591d5ab33 422 }
be_bryan 0:b74591d5ab33 423
be_bryan 0:b74591d5ab33 424 return -1;
be_bryan 0:b74591d5ab33 425 }
be_bryan 0:b74591d5ab33 426
be_bryan 0:b74591d5ab33 427 static void txdscr_init()
be_bryan 0:b74591d5ab33 428 {
be_bryan 0:b74591d5ab33 429 int i;
be_bryan 0:b74591d5ab33 430
be_bryan 0:b74591d5ab33 431 for(i = 0; i < NUM_TX_FRAG; i++) {
be_bryan 0:b74591d5ab33 432 txdesc[i].Status = TX_LAST_SEGM | TX_FIRST_SEGM;;
be_bryan 0:b74591d5ab33 433 txdesc[i].Ctrl = 0;
be_bryan 0:b74591d5ab33 434 txdesc[i].BufAddr1 = (uint32_t)&txbuf[i];
be_bryan 0:b74591d5ab33 435 if (i == (NUM_TX_FRAG - 1)) {
be_bryan 0:b74591d5ab33 436 txdesc[i].Status |= TX_END_RING;
be_bryan 0:b74591d5ab33 437 }
be_bryan 0:b74591d5ab33 438 }
be_bryan 0:b74591d5ab33 439
be_bryan 0:b74591d5ab33 440 LPC_ETHERNET->DMA_TRANS_DES_ADDR = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */
be_bryan 0:b74591d5ab33 441 }
be_bryan 0:b74591d5ab33 442
be_bryan 0:b74591d5ab33 443
be_bryan 0:b74591d5ab33 444 static void rxdscr_init()
be_bryan 0:b74591d5ab33 445 {
be_bryan 0:b74591d5ab33 446 int i;
be_bryan 0:b74591d5ab33 447
be_bryan 0:b74591d5ab33 448 for(i = 0; i < NUM_RX_FRAG; i++) {
be_bryan 0:b74591d5ab33 449 rxdesc[i].Status = TRDES_OWN_BIT;
be_bryan 0:b74591d5ab33 450 rxdesc[i].Ctrl = ETH_FRAG_SIZE;
be_bryan 0:b74591d5ab33 451 rxdesc[i].BufAddr1 = (uint32_t)&rxbuf[i];
be_bryan 0:b74591d5ab33 452 if (i == (NUM_RX_FRAG - 1)) {
be_bryan 0:b74591d5ab33 453 rxdesc[i].Ctrl |= RX_END_RING;
be_bryan 0:b74591d5ab33 454 }
be_bryan 0:b74591d5ab33 455 }
be_bryan 0:b74591d5ab33 456
be_bryan 0:b74591d5ab33 457 LPC_ETHERNET->DMA_REC_DES_ADDR = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */
be_bryan 0:b74591d5ab33 458 }
be_bryan 0:b74591d5ab33 459
be_bryan 0:b74591d5ab33 460 void ethernet_address(char *mac)
be_bryan 0:b74591d5ab33 461 {
be_bryan 0:b74591d5ab33 462 mbed_mac_address(mac);
be_bryan 0:b74591d5ab33 463 }
be_bryan 0:b74591d5ab33 464
be_bryan 0:b74591d5ab33 465 void ethernet_set_link(int speed, int duplex)
be_bryan 0:b74591d5ab33 466 {
be_bryan 0:b74591d5ab33 467 volatile unsigned short phy_data;
be_bryan 0:b74591d5ab33 468 int tout;
be_bryan 0:b74591d5ab33 469
be_bryan 0:b74591d5ab33 470 if((speed < 0) || (speed > 1)) {
be_bryan 0:b74591d5ab33 471
be_bryan 0:b74591d5ab33 472 phy_data = PHY_AUTO_NEG;
be_bryan 0:b74591d5ab33 473
be_bryan 0:b74591d5ab33 474 } else {
be_bryan 0:b74591d5ab33 475
be_bryan 0:b74591d5ab33 476 phy_data = (((unsigned short) speed << 13) |
be_bryan 0:b74591d5ab33 477 ((unsigned short) duplex << 8));
be_bryan 0:b74591d5ab33 478 }
be_bryan 0:b74591d5ab33 479
be_bryan 0:b74591d5ab33 480 phy_write(PHY_REG_BMCR, phy_data);
be_bryan 0:b74591d5ab33 481
be_bryan 0:b74591d5ab33 482 for(tout = 100; tout; tout--) {
be_bryan 0:b74591d5ab33 483 __NOP(); /* A short delay */
be_bryan 0:b74591d5ab33 484 }
be_bryan 0:b74591d5ab33 485
be_bryan 0:b74591d5ab33 486 switch(phy_id) {
be_bryan 0:b74591d5ab33 487 case DP83848C_ID:
be_bryan 0:b74591d5ab33 488
be_bryan 0:b74591d5ab33 489 phy_data = phy_read(PHY_REG_STS);
be_bryan 0:b74591d5ab33 490
be_bryan 0:b74591d5ab33 491 if(phy_data & PHY_STS_DUPLEX) {
be_bryan 0:b74591d5ab33 492 /* Full duplex is enabled. */
be_bryan 0:b74591d5ab33 493 LPC_ETHERNET->MAC_CONFIG |= MAC_DUPLEX_MODE;
be_bryan 0:b74591d5ab33 494 } else {
be_bryan 0:b74591d5ab33 495 LPC_ETHERNET->MAC_CONFIG &= ~MAC_DUPLEX_MODE;
be_bryan 0:b74591d5ab33 496 }
be_bryan 0:b74591d5ab33 497
be_bryan 0:b74591d5ab33 498 if(phy_data & PHY_STS_SPEED) {
be_bryan 0:b74591d5ab33 499 LPC_ETHERNET->MAC_CONFIG &= ~SUPP_SPEED;
be_bryan 0:b74591d5ab33 500 } else {
be_bryan 0:b74591d5ab33 501 LPC_ETHERNET->MAC_CONFIG |= SUPP_SPEED;
be_bryan 0:b74591d5ab33 502 }
be_bryan 0:b74591d5ab33 503 break;
be_bryan 0:b74591d5ab33 504
be_bryan 0:b74591d5ab33 505 case LAN8720_ID:
be_bryan 0:b74591d5ab33 506
be_bryan 0:b74591d5ab33 507 for(tout = 100; tout; tout--) {
be_bryan 0:b74591d5ab33 508 phy_data = phy_read(PHY_REG_BMSR);
be_bryan 0:b74591d5ab33 509 if (phy_data & PHY_STS_DUPLEX)
be_bryan 0:b74591d5ab33 510 break;
be_bryan 0:b74591d5ab33 511 }
be_bryan 0:b74591d5ab33 512
be_bryan 0:b74591d5ab33 513 if (phy_data & PHY_STS_DUPLEX) {
be_bryan 0:b74591d5ab33 514 /* Full duplex is enabled. */
be_bryan 0:b74591d5ab33 515 LPC_ETHERNET->MAC_CONFIG |= MAC_DUPLEX_MODE;
be_bryan 0:b74591d5ab33 516 } else {
be_bryan 0:b74591d5ab33 517 LPC_ETHERNET->MAC_CONFIG &= ~MAC_DUPLEX_MODE;
be_bryan 0:b74591d5ab33 518 }
be_bryan 0:b74591d5ab33 519
be_bryan 0:b74591d5ab33 520 if(phy_data & PHY_STS_SPEED) {
be_bryan 0:b74591d5ab33 521 LPC_ETHERNET->MAC_CONFIG &= ~SUPP_SPEED;
be_bryan 0:b74591d5ab33 522 } else {
be_bryan 0:b74591d5ab33 523 LPC_ETHERNET->MAC_CONFIG |= SUPP_SPEED;
be_bryan 0:b74591d5ab33 524 }
be_bryan 0:b74591d5ab33 525 break;
be_bryan 0:b74591d5ab33 526 }
be_bryan 0:b74591d5ab33 527 }
be_bryan 0:b74591d5ab33 528