EL4121 Embedded System / mbed-os

mbed-os

Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_NXP/TARGET_LPC176X/gpio_irq_api.c@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /* mbed Microcontroller Library
be_bryan 0:b74591d5ab33 2 * Copyright (c) 2006-2013 ARM Limited
be_bryan 0:b74591d5ab33 3 *
be_bryan 0:b74591d5ab33 4 * Licensed under the Apache License, Version 2.0 (the "License");
be_bryan 0:b74591d5ab33 5 * you may not use this file except in compliance with the License.
be_bryan 0:b74591d5ab33 6 * You may obtain a copy of the License at
be_bryan 0:b74591d5ab33 7 *
be_bryan 0:b74591d5ab33 8 * http://www.apache.org/licenses/LICENSE-2.0
be_bryan 0:b74591d5ab33 9 *
be_bryan 0:b74591d5ab33 10 * Unless required by applicable law or agreed to in writing, software
be_bryan 0:b74591d5ab33 11 * distributed under the License is distributed on an "AS IS" BASIS,
be_bryan 0:b74591d5ab33 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan 0:b74591d5ab33 13 * See the License for the specific language governing permissions and
be_bryan 0:b74591d5ab33 14 * limitations under the License.
be_bryan 0:b74591d5ab33 15 */
be_bryan 0:b74591d5ab33 16 #include <stddef.h>
be_bryan 0:b74591d5ab33 17
be_bryan 0:b74591d5ab33 18 #include "gpio_irq_api.h"
be_bryan 0:b74591d5ab33 19 #include "mbed_error.h"
be_bryan 0:b74591d5ab33 20 #include "cmsis.h"
be_bryan 0:b74591d5ab33 21
be_bryan 0:b74591d5ab33 22 #define CHANNEL_NUM 48
be_bryan 0:b74591d5ab33 23
be_bryan 0:b74591d5ab33 24 static uint32_t channel_ids[CHANNEL_NUM] = {0};
be_bryan 0:b74591d5ab33 25 static gpio_irq_handler irq_handler;
be_bryan 0:b74591d5ab33 26
be_bryan 0:b74591d5ab33 27 static void handle_interrupt_in(void) {
be_bryan 0:b74591d5ab33 28 // Read in all current interrupt registers. We do this once as the
be_bryan 0:b74591d5ab33 29 // GPIO interrupt registers are on the APB bus, and this is slow.
be_bryan 0:b74591d5ab33 30 uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
be_bryan 0:b74591d5ab33 31 uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
be_bryan 0:b74591d5ab33 32 uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
be_bryan 0:b74591d5ab33 33 uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
be_bryan 0:b74591d5ab33 34 uint8_t bitloc;
be_bryan 0:b74591d5ab33 35
be_bryan 0:b74591d5ab33 36 while(rise0 > 0) { //Continue as long as there are interrupts pending
be_bryan 0:b74591d5ab33 37 bitloc = 31 - __CLZ(rise0); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
be_bryan 0:b74591d5ab33 38 if (channel_ids[bitloc] != 0)
be_bryan 0:b74591d5ab33 39 irq_handler(channel_ids[bitloc], IRQ_RISE); //Run that interrupt
be_bryan 0:b74591d5ab33 40
be_bryan 0:b74591d5ab33 41 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
be_bryan 0:b74591d5ab33 42 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
be_bryan 0:b74591d5ab33 43 rise0 -= 1<<bitloc;
be_bryan 0:b74591d5ab33 44 }
be_bryan 0:b74591d5ab33 45
be_bryan 0:b74591d5ab33 46 while(fall0 > 0) { //Continue as long as there are interrupts pending
be_bryan 0:b74591d5ab33 47 bitloc = 31 - __CLZ(fall0); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
be_bryan 0:b74591d5ab33 48 if (channel_ids[bitloc] != 0)
be_bryan 0:b74591d5ab33 49 irq_handler(channel_ids[bitloc], IRQ_FALL); //Run that interrupt
be_bryan 0:b74591d5ab33 50
be_bryan 0:b74591d5ab33 51 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
be_bryan 0:b74591d5ab33 52 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
be_bryan 0:b74591d5ab33 53 fall0 -= 1<<bitloc;
be_bryan 0:b74591d5ab33 54 }
be_bryan 0:b74591d5ab33 55
be_bryan 0:b74591d5ab33 56 //Same for port 2, only we need to watch the channel_index
be_bryan 0:b74591d5ab33 57 while(rise2 > 0) { //Continue as long as there are interrupts pending
be_bryan 0:b74591d5ab33 58 bitloc = 31 - __CLZ(rise2); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
be_bryan 0:b74591d5ab33 59
be_bryan 0:b74591d5ab33 60 if (bitloc < 16) //Not sure if this is actually needed
be_bryan 0:b74591d5ab33 61 if (channel_ids[bitloc+32] != 0)
be_bryan 0:b74591d5ab33 62 irq_handler(channel_ids[bitloc+32], IRQ_RISE); //Run that interrupt
be_bryan 0:b74591d5ab33 63
be_bryan 0:b74591d5ab33 64 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
be_bryan 0:b74591d5ab33 65 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
be_bryan 0:b74591d5ab33 66 rise2 -= 1<<bitloc;
be_bryan 0:b74591d5ab33 67 }
be_bryan 0:b74591d5ab33 68
be_bryan 0:b74591d5ab33 69 while(fall2 > 0) { //Continue as long as there are interrupts pending
be_bryan 0:b74591d5ab33 70 bitloc = 31 - __CLZ(fall2); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
be_bryan 0:b74591d5ab33 71
be_bryan 0:b74591d5ab33 72 if (bitloc < 16) //Not sure if this is actually needed
be_bryan 0:b74591d5ab33 73 if (channel_ids[bitloc+32] != 0)
be_bryan 0:b74591d5ab33 74 irq_handler(channel_ids[bitloc+32], IRQ_FALL); //Run that interrupt
be_bryan 0:b74591d5ab33 75
be_bryan 0:b74591d5ab33 76 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
be_bryan 0:b74591d5ab33 77 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
be_bryan 0:b74591d5ab33 78 fall2 -= 1<<bitloc;
be_bryan 0:b74591d5ab33 79 }
be_bryan 0:b74591d5ab33 80 }
be_bryan 0:b74591d5ab33 81
be_bryan 0:b74591d5ab33 82 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
be_bryan 0:b74591d5ab33 83 if (pin == NC) return -1;
be_bryan 0:b74591d5ab33 84
be_bryan 0:b74591d5ab33 85 irq_handler = handler;
be_bryan 0:b74591d5ab33 86
be_bryan 0:b74591d5ab33 87 obj->port = (int)pin & ~0x1F;
be_bryan 0:b74591d5ab33 88 obj->pin = (int)pin & 0x1F;
be_bryan 0:b74591d5ab33 89
be_bryan 0:b74591d5ab33 90 // Interrupts available only on GPIO0 and GPIO2
be_bryan 0:b74591d5ab33 91 if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
be_bryan 0:b74591d5ab33 92 error("pins on this port cannot generate interrupts");
be_bryan 0:b74591d5ab33 93 }
be_bryan 0:b74591d5ab33 94
be_bryan 0:b74591d5ab33 95 // put us in the interrupt table
be_bryan 0:b74591d5ab33 96 int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
be_bryan 0:b74591d5ab33 97 channel_ids[index] = id;
be_bryan 0:b74591d5ab33 98 obj->ch = index;
be_bryan 0:b74591d5ab33 99
be_bryan 0:b74591d5ab33 100 NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
be_bryan 0:b74591d5ab33 101 NVIC_EnableIRQ(EINT3_IRQn);
be_bryan 0:b74591d5ab33 102 return 0;
be_bryan 0:b74591d5ab33 103 }
be_bryan 0:b74591d5ab33 104
be_bryan 0:b74591d5ab33 105 void gpio_irq_free(gpio_irq_t *obj) {
be_bryan 0:b74591d5ab33 106 channel_ids[obj->ch] = 0;
be_bryan 0:b74591d5ab33 107 }
be_bryan 0:b74591d5ab33 108
be_bryan 0:b74591d5ab33 109 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
be_bryan 0:b74591d5ab33 110 // ensure nothing is pending
be_bryan 0:b74591d5ab33 111 switch (obj->port) {
be_bryan 0:b74591d5ab33 112 case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
be_bryan 0:b74591d5ab33 113 case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
be_bryan 0:b74591d5ab33 114 }
be_bryan 0:b74591d5ab33 115
be_bryan 0:b74591d5ab33 116 // enable the pin interrupt
be_bryan 0:b74591d5ab33 117 if (event == IRQ_RISE) {
be_bryan 0:b74591d5ab33 118 switch (obj->port) {
be_bryan 0:b74591d5ab33 119 case LPC_GPIO0_BASE:
be_bryan 0:b74591d5ab33 120 if (enable) {
be_bryan 0:b74591d5ab33 121 LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
be_bryan 0:b74591d5ab33 122 } else {
be_bryan 0:b74591d5ab33 123 LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
be_bryan 0:b74591d5ab33 124 }
be_bryan 0:b74591d5ab33 125 break;
be_bryan 0:b74591d5ab33 126 case LPC_GPIO2_BASE:
be_bryan 0:b74591d5ab33 127 if (enable) {
be_bryan 0:b74591d5ab33 128 LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
be_bryan 0:b74591d5ab33 129 } else {
be_bryan 0:b74591d5ab33 130 LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
be_bryan 0:b74591d5ab33 131 }
be_bryan 0:b74591d5ab33 132 break;
be_bryan 0:b74591d5ab33 133 }
be_bryan 0:b74591d5ab33 134 } else {
be_bryan 0:b74591d5ab33 135 switch (obj->port) {
be_bryan 0:b74591d5ab33 136 case LPC_GPIO0_BASE:
be_bryan 0:b74591d5ab33 137 if (enable) {
be_bryan 0:b74591d5ab33 138 LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
be_bryan 0:b74591d5ab33 139 } else {
be_bryan 0:b74591d5ab33 140 LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
be_bryan 0:b74591d5ab33 141 }
be_bryan 0:b74591d5ab33 142 break;
be_bryan 0:b74591d5ab33 143 case LPC_GPIO2_BASE:
be_bryan 0:b74591d5ab33 144 if (enable) {
be_bryan 0:b74591d5ab33 145 LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
be_bryan 0:b74591d5ab33 146 } else {
be_bryan 0:b74591d5ab33 147 LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
be_bryan 0:b74591d5ab33 148 }
be_bryan 0:b74591d5ab33 149 break;
be_bryan 0:b74591d5ab33 150 }
be_bryan 0:b74591d5ab33 151 }
be_bryan 0:b74591d5ab33 152 }
be_bryan 0:b74591d5ab33 153
be_bryan 0:b74591d5ab33 154 void gpio_irq_enable(gpio_irq_t *obj) {
be_bryan 0:b74591d5ab33 155 NVIC_EnableIRQ(EINT3_IRQn);
be_bryan 0:b74591d5ab33 156 }
be_bryan 0:b74591d5ab33 157
be_bryan 0:b74591d5ab33 158 void gpio_irq_disable(gpio_irq_t *obj) {
be_bryan 0:b74591d5ab33 159 NVIC_DisableIRQ(EINT3_IRQn);
be_bryan 0:b74591d5ab33 160 }
be_bryan 0:b74591d5ab33 161