EL4121 Embedded System / mbed-os

mbed-os

Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /* mbed Microcontroller Library
be_bryan 0:b74591d5ab33 2 * Copyright (c) 2006-2013 ARM Limited
be_bryan 0:b74591d5ab33 3 *
be_bryan 0:b74591d5ab33 4 * Licensed under the Apache License, Version 2.0 (the "License");
be_bryan 0:b74591d5ab33 5 * you may not use this file except in compliance with the License.
be_bryan 0:b74591d5ab33 6 * You may obtain a copy of the License at
be_bryan 0:b74591d5ab33 7 *
be_bryan 0:b74591d5ab33 8 * http://www.apache.org/licenses/LICENSE-2.0
be_bryan 0:b74591d5ab33 9 *
be_bryan 0:b74591d5ab33 10 * Unless required by applicable law or agreed to in writing, software
be_bryan 0:b74591d5ab33 11 * distributed under the License is distributed on an "AS IS" BASIS,
be_bryan 0:b74591d5ab33 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan 0:b74591d5ab33 13 * See the License for the specific language governing permissions and
be_bryan 0:b74591d5ab33 14 * limitations under the License.
be_bryan 0:b74591d5ab33 15 */
be_bryan 0:b74591d5ab33 16 #include "ethernet_api.h"
be_bryan 0:b74591d5ab33 17
be_bryan 0:b74591d5ab33 18 #include <string.h>
be_bryan 0:b74591d5ab33 19 #include "cmsis.h"
be_bryan 0:b74591d5ab33 20 #include "mbed_interface.h"
be_bryan 0:b74591d5ab33 21 #include "mbed_toolchain.h"
be_bryan 0:b74591d5ab33 22 #include "mbed_error.h"
be_bryan 0:b74591d5ab33 23
be_bryan 0:b74591d5ab33 24 #define NEW_LOGIC 0
be_bryan 0:b74591d5ab33 25 #define NEW_ETH_BUFFER 0
be_bryan 0:b74591d5ab33 26
be_bryan 0:b74591d5ab33 27 #if NEW_ETH_BUFFER
be_bryan 0:b74591d5ab33 28
be_bryan 0:b74591d5ab33 29 #define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets)
be_bryan 0:b74591d5ab33 30 #define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets)
be_bryan 0:b74591d5ab33 31
be_bryan 0:b74591d5ab33 32 #define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size
be_bryan 0:b74591d5ab33 33 #define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length)
be_bryan 0:b74591d5ab33 34
be_bryan 0:b74591d5ab33 35 #else
be_bryan 0:b74591d5ab33 36
be_bryan 0:b74591d5ab33 37 // Memfree calculation:
be_bryan 0:b74591d5ab33 38 // (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
be_bryan 0:b74591d5ab33 39 // (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
be_bryan 0:b74591d5ab33 40 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
be_bryan 0:b74591d5ab33 41 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
be_bryan 0:b74591d5ab33 42 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
be_bryan 0:b74591d5ab33 43 //#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
be_bryan 0:b74591d5ab33 44
be_bryan 0:b74591d5ab33 45 //#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
be_bryan 0:b74591d5ab33 46 #define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */
be_bryan 0:b74591d5ab33 47 #define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */
be_bryan 0:b74591d5ab33 48
be_bryan 0:b74591d5ab33 49 const int ethernet_MTU_SIZE = 0x300;
be_bryan 0:b74591d5ab33 50
be_bryan 0:b74591d5ab33 51 #endif
be_bryan 0:b74591d5ab33 52
be_bryan 0:b74591d5ab33 53 #define ETHERNET_ADDR_SIZE 6
be_bryan 0:b74591d5ab33 54
be_bryan 0:b74591d5ab33 55 struct RX_DESC_TypeDef { /* RX Descriptor struct */
be_bryan 0:b74591d5ab33 56 unsigned int Packet;
be_bryan 0:b74591d5ab33 57 unsigned int Ctrl;
be_bryan 0:b74591d5ab33 58 } PACKED;
be_bryan 0:b74591d5ab33 59 typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
be_bryan 0:b74591d5ab33 60
be_bryan 0:b74591d5ab33 61 struct RX_STAT_TypeDef { /* RX Status struct */
be_bryan 0:b74591d5ab33 62 unsigned int Info;
be_bryan 0:b74591d5ab33 63 unsigned int HashCRC;
be_bryan 0:b74591d5ab33 64 } PACKED;
be_bryan 0:b74591d5ab33 65 typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
be_bryan 0:b74591d5ab33 66
be_bryan 0:b74591d5ab33 67 struct TX_DESC_TypeDef { /* TX Descriptor struct */
be_bryan 0:b74591d5ab33 68 unsigned int Packet;
be_bryan 0:b74591d5ab33 69 unsigned int Ctrl;
be_bryan 0:b74591d5ab33 70 } PACKED;
be_bryan 0:b74591d5ab33 71 typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
be_bryan 0:b74591d5ab33 72
be_bryan 0:b74591d5ab33 73 struct TX_STAT_TypeDef { /* TX Status struct */
be_bryan 0:b74591d5ab33 74 unsigned int Info;
be_bryan 0:b74591d5ab33 75 } PACKED;
be_bryan 0:b74591d5ab33 76 typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
be_bryan 0:b74591d5ab33 77
be_bryan 0:b74591d5ab33 78 /* MAC Configuration Register 1 */
be_bryan 0:b74591d5ab33 79 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
be_bryan 0:b74591d5ab33 80 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
be_bryan 0:b74591d5ab33 81 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
be_bryan 0:b74591d5ab33 82 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
be_bryan 0:b74591d5ab33 83 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
be_bryan 0:b74591d5ab33 84 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
be_bryan 0:b74591d5ab33 85 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
be_bryan 0:b74591d5ab33 86 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
be_bryan 0:b74591d5ab33 87 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
be_bryan 0:b74591d5ab33 88 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
be_bryan 0:b74591d5ab33 89 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
be_bryan 0:b74591d5ab33 90
be_bryan 0:b74591d5ab33 91 /* MAC Configuration Register 2 */
be_bryan 0:b74591d5ab33 92 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
be_bryan 0:b74591d5ab33 93 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
be_bryan 0:b74591d5ab33 94 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
be_bryan 0:b74591d5ab33 95 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
be_bryan 0:b74591d5ab33 96 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
be_bryan 0:b74591d5ab33 97 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
be_bryan 0:b74591d5ab33 98 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
be_bryan 0:b74591d5ab33 99 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
be_bryan 0:b74591d5ab33 100 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
be_bryan 0:b74591d5ab33 101 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
be_bryan 0:b74591d5ab33 102 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
be_bryan 0:b74591d5ab33 103 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
be_bryan 0:b74591d5ab33 104 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
be_bryan 0:b74591d5ab33 105
be_bryan 0:b74591d5ab33 106 /* Back-to-Back Inter-Packet-Gap Register */
be_bryan 0:b74591d5ab33 107 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
be_bryan 0:b74591d5ab33 108 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
be_bryan 0:b74591d5ab33 109
be_bryan 0:b74591d5ab33 110 /* Non Back-to-Back Inter-Packet-Gap Register */
be_bryan 0:b74591d5ab33 111 #define IPGR_DEF 0x00000012 /* Recommended value */
be_bryan 0:b74591d5ab33 112
be_bryan 0:b74591d5ab33 113 /* Collision Window/Retry Register */
be_bryan 0:b74591d5ab33 114 #define CLRT_DEF 0x0000370F /* Default value */
be_bryan 0:b74591d5ab33 115
be_bryan 0:b74591d5ab33 116 /* PHY Support Register */
be_bryan 0:b74591d5ab33 117 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
be_bryan 0:b74591d5ab33 118 //#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
be_bryan 0:b74591d5ab33 119 #define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
be_bryan 0:b74591d5ab33 120
be_bryan 0:b74591d5ab33 121 /* Test Register */
be_bryan 0:b74591d5ab33 122 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
be_bryan 0:b74591d5ab33 123 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
be_bryan 0:b74591d5ab33 124 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
be_bryan 0:b74591d5ab33 125
be_bryan 0:b74591d5ab33 126 /* MII Management Configuration Register */
be_bryan 0:b74591d5ab33 127 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
be_bryan 0:b74591d5ab33 128 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
be_bryan 0:b74591d5ab33 129 #define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */
be_bryan 0:b74591d5ab33 130 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
be_bryan 0:b74591d5ab33 131
be_bryan 0:b74591d5ab33 132 /* MII Management Command Register */
be_bryan 0:b74591d5ab33 133 #define MCMD_READ 0x00000001 /* MII Read */
be_bryan 0:b74591d5ab33 134 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
be_bryan 0:b74591d5ab33 135
be_bryan 0:b74591d5ab33 136 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
be_bryan 0:b74591d5ab33 137 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
be_bryan 0:b74591d5ab33 138
be_bryan 0:b74591d5ab33 139 /* MII Management Address Register */
be_bryan 0:b74591d5ab33 140 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
be_bryan 0:b74591d5ab33 141 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
be_bryan 0:b74591d5ab33 142
be_bryan 0:b74591d5ab33 143 /* MII Management Indicators Register */
be_bryan 0:b74591d5ab33 144 #define MIND_BUSY 0x00000001 /* MII is Busy */
be_bryan 0:b74591d5ab33 145 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
be_bryan 0:b74591d5ab33 146 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
be_bryan 0:b74591d5ab33 147 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
be_bryan 0:b74591d5ab33 148
be_bryan 0:b74591d5ab33 149 /* Command Register */
be_bryan 0:b74591d5ab33 150 #define CR_RX_EN 0x00000001 /* Enable Receive */
be_bryan 0:b74591d5ab33 151 #define CR_TX_EN 0x00000002 /* Enable Transmit */
be_bryan 0:b74591d5ab33 152 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
be_bryan 0:b74591d5ab33 153 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
be_bryan 0:b74591d5ab33 154 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
be_bryan 0:b74591d5ab33 155 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
be_bryan 0:b74591d5ab33 156 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
be_bryan 0:b74591d5ab33 157 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
be_bryan 0:b74591d5ab33 158 #define CR_RMII 0x00000200 /* Reduced MII Interface */
be_bryan 0:b74591d5ab33 159 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
be_bryan 0:b74591d5ab33 160
be_bryan 0:b74591d5ab33 161 /* Status Register */
be_bryan 0:b74591d5ab33 162 #define SR_RX_EN 0x00000001 /* Enable Receive */
be_bryan 0:b74591d5ab33 163 #define SR_TX_EN 0x00000002 /* Enable Transmit */
be_bryan 0:b74591d5ab33 164
be_bryan 0:b74591d5ab33 165 /* Transmit Status Vector 0 Register */
be_bryan 0:b74591d5ab33 166 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
be_bryan 0:b74591d5ab33 167 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
be_bryan 0:b74591d5ab33 168 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
be_bryan 0:b74591d5ab33 169 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
be_bryan 0:b74591d5ab33 170 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
be_bryan 0:b74591d5ab33 171 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
be_bryan 0:b74591d5ab33 172 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
be_bryan 0:b74591d5ab33 173 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
be_bryan 0:b74591d5ab33 174 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
be_bryan 0:b74591d5ab33 175 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
be_bryan 0:b74591d5ab33 176 #define TSV0_GIANT 0x00000400 /* Giant Frame */
be_bryan 0:b74591d5ab33 177 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
be_bryan 0:b74591d5ab33 178 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
be_bryan 0:b74591d5ab33 179 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
be_bryan 0:b74591d5ab33 180 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
be_bryan 0:b74591d5ab33 181 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
be_bryan 0:b74591d5ab33 182 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
be_bryan 0:b74591d5ab33 183
be_bryan 0:b74591d5ab33 184 /* Transmit Status Vector 1 Register */
be_bryan 0:b74591d5ab33 185 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
be_bryan 0:b74591d5ab33 186 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
be_bryan 0:b74591d5ab33 187
be_bryan 0:b74591d5ab33 188 /* Receive Status Vector Register */
be_bryan 0:b74591d5ab33 189 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
be_bryan 0:b74591d5ab33 190 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
be_bryan 0:b74591d5ab33 191 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
be_bryan 0:b74591d5ab33 192 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
be_bryan 0:b74591d5ab33 193 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
be_bryan 0:b74591d5ab33 194 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
be_bryan 0:b74591d5ab33 195 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
be_bryan 0:b74591d5ab33 196 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
be_bryan 0:b74591d5ab33 197 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
be_bryan 0:b74591d5ab33 198 #define RSV_MCAST 0x01000000 /* Multicast Frame */
be_bryan 0:b74591d5ab33 199 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
be_bryan 0:b74591d5ab33 200 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
be_bryan 0:b74591d5ab33 201 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
be_bryan 0:b74591d5ab33 202 #define RSV_PAUSE 0x10000000 /* Pause Frame */
be_bryan 0:b74591d5ab33 203 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
be_bryan 0:b74591d5ab33 204 #define RSV_VLAN 0x40000000 /* VLAN Frame */
be_bryan 0:b74591d5ab33 205
be_bryan 0:b74591d5ab33 206 /* Flow Control Counter Register */
be_bryan 0:b74591d5ab33 207 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
be_bryan 0:b74591d5ab33 208 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
be_bryan 0:b74591d5ab33 209
be_bryan 0:b74591d5ab33 210 /* Flow Control Status Register */
be_bryan 0:b74591d5ab33 211 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
be_bryan 0:b74591d5ab33 212
be_bryan 0:b74591d5ab33 213 /* Receive Filter Control Register */
be_bryan 0:b74591d5ab33 214 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
be_bryan 0:b74591d5ab33 215 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
be_bryan 0:b74591d5ab33 216 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
be_bryan 0:b74591d5ab33 217 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
be_bryan 0:b74591d5ab33 218 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
be_bryan 0:b74591d5ab33 219 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
be_bryan 0:b74591d5ab33 220 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
be_bryan 0:b74591d5ab33 221 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
be_bryan 0:b74591d5ab33 222
be_bryan 0:b74591d5ab33 223 /* Receive Filter WoL Status/Clear Registers */
be_bryan 0:b74591d5ab33 224 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
be_bryan 0:b74591d5ab33 225 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
be_bryan 0:b74591d5ab33 226 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
be_bryan 0:b74591d5ab33 227 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
be_bryan 0:b74591d5ab33 228 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
be_bryan 0:b74591d5ab33 229 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
be_bryan 0:b74591d5ab33 230 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
be_bryan 0:b74591d5ab33 231 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
be_bryan 0:b74591d5ab33 232
be_bryan 0:b74591d5ab33 233 /* Interrupt Status/Enable/Clear/Set Registers */
be_bryan 0:b74591d5ab33 234 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
be_bryan 0:b74591d5ab33 235 #define INT_RX_ERR 0x00000002 /* Receive Error */
be_bryan 0:b74591d5ab33 236 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
be_bryan 0:b74591d5ab33 237 #define INT_RX_DONE 0x00000008 /* Receive Done */
be_bryan 0:b74591d5ab33 238 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
be_bryan 0:b74591d5ab33 239 #define INT_TX_ERR 0x00000020 /* Transmit Error */
be_bryan 0:b74591d5ab33 240 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
be_bryan 0:b74591d5ab33 241 #define INT_TX_DONE 0x00000080 /* Transmit Done */
be_bryan 0:b74591d5ab33 242 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
be_bryan 0:b74591d5ab33 243 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
be_bryan 0:b74591d5ab33 244
be_bryan 0:b74591d5ab33 245 /* Power Down Register */
be_bryan 0:b74591d5ab33 246 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
be_bryan 0:b74591d5ab33 247
be_bryan 0:b74591d5ab33 248 /* RX Descriptor Control Word */
be_bryan 0:b74591d5ab33 249 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
be_bryan 0:b74591d5ab33 250 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
be_bryan 0:b74591d5ab33 251
be_bryan 0:b74591d5ab33 252 /* RX Status Hash CRC Word */
be_bryan 0:b74591d5ab33 253 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
be_bryan 0:b74591d5ab33 254 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
be_bryan 0:b74591d5ab33 255
be_bryan 0:b74591d5ab33 256 /* RX Status Information Word */
be_bryan 0:b74591d5ab33 257 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
be_bryan 0:b74591d5ab33 258 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
be_bryan 0:b74591d5ab33 259 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
be_bryan 0:b74591d5ab33 260 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
be_bryan 0:b74591d5ab33 261 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
be_bryan 0:b74591d5ab33 262 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
be_bryan 0:b74591d5ab33 263 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
be_bryan 0:b74591d5ab33 264 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
be_bryan 0:b74591d5ab33 265 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
be_bryan 0:b74591d5ab33 266 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
be_bryan 0:b74591d5ab33 267 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
be_bryan 0:b74591d5ab33 268 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
be_bryan 0:b74591d5ab33 269 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
be_bryan 0:b74591d5ab33 270 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
be_bryan 0:b74591d5ab33 271 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
be_bryan 0:b74591d5ab33 272
be_bryan 0:b74591d5ab33 273 //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
be_bryan 0:b74591d5ab33 274 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
be_bryan 0:b74591d5ab33 275 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
be_bryan 0:b74591d5ab33 276
be_bryan 0:b74591d5ab33 277
be_bryan 0:b74591d5ab33 278 /* TX Descriptor Control Word */
be_bryan 0:b74591d5ab33 279 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
be_bryan 0:b74591d5ab33 280 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
be_bryan 0:b74591d5ab33 281 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
be_bryan 0:b74591d5ab33 282 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
be_bryan 0:b74591d5ab33 283 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
be_bryan 0:b74591d5ab33 284 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
be_bryan 0:b74591d5ab33 285 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
be_bryan 0:b74591d5ab33 286
be_bryan 0:b74591d5ab33 287 /* TX Status Information Word */
be_bryan 0:b74591d5ab33 288 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
be_bryan 0:b74591d5ab33 289 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
be_bryan 0:b74591d5ab33 290 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
be_bryan 0:b74591d5ab33 291 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
be_bryan 0:b74591d5ab33 292 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
be_bryan 0:b74591d5ab33 293 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
be_bryan 0:b74591d5ab33 294 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
be_bryan 0:b74591d5ab33 295 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
be_bryan 0:b74591d5ab33 296
be_bryan 0:b74591d5ab33 297 /* ENET Device Revision ID */
be_bryan 0:b74591d5ab33 298 #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
be_bryan 0:b74591d5ab33 299
be_bryan 0:b74591d5ab33 300 /* DP83848C PHY Registers */
be_bryan 0:b74591d5ab33 301 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
be_bryan 0:b74591d5ab33 302 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
be_bryan 0:b74591d5ab33 303 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
be_bryan 0:b74591d5ab33 304 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
be_bryan 0:b74591d5ab33 305 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
be_bryan 0:b74591d5ab33 306 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
be_bryan 0:b74591d5ab33 307 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
be_bryan 0:b74591d5ab33 308 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
be_bryan 0:b74591d5ab33 309
be_bryan 0:b74591d5ab33 310 /* PHY Extended Registers */
be_bryan 0:b74591d5ab33 311 #define PHY_REG_STS 0x10 /* Status Register */
be_bryan 0:b74591d5ab33 312 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
be_bryan 0:b74591d5ab33 313 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
be_bryan 0:b74591d5ab33 314 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
be_bryan 0:b74591d5ab33 315 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
be_bryan 0:b74591d5ab33 316 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
be_bryan 0:b74591d5ab33 317 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
be_bryan 0:b74591d5ab33 318 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
be_bryan 0:b74591d5ab33 319 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
be_bryan 0:b74591d5ab33 320 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
be_bryan 0:b74591d5ab33 321 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
be_bryan 0:b74591d5ab33 322 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
be_bryan 0:b74591d5ab33 323
be_bryan 0:b74591d5ab33 324 #define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
be_bryan 0:b74591d5ab33 325
be_bryan 0:b74591d5ab33 326 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
be_bryan 0:b74591d5ab33 327 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
be_bryan 0:b74591d5ab33 328 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
be_bryan 0:b74591d5ab33 329 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
be_bryan 0:b74591d5ab33 330 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
be_bryan 0:b74591d5ab33 331
be_bryan 0:b74591d5ab33 332 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
be_bryan 0:b74591d5ab33 333 #define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
be_bryan 0:b74591d5ab33 334
be_bryan 0:b74591d5ab33 335 #define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
be_bryan 0:b74591d5ab33 336
be_bryan 0:b74591d5ab33 337 #define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
be_bryan 0:b74591d5ab33 338 #define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
be_bryan 0:b74591d5ab33 339 #define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
be_bryan 0:b74591d5ab33 340
be_bryan 0:b74591d5ab33 341 #define PHY_BMCR_RESET 0x8000 /* PHY Reset */
be_bryan 0:b74591d5ab33 342
be_bryan 0:b74591d5ab33 343 #define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
be_bryan 0:b74591d5ab33 344
be_bryan 0:b74591d5ab33 345 #define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
be_bryan 0:b74591d5ab33 346 #define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
be_bryan 0:b74591d5ab33 347
be_bryan 0:b74591d5ab33 348
be_bryan 0:b74591d5ab33 349 static int phy_read(unsigned int PhyReg);
be_bryan 0:b74591d5ab33 350 static int phy_write(unsigned int PhyReg, unsigned short Data);
be_bryan 0:b74591d5ab33 351
be_bryan 0:b74591d5ab33 352 static void txdscr_init(void);
be_bryan 0:b74591d5ab33 353 static void rxdscr_init(void);
be_bryan 0:b74591d5ab33 354
be_bryan 0:b74591d5ab33 355 #if defined (__ICCARM__)
be_bryan 0:b74591d5ab33 356 # define AHBSRAM1
be_bryan 0:b74591d5ab33 357 #elif defined(TOOLCHAIN_GCC_CR)
be_bryan 0:b74591d5ab33 358 # define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
be_bryan 0:b74591d5ab33 359 #else
be_bryan 0:b74591d5ab33 360 # define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned))
be_bryan 0:b74591d5ab33 361 #endif
be_bryan 0:b74591d5ab33 362
be_bryan 0:b74591d5ab33 363 AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
be_bryan 0:b74591d5ab33 364 AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
be_bryan 0:b74591d5ab33 365 AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
be_bryan 0:b74591d5ab33 366 AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
be_bryan 0:b74591d5ab33 367 AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
be_bryan 0:b74591d5ab33 368 AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
be_bryan 0:b74591d5ab33 369
be_bryan 0:b74591d5ab33 370
be_bryan 0:b74591d5ab33 371 #if NEW_LOGIC
be_bryan 0:b74591d5ab33 372 static int rx_consume_offset = -1;
be_bryan 0:b74591d5ab33 373 static int tx_produce_offset = -1;
be_bryan 0:b74591d5ab33 374 #else
be_bryan 0:b74591d5ab33 375 static int send_doff = 0;
be_bryan 0:b74591d5ab33 376 static int send_idx = -1;
be_bryan 0:b74591d5ab33 377 static int send_size = 0;
be_bryan 0:b74591d5ab33 378
be_bryan 0:b74591d5ab33 379 static int receive_soff = 0;
be_bryan 0:b74591d5ab33 380 static int receive_idx = -1;
be_bryan 0:b74591d5ab33 381 #endif
be_bryan 0:b74591d5ab33 382
be_bryan 0:b74591d5ab33 383 static uint32_t phy_id = 0;
be_bryan 0:b74591d5ab33 384
be_bryan 0:b74591d5ab33 385 static inline int rinc(int idx, int mod) {
be_bryan 0:b74591d5ab33 386 ++idx;
be_bryan 0:b74591d5ab33 387 idx %= mod;
be_bryan 0:b74591d5ab33 388 return idx;
be_bryan 0:b74591d5ab33 389 }
be_bryan 0:b74591d5ab33 390
be_bryan 0:b74591d5ab33 391 //extern unsigned int SystemFrequency;
be_bryan 0:b74591d5ab33 392 static inline unsigned int clockselect() {
be_bryan 0:b74591d5ab33 393 if(SystemCoreClock < 10000000) {
be_bryan 0:b74591d5ab33 394 return 1;
be_bryan 0:b74591d5ab33 395 } else if(SystemCoreClock < 15000000) {
be_bryan 0:b74591d5ab33 396 return 2;
be_bryan 0:b74591d5ab33 397 } else if(SystemCoreClock < 20000000) {
be_bryan 0:b74591d5ab33 398 return 3;
be_bryan 0:b74591d5ab33 399 } else if(SystemCoreClock < 25000000) {
be_bryan 0:b74591d5ab33 400 return 4;
be_bryan 0:b74591d5ab33 401 } else if(SystemCoreClock < 35000000) {
be_bryan 0:b74591d5ab33 402 return 5;
be_bryan 0:b74591d5ab33 403 } else if(SystemCoreClock < 50000000) {
be_bryan 0:b74591d5ab33 404 return 6;
be_bryan 0:b74591d5ab33 405 } else if(SystemCoreClock < 70000000) {
be_bryan 0:b74591d5ab33 406 return 7;
be_bryan 0:b74591d5ab33 407 } else if(SystemCoreClock < 80000000) {
be_bryan 0:b74591d5ab33 408 return 8;
be_bryan 0:b74591d5ab33 409 } else if(SystemCoreClock < 90000000) {
be_bryan 0:b74591d5ab33 410 return 9;
be_bryan 0:b74591d5ab33 411 } else if(SystemCoreClock < 100000000) {
be_bryan 0:b74591d5ab33 412 return 10;
be_bryan 0:b74591d5ab33 413 } else if(SystemCoreClock < 120000000) {
be_bryan 0:b74591d5ab33 414 return 11;
be_bryan 0:b74591d5ab33 415 } else if(SystemCoreClock < 130000000) {
be_bryan 0:b74591d5ab33 416 return 12;
be_bryan 0:b74591d5ab33 417 } else if(SystemCoreClock < 140000000) {
be_bryan 0:b74591d5ab33 418 return 13;
be_bryan 0:b74591d5ab33 419 } else if(SystemCoreClock < 150000000) {
be_bryan 0:b74591d5ab33 420 return 15;
be_bryan 0:b74591d5ab33 421 } else if(SystemCoreClock < 160000000) {
be_bryan 0:b74591d5ab33 422 return 16;
be_bryan 0:b74591d5ab33 423 } else {
be_bryan 0:b74591d5ab33 424 return 0;
be_bryan 0:b74591d5ab33 425 }
be_bryan 0:b74591d5ab33 426 }
be_bryan 0:b74591d5ab33 427
be_bryan 0:b74591d5ab33 428 #ifndef min
be_bryan 0:b74591d5ab33 429 #define min(x, y) (((x)<(y))?(x):(y))
be_bryan 0:b74591d5ab33 430 #endif
be_bryan 0:b74591d5ab33 431
be_bryan 0:b74591d5ab33 432 /*----------------------------------------------------------------------------
be_bryan 0:b74591d5ab33 433 Ethernet Device initialize
be_bryan 0:b74591d5ab33 434 *----------------------------------------------------------------------------*/
be_bryan 0:b74591d5ab33 435 int ethernet_init() {
be_bryan 0:b74591d5ab33 436 int regv, tout;
be_bryan 0:b74591d5ab33 437 char mac[ETHERNET_ADDR_SIZE];
be_bryan 0:b74591d5ab33 438 unsigned int clock = clockselect();
be_bryan 0:b74591d5ab33 439
be_bryan 0:b74591d5ab33 440 LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */
be_bryan 0:b74591d5ab33 441
be_bryan 0:b74591d5ab33 442 LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */
be_bryan 0:b74591d5ab33 443 LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
be_bryan 0:b74591d5ab33 444
be_bryan 0:b74591d5ab33 445 /* Reset all EMAC internal modules. */
be_bryan 0:b74591d5ab33 446 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
be_bryan 0:b74591d5ab33 447 MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
be_bryan 0:b74591d5ab33 448 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
be_bryan 0:b74591d5ab33 449
be_bryan 0:b74591d5ab33 450 for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */
be_bryan 0:b74591d5ab33 451
be_bryan 0:b74591d5ab33 452 LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */
be_bryan 0:b74591d5ab33 453 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
be_bryan 0:b74591d5ab33 454 LPC_EMAC->MAXF = ETH_MAX_FLEN;
be_bryan 0:b74591d5ab33 455 LPC_EMAC->CLRT = CLRT_DEF;
be_bryan 0:b74591d5ab33 456 LPC_EMAC->IPGR = IPGR_DEF;
be_bryan 0:b74591d5ab33 457
be_bryan 0:b74591d5ab33 458 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */
be_bryan 0:b74591d5ab33 459
be_bryan 0:b74591d5ab33 460 LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */
be_bryan 0:b74591d5ab33 461 LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */
be_bryan 0:b74591d5ab33 462
be_bryan 0:b74591d5ab33 463 for(tout = 100; tout; tout--) __NOP(); /* A short delay */
be_bryan 0:b74591d5ab33 464
be_bryan 0:b74591d5ab33 465 LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
be_bryan 0:b74591d5ab33 466 LPC_EMAC->MCMD = 0;
be_bryan 0:b74591d5ab33 467
be_bryan 0:b74591d5ab33 468 LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */
be_bryan 0:b74591d5ab33 469
be_bryan 0:b74591d5ab33 470 for (tout = 100; tout; tout--) __NOP(); /* A short delay */
be_bryan 0:b74591d5ab33 471
be_bryan 0:b74591d5ab33 472 LPC_EMAC->SUPP = 0;
be_bryan 0:b74591d5ab33 473
be_bryan 0:b74591d5ab33 474 phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */
be_bryan 0:b74591d5ab33 475 for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */
be_bryan 0:b74591d5ab33 476 regv = phy_read(PHY_REG_BMCR);
be_bryan 0:b74591d5ab33 477 if(regv < 0 || tout == 0) {
be_bryan 0:b74591d5ab33 478 return -1; /* Error */
be_bryan 0:b74591d5ab33 479 }
be_bryan 0:b74591d5ab33 480 if(!(regv & PHY_BMCR_RESET)) {
be_bryan 0:b74591d5ab33 481 break; /* Reset complete. */
be_bryan 0:b74591d5ab33 482 }
be_bryan 0:b74591d5ab33 483 }
be_bryan 0:b74591d5ab33 484
be_bryan 0:b74591d5ab33 485 phy_id = (phy_read(PHY_REG_IDR1) << 16);
be_bryan 0:b74591d5ab33 486 phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
be_bryan 0:b74591d5ab33 487
be_bryan 0:b74591d5ab33 488 if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
be_bryan 0:b74591d5ab33 489 error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
be_bryan 0:b74591d5ab33 490 }
be_bryan 0:b74591d5ab33 491
be_bryan 0:b74591d5ab33 492 ethernet_set_link(-1, 0);
be_bryan 0:b74591d5ab33 493
be_bryan 0:b74591d5ab33 494 /* Set the Ethernet MAC Address registers */
be_bryan 0:b74591d5ab33 495 ethernet_address(mac);
be_bryan 0:b74591d5ab33 496 LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
be_bryan 0:b74591d5ab33 497 LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
be_bryan 0:b74591d5ab33 498 LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
be_bryan 0:b74591d5ab33 499
be_bryan 0:b74591d5ab33 500 txdscr_init(); /* initialize DMA TX Descriptor */
be_bryan 0:b74591d5ab33 501 rxdscr_init(); /* initialize DMA RX Descriptor */
be_bryan 0:b74591d5ab33 502
be_bryan 0:b74591d5ab33 503 LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
be_bryan 0:b74591d5ab33 504 /* Receive Broadcast, Perfect Match Packets */
be_bryan 0:b74591d5ab33 505
be_bryan 0:b74591d5ab33 506 LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */
be_bryan 0:b74591d5ab33 507 LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */
be_bryan 0:b74591d5ab33 508
be_bryan 0:b74591d5ab33 509
be_bryan 0:b74591d5ab33 510 LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */
be_bryan 0:b74591d5ab33 511 LPC_EMAC->MAC1 |= MAC1_REC_EN;
be_bryan 0:b74591d5ab33 512
be_bryan 0:b74591d5ab33 513 #if NEW_LOGIC
be_bryan 0:b74591d5ab33 514 rx_consume_offset = -1;
be_bryan 0:b74591d5ab33 515 tx_produce_offset = -1;
be_bryan 0:b74591d5ab33 516 #else
be_bryan 0:b74591d5ab33 517 send_doff = 0;
be_bryan 0:b74591d5ab33 518 send_idx = -1;
be_bryan 0:b74591d5ab33 519 send_size = 0;
be_bryan 0:b74591d5ab33 520
be_bryan 0:b74591d5ab33 521 receive_soff = 0;
be_bryan 0:b74591d5ab33 522 receive_idx = -1;
be_bryan 0:b74591d5ab33 523 #endif
be_bryan 0:b74591d5ab33 524
be_bryan 0:b74591d5ab33 525 return 0;
be_bryan 0:b74591d5ab33 526 }
be_bryan 0:b74591d5ab33 527
be_bryan 0:b74591d5ab33 528 /*----------------------------------------------------------------------------
be_bryan 0:b74591d5ab33 529 Ethernet Device Uninitialize
be_bryan 0:b74591d5ab33 530 *----------------------------------------------------------------------------*/
be_bryan 0:b74591d5ab33 531 void ethernet_free() {
be_bryan 0:b74591d5ab33 532 LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
be_bryan 0:b74591d5ab33 533 LPC_EMAC->IntClear = 0xFFFF;
be_bryan 0:b74591d5ab33 534
be_bryan 0:b74591d5ab33 535 LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */
be_bryan 0:b74591d5ab33 536
be_bryan 0:b74591d5ab33 537 LPC_PINCON->PINSEL2 &= ~0x50150105; /* Disable P1 ethernet pins. */
be_bryan 0:b74591d5ab33 538 LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000000;
be_bryan 0:b74591d5ab33 539 }
be_bryan 0:b74591d5ab33 540
be_bryan 0:b74591d5ab33 541 // if(TxProduceIndex == TxConsumeIndex) buffer array is empty
be_bryan 0:b74591d5ab33 542 // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
be_bryan 0:b74591d5ab33 543 // TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
be_bryan 0:b74591d5ab33 544 // TxConsumeIndex - The buffer that will/is beign sent by hardware
be_bryan 0:b74591d5ab33 545
be_bryan 0:b74591d5ab33 546 int ethernet_write(const char *data, int slen) {
be_bryan 0:b74591d5ab33 547
be_bryan 0:b74591d5ab33 548 #if NEW_LOGIC
be_bryan 0:b74591d5ab33 549
be_bryan 0:b74591d5ab33 550 if(tx_produce_offset < 0) { // mark as active if not already
be_bryan 0:b74591d5ab33 551 tx_produce_offset = 0;
be_bryan 0:b74591d5ab33 552 }
be_bryan 0:b74591d5ab33 553
be_bryan 0:b74591d5ab33 554 int index = LPC_EMAC->TxProduceIndex;
be_bryan 0:b74591d5ab33 555
be_bryan 0:b74591d5ab33 556 int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
be_bryan 0:b74591d5ab33 557 int requested = slen;
be_bryan 0:b74591d5ab33 558 int ncopy = min(remaining, requested);
be_bryan 0:b74591d5ab33 559
be_bryan 0:b74591d5ab33 560 void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
be_bryan 0:b74591d5ab33 561 void *psrc = (void *)(data);
be_bryan 0:b74591d5ab33 562
be_bryan 0:b74591d5ab33 563 if(ncopy > 0 ){
be_bryan 0:b74591d5ab33 564 if(data != NULL) {
be_bryan 0:b74591d5ab33 565 memcpy(pdst, psrc, ncopy);
be_bryan 0:b74591d5ab33 566 } else {
be_bryan 0:b74591d5ab33 567 memset(pdst, 0, ncopy);
be_bryan 0:b74591d5ab33 568 }
be_bryan 0:b74591d5ab33 569 }
be_bryan 0:b74591d5ab33 570
be_bryan 0:b74591d5ab33 571 tx_produce_offset += ncopy;
be_bryan 0:b74591d5ab33 572
be_bryan 0:b74591d5ab33 573 return ncopy;
be_bryan 0:b74591d5ab33 574
be_bryan 0:b74591d5ab33 575 #else
be_bryan 0:b74591d5ab33 576 void *pdst, *psrc;
be_bryan 0:b74591d5ab33 577 const int dlen = ETH_FRAG_SIZE;
be_bryan 0:b74591d5ab33 578 int copy = 0;
be_bryan 0:b74591d5ab33 579 int soff = 0;
be_bryan 0:b74591d5ab33 580
be_bryan 0:b74591d5ab33 581 if(send_idx == -1) {
be_bryan 0:b74591d5ab33 582 send_idx = LPC_EMAC->TxProduceIndex;
be_bryan 0:b74591d5ab33 583 }
be_bryan 0:b74591d5ab33 584
be_bryan 0:b74591d5ab33 585 if(slen + send_doff > ethernet_MTU_SIZE) {
be_bryan 0:b74591d5ab33 586 return -1;
be_bryan 0:b74591d5ab33 587 }
be_bryan 0:b74591d5ab33 588
be_bryan 0:b74591d5ab33 589 do {
be_bryan 0:b74591d5ab33 590 copy = min(slen - soff, dlen - send_doff);
be_bryan 0:b74591d5ab33 591 pdst = (void *)(txdesc[send_idx].Packet + send_doff);
be_bryan 0:b74591d5ab33 592 psrc = (void *)(data + soff);
be_bryan 0:b74591d5ab33 593 if(send_doff + copy > ETH_FRAG_SIZE) {
be_bryan 0:b74591d5ab33 594 txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
be_bryan 0:b74591d5ab33 595 send_idx = rinc(send_idx, NUM_TX_FRAG);
be_bryan 0:b74591d5ab33 596 send_doff = 0;
be_bryan 0:b74591d5ab33 597 }
be_bryan 0:b74591d5ab33 598
be_bryan 0:b74591d5ab33 599 if(data != NULL) {
be_bryan 0:b74591d5ab33 600 memcpy(pdst, psrc, copy);
be_bryan 0:b74591d5ab33 601 } else {
be_bryan 0:b74591d5ab33 602 memset(pdst, 0, copy);
be_bryan 0:b74591d5ab33 603 }
be_bryan 0:b74591d5ab33 604
be_bryan 0:b74591d5ab33 605 soff += copy;
be_bryan 0:b74591d5ab33 606 send_doff += copy;
be_bryan 0:b74591d5ab33 607 send_size += copy;
be_bryan 0:b74591d5ab33 608 } while(soff != slen);
be_bryan 0:b74591d5ab33 609
be_bryan 0:b74591d5ab33 610 return soff;
be_bryan 0:b74591d5ab33 611 #endif
be_bryan 0:b74591d5ab33 612 }
be_bryan 0:b74591d5ab33 613
be_bryan 0:b74591d5ab33 614 int ethernet_send() {
be_bryan 0:b74591d5ab33 615
be_bryan 0:b74591d5ab33 616 #if NEW_LOGIC
be_bryan 0:b74591d5ab33 617 if(tx_produce_offset < 0) { // no buffer active
be_bryan 0:b74591d5ab33 618 return -1;
be_bryan 0:b74591d5ab33 619 }
be_bryan 0:b74591d5ab33 620
be_bryan 0:b74591d5ab33 621 // ensure there is a link
be_bryan 0:b74591d5ab33 622 if(!ethernet_link()) {
be_bryan 0:b74591d5ab33 623 return -2;
be_bryan 0:b74591d5ab33 624 }
be_bryan 0:b74591d5ab33 625
be_bryan 0:b74591d5ab33 626 // we have been writing in to a buffer, so finalise it
be_bryan 0:b74591d5ab33 627 int size = tx_produce_offset;
be_bryan 0:b74591d5ab33 628 int index = LPC_EMAC->TxProduceIndex;
be_bryan 0:b74591d5ab33 629 txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
be_bryan 0:b74591d5ab33 630
be_bryan 0:b74591d5ab33 631 // Increment ProduceIndex to allow it to be sent
be_bryan 0:b74591d5ab33 632 // We can only do this if the next slot is free
be_bryan 0:b74591d5ab33 633 int next = rinc(index, NUM_TX_FRAG);
be_bryan 0:b74591d5ab33 634 while(next == LPC_EMAC->TxConsumeIndex) {
be_bryan 0:b74591d5ab33 635 for(int i=0; i<1000; i++) { __NOP(); }
be_bryan 0:b74591d5ab33 636 }
be_bryan 0:b74591d5ab33 637
be_bryan 0:b74591d5ab33 638 LPC_EMAC->TxProduceIndex = next;
be_bryan 0:b74591d5ab33 639 tx_produce_offset = -1;
be_bryan 0:b74591d5ab33 640 return size;
be_bryan 0:b74591d5ab33 641
be_bryan 0:b74591d5ab33 642 #else
be_bryan 0:b74591d5ab33 643 int s = send_size;
be_bryan 0:b74591d5ab33 644 txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
be_bryan 0:b74591d5ab33 645 send_idx = rinc(send_idx, NUM_TX_FRAG);
be_bryan 0:b74591d5ab33 646 LPC_EMAC->TxProduceIndex = send_idx;
be_bryan 0:b74591d5ab33 647 send_doff = 0;
be_bryan 0:b74591d5ab33 648 send_idx = -1;
be_bryan 0:b74591d5ab33 649 send_size = 0;
be_bryan 0:b74591d5ab33 650 return s;
be_bryan 0:b74591d5ab33 651 #endif
be_bryan 0:b74591d5ab33 652 }
be_bryan 0:b74591d5ab33 653
be_bryan 0:b74591d5ab33 654 // RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
be_bryan 0:b74591d5ab33 655 // RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
be_bryan 0:b74591d5ab33 656 //
be_bryan 0:b74591d5ab33 657 // if(RxConsumeIndex == RxProduceIndex) buffer array is empty
be_bryan 0:b74591d5ab33 658 // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
be_bryan 0:b74591d5ab33 659
be_bryan 0:b74591d5ab33 660 // Recevies an arrived ethernet packet.
be_bryan 0:b74591d5ab33 661 // Receiving an ethernet packet will drop the last received ethernet packet
be_bryan 0:b74591d5ab33 662 // and make a new ethernet packet ready to read.
be_bryan 0:b74591d5ab33 663 // Returns size of packet, else 0 if nothing to receive
be_bryan 0:b74591d5ab33 664
be_bryan 0:b74591d5ab33 665 // We read from RxConsumeIndex from position rx_consume_offset
be_bryan 0:b74591d5ab33 666 // if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
be_bryan 0:b74591d5ab33 667 // rx_consume_offset = -1 // no frame
be_bryan 0:b74591d5ab33 668 // rx_consume_offset = 0 // start of frame
be_bryan 0:b74591d5ab33 669 // Assumption: A fragment should alway be a whole frame
be_bryan 0:b74591d5ab33 670
be_bryan 0:b74591d5ab33 671 int ethernet_receive() {
be_bryan 0:b74591d5ab33 672 #if NEW_LOGIC
be_bryan 0:b74591d5ab33 673
be_bryan 0:b74591d5ab33 674 // if we are currently reading a valid RxConsume buffer, increment to the next one
be_bryan 0:b74591d5ab33 675 if(rx_consume_offset >= 0) {
be_bryan 0:b74591d5ab33 676 LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
be_bryan 0:b74591d5ab33 677 }
be_bryan 0:b74591d5ab33 678
be_bryan 0:b74591d5ab33 679 // if the buffer is empty, mark it as no valid buffer
be_bryan 0:b74591d5ab33 680 if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
be_bryan 0:b74591d5ab33 681 rx_consume_offset = -1;
be_bryan 0:b74591d5ab33 682 return 0;
be_bryan 0:b74591d5ab33 683 }
be_bryan 0:b74591d5ab33 684
be_bryan 0:b74591d5ab33 685 uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
be_bryan 0:b74591d5ab33 686 rx_consume_offset = 0;
be_bryan 0:b74591d5ab33 687
be_bryan 0:b74591d5ab33 688 // check if it is not marked as last or for errors
be_bryan 0:b74591d5ab33 689 if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
be_bryan 0:b74591d5ab33 690 return -1;
be_bryan 0:b74591d5ab33 691 }
be_bryan 0:b74591d5ab33 692
be_bryan 0:b74591d5ab33 693 int size = (info & RINFO_SIZE) + 1;
be_bryan 0:b74591d5ab33 694 return size - 4; // don't include checksum bytes
be_bryan 0:b74591d5ab33 695
be_bryan 0:b74591d5ab33 696 #else
be_bryan 0:b74591d5ab33 697 if(receive_idx == -1) {
be_bryan 0:b74591d5ab33 698 receive_idx = LPC_EMAC->RxConsumeIndex;
be_bryan 0:b74591d5ab33 699 } else {
be_bryan 0:b74591d5ab33 700 while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && ((uint32_t)receive_idx != LPC_EMAC->RxProduceIndex)) {
be_bryan 0:b74591d5ab33 701 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
be_bryan 0:b74591d5ab33 702 }
be_bryan 0:b74591d5ab33 703 unsigned int info = rxstat[receive_idx].Info;
be_bryan 0:b74591d5ab33 704 int slen = (info & RINFO_SIZE) + 1;
be_bryan 0:b74591d5ab33 705
be_bryan 0:b74591d5ab33 706 if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
be_bryan 0:b74591d5ab33 707 /* Invalid frame, ignore it and free buffer. */
be_bryan 0:b74591d5ab33 708 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
be_bryan 0:b74591d5ab33 709 }
be_bryan 0:b74591d5ab33 710 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
be_bryan 0:b74591d5ab33 711 receive_soff = 0;
be_bryan 0:b74591d5ab33 712
be_bryan 0:b74591d5ab33 713 LPC_EMAC->RxConsumeIndex = receive_idx;
be_bryan 0:b74591d5ab33 714 }
be_bryan 0:b74591d5ab33 715
be_bryan 0:b74591d5ab33 716 if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex) {
be_bryan 0:b74591d5ab33 717 receive_idx = -1;
be_bryan 0:b74591d5ab33 718 return 0;
be_bryan 0:b74591d5ab33 719 }
be_bryan 0:b74591d5ab33 720
be_bryan 0:b74591d5ab33 721 return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
be_bryan 0:b74591d5ab33 722 #endif
be_bryan 0:b74591d5ab33 723 }
be_bryan 0:b74591d5ab33 724
be_bryan 0:b74591d5ab33 725 // Read from an recevied ethernet packet.
be_bryan 0:b74591d5ab33 726 // After receive returnd a number bigger than 0 it is
be_bryan 0:b74591d5ab33 727 // possible to read bytes from this packet.
be_bryan 0:b74591d5ab33 728 // Read will write up to size bytes into data.
be_bryan 0:b74591d5ab33 729 // It is possible to use read multible times.
be_bryan 0:b74591d5ab33 730 // Each time read will start reading after the last read byte before.
be_bryan 0:b74591d5ab33 731
be_bryan 0:b74591d5ab33 732 int ethernet_read(char *data, int dlen) {
be_bryan 0:b74591d5ab33 733 #if NEW_LOGIC
be_bryan 0:b74591d5ab33 734 // Check we have a valid buffer to read
be_bryan 0:b74591d5ab33 735 if(rx_consume_offset < 0) {
be_bryan 0:b74591d5ab33 736 return 0;
be_bryan 0:b74591d5ab33 737 }
be_bryan 0:b74591d5ab33 738
be_bryan 0:b74591d5ab33 739 // Assume 1 fragment block
be_bryan 0:b74591d5ab33 740 uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
be_bryan 0:b74591d5ab33 741 int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
be_bryan 0:b74591d5ab33 742
be_bryan 0:b74591d5ab33 743 int remaining = size - rx_consume_offset;
be_bryan 0:b74591d5ab33 744 int requested = dlen;
be_bryan 0:b74591d5ab33 745 int ncopy = min(remaining, requested);
be_bryan 0:b74591d5ab33 746
be_bryan 0:b74591d5ab33 747 void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
be_bryan 0:b74591d5ab33 748 void *pdst = (void *)(data);
be_bryan 0:b74591d5ab33 749
be_bryan 0:b74591d5ab33 750 if(data != NULL && ncopy > 0) {
be_bryan 0:b74591d5ab33 751 memcpy(pdst, psrc, ncopy);
be_bryan 0:b74591d5ab33 752 }
be_bryan 0:b74591d5ab33 753
be_bryan 0:b74591d5ab33 754 rx_consume_offset += ncopy;
be_bryan 0:b74591d5ab33 755
be_bryan 0:b74591d5ab33 756 return ncopy;
be_bryan 0:b74591d5ab33 757 #else
be_bryan 0:b74591d5ab33 758 int slen;
be_bryan 0:b74591d5ab33 759 int copy = 0;
be_bryan 0:b74591d5ab33 760 unsigned int more;
be_bryan 0:b74591d5ab33 761 unsigned int info;
be_bryan 0:b74591d5ab33 762 void *pdst, *psrc;
be_bryan 0:b74591d5ab33 763 int doff = 0;
be_bryan 0:b74591d5ab33 764
be_bryan 0:b74591d5ab33 765 if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
be_bryan 0:b74591d5ab33 766 return 0;
be_bryan 0:b74591d5ab33 767 }
be_bryan 0:b74591d5ab33 768
be_bryan 0:b74591d5ab33 769 do {
be_bryan 0:b74591d5ab33 770 info = rxstat[receive_idx].Info;
be_bryan 0:b74591d5ab33 771 more = !(info & RINFO_LAST_FLAG);
be_bryan 0:b74591d5ab33 772 slen = (info & RINFO_SIZE) + 1;
be_bryan 0:b74591d5ab33 773
be_bryan 0:b74591d5ab33 774 if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
be_bryan 0:b74591d5ab33 775 /* Invalid frame, ignore it and free buffer. */
be_bryan 0:b74591d5ab33 776 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
be_bryan 0:b74591d5ab33 777 } else {
be_bryan 0:b74591d5ab33 778
be_bryan 0:b74591d5ab33 779 copy = min(slen - receive_soff, dlen - doff);
be_bryan 0:b74591d5ab33 780 psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
be_bryan 0:b74591d5ab33 781 pdst = (void *)(data + doff);
be_bryan 0:b74591d5ab33 782
be_bryan 0:b74591d5ab33 783 if(data != NULL) {
be_bryan 0:b74591d5ab33 784 /* check if Buffer available */
be_bryan 0:b74591d5ab33 785 memcpy(pdst, psrc, copy);
be_bryan 0:b74591d5ab33 786 }
be_bryan 0:b74591d5ab33 787
be_bryan 0:b74591d5ab33 788 receive_soff += copy;
be_bryan 0:b74591d5ab33 789 doff += copy;
be_bryan 0:b74591d5ab33 790
be_bryan 0:b74591d5ab33 791 if((more && (receive_soff == slen))) {
be_bryan 0:b74591d5ab33 792 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
be_bryan 0:b74591d5ab33 793 receive_soff = 0;
be_bryan 0:b74591d5ab33 794 }
be_bryan 0:b74591d5ab33 795 }
be_bryan 0:b74591d5ab33 796 } while(more && !(doff == dlen) && !receive_soff);
be_bryan 0:b74591d5ab33 797
be_bryan 0:b74591d5ab33 798 return doff;
be_bryan 0:b74591d5ab33 799 #endif
be_bryan 0:b74591d5ab33 800 }
be_bryan 0:b74591d5ab33 801
be_bryan 0:b74591d5ab33 802 int ethernet_link(void) {
be_bryan 0:b74591d5ab33 803
be_bryan 0:b74591d5ab33 804 if (phy_id == DP83848C_ID) {
be_bryan 0:b74591d5ab33 805 return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
be_bryan 0:b74591d5ab33 806 }
be_bryan 0:b74591d5ab33 807 else { // LAN8720_ID
be_bryan 0:b74591d5ab33 808 return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
be_bryan 0:b74591d5ab33 809 }
be_bryan 0:b74591d5ab33 810 }
be_bryan 0:b74591d5ab33 811
be_bryan 0:b74591d5ab33 812 static int phy_write(unsigned int PhyReg, unsigned short Data) {
be_bryan 0:b74591d5ab33 813 unsigned int timeOut;
be_bryan 0:b74591d5ab33 814
be_bryan 0:b74591d5ab33 815 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
be_bryan 0:b74591d5ab33 816 LPC_EMAC->MWTD = Data;
be_bryan 0:b74591d5ab33 817
be_bryan 0:b74591d5ab33 818 for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { /* Wait until operation completed */
be_bryan 0:b74591d5ab33 819 if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
be_bryan 0:b74591d5ab33 820 return 0;
be_bryan 0:b74591d5ab33 821 }
be_bryan 0:b74591d5ab33 822 }
be_bryan 0:b74591d5ab33 823
be_bryan 0:b74591d5ab33 824 return -1;
be_bryan 0:b74591d5ab33 825 }
be_bryan 0:b74591d5ab33 826
be_bryan 0:b74591d5ab33 827
be_bryan 0:b74591d5ab33 828 static int phy_read(unsigned int PhyReg) {
be_bryan 0:b74591d5ab33 829 unsigned int timeOut;
be_bryan 0:b74591d5ab33 830
be_bryan 0:b74591d5ab33 831 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
be_bryan 0:b74591d5ab33 832 LPC_EMAC->MCMD = MCMD_READ;
be_bryan 0:b74591d5ab33 833
be_bryan 0:b74591d5ab33 834 for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */
be_bryan 0:b74591d5ab33 835 if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
be_bryan 0:b74591d5ab33 836 LPC_EMAC->MCMD = 0;
be_bryan 0:b74591d5ab33 837 return LPC_EMAC->MRDD; /* Return a 16-bit value. */
be_bryan 0:b74591d5ab33 838 }
be_bryan 0:b74591d5ab33 839 }
be_bryan 0:b74591d5ab33 840
be_bryan 0:b74591d5ab33 841 return -1;
be_bryan 0:b74591d5ab33 842 }
be_bryan 0:b74591d5ab33 843
be_bryan 0:b74591d5ab33 844
be_bryan 0:b74591d5ab33 845 static void txdscr_init() {
be_bryan 0:b74591d5ab33 846 int i;
be_bryan 0:b74591d5ab33 847
be_bryan 0:b74591d5ab33 848 for(i = 0; i < NUM_TX_FRAG; i++) {
be_bryan 0:b74591d5ab33 849 txdesc[i].Packet = (uint32_t)&txbuf[i];
be_bryan 0:b74591d5ab33 850 txdesc[i].Ctrl = 0;
be_bryan 0:b74591d5ab33 851 txstat[i].Info = 0;
be_bryan 0:b74591d5ab33 852 }
be_bryan 0:b74591d5ab33 853
be_bryan 0:b74591d5ab33 854 LPC_EMAC->TxDescriptor = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */
be_bryan 0:b74591d5ab33 855 LPC_EMAC->TxStatus = (uint32_t)txstat;
be_bryan 0:b74591d5ab33 856 LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
be_bryan 0:b74591d5ab33 857
be_bryan 0:b74591d5ab33 858 LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */
be_bryan 0:b74591d5ab33 859 }
be_bryan 0:b74591d5ab33 860
be_bryan 0:b74591d5ab33 861
be_bryan 0:b74591d5ab33 862 static void rxdscr_init() {
be_bryan 0:b74591d5ab33 863 int i;
be_bryan 0:b74591d5ab33 864
be_bryan 0:b74591d5ab33 865 for(i = 0; i < NUM_RX_FRAG; i++) {
be_bryan 0:b74591d5ab33 866 rxdesc[i].Packet = (uint32_t)&rxbuf[i];
be_bryan 0:b74591d5ab33 867 rxdesc[i].Ctrl = RCTRL_INT | (ETH_FRAG_SIZE-1);
be_bryan 0:b74591d5ab33 868 rxstat[i].Info = 0;
be_bryan 0:b74591d5ab33 869 rxstat[i].HashCRC = 0;
be_bryan 0:b74591d5ab33 870 }
be_bryan 0:b74591d5ab33 871
be_bryan 0:b74591d5ab33 872 LPC_EMAC->RxDescriptor = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */
be_bryan 0:b74591d5ab33 873 LPC_EMAC->RxStatus = (uint32_t)rxstat;
be_bryan 0:b74591d5ab33 874 LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
be_bryan 0:b74591d5ab33 875
be_bryan 0:b74591d5ab33 876 LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */
be_bryan 0:b74591d5ab33 877 }
be_bryan 0:b74591d5ab33 878
be_bryan 0:b74591d5ab33 879 void ethernet_address(char *mac) {
be_bryan 0:b74591d5ab33 880 mbed_mac_address(mac);
be_bryan 0:b74591d5ab33 881 }
be_bryan 0:b74591d5ab33 882
be_bryan 0:b74591d5ab33 883 void ethernet_set_link(int speed, int duplex) {
be_bryan 0:b74591d5ab33 884 unsigned short phy_data;
be_bryan 0:b74591d5ab33 885 int tout;
be_bryan 0:b74591d5ab33 886
be_bryan 0:b74591d5ab33 887 if((speed < 0) || (speed > 1)) {
be_bryan 0:b74591d5ab33 888
be_bryan 0:b74591d5ab33 889 phy_data = PHY_AUTO_NEG;
be_bryan 0:b74591d5ab33 890
be_bryan 0:b74591d5ab33 891 } else {
be_bryan 0:b74591d5ab33 892
be_bryan 0:b74591d5ab33 893 phy_data = (((unsigned short) speed << 13) |
be_bryan 0:b74591d5ab33 894 ((unsigned short) duplex << 8));
be_bryan 0:b74591d5ab33 895 }
be_bryan 0:b74591d5ab33 896
be_bryan 0:b74591d5ab33 897 phy_write(PHY_REG_BMCR, phy_data);
be_bryan 0:b74591d5ab33 898
be_bryan 0:b74591d5ab33 899 for(tout = 100; tout; tout--) { __NOP(); } /* A short delay */
be_bryan 0:b74591d5ab33 900
be_bryan 0:b74591d5ab33 901 switch(phy_id) {
be_bryan 0:b74591d5ab33 902 case DP83848C_ID:
be_bryan 0:b74591d5ab33 903
be_bryan 0:b74591d5ab33 904 phy_data = phy_read(PHY_REG_STS);
be_bryan 0:b74591d5ab33 905
be_bryan 0:b74591d5ab33 906 if(phy_data & PHY_STS_DUPLEX) {
be_bryan 0:b74591d5ab33 907 LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
be_bryan 0:b74591d5ab33 908 LPC_EMAC->Command |= CR_FULL_DUP;
be_bryan 0:b74591d5ab33 909 LPC_EMAC->IPGT = IPGT_FULL_DUP;
be_bryan 0:b74591d5ab33 910 } else {
be_bryan 0:b74591d5ab33 911 LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
be_bryan 0:b74591d5ab33 912 LPC_EMAC->Command &= ~CR_FULL_DUP;
be_bryan 0:b74591d5ab33 913 LPC_EMAC->IPGT = IPGT_HALF_DUP;
be_bryan 0:b74591d5ab33 914 }
be_bryan 0:b74591d5ab33 915
be_bryan 0:b74591d5ab33 916 if(phy_data & PHY_STS_SPEED) {
be_bryan 0:b74591d5ab33 917 LPC_EMAC->SUPP &= ~SUPP_SPEED;
be_bryan 0:b74591d5ab33 918 } else {
be_bryan 0:b74591d5ab33 919 LPC_EMAC->SUPP |= SUPP_SPEED;
be_bryan 0:b74591d5ab33 920 }
be_bryan 0:b74591d5ab33 921
be_bryan 0:b74591d5ab33 922
be_bryan 0:b74591d5ab33 923 break;
be_bryan 0:b74591d5ab33 924 case LAN8720_ID:
be_bryan 0:b74591d5ab33 925
be_bryan 0:b74591d5ab33 926 phy_data = phy_read(PHY_REG_SCSR);
be_bryan 0:b74591d5ab33 927
be_bryan 0:b74591d5ab33 928 if (phy_data & PHY_SCSR_DUPLEX) {
be_bryan 0:b74591d5ab33 929 LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
be_bryan 0:b74591d5ab33 930 LPC_EMAC->Command |= CR_FULL_DUP;
be_bryan 0:b74591d5ab33 931 LPC_EMAC->IPGT = IPGT_FULL_DUP;
be_bryan 0:b74591d5ab33 932 } else {
be_bryan 0:b74591d5ab33 933 LPC_EMAC->Command &= ~CR_FULL_DUP;
be_bryan 0:b74591d5ab33 934 LPC_EMAC->IPGT = IPGT_HALF_DUP;
be_bryan 0:b74591d5ab33 935 }
be_bryan 0:b74591d5ab33 936
be_bryan 0:b74591d5ab33 937 if(phy_data & PHY_SCSR_100MBIT) {
be_bryan 0:b74591d5ab33 938 LPC_EMAC->SUPP |= SUPP_SPEED;
be_bryan 0:b74591d5ab33 939 } else {
be_bryan 0:b74591d5ab33 940 LPC_EMAC->SUPP &= ~SUPP_SPEED;
be_bryan 0:b74591d5ab33 941 }
be_bryan 0:b74591d5ab33 942
be_bryan 0:b74591d5ab33 943
be_bryan 0:b74591d5ab33 944 break;
be_bryan 0:b74591d5ab33 945 }
be_bryan 0:b74591d5ab33 946
be_bryan 0:b74591d5ab33 947
be_bryan 0:b74591d5ab33 948 }