EL4121 Embedded System / mbed-os

mbed-os

Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_NXP/TARGET_LPC15XX/can_api.c@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /* mbed Microcontroller Library
be_bryan 0:b74591d5ab33 2 * Copyright (c) 2006-2013 ARM Limited
be_bryan 0:b74591d5ab33 3 *
be_bryan 0:b74591d5ab33 4 * Licensed under the Apache License, Version 2.0 (the "License");
be_bryan 0:b74591d5ab33 5 * you may not use this file except in compliance with the License.
be_bryan 0:b74591d5ab33 6 * You may obtain a copy of the License at
be_bryan 0:b74591d5ab33 7 *
be_bryan 0:b74591d5ab33 8 * http://www.apache.org/licenses/LICENSE-2.0
be_bryan 0:b74591d5ab33 9 *
be_bryan 0:b74591d5ab33 10 * Unless required by applicable law or agreed to in writing, software
be_bryan 0:b74591d5ab33 11 * distributed under the License is distributed on an "AS IS" BASIS,
be_bryan 0:b74591d5ab33 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan 0:b74591d5ab33 13 * See the License for the specific language governing permissions and
be_bryan 0:b74591d5ab33 14 * limitations under the License.
be_bryan 0:b74591d5ab33 15 */
be_bryan 0:b74591d5ab33 16
be_bryan 0:b74591d5ab33 17 #include "can_api.h"
be_bryan 0:b74591d5ab33 18
be_bryan 0:b74591d5ab33 19 #include "cmsis.h"
be_bryan 0:b74591d5ab33 20 #include "mbed_error.h"
be_bryan 0:b74591d5ab33 21
be_bryan 0:b74591d5ab33 22 #include <math.h>
be_bryan 0:b74591d5ab33 23 #include <string.h>
be_bryan 0:b74591d5ab33 24
be_bryan 0:b74591d5ab33 25 /* Handy defines */
be_bryan 0:b74591d5ab33 26 #define RX_MSG_OBJ_COUNT 31
be_bryan 0:b74591d5ab33 27 #define TX_MSG_OBJ_COUNT 1
be_bryan 0:b74591d5ab33 28 #define DLC_MAX 8
be_bryan 0:b74591d5ab33 29
be_bryan 0:b74591d5ab33 30 #define ID_STD_MASK 0x07FF
be_bryan 0:b74591d5ab33 31 #define ID_EXT_MASK 0x1FFFFFFF
be_bryan 0:b74591d5ab33 32 #define DLC_MASK 0x0F
be_bryan 0:b74591d5ab33 33
be_bryan 0:b74591d5ab33 34 #define CANIFn_ARB2_DIR (1UL << 13)
be_bryan 0:b74591d5ab33 35 #define CANIFn_ARB2_XTD (1UL << 14)
be_bryan 0:b74591d5ab33 36 #define CANIFn_ARB2_MSGVAL (1UL << 15)
be_bryan 0:b74591d5ab33 37 #define CANIFn_MSK2_MXTD (1UL << 15)
be_bryan 0:b74591d5ab33 38 #define CANIFn_MSK2_MDIR (1UL << 14)
be_bryan 0:b74591d5ab33 39 #define CANIFn_MCTRL_EOB (1UL << 7)
be_bryan 0:b74591d5ab33 40 #define CANIFn_MCTRL_TXRQST (1UL << 8)
be_bryan 0:b74591d5ab33 41 #define CANIFn_MCTRL_RMTEN (1UL << 9)
be_bryan 0:b74591d5ab33 42 #define CANIFn_MCTRL_RXIE (1UL << 10)
be_bryan 0:b74591d5ab33 43 #define CANIFn_MCTRL_TXIE (1UL << 11)
be_bryan 0:b74591d5ab33 44 #define CANIFn_MCTRL_UMASK (1UL << 12)
be_bryan 0:b74591d5ab33 45 #define CANIFn_MCTRL_INTPND (1UL << 13)
be_bryan 0:b74591d5ab33 46 #define CANIFn_MCTRL_MSGLST (1UL << 14)
be_bryan 0:b74591d5ab33 47 #define CANIFn_MCTRL_NEWDAT (1UL << 15)
be_bryan 0:b74591d5ab33 48 #define CANIFn_CMDMSK_DATA_B (1UL << 0)
be_bryan 0:b74591d5ab33 49 #define CANIFn_CMDMSK_DATA_A (1UL << 1)
be_bryan 0:b74591d5ab33 50 #define CANIFn_CMDMSK_TXRQST (1UL << 2)
be_bryan 0:b74591d5ab33 51 #define CANIFn_CMDMSK_NEWDAT (1UL << 2)
be_bryan 0:b74591d5ab33 52 #define CANIFn_CMDMSK_CLRINTPND (1UL << 3)
be_bryan 0:b74591d5ab33 53 #define CANIFn_CMDMSK_CTRL (1UL << 4)
be_bryan 0:b74591d5ab33 54 #define CANIFn_CMDMSK_ARB (1UL << 5)
be_bryan 0:b74591d5ab33 55 #define CANIFn_CMDMSK_MASK (1UL << 6)
be_bryan 0:b74591d5ab33 56 #define CANIFn_CMDMSK_WR (1UL << 7)
be_bryan 0:b74591d5ab33 57 #define CANIFn_CMDMSK_RD (0UL << 7)
be_bryan 0:b74591d5ab33 58 #define CANIFn_CMDREQ_BUSY (1UL << 15)
be_bryan 0:b74591d5ab33 59
be_bryan 0:b74591d5ab33 60 #define CANSTAT_TXOK (1 << 3) // Transmitted a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
be_bryan 0:b74591d5ab33 61 #define CANSTAT_RXOK (1 << 4) // Received a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
be_bryan 0:b74591d5ab33 62 #define CANSTAT_EPASS (1 << 5) // Error passive
be_bryan 0:b74591d5ab33 63 #define CANSTAT_EWARN (1 << 6) // Warning status
be_bryan 0:b74591d5ab33 64 #define CANSTAT_BOFF (1 << 7) // Busoff status
be_bryan 0:b74591d5ab33 65
be_bryan 0:b74591d5ab33 66 #define CANCNTL_INIT (1 << 0) // Initialization
be_bryan 0:b74591d5ab33 67 #define CANCNTL_IE (1 << 1) // Module interrupt enable
be_bryan 0:b74591d5ab33 68 #define CANCNTL_SIE (1 << 2) // Status change interrupt enable
be_bryan 0:b74591d5ab33 69 #define CANCNTL_EIE (1 << 3) // Error interrupt enable
be_bryan 0:b74591d5ab33 70 #define CANCNTL_DAR (1 << 5) // Disable automatic retransmission
be_bryan 0:b74591d5ab33 71 #define CANCNTL_CCE (1 << 6) // Configuration change enable
be_bryan 0:b74591d5ab33 72 #define CANCNTL_TEST (1 << 7) // Test mode enable
be_bryan 0:b74591d5ab33 73
be_bryan 0:b74591d5ab33 74 #define CANTEST_BASIC (1 << 2) // Basic mode
be_bryan 0:b74591d5ab33 75 #define CANTEST_SILENT (1 << 3) // Silent mode
be_bryan 0:b74591d5ab33 76 #define CANTEST_LBACK (1 << 4) // Loop back mode
be_bryan 0:b74591d5ab33 77 #define CANTEST_TX_MASK 0x0060 // Control of CAN_TXD pins
be_bryan 0:b74591d5ab33 78 #define CANTEST_TX_SHIFT 5
be_bryan 0:b74591d5ab33 79 #define CANTEST_RX (1 << 7) // Monitors the actual value of the CAN_RXD pin.
be_bryan 0:b74591d5ab33 80
be_bryan 0:b74591d5ab33 81 static uint32_t can_irq_id = 0;
be_bryan 0:b74591d5ab33 82 static can_irq_handler irq_handler;
be_bryan 0:b74591d5ab33 83
be_bryan 0:b74591d5ab33 84 #define IRQ_ENABLE_TX (1 << 0)
be_bryan 0:b74591d5ab33 85 #define IRQ_ENABLE_RX (1 << 1)
be_bryan 0:b74591d5ab33 86 #define IRQ_ENABLE_EW (1 << 2)
be_bryan 0:b74591d5ab33 87 #define IRQ_ENABLE_EP (1 << 3)
be_bryan 0:b74591d5ab33 88 #define IRQ_ENABLE_BE (1 << 4)
be_bryan 0:b74591d5ab33 89 #define IRQ_ENABLE_STATUS (IRQ_ENABLE_TX | IRQ_ENABLE_RX)
be_bryan 0:b74591d5ab33 90 #define IRQ_ENABLE_ERROR (IRQ_ENABLE_EW | IRQ_ENABLE_EP | IRQ_ENABLE_BE)
be_bryan 0:b74591d5ab33 91 #define IRQ_ENABLE_ANY (IRQ_ENABLE_STATUS | IRQ_ENABLE_ERROR)
be_bryan 0:b74591d5ab33 92 static uint32_t enabled_irqs = 0;
be_bryan 0:b74591d5ab33 93
be_bryan 0:b74591d5ab33 94 static inline void can_disable(can_t *obj) {
be_bryan 0:b74591d5ab33 95 LPC_C_CAN0->CANCNTL |= 0x1;
be_bryan 0:b74591d5ab33 96 }
be_bryan 0:b74591d5ab33 97
be_bryan 0:b74591d5ab33 98 static inline void can_enable(can_t *obj) {
be_bryan 0:b74591d5ab33 99 if (LPC_C_CAN0->CANCNTL & 0x1) {
be_bryan 0:b74591d5ab33 100 LPC_C_CAN0->CANCNTL &= ~(0x1);
be_bryan 0:b74591d5ab33 101 }
be_bryan 0:b74591d5ab33 102 }
be_bryan 0:b74591d5ab33 103
be_bryan 0:b74591d5ab33 104 int can_mode(can_t *obj, CanMode mode) {
be_bryan 0:b74591d5ab33 105 int success = 0;
be_bryan 0:b74591d5ab33 106 switch (mode) {
be_bryan 0:b74591d5ab33 107 case MODE_RESET:
be_bryan 0:b74591d5ab33 108 LPC_C_CAN0->CANCNTL &=~CANCNTL_TEST;
be_bryan 0:b74591d5ab33 109 can_disable(obj);
be_bryan 0:b74591d5ab33 110 success = 1;
be_bryan 0:b74591d5ab33 111 break;
be_bryan 0:b74591d5ab33 112 case MODE_NORMAL:
be_bryan 0:b74591d5ab33 113 LPC_C_CAN0->CANCNTL &=~CANCNTL_TEST;
be_bryan 0:b74591d5ab33 114 can_enable(obj);
be_bryan 0:b74591d5ab33 115 success = 1;
be_bryan 0:b74591d5ab33 116 break;
be_bryan 0:b74591d5ab33 117 case MODE_SILENT:
be_bryan 0:b74591d5ab33 118 LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
be_bryan 0:b74591d5ab33 119 LPC_C_CAN0->CANTEST |= CANTEST_SILENT;
be_bryan 0:b74591d5ab33 120 LPC_C_CAN0->CANTEST &=~ CANTEST_LBACK;
be_bryan 0:b74591d5ab33 121 success = 1;
be_bryan 0:b74591d5ab33 122 break;
be_bryan 0:b74591d5ab33 123 case MODE_TEST_LOCAL:
be_bryan 0:b74591d5ab33 124 LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
be_bryan 0:b74591d5ab33 125 LPC_C_CAN0->CANTEST &=~CANTEST_SILENT;
be_bryan 0:b74591d5ab33 126 LPC_C_CAN0->CANTEST |= CANTEST_LBACK;
be_bryan 0:b74591d5ab33 127 success = 1;
be_bryan 0:b74591d5ab33 128 break;
be_bryan 0:b74591d5ab33 129 case MODE_TEST_SILENT:
be_bryan 0:b74591d5ab33 130 LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
be_bryan 0:b74591d5ab33 131 LPC_C_CAN0->CANTEST |= (CANTEST_LBACK | CANTEST_SILENT);
be_bryan 0:b74591d5ab33 132 success = 1;
be_bryan 0:b74591d5ab33 133 break;
be_bryan 0:b74591d5ab33 134 case MODE_TEST_GLOBAL:
be_bryan 0:b74591d5ab33 135 default:
be_bryan 0:b74591d5ab33 136 success = 0;
be_bryan 0:b74591d5ab33 137 break;
be_bryan 0:b74591d5ab33 138 }
be_bryan 0:b74591d5ab33 139
be_bryan 0:b74591d5ab33 140 return success;
be_bryan 0:b74591d5ab33 141 }
be_bryan 0:b74591d5ab33 142
be_bryan 0:b74591d5ab33 143 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
be_bryan 0:b74591d5ab33 144 uint16_t i;
be_bryan 0:b74591d5ab33 145
be_bryan 0:b74591d5ab33 146 // Find first free message object
be_bryan 0:b74591d5ab33 147 if (handle == 0) {
be_bryan 0:b74591d5ab33 148 uint32_t msgval = LPC_C_CAN0->CANMSGV1 | (LPC_C_CAN0->CANMSGV2 << 16);
be_bryan 0:b74591d5ab33 149
be_bryan 0:b74591d5ab33 150 // Find first free messagebox
be_bryan 0:b74591d5ab33 151 for (i = 0; i < 32; i++) {
be_bryan 0:b74591d5ab33 152 if ((msgval & (1 << i)) == 0) {
be_bryan 0:b74591d5ab33 153 handle = i+1;
be_bryan 0:b74591d5ab33 154 break;
be_bryan 0:b74591d5ab33 155 }
be_bryan 0:b74591d5ab33 156 }
be_bryan 0:b74591d5ab33 157 }
be_bryan 0:b74591d5ab33 158
be_bryan 0:b74591d5ab33 159 if (handle > 0 && handle <= 32) {
be_bryan 0:b74591d5ab33 160 if (format == CANExtended) {
be_bryan 0:b74591d5ab33 161 // Mark message valid, Direction = TX, Extended Frame, Set Identifier and mask everything
be_bryan 0:b74591d5ab33 162 LPC_C_CAN0->CANIF1_ARB1 = (id & 0xFFFF);
be_bryan 0:b74591d5ab33 163 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | ((id >> 16) & 0x1FFF);
be_bryan 0:b74591d5ab33 164 LPC_C_CAN0->CANIF1_MSK1 = (mask & 0xFFFF);
be_bryan 0:b74591d5ab33 165 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD /*| CANIFn_MSK2_MDIR*/ | ((mask >> 16) & 0x1FFF);
be_bryan 0:b74591d5ab33 166 } else {
be_bryan 0:b74591d5ab33 167 // Mark message valid, Direction = TX, Set Identifier and mask everything
be_bryan 0:b74591d5ab33 168 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | ((id << 2) & 0x1FFF);
be_bryan 0:b74591d5ab33 169 LPC_C_CAN0->CANIF1_MSK2 = /*CANIFn_MSK2_MDIR |*/ ((mask << 2) & 0x1FFF);
be_bryan 0:b74591d5ab33 170 }
be_bryan 0:b74591d5ab33 171
be_bryan 0:b74591d5ab33 172 // Use mask, single message object and set DLC
be_bryan 0:b74591d5ab33 173 LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_EOB | (DLC_MAX & 0xF);
be_bryan 0:b74591d5ab33 174
be_bryan 0:b74591d5ab33 175 // Transfer all fields to message object
be_bryan 0:b74591d5ab33 176 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
be_bryan 0:b74591d5ab33 177
be_bryan 0:b74591d5ab33 178 // Start Transfer to given message number
be_bryan 0:b74591d5ab33 179 LPC_C_CAN0->CANIF1_CMDREQ = (handle & 0x3F);
be_bryan 0:b74591d5ab33 180
be_bryan 0:b74591d5ab33 181 // Wait until transfer to message ram complete - TODO: maybe not block??
be_bryan 0:b74591d5ab33 182 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
be_bryan 0:b74591d5ab33 183 }
be_bryan 0:b74591d5ab33 184
be_bryan 0:b74591d5ab33 185 return handle;
be_bryan 0:b74591d5ab33 186 }
be_bryan 0:b74591d5ab33 187
be_bryan 0:b74591d5ab33 188 static inline void can_irq() {
be_bryan 0:b74591d5ab33 189 uint32_t intid = LPC_C_CAN0->CANINT & 0xFFFF;
be_bryan 0:b74591d5ab33 190
be_bryan 0:b74591d5ab33 191 if (intid == 0x8000) {
be_bryan 0:b74591d5ab33 192 uint32_t status = LPC_C_CAN0->CANSTAT;
be_bryan 0:b74591d5ab33 193 // Note that since it's impossible to tell which specific status caused
be_bryan 0:b74591d5ab33 194 // the interrupt to fire, this just fires them all.
be_bryan 0:b74591d5ab33 195 // In particular, EWARN is not mutually exclusive with the others and
be_bryan 0:b74591d5ab33 196 // may fire multiple times with other status transitions, including
be_bryan 0:b74591d5ab33 197 // transmit and receive completion (if enabled). Ignoring EWARN with a
be_bryan 0:b74591d5ab33 198 // priority system (i.e. blocking EWARN interrupts if EPASS or BOFF is
be_bryan 0:b74591d5ab33 199 // set) may discard some EWARN interrupts.
be_bryan 0:b74591d5ab33 200 if (status & CANSTAT_BOFF) {
be_bryan 0:b74591d5ab33 201 if (enabled_irqs & IRQ_ENABLE_BE) {
be_bryan 0:b74591d5ab33 202 irq_handler(can_irq_id, IRQ_BUS);
be_bryan 0:b74591d5ab33 203 }
be_bryan 0:b74591d5ab33 204 }
be_bryan 0:b74591d5ab33 205 if (status & CANSTAT_EPASS) {
be_bryan 0:b74591d5ab33 206 if (enabled_irqs & IRQ_ENABLE_EP) {
be_bryan 0:b74591d5ab33 207 irq_handler(can_irq_id, IRQ_PASSIVE);
be_bryan 0:b74591d5ab33 208 }
be_bryan 0:b74591d5ab33 209 }
be_bryan 0:b74591d5ab33 210 if (status & CANSTAT_EWARN) {
be_bryan 0:b74591d5ab33 211 if (enabled_irqs & IRQ_ENABLE_EW) {
be_bryan 0:b74591d5ab33 212 irq_handler(can_irq_id, IRQ_ERROR);
be_bryan 0:b74591d5ab33 213 }
be_bryan 0:b74591d5ab33 214 }
be_bryan 0:b74591d5ab33 215 if ((status & CANSTAT_RXOK) != 0) {
be_bryan 0:b74591d5ab33 216 LPC_C_CAN0->CANSTAT &= ~CANSTAT_RXOK;
be_bryan 0:b74591d5ab33 217 irq_handler(can_irq_id, IRQ_RX);
be_bryan 0:b74591d5ab33 218 }
be_bryan 0:b74591d5ab33 219 if ((status & CANSTAT_TXOK) != 0) {
be_bryan 0:b74591d5ab33 220 LPC_C_CAN0->CANSTAT &= ~CANSTAT_TXOK;
be_bryan 0:b74591d5ab33 221 irq_handler(can_irq_id, IRQ_TX);
be_bryan 0:b74591d5ab33 222 }
be_bryan 0:b74591d5ab33 223 }
be_bryan 0:b74591d5ab33 224 }
be_bryan 0:b74591d5ab33 225
be_bryan 0:b74591d5ab33 226 // Register CAN object's irq handler
be_bryan 0:b74591d5ab33 227 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
be_bryan 0:b74591d5ab33 228 irq_handler = handler;
be_bryan 0:b74591d5ab33 229 can_irq_id = id;
be_bryan 0:b74591d5ab33 230 }
be_bryan 0:b74591d5ab33 231
be_bryan 0:b74591d5ab33 232 // Unregister CAN object's irq handler
be_bryan 0:b74591d5ab33 233 void can_irq_free(can_t *obj) {
be_bryan 0:b74591d5ab33 234 LPC_C_CAN0->CANCNTL &= ~(1UL << 1); // Disable Interrupts :)
be_bryan 0:b74591d5ab33 235 can_irq_id = 0;
be_bryan 0:b74591d5ab33 236 NVIC_DisableIRQ(C_CAN0_IRQn);
be_bryan 0:b74591d5ab33 237 }
be_bryan 0:b74591d5ab33 238
be_bryan 0:b74591d5ab33 239 // Clear or set a irq
be_bryan 0:b74591d5ab33 240 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
be_bryan 0:b74591d5ab33 241 uint32_t mask_enable;
be_bryan 0:b74591d5ab33 242 switch (type) {
be_bryan 0:b74591d5ab33 243 case IRQ_RX:
be_bryan 0:b74591d5ab33 244 mask_enable = IRQ_ENABLE_RX;
be_bryan 0:b74591d5ab33 245 break;
be_bryan 0:b74591d5ab33 246 case IRQ_TX:
be_bryan 0:b74591d5ab33 247 mask_enable = IRQ_ENABLE_TX;
be_bryan 0:b74591d5ab33 248 break;
be_bryan 0:b74591d5ab33 249 case IRQ_BUS:
be_bryan 0:b74591d5ab33 250 mask_enable = IRQ_ENABLE_BE;
be_bryan 0:b74591d5ab33 251 break;
be_bryan 0:b74591d5ab33 252 case IRQ_PASSIVE:
be_bryan 0:b74591d5ab33 253 mask_enable = IRQ_ENABLE_EP;
be_bryan 0:b74591d5ab33 254 break;
be_bryan 0:b74591d5ab33 255 case IRQ_ERROR:
be_bryan 0:b74591d5ab33 256 mask_enable = IRQ_ENABLE_EW;
be_bryan 0:b74591d5ab33 257 break;
be_bryan 0:b74591d5ab33 258 default:
be_bryan 0:b74591d5ab33 259 return;
be_bryan 0:b74591d5ab33 260 }
be_bryan 0:b74591d5ab33 261
be_bryan 0:b74591d5ab33 262 if (enable) {
be_bryan 0:b74591d5ab33 263 enabled_irqs = enabled_irqs | mask_enable;
be_bryan 0:b74591d5ab33 264 } else {
be_bryan 0:b74591d5ab33 265 enabled_irqs = enabled_irqs & ~mask_enable;
be_bryan 0:b74591d5ab33 266 }
be_bryan 0:b74591d5ab33 267
be_bryan 0:b74591d5ab33 268 // Put CAN in Reset Mode and enable interrupt
be_bryan 0:b74591d5ab33 269 can_disable(obj);
be_bryan 0:b74591d5ab33 270 if (!(enabled_irqs & IRQ_ENABLE_ANY)) {
be_bryan 0:b74591d5ab33 271 LPC_C_CAN0->CANCNTL &= ~(1UL << 1 | 1UL << 2 | 1UL << 3);
be_bryan 0:b74591d5ab33 272 } else {
be_bryan 0:b74591d5ab33 273 LPC_C_CAN0->CANCNTL |= 1UL << 1;
be_bryan 0:b74591d5ab33 274 // Use status interrupts instead of message interrupts to avoid
be_bryan 0:b74591d5ab33 275 // stomping over potential filter configurations.
be_bryan 0:b74591d5ab33 276 if (enabled_irqs & IRQ_ENABLE_STATUS) {
be_bryan 0:b74591d5ab33 277 LPC_C_CAN0->CANCNTL |= 1UL << 2;
be_bryan 0:b74591d5ab33 278 } else {
be_bryan 0:b74591d5ab33 279 LPC_C_CAN0->CANCNTL &= ~(1UL << 2);
be_bryan 0:b74591d5ab33 280 }
be_bryan 0:b74591d5ab33 281 if (enabled_irqs & IRQ_ENABLE_ERROR) {
be_bryan 0:b74591d5ab33 282 LPC_C_CAN0->CANCNTL |= 1UL << 3;
be_bryan 0:b74591d5ab33 283 } else {
be_bryan 0:b74591d5ab33 284 LPC_C_CAN0->CANCNTL &= ~(1UL << 3);
be_bryan 0:b74591d5ab33 285 }
be_bryan 0:b74591d5ab33 286 }
be_bryan 0:b74591d5ab33 287
be_bryan 0:b74591d5ab33 288 // Take it out of reset...
be_bryan 0:b74591d5ab33 289 can_enable(obj);
be_bryan 0:b74591d5ab33 290
be_bryan 0:b74591d5ab33 291 // Enable NVIC if at least 1 interrupt is active
be_bryan 0:b74591d5ab33 292 NVIC_SetVector(C_CAN0_IRQn, (uint32_t) &can_irq);
be_bryan 0:b74591d5ab33 293 NVIC_EnableIRQ(C_CAN0_IRQn);
be_bryan 0:b74591d5ab33 294 }
be_bryan 0:b74591d5ab33 295
be_bryan 0:b74591d5ab33 296 // This table has the sampling points as close to 75% as possible. The first
be_bryan 0:b74591d5ab33 297 // value is TSEG1, the second TSEG2.
be_bryan 0:b74591d5ab33 298 static const int timing_pts[23][2] = {
be_bryan 0:b74591d5ab33 299 {0x0, 0x0}, // 2, 50%
be_bryan 0:b74591d5ab33 300 {0x1, 0x0}, // 3, 67%
be_bryan 0:b74591d5ab33 301 {0x2, 0x0}, // 4, 75%
be_bryan 0:b74591d5ab33 302 {0x3, 0x0}, // 5, 80%
be_bryan 0:b74591d5ab33 303 {0x3, 0x1}, // 6, 67%
be_bryan 0:b74591d5ab33 304 {0x4, 0x1}, // 7, 71%
be_bryan 0:b74591d5ab33 305 {0x5, 0x1}, // 8, 75%
be_bryan 0:b74591d5ab33 306 {0x6, 0x1}, // 9, 78%
be_bryan 0:b74591d5ab33 307 {0x6, 0x2}, // 10, 70%
be_bryan 0:b74591d5ab33 308 {0x7, 0x2}, // 11, 73%
be_bryan 0:b74591d5ab33 309 {0x8, 0x2}, // 12, 75%
be_bryan 0:b74591d5ab33 310 {0x9, 0x2}, // 13, 77%
be_bryan 0:b74591d5ab33 311 {0x9, 0x3}, // 14, 71%
be_bryan 0:b74591d5ab33 312 {0xA, 0x3}, // 15, 73%
be_bryan 0:b74591d5ab33 313 {0xB, 0x3}, // 16, 75%
be_bryan 0:b74591d5ab33 314 {0xC, 0x3}, // 17, 76%
be_bryan 0:b74591d5ab33 315 {0xD, 0x3}, // 18, 78%
be_bryan 0:b74591d5ab33 316 {0xD, 0x4}, // 19, 74%
be_bryan 0:b74591d5ab33 317 {0xE, 0x4}, // 20, 75%
be_bryan 0:b74591d5ab33 318 {0xF, 0x4}, // 21, 76%
be_bryan 0:b74591d5ab33 319 {0xF, 0x5}, // 22, 73%
be_bryan 0:b74591d5ab33 320 {0xF, 0x6}, // 23, 70%
be_bryan 0:b74591d5ab33 321 {0xF, 0x7}, // 24, 67%
be_bryan 0:b74591d5ab33 322 };
be_bryan 0:b74591d5ab33 323
be_bryan 0:b74591d5ab33 324 static unsigned int can_speed(unsigned int sclk, unsigned int cclk, unsigned char psjw) {
be_bryan 0:b74591d5ab33 325 uint32_t btr;
be_bryan 0:b74591d5ab33 326 uint32_t clkdiv = 1;
be_bryan 0:b74591d5ab33 327 uint16_t brp = 0;
be_bryan 0:b74591d5ab33 328 uint32_t calcbit;
be_bryan 0:b74591d5ab33 329 uint32_t bitwidth;
be_bryan 0:b74591d5ab33 330 int hit = 0;
be_bryan 0:b74591d5ab33 331 int bits = 0;
be_bryan 0:b74591d5ab33 332
be_bryan 0:b74591d5ab33 333 bitwidth = sclk / cclk;
be_bryan 0:b74591d5ab33 334
be_bryan 0:b74591d5ab33 335 brp = bitwidth / 0x18;
be_bryan 0:b74591d5ab33 336 while ((!hit) && (brp < bitwidth / 4)) {
be_bryan 0:b74591d5ab33 337 brp++;
be_bryan 0:b74591d5ab33 338 for (bits = 22; bits > 0; bits--) {
be_bryan 0:b74591d5ab33 339 calcbit = (bits + 3) * (brp + 1);
be_bryan 0:b74591d5ab33 340 if (calcbit == bitwidth) {
be_bryan 0:b74591d5ab33 341 hit = 1;
be_bryan 0:b74591d5ab33 342 break;
be_bryan 0:b74591d5ab33 343 }
be_bryan 0:b74591d5ab33 344 }
be_bryan 0:b74591d5ab33 345 }
be_bryan 0:b74591d5ab33 346
be_bryan 0:b74591d5ab33 347 clkdiv = clkdiv - 1;
be_bryan 0:b74591d5ab33 348
be_bryan 0:b74591d5ab33 349 if (hit) {
be_bryan 0:b74591d5ab33 350 btr = (timing_pts[bits][1] & 0x7) << 12
be_bryan 0:b74591d5ab33 351 | (timing_pts[bits][0] & 0xf) << 8
be_bryan 0:b74591d5ab33 352 | (psjw & 0x3) << 6
be_bryan 0:b74591d5ab33 353 | (brp & 0x3F);
be_bryan 0:b74591d5ab33 354 btr = btr | (clkdiv << 16);
be_bryan 0:b74591d5ab33 355 } else {
be_bryan 0:b74591d5ab33 356 btr = 0;
be_bryan 0:b74591d5ab33 357 }
be_bryan 0:b74591d5ab33 358
be_bryan 0:b74591d5ab33 359 return btr;
be_bryan 0:b74591d5ab33 360 }
be_bryan 0:b74591d5ab33 361
be_bryan 0:b74591d5ab33 362
be_bryan 0:b74591d5ab33 363 int can_config_rxmsgobj(can_t *obj) {
be_bryan 0:b74591d5ab33 364 uint16_t i = 0;
be_bryan 0:b74591d5ab33 365
be_bryan 0:b74591d5ab33 366 // Make sure the interface is available
be_bryan 0:b74591d5ab33 367 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
be_bryan 0:b74591d5ab33 368
be_bryan 0:b74591d5ab33 369 // Mark message valid, Direction = RX, Don't care about anything else
be_bryan 0:b74591d5ab33 370 LPC_C_CAN0->CANIF1_ARB1 = 0;
be_bryan 0:b74591d5ab33 371 LPC_C_CAN0->CANIF1_ARB2 = 0;
be_bryan 0:b74591d5ab33 372 LPC_C_CAN0->CANIF1_MCTRL = 0;
be_bryan 0:b74591d5ab33 373
be_bryan 0:b74591d5ab33 374 for ( i = 1; i <= RX_MSG_OBJ_COUNT; i++ ) {
be_bryan 0:b74591d5ab33 375 // Transfer arb and control fields to message object
be_bryan 0:b74591d5ab33 376 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
be_bryan 0:b74591d5ab33 377
be_bryan 0:b74591d5ab33 378 // Start Transfer to given message number
be_bryan 0:b74591d5ab33 379 LPC_C_CAN0->CANIF1_CMDREQ = (i & 0x3F);
be_bryan 0:b74591d5ab33 380
be_bryan 0:b74591d5ab33 381 // Wait until transfer to message ram complete - TODO: maybe not block??
be_bryan 0:b74591d5ab33 382 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
be_bryan 0:b74591d5ab33 383 }
be_bryan 0:b74591d5ab33 384
be_bryan 0:b74591d5ab33 385 // Accept all messages
be_bryan 0:b74591d5ab33 386 can_filter(obj, 0, 0, CANStandard, 1);
be_bryan 0:b74591d5ab33 387
be_bryan 0:b74591d5ab33 388 return 1;
be_bryan 0:b74591d5ab33 389 }
be_bryan 0:b74591d5ab33 390
be_bryan 0:b74591d5ab33 391 int can_config_txmsgobj(can_t *obj) {
be_bryan 0:b74591d5ab33 392 uint16_t i = 0;
be_bryan 0:b74591d5ab33 393
be_bryan 0:b74591d5ab33 394 // Make sure the interface is available
be_bryan 0:b74591d5ab33 395 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
be_bryan 0:b74591d5ab33 396
be_bryan 0:b74591d5ab33 397 // Mark message valid, Direction = TX, Don't care about anything else
be_bryan 0:b74591d5ab33 398 LPC_C_CAN0->CANIF1_ARB1 = 0;
be_bryan 0:b74591d5ab33 399 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_DIR;
be_bryan 0:b74591d5ab33 400 LPC_C_CAN0->CANIF1_MCTRL = 0;
be_bryan 0:b74591d5ab33 401
be_bryan 0:b74591d5ab33 402 for ( i = RX_MSG_OBJ_COUNT + 1; i <= (TX_MSG_OBJ_COUNT + RX_MSG_OBJ_COUNT); i++ )
be_bryan 0:b74591d5ab33 403 {
be_bryan 0:b74591d5ab33 404 // Transfer arb and control fields to message object
be_bryan 0:b74591d5ab33 405 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
be_bryan 0:b74591d5ab33 406 // In a union with CANIF1_CMDMSK_R
be_bryan 0:b74591d5ab33 407
be_bryan 0:b74591d5ab33 408 // Start Transfer to given message number
be_bryan 0:b74591d5ab33 409 LPC_C_CAN0->CANIF1_CMDREQ = i & 0x3F;
be_bryan 0:b74591d5ab33 410
be_bryan 0:b74591d5ab33 411 // Wait until transfer to message ram complete - TODO: maybe not block??
be_bryan 0:b74591d5ab33 412 while( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
be_bryan 0:b74591d5ab33 413 }
be_bryan 0:b74591d5ab33 414
be_bryan 0:b74591d5ab33 415 return 1;
be_bryan 0:b74591d5ab33 416 }
be_bryan 0:b74591d5ab33 417
be_bryan 0:b74591d5ab33 418 void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) {
be_bryan 0:b74591d5ab33 419 // Enable power and clock
be_bryan 0:b74591d5ab33 420 LPC_SYSCON->SYSAHBCLKCTRL1 |= (1UL << 7);
be_bryan 0:b74591d5ab33 421 LPC_SYSCON->PRESETCTRL1 |= (1UL << 7);
be_bryan 0:b74591d5ab33 422 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
be_bryan 0:b74591d5ab33 423
be_bryan 0:b74591d5ab33 424 // Enable Initialization mode
be_bryan 0:b74591d5ab33 425 if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
be_bryan 0:b74591d5ab33 426 LPC_C_CAN0->CANCNTL |= (1UL << 0);
be_bryan 0:b74591d5ab33 427 }
be_bryan 0:b74591d5ab33 428
be_bryan 0:b74591d5ab33 429 LPC_SWM->PINASSIGN[6] &= ~(0x00FFFF00L);
be_bryan 0:b74591d5ab33 430 LPC_SWM->PINASSIGN[6] |= (rd << 16) | (td << 8);
be_bryan 0:b74591d5ab33 431
be_bryan 0:b74591d5ab33 432 can_frequency(obj, hz);
be_bryan 0:b74591d5ab33 433
be_bryan 0:b74591d5ab33 434 // Resume operation
be_bryan 0:b74591d5ab33 435 LPC_C_CAN0->CANCNTL &= ~(1UL << 0);
be_bryan 0:b74591d5ab33 436 while ( LPC_C_CAN0->CANCNTL & (1UL << 0) );
be_bryan 0:b74591d5ab33 437
be_bryan 0:b74591d5ab33 438 // Initialize RX message object
be_bryan 0:b74591d5ab33 439 can_config_rxmsgobj(obj);
be_bryan 0:b74591d5ab33 440 // Initialize TX message object
be_bryan 0:b74591d5ab33 441 can_config_txmsgobj(obj);
be_bryan 0:b74591d5ab33 442 }
be_bryan 0:b74591d5ab33 443
be_bryan 0:b74591d5ab33 444 void can_init(can_t *obj, PinName rd, PinName td) {
be_bryan 0:b74591d5ab33 445 can_init_freq(obj, rd, td, 100000);
be_bryan 0:b74591d5ab33 446 }
be_bryan 0:b74591d5ab33 447
be_bryan 0:b74591d5ab33 448 void can_free(can_t *obj) {
be_bryan 0:b74591d5ab33 449 LPC_SYSCON->SYSAHBCLKCTRL1 &= ~(1UL << 7);
be_bryan 0:b74591d5ab33 450 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
be_bryan 0:b74591d5ab33 451 }
be_bryan 0:b74591d5ab33 452
be_bryan 0:b74591d5ab33 453 int can_frequency(can_t *obj, int f) {
be_bryan 0:b74591d5ab33 454 int btr = can_speed(SystemCoreClock, (unsigned int)f, 1);
be_bryan 0:b74591d5ab33 455 int clkdiv = (btr >> 16) & 0x0F;
be_bryan 0:b74591d5ab33 456 btr = btr & 0xFFFF;
be_bryan 0:b74591d5ab33 457
be_bryan 0:b74591d5ab33 458 if (btr > 0) {
be_bryan 0:b74591d5ab33 459 // Set the bit clock
be_bryan 0:b74591d5ab33 460 LPC_C_CAN0->CANCNTL |= (1UL << 6 | 1UL << 0); // set CCE and INIT
be_bryan 0:b74591d5ab33 461 LPC_C_CAN0->CANCLKDIV = clkdiv;
be_bryan 0:b74591d5ab33 462 LPC_C_CAN0->CANBT = btr;
be_bryan 0:b74591d5ab33 463 LPC_C_CAN0->CANBRPE = 0x0000;
be_bryan 0:b74591d5ab33 464 LPC_C_CAN0->CANCNTL &= ~(1UL << 6 | 1UL << 0); // clear CCE and INIT
be_bryan 0:b74591d5ab33 465 return 1;
be_bryan 0:b74591d5ab33 466 }
be_bryan 0:b74591d5ab33 467 return 0;
be_bryan 0:b74591d5ab33 468 }
be_bryan 0:b74591d5ab33 469
be_bryan 0:b74591d5ab33 470 int can_write(can_t *obj, CAN_Message msg, int cc) {
be_bryan 0:b74591d5ab33 471
be_bryan 0:b74591d5ab33 472 // Make sure controller is enabled
be_bryan 0:b74591d5ab33 473 can_enable(obj);
be_bryan 0:b74591d5ab33 474
be_bryan 0:b74591d5ab33 475 // Find first message object that isn't pending to send
be_bryan 0:b74591d5ab33 476 uint16_t msgnum = 0;
be_bryan 0:b74591d5ab33 477 uint32_t txPending = (LPC_C_CAN0->CANTXREQ1 & 0xFF) | (LPC_C_CAN0->CANTXREQ2 << 16);
be_bryan 0:b74591d5ab33 478 uint16_t i = 0;
be_bryan 0:b74591d5ab33 479 for(i = RX_MSG_OBJ_COUNT; i < 32; i++) {
be_bryan 0:b74591d5ab33 480 if ((txPending & (1 << i)) == 0) {
be_bryan 0:b74591d5ab33 481 msgnum = i+1;
be_bryan 0:b74591d5ab33 482 break;
be_bryan 0:b74591d5ab33 483 }
be_bryan 0:b74591d5ab33 484 }
be_bryan 0:b74591d5ab33 485
be_bryan 0:b74591d5ab33 486 // If no messageboxes are available, stop and return failure
be_bryan 0:b74591d5ab33 487 if (msgnum == 0) {
be_bryan 0:b74591d5ab33 488 return 0;
be_bryan 0:b74591d5ab33 489 }
be_bryan 0:b74591d5ab33 490
be_bryan 0:b74591d5ab33 491 // Make sure the interface is available
be_bryan 0:b74591d5ab33 492 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
be_bryan 0:b74591d5ab33 493
be_bryan 0:b74591d5ab33 494 // Set the direction bit based on the message type
be_bryan 0:b74591d5ab33 495 uint32_t direction = 0;
be_bryan 0:b74591d5ab33 496 if (msg.type == CANData) {
be_bryan 0:b74591d5ab33 497 direction = CANIFn_ARB2_DIR;
be_bryan 0:b74591d5ab33 498 }
be_bryan 0:b74591d5ab33 499
be_bryan 0:b74591d5ab33 500 if (msg.format == CANExtended) {
be_bryan 0:b74591d5ab33 501 // Mark message valid, Extended Frame, Set Identifier and mask everything
be_bryan 0:b74591d5ab33 502 LPC_C_CAN0->CANIF1_ARB1 = (msg.id & 0xFFFF);
be_bryan 0:b74591d5ab33 503 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | direction | ((msg.id >> 16) & 0x1FFFF);
be_bryan 0:b74591d5ab33 504 LPC_C_CAN0->CANIF1_MSK1 = (ID_EXT_MASK & 0xFFFF);
be_bryan 0:b74591d5ab33 505 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD | CANIFn_MSK2_MDIR | ((ID_EXT_MASK >> 16) & 0x1FFF);
be_bryan 0:b74591d5ab33 506 } else {
be_bryan 0:b74591d5ab33 507 // Mark message valid, Set Identifier and mask everything
be_bryan 0:b74591d5ab33 508 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | direction | ((msg.id << 2) & 0x1FFF);
be_bryan 0:b74591d5ab33 509 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MDIR | ((ID_STD_MASK << 2) & 0x1FFF);
be_bryan 0:b74591d5ab33 510 }
be_bryan 0:b74591d5ab33 511
be_bryan 0:b74591d5ab33 512 // Use mask, request transmission, single message object and set DLC
be_bryan 0:b74591d5ab33 513 LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_TXRQST | CANIFn_MCTRL_EOB | (msg.len & 0xF);
be_bryan 0:b74591d5ab33 514
be_bryan 0:b74591d5ab33 515 LPC_C_CAN0->CANIF1_DA1 = ((msg.data[1] & 0xFF) << 8) | (msg.data[0] & 0xFF);
be_bryan 0:b74591d5ab33 516 LPC_C_CAN0->CANIF1_DA2 = ((msg.data[3] & 0xFF) << 8) | (msg.data[2] & 0xFF);
be_bryan 0:b74591d5ab33 517 LPC_C_CAN0->CANIF1_DB1 = ((msg.data[5] & 0xFF) << 8) | (msg.data[4] & 0xFF);
be_bryan 0:b74591d5ab33 518 LPC_C_CAN0->CANIF1_DB2 = ((msg.data[7] & 0xFF) << 8) | (msg.data[6] & 0xFF);
be_bryan 0:b74591d5ab33 519
be_bryan 0:b74591d5ab33 520 // Transfer all fields to message object
be_bryan 0:b74591d5ab33 521 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
be_bryan 0:b74591d5ab33 522
be_bryan 0:b74591d5ab33 523 // Start Transfer to given message number
be_bryan 0:b74591d5ab33 524 LPC_C_CAN0->CANIF1_CMDREQ = (msgnum & 0x3F);
be_bryan 0:b74591d5ab33 525
be_bryan 0:b74591d5ab33 526 // Wait until transfer to message ram complete - TODO: maybe not block??
be_bryan 0:b74591d5ab33 527 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY);
be_bryan 0:b74591d5ab33 528
be_bryan 0:b74591d5ab33 529 // Wait until TXOK is set, then clear it - TODO: maybe not block
be_bryan 0:b74591d5ab33 530 //while ( !(LPC_C_CAN0->STAT & CANSTAT_TXOK) );
be_bryan 0:b74591d5ab33 531 LPC_C_CAN0->CANSTAT &= ~(1UL << 3);
be_bryan 0:b74591d5ab33 532
be_bryan 0:b74591d5ab33 533 return 1;
be_bryan 0:b74591d5ab33 534 }
be_bryan 0:b74591d5ab33 535
be_bryan 0:b74591d5ab33 536 int can_read(can_t *obj, CAN_Message *msg, int handle) {
be_bryan 0:b74591d5ab33 537 uint16_t i;
be_bryan 0:b74591d5ab33 538
be_bryan 0:b74591d5ab33 539 // Make sure controller is enabled
be_bryan 0:b74591d5ab33 540 can_enable(obj);
be_bryan 0:b74591d5ab33 541
be_bryan 0:b74591d5ab33 542 // Find first message object with new data
be_bryan 0:b74591d5ab33 543 if (handle == 0) {
be_bryan 0:b74591d5ab33 544 uint32_t newdata = LPC_C_CAN0->CANND1 | (LPC_C_CAN0->CANND2 << 16);
be_bryan 0:b74591d5ab33 545 // Find first free messagebox
be_bryan 0:b74591d5ab33 546 for (i = 0; i < RX_MSG_OBJ_COUNT; i++) {
be_bryan 0:b74591d5ab33 547 if (newdata & (1 << i)) {
be_bryan 0:b74591d5ab33 548 handle = i+1;
be_bryan 0:b74591d5ab33 549 break;
be_bryan 0:b74591d5ab33 550 }
be_bryan 0:b74591d5ab33 551 }
be_bryan 0:b74591d5ab33 552 }
be_bryan 0:b74591d5ab33 553
be_bryan 0:b74591d5ab33 554 if (handle > 0 && handle <= 32) {
be_bryan 0:b74591d5ab33 555 // Wait until message interface is free
be_bryan 0:b74591d5ab33 556 while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
be_bryan 0:b74591d5ab33 557
be_bryan 0:b74591d5ab33 558 // Transfer all fields to message object
be_bryan 0:b74591d5ab33 559 LPC_C_CAN0->CANIF2_CMDMSK_W = CANIFn_CMDMSK_RD | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_CLRINTPND | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
be_bryan 0:b74591d5ab33 560
be_bryan 0:b74591d5ab33 561 // Start Transfer from given message number
be_bryan 0:b74591d5ab33 562 LPC_C_CAN0->CANIF2_CMDREQ = (handle & 0x3F);
be_bryan 0:b74591d5ab33 563
be_bryan 0:b74591d5ab33 564 // Wait until transfer to message ram complete
be_bryan 0:b74591d5ab33 565 while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
be_bryan 0:b74591d5ab33 566
be_bryan 0:b74591d5ab33 567 if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_XTD) {
be_bryan 0:b74591d5ab33 568 msg->format = CANExtended;
be_bryan 0:b74591d5ab33 569 msg->id = (LPC_C_CAN0->CANIF2_ARB1 & 0x1FFF) << 16;
be_bryan 0:b74591d5ab33 570 msg->id |= (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF);
be_bryan 0:b74591d5ab33 571 } else {
be_bryan 0:b74591d5ab33 572 msg->format = CANStandard;
be_bryan 0:b74591d5ab33 573 msg->id = (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF) >> 2;
be_bryan 0:b74591d5ab33 574 }
be_bryan 0:b74591d5ab33 575
be_bryan 0:b74591d5ab33 576 if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_DIR) {
be_bryan 0:b74591d5ab33 577 msg->type = CANRemote;
be_bryan 0:b74591d5ab33 578 }
be_bryan 0:b74591d5ab33 579 else {
be_bryan 0:b74591d5ab33 580 msg->type = CANData;
be_bryan 0:b74591d5ab33 581 }
be_bryan 0:b74591d5ab33 582
be_bryan 0:b74591d5ab33 583 msg->len = (LPC_C_CAN0->CANIF2_MCTRL & 0xF); // TODO: If > 8, len = 8
be_bryan 0:b74591d5ab33 584 msg->data[0] = ((LPC_C_CAN0->CANIF2_DA1 >> 0) & 0xFF);
be_bryan 0:b74591d5ab33 585 msg->data[1] = ((LPC_C_CAN0->CANIF2_DA1 >> 8) & 0xFF);
be_bryan 0:b74591d5ab33 586 msg->data[2] = ((LPC_C_CAN0->CANIF2_DA2 >> 0) & 0xFF);
be_bryan 0:b74591d5ab33 587 msg->data[3] = ((LPC_C_CAN0->CANIF2_DA2 >> 8) & 0xFF);
be_bryan 0:b74591d5ab33 588 msg->data[4] = ((LPC_C_CAN0->CANIF2_DB1 >> 0) & 0xFF);
be_bryan 0:b74591d5ab33 589 msg->data[5] = ((LPC_C_CAN0->CANIF2_DB1 >> 8) & 0xFF);
be_bryan 0:b74591d5ab33 590 msg->data[6] = ((LPC_C_CAN0->CANIF2_DB2 >> 0) & 0xFF);
be_bryan 0:b74591d5ab33 591 msg->data[7] = ((LPC_C_CAN0->CANIF2_DB2 >> 8) & 0xFF);
be_bryan 0:b74591d5ab33 592
be_bryan 0:b74591d5ab33 593 LPC_C_CAN0->CANSTAT &= ~(1UL << 4);
be_bryan 0:b74591d5ab33 594 return 1;
be_bryan 0:b74591d5ab33 595 }
be_bryan 0:b74591d5ab33 596 return 0;
be_bryan 0:b74591d5ab33 597 }
be_bryan 0:b74591d5ab33 598
be_bryan 0:b74591d5ab33 599 void can_reset(can_t *obj) {
be_bryan 0:b74591d5ab33 600 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
be_bryan 0:b74591d5ab33 601 LPC_C_CAN0->CANSTAT = 0;
be_bryan 0:b74591d5ab33 602 can_config_rxmsgobj(obj);
be_bryan 0:b74591d5ab33 603 can_config_txmsgobj(obj);
be_bryan 0:b74591d5ab33 604
be_bryan 0:b74591d5ab33 605 can_enable(obj); // clears a bus-off condition if necessary
be_bryan 0:b74591d5ab33 606 }
be_bryan 0:b74591d5ab33 607
be_bryan 0:b74591d5ab33 608 unsigned char can_rderror(can_t *obj) {
be_bryan 0:b74591d5ab33 609 return ((LPC_C_CAN0->CANEC >> 8) & 0x7F);
be_bryan 0:b74591d5ab33 610 }
be_bryan 0:b74591d5ab33 611
be_bryan 0:b74591d5ab33 612 unsigned char can_tderror(can_t *obj) {
be_bryan 0:b74591d5ab33 613 return (LPC_C_CAN0->CANEC & 0xFF);
be_bryan 0:b74591d5ab33 614 }
be_bryan 0:b74591d5ab33 615
be_bryan 0:b74591d5ab33 616 void can_monitor(can_t *obj, int silent) {
be_bryan 0:b74591d5ab33 617 if (silent) {
be_bryan 0:b74591d5ab33 618 LPC_C_CAN0->CANCNTL |= (1UL << 7);
be_bryan 0:b74591d5ab33 619 LPC_C_CAN0->CANTEST |= (1UL << 3);
be_bryan 0:b74591d5ab33 620 } else {
be_bryan 0:b74591d5ab33 621 LPC_C_CAN0->CANCNTL &= ~(1UL << 7);
be_bryan 0:b74591d5ab33 622 LPC_C_CAN0->CANTEST &= ~(1UL << 3);
be_bryan 0:b74591d5ab33 623 }
be_bryan 0:b74591d5ab33 624
be_bryan 0:b74591d5ab33 625 if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
be_bryan 0:b74591d5ab33 626 LPC_C_CAN0->CANCNTL |= (1UL << 0);
be_bryan 0:b74591d5ab33 627 }
be_bryan 0:b74591d5ab33 628 }