EL4121 Embedded System / mbed-os

mbed-os

Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_Freescale/TARGET_K20XX/spi_api.c@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /* mbed Microcontroller Library
be_bryan 0:b74591d5ab33 2 * Copyright (c) 2015 ARM Limited
be_bryan 0:b74591d5ab33 3 *
be_bryan 0:b74591d5ab33 4 * Licensed under the Apache License, Version 2.0 (the "License");
be_bryan 0:b74591d5ab33 5 * you may not use this file except in compliance with the License.
be_bryan 0:b74591d5ab33 6 * You may obtain a copy of the License at
be_bryan 0:b74591d5ab33 7 *
be_bryan 0:b74591d5ab33 8 * http://www.apache.org/licenses/LICENSE-2.0
be_bryan 0:b74591d5ab33 9 *
be_bryan 0:b74591d5ab33 10 * Unless required by applicable law or agreed to in writing, software
be_bryan 0:b74591d5ab33 11 * distributed under the License is distributed on an "AS IS" BASIS,
be_bryan 0:b74591d5ab33 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan 0:b74591d5ab33 13 * See the License for the specific language governing permissions and
be_bryan 0:b74591d5ab33 14 * limitations under the License.
be_bryan 0:b74591d5ab33 15 */
be_bryan 0:b74591d5ab33 16 #include "mbed_assert.h"
be_bryan 0:b74591d5ab33 17 #include "spi_api.h"
be_bryan 0:b74591d5ab33 18
be_bryan 0:b74591d5ab33 19 #include <math.h>
be_bryan 0:b74591d5ab33 20
be_bryan 0:b74591d5ab33 21 #include "cmsis.h"
be_bryan 0:b74591d5ab33 22 #include "pinmap.h"
be_bryan 0:b74591d5ab33 23 #include "clk_freqs.h"
be_bryan 0:b74591d5ab33 24 #include "PeripheralPins.h"
be_bryan 0:b74591d5ab33 25
be_bryan 0:b74591d5ab33 26 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
be_bryan 0:b74591d5ab33 27 // determine the SPI to use
be_bryan 0:b74591d5ab33 28 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
be_bryan 0:b74591d5ab33 29 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
be_bryan 0:b74591d5ab33 30 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
be_bryan 0:b74591d5ab33 31 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
be_bryan 0:b74591d5ab33 32 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
be_bryan 0:b74591d5ab33 33 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
be_bryan 0:b74591d5ab33 34
be_bryan 0:b74591d5ab33 35 obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
be_bryan 0:b74591d5ab33 36 MBED_ASSERT((int)obj->spi != NC);
be_bryan 0:b74591d5ab33 37
be_bryan 0:b74591d5ab33 38 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK;
be_bryan 0:b74591d5ab33 39 SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
be_bryan 0:b74591d5ab33 40
be_bryan 0:b74591d5ab33 41 obj->spi->MCR &= ~(SPI_MCR_MDIS_MASK | SPI_MCR_HALT_MASK);
be_bryan 0:b74591d5ab33 42 //obj->spi->MCR |= SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK;
be_bryan 0:b74591d5ab33 43
be_bryan 0:b74591d5ab33 44 // not halt in the debug mode
be_bryan 0:b74591d5ab33 45 obj->spi->SR |= SPI_SR_EOQF_MASK;
be_bryan 0:b74591d5ab33 46
be_bryan 0:b74591d5ab33 47 // pin out the spi pins
be_bryan 0:b74591d5ab33 48 pinmap_pinout(mosi, PinMap_SPI_MOSI);
be_bryan 0:b74591d5ab33 49 pinmap_pinout(miso, PinMap_SPI_MISO);
be_bryan 0:b74591d5ab33 50 pinmap_pinout(sclk, PinMap_SPI_SCLK);
be_bryan 0:b74591d5ab33 51 if (ssel != NC) {
be_bryan 0:b74591d5ab33 52 pinmap_pinout(ssel, PinMap_SPI_SSEL);
be_bryan 0:b74591d5ab33 53 }
be_bryan 0:b74591d5ab33 54 }
be_bryan 0:b74591d5ab33 55
be_bryan 0:b74591d5ab33 56 void spi_free(spi_t *obj) {
be_bryan 0:b74591d5ab33 57 // [TODO]
be_bryan 0:b74591d5ab33 58 }
be_bryan 0:b74591d5ab33 59 void spi_format(spi_t *obj, int bits, int mode, int slave) {
be_bryan 0:b74591d5ab33 60 MBED_ASSERT((bits > 4) || (bits < 16));
be_bryan 0:b74591d5ab33 61 MBED_ASSERT((mode >= 0) && (mode <= 3));
be_bryan 0:b74591d5ab33 62
be_bryan 0:b74591d5ab33 63 uint8_t polarity = (mode & 0x2) ? 1 : 0;
be_bryan 0:b74591d5ab33 64 uint8_t phase = (mode & 0x1) ? 1 : 0;
be_bryan 0:b74591d5ab33 65 uint8_t old_polarity = (obj->spi->CTAR[0] & SPI_CTAR_CPOL_MASK) != 0;
be_bryan 0:b74591d5ab33 66
be_bryan 0:b74591d5ab33 67 // set master/slave
be_bryan 0:b74591d5ab33 68 if (slave) {
be_bryan 0:b74591d5ab33 69 obj->spi->MCR &= ~SPI_MCR_MSTR_MASK;
be_bryan 0:b74591d5ab33 70 } else {
be_bryan 0:b74591d5ab33 71 obj->spi->MCR |= (1UL << SPI_MCR_MSTR_SHIFT);
be_bryan 0:b74591d5ab33 72 }
be_bryan 0:b74591d5ab33 73
be_bryan 0:b74591d5ab33 74 // CTAR0 is used
be_bryan 0:b74591d5ab33 75 obj->spi->CTAR[0] &= ~(SPI_CTAR_CPHA_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_FMSZ_MASK);
be_bryan 0:b74591d5ab33 76 obj->spi->CTAR[0] |= (polarity << SPI_CTAR_CPOL_SHIFT) | (phase << SPI_CTAR_CPHA_SHIFT) | ((bits - 1) << SPI_CTAR_FMSZ_SHIFT);
be_bryan 0:b74591d5ab33 77
be_bryan 0:b74591d5ab33 78 //If clk idle state was changed, start a dummy transmission
be_bryan 0:b74591d5ab33 79 //This is a 'feature' in DSPI: https://community.freescale.com/thread/105526
be_bryan 0:b74591d5ab33 80 if ((old_polarity != polarity) && (slave == 0)) {
be_bryan 0:b74591d5ab33 81 //Start transfer (CS should be high, so shouldn't matter)
be_bryan 0:b74591d5ab33 82 spi_master_write(obj, 0xFFFF);
be_bryan 0:b74591d5ab33 83 }
be_bryan 0:b74591d5ab33 84 }
be_bryan 0:b74591d5ab33 85
be_bryan 0:b74591d5ab33 86 static const uint8_t baudrate_prescaler[] = {2,3,5,7};
be_bryan 0:b74591d5ab33 87 static const uint16_t baudrate_scaler[] = {2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768};
be_bryan 0:b74591d5ab33 88
be_bryan 0:b74591d5ab33 89 void spi_frequency(spi_t *obj, int hz) {
be_bryan 0:b74591d5ab33 90 uint32_t f_error = 0;
be_bryan 0:b74591d5ab33 91 uint32_t p_error = 0xffffffff;
be_bryan 0:b74591d5ab33 92 uint32_t ref = 0;
be_bryan 0:b74591d5ab33 93 uint32_t br = 0;
be_bryan 0:b74591d5ab33 94 uint32_t ref_spr = 0;
be_bryan 0:b74591d5ab33 95 uint32_t ref_prescaler = 0;
be_bryan 0:b74591d5ab33 96 uint32_t ref_dr = 0;
be_bryan 0:b74591d5ab33 97
be_bryan 0:b74591d5ab33 98 // bus clk
be_bryan 0:b74591d5ab33 99 uint32_t PCLK = bus_frequency();
be_bryan 0:b74591d5ab33 100
be_bryan 0:b74591d5ab33 101 for (uint32_t i = 0; i < 4; i++) {
be_bryan 0:b74591d5ab33 102 for (br = 0; br <= 15; br++) {
be_bryan 0:b74591d5ab33 103 for (uint32_t dr = 0; dr < 2; dr++) {
be_bryan 0:b74591d5ab33 104 ref = (PCLK * (1U + dr) / baudrate_prescaler[i]) / baudrate_scaler[br];
be_bryan 0:b74591d5ab33 105 if (ref > (uint32_t)hz)
be_bryan 0:b74591d5ab33 106 continue;
be_bryan 0:b74591d5ab33 107 f_error = hz - ref;
be_bryan 0:b74591d5ab33 108 if (f_error < p_error) {
be_bryan 0:b74591d5ab33 109 ref_spr = br;
be_bryan 0:b74591d5ab33 110 ref_prescaler = i;
be_bryan 0:b74591d5ab33 111 ref_dr = dr;
be_bryan 0:b74591d5ab33 112 p_error = f_error;
be_bryan 0:b74591d5ab33 113 }
be_bryan 0:b74591d5ab33 114 }
be_bryan 0:b74591d5ab33 115 }
be_bryan 0:b74591d5ab33 116 }
be_bryan 0:b74591d5ab33 117
be_bryan 0:b74591d5ab33 118 // set PBR and BR
be_bryan 0:b74591d5ab33 119 obj->spi->CTAR[0] &= ~(SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK | SPI_CTAR_DBR_MASK);
be_bryan 0:b74591d5ab33 120 obj->spi->CTAR[0] |= (ref_prescaler << SPI_CTAR_PBR_SHIFT) | (ref_spr << SPI_CTAR_BR_SHIFT) | (ref_dr << SPI_CTAR_DBR_SHIFT);
be_bryan 0:b74591d5ab33 121 }
be_bryan 0:b74591d5ab33 122
be_bryan 0:b74591d5ab33 123 static inline int spi_writeable(spi_t *obj) {
be_bryan 0:b74591d5ab33 124 return (obj->spi->SR & SPI_SR_TFFF_MASK) ? 1 : 0;
be_bryan 0:b74591d5ab33 125 }
be_bryan 0:b74591d5ab33 126
be_bryan 0:b74591d5ab33 127 static inline int spi_readable(spi_t *obj) {
be_bryan 0:b74591d5ab33 128 return (obj->spi->SR & SPI_SR_RFDF_MASK) ? 1 : 0;
be_bryan 0:b74591d5ab33 129 }
be_bryan 0:b74591d5ab33 130
be_bryan 0:b74591d5ab33 131 int spi_master_write(spi_t *obj, int value) {
be_bryan 0:b74591d5ab33 132 //clear RX buffer flag
be_bryan 0:b74591d5ab33 133 obj->spi->SR |= SPI_SR_RFDF_MASK;
be_bryan 0:b74591d5ab33 134 // wait tx buffer empty
be_bryan 0:b74591d5ab33 135 while(!spi_writeable(obj));
be_bryan 0:b74591d5ab33 136 obj->spi->PUSHR = SPI_PUSHR_TXDATA(value & 0xffff) /*| SPI_PUSHR_EOQ_MASK*/;
be_bryan 0:b74591d5ab33 137
be_bryan 0:b74591d5ab33 138 // wait rx buffer full
be_bryan 0:b74591d5ab33 139 while (!spi_readable(obj));
be_bryan 0:b74591d5ab33 140 return obj->spi->POPR;
be_bryan 0:b74591d5ab33 141 }
be_bryan 0:b74591d5ab33 142
be_bryan 0:b74591d5ab33 143 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
be_bryan 0:b74591d5ab33 144 char *rx_buffer, int rx_length, char write_fill) {
be_bryan 0:b74591d5ab33 145 int total = (tx_length > rx_length) ? tx_length : rx_length;
be_bryan 0:b74591d5ab33 146
be_bryan 0:b74591d5ab33 147 for (int i = 0; i < total; i++) {
be_bryan 0:b74591d5ab33 148 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
be_bryan 0:b74591d5ab33 149 char in = spi_master_write(obj, out);
be_bryan 0:b74591d5ab33 150 if (i < rx_length) {
be_bryan 0:b74591d5ab33 151 rx_buffer[i] = in;
be_bryan 0:b74591d5ab33 152 }
be_bryan 0:b74591d5ab33 153 }
be_bryan 0:b74591d5ab33 154
be_bryan 0:b74591d5ab33 155 return total;
be_bryan 0:b74591d5ab33 156 }
be_bryan 0:b74591d5ab33 157
be_bryan 0:b74591d5ab33 158 int spi_slave_receive(spi_t *obj) {
be_bryan 0:b74591d5ab33 159 return spi_readable(obj);
be_bryan 0:b74591d5ab33 160 }
be_bryan 0:b74591d5ab33 161
be_bryan 0:b74591d5ab33 162 int spi_slave_read(spi_t *obj) {
be_bryan 0:b74591d5ab33 163 obj->spi->SR |= SPI_SR_RFDF_MASK;
be_bryan 0:b74591d5ab33 164 return obj->spi->POPR;
be_bryan 0:b74591d5ab33 165 }
be_bryan 0:b74591d5ab33 166
be_bryan 0:b74591d5ab33 167 void spi_slave_write(spi_t *obj, int value) {
be_bryan 0:b74591d5ab33 168 while (!spi_writeable(obj));
be_bryan 0:b74591d5ab33 169 }