EL4121 Embedded System / mbed-os

mbed-os

Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_Freescale/TARGET_K20XX/clk_freqs.h@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /* mbed Microcontroller Library
be_bryan 0:b74591d5ab33 2 * Copyright (c) 2006-2015 ARM Limited
be_bryan 0:b74591d5ab33 3 *
be_bryan 0:b74591d5ab33 4 * Licensed under the Apache License, Version 2.0 (the "License");
be_bryan 0:b74591d5ab33 5 * you may not use this file except in compliance with the License.
be_bryan 0:b74591d5ab33 6 * You may obtain a copy of the License at
be_bryan 0:b74591d5ab33 7 *
be_bryan 0:b74591d5ab33 8 * http://www.apache.org/licenses/LICENSE-2.0
be_bryan 0:b74591d5ab33 9 *
be_bryan 0:b74591d5ab33 10 * Unless required by applicable law or agreed to in writing, software
be_bryan 0:b74591d5ab33 11 * distributed under the License is distributed on an "AS IS" BASIS,
be_bryan 0:b74591d5ab33 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan 0:b74591d5ab33 13 * See the License for the specific language governing permissions and
be_bryan 0:b74591d5ab33 14 * limitations under the License.
be_bryan 0:b74591d5ab33 15 */
be_bryan 0:b74591d5ab33 16 #ifndef CLK_FREQS_H
be_bryan 0:b74591d5ab33 17 #define CLK_FREQS_H
be_bryan 0:b74591d5ab33 18
be_bryan 0:b74591d5ab33 19 #ifdef __cplusplus
be_bryan 0:b74591d5ab33 20 extern "C" {
be_bryan 0:b74591d5ab33 21 #endif
be_bryan 0:b74591d5ab33 22
be_bryan 0:b74591d5ab33 23 /*!
be_bryan 0:b74591d5ab33 24 * \brief Get the peripheral bus clock frequency
be_bryan 0:b74591d5ab33 25 * \return Bus frequency
be_bryan 0:b74591d5ab33 26 */
be_bryan 0:b74591d5ab33 27 static inline uint32_t bus_frequency(void) {
be_bryan 0:b74591d5ab33 28 return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1);
be_bryan 0:b74591d5ab33 29 }
be_bryan 0:b74591d5ab33 30
be_bryan 0:b74591d5ab33 31 /*!
be_bryan 0:b74591d5ab33 32 * \brief Get external oscillator (crystal) frequency
be_bryan 0:b74591d5ab33 33 * \return External osc frequency
be_bryan 0:b74591d5ab33 34 */
be_bryan 0:b74591d5ab33 35 static uint32_t extosc_frequency(void) {
be_bryan 0:b74591d5ab33 36 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
be_bryan 0:b74591d5ab33 37
be_bryan 0:b74591d5ab33 38 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
be_bryan 0:b74591d5ab33 39 return MCGClock;
be_bryan 0:b74591d5ab33 40
be_bryan 0:b74591d5ab33 41 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
be_bryan 0:b74591d5ab33 42 uint32_t divider, multiplier;
be_bryan 0:b74591d5ab33 43 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
be_bryan 0:b74591d5ab33 44 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
be_bryan 0:b74591d5ab33 45 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
be_bryan 0:b74591d5ab33 46 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
be_bryan 0:b74591d5ab33 47 divider <<= 5u;
be_bryan 0:b74591d5ab33 48 /* Select correct multiplier to calculate the MCG output clock */
be_bryan 0:b74591d5ab33 49 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
be_bryan 0:b74591d5ab33 50 case 0x0u:
be_bryan 0:b74591d5ab33 51 multiplier = 640u;
be_bryan 0:b74591d5ab33 52 break;
be_bryan 0:b74591d5ab33 53 case 0x20u:
be_bryan 0:b74591d5ab33 54 multiplier = 1280u;
be_bryan 0:b74591d5ab33 55 break;
be_bryan 0:b74591d5ab33 56 case 0x40u:
be_bryan 0:b74591d5ab33 57 multiplier = 1920u;
be_bryan 0:b74591d5ab33 58 break;
be_bryan 0:b74591d5ab33 59 case 0x60u:
be_bryan 0:b74591d5ab33 60 multiplier = 2560u;
be_bryan 0:b74591d5ab33 61 break;
be_bryan 0:b74591d5ab33 62 case 0x80u:
be_bryan 0:b74591d5ab33 63 multiplier = 732u;
be_bryan 0:b74591d5ab33 64 break;
be_bryan 0:b74591d5ab33 65 case 0xA0u:
be_bryan 0:b74591d5ab33 66 multiplier = 1464u;
be_bryan 0:b74591d5ab33 67 break;
be_bryan 0:b74591d5ab33 68 case 0xC0u:
be_bryan 0:b74591d5ab33 69 multiplier = 2197u;
be_bryan 0:b74591d5ab33 70 break;
be_bryan 0:b74591d5ab33 71 case 0xE0u:
be_bryan 0:b74591d5ab33 72 default:
be_bryan 0:b74591d5ab33 73 multiplier = 2929u;
be_bryan 0:b74591d5ab33 74 break;
be_bryan 0:b74591d5ab33 75 }
be_bryan 0:b74591d5ab33 76
be_bryan 0:b74591d5ab33 77 return MCGClock * divider / multiplier;
be_bryan 0:b74591d5ab33 78 }
be_bryan 0:b74591d5ab33 79 } else { //PLL is selected
be_bryan 0:b74591d5ab33 80 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
be_bryan 0:b74591d5ab33 81 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
be_bryan 0:b74591d5ab33 82 return MCGClock * divider / multiplier;
be_bryan 0:b74591d5ab33 83 }
be_bryan 0:b74591d5ab33 84 }
be_bryan 0:b74591d5ab33 85
be_bryan 0:b74591d5ab33 86 //In all other cases either there is no crystal or we cannot determine it
be_bryan 0:b74591d5ab33 87 //For example when the FLL is running on the internal reference, and there is also an
be_bryan 0:b74591d5ab33 88 //external crystal. However these are unlikely situations
be_bryan 0:b74591d5ab33 89 return 0;
be_bryan 0:b74591d5ab33 90 }
be_bryan 0:b74591d5ab33 91
be_bryan 0:b74591d5ab33 92 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
be_bryan 0:b74591d5ab33 93 static uint32_t mcgpllfll_frequency(void) {
be_bryan 0:b74591d5ab33 94 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
be_bryan 0:b74591d5ab33 95 return 0;
be_bryan 0:b74591d5ab33 96
be_bryan 0:b74591d5ab33 97 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
be_bryan 0:b74591d5ab33 98 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
be_bryan 0:b74591d5ab33 99 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
be_bryan 0:b74591d5ab33 100 return MCGClock;
be_bryan 0:b74591d5ab33 101 } else { //PLL is selected
be_bryan 0:b74591d5ab33 102 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
be_bryan 0:b74591d5ab33 103 return MCGClock;
be_bryan 0:b74591d5ab33 104 }
be_bryan 0:b74591d5ab33 105
be_bryan 0:b74591d5ab33 106 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
be_bryan 0:b74591d5ab33 107 //for the peripherals, this is however an unlikely setup
be_bryan 0:b74591d5ab33 108 }
be_bryan 0:b74591d5ab33 109
be_bryan 0:b74591d5ab33 110
be_bryan 0:b74591d5ab33 111 #ifdef __cplusplus
be_bryan 0:b74591d5ab33 112 }
be_bryan 0:b74591d5ab33 113 #endif
be_bryan 0:b74591d5ab33 114
be_bryan 0:b74591d5ab33 115 #endif