ECE4333 - 2018 - Ahmed & Brandon / Mbed OS PlayBackFinal

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Drivers/DE0_driver.cpp@1:3e9684e81312, 2018-02-03 (annotated)

Committer:
asobhy
Date:
Sat Feb 03 00:05:08 2018 +0000
Revision:
1:3e9684e81312
Parent:
0:a355e511bc5d
Child:
7:73fd05fe556a
setpoint represent velocity

Who changed what in which revision?

UserRevisionLine numberNew contents of line
asobhy 0:a355e511bc5d 1 // DE0 FPGA driver
asobhy 0:a355e511bc5d 2
asobhy 0:a355e511bc5d 3 #include "mbed.h"
asobhy 0:a355e511bc5d 4
asobhy 0:a355e511bc5d 5 #define DUMMY 0
asobhy 0:a355e511bc5d 6
asobhy 0:a355e511bc5d 7 SPI DE0(p5, p6, p7); // Configure pins and name SPI port.
asobhy 0:a355e511bc5d 8
asobhy 0:a355e511bc5d 9 void ResetDE0(void);
asobhy 0:a355e511bc5d 10 void RestartSpi(void);
asobhy 0:a355e511bc5d 11
asobhy 0:a355e511bc5d 12 DigitalOut IoReset(p15); // 0-1-0 reset for all SPI peripherals in the DE0 FPGA
asobhy 0:a355e511bc5d 13 DigitalOut SpiReset(p14); // 0-1-0 tells the DE0 SPI interace that the next word sent is a control word
asobhy 0:a355e511bc5d 14
asobhy 0:a355e511bc5d 15
asobhy 1:3e9684e81312 16 int SignExtend(int16_t x)
asobhy 1:3e9684e81312 17 {
asobhy 1:3e9684e81312 18
asobhy 1:3e9684e81312 19 // if number is negative
asobhy 1:3e9684e81312 20 if(x&0x00008000) {
asobhy 1:3e9684e81312 21 // reserve the sign bit into the 32-bit number
asobhy 1:3e9684e81312 22 x = x|0xFFFF0000;
asobhy 1:3e9684e81312 23 }
asobhy 1:3e9684e81312 24
asobhy 1:3e9684e81312 25 return x;
asobhy 1:3e9684e81312 26 }
asobhy 1:3e9684e81312 27
asobhy 1:3e9684e81312 28
asobhy 0:a355e511bc5d 29 // To reset all SPI peripheral on the FPGA:
asobhy 0:a355e511bc5d 30 void ResetDE0(void){
asobhy 0:a355e511bc5d 31 IoReset=0; // Reset all DE0 peripherals
asobhy 0:a355e511bc5d 32 IoReset=1;
asobhy 0:a355e511bc5d 33 wait_us(5);
asobhy 0:a355e511bc5d 34 IoReset=0;
asobhy 0:a355e511bc5d 35 }
asobhy 0:a355e511bc5d 36
asobhy 0:a355e511bc5d 37 // To reset the SPI channel in the slave and restart with a new SPI protocol.
asobhy 0:a355e511bc5d 38 void RestartSpi(void) {
asobhy 0:a355e511bc5d 39 // Restart DE0 SPI channel so the next word sent is interpreted as the Control Word
asobhy 0:a355e511bc5d 40 SpiReset=0;
asobhy 0:a355e511bc5d 41 SpiReset=1;
asobhy 0:a355e511bc5d 42 wait_us(5);
asobhy 0:a355e511bc5d 43 SpiReset=0;
asobhy 0:a355e511bc5d 44 }
asobhy 0:a355e511bc5d 45
asobhy 0:a355e511bc5d 46 void DE0_init(void)
asobhy 0:a355e511bc5d 47 {
asobhy 0:a355e511bc5d 48 DE0.format(16,1); // Define SPI format: 16-bit words, mode 1 protocol.
asobhy 0:a355e511bc5d 49 DE0.frequency(500000); // Set SPI bit rate (Hz). Default is 1 MHz
asobhy 0:a355e511bc5d 50 ResetDE0();
asobhy 0:a355e511bc5d 51 }
asobhy 0:a355e511bc5d 52
asobhy 0:a355e511bc5d 53 /*
asobhy 0:a355e511bc5d 54
asobhy 0:a355e511bc5d 55 Before an SPI data transaction with the DE0 FPGA can occur, a control word must
asobhy 0:a355e511bc5d 56 first be written to the slave that specifies:
asobhy 0:a355e511bc5d 57
asobhy 0:a355e511bc5d 58 i) the number of word transfers,
asobhy 0:a355e511bc5d 59 ii) the offset or starting address within the slave, and
asobhy 0:a355e511bc5d 60 iii) whether the transaction consists of ‘simultaneous read write’ or whether the
asobhy 0:a355e511bc5d 61 transactions are ‘read only’ (from the slave).
asobhy 0:a355e511bc5d 62
asobhy 0:a355e511bc5d 63 A control word need only be written once – if the same transactions are repeated.
asobhy 0:a355e511bc5d 64 Subsequent transactions use the protocol specified by the last control word that
asobhy 0:a355e511bc5d 65 was written. To change the transaction protocol a new control needs to be
asobhy 0:a355e511bc5d 66 written. To write a new control word, the SpiReset input must first be set then
asobhy 0:a355e511bc5d 67 cleared followed by a SPI write of a 16-bit word that is interpreted as the
asobhy 0:a355e511bc5d 68 control word by the slave.
asobhy 0:a355e511bc5d 69
asobhy 0:a355e511bc5d 70 The 16-bit control word format appears below.
asobhy 0:a355e511bc5d 71
asobhy 0:a355e511bc5d 72 1 7bits 8bits
asobhy 0:a355e511bc5d 73 rd | address offset | number of words
asobhy 0:a355e511bc5d 74
asobhy 0:a355e511bc5d 75
asobhy 0:a355e511bc5d 76 When RD = 1, no write operation occurs within the slave. Data on the MOSI is
asobhy 0:a355e511bc5d 77 ignored by the slave. When RD = 0, a simultaneous read + write of the slave
asobhy 0:a355e511bc5d 78 occurs.
asobhy 0:a355e511bc5d 79
asobhy 0:a355e511bc5d 80 */
asobhy 0:a355e511bc5d 81
asobhy 0:a355e511bc5d 82
asobhy 1:3e9684e81312 83 void DE0_read(uint16_t * id, int * dP, uint16_t * dT)
asobhy 0:a355e511bc5d 84 {
asobhy 0:a355e511bc5d 85 // To place SPI module into control mode, where the next word received by the
asobhy 0:a355e511bc5d 86 // slave is interpreted as a control word.
asobhy 0:a355e511bc5d 87 RestartSpi();
asobhy 0:a355e511bc5d 88
asobhy 0:a355e511bc5d 89 // rd = 1 (control if 1) address = 0 no of word = 2 - Specify a read only transactions of 2 words
asobhy 0:a355e511bc5d 90 *id = (uint16_t)DE0.write(0x8002);
asobhy 0:a355e511bc5d 91
asobhy 0:a355e511bc5d 92 // Read the two 16 bits registers from the FPGA
asobhy 1:3e9684e81312 93 *dP = SignExtend(DE0.write(DUMMY)); // A SPI read only transaction occurs.
asobhy 1:3e9684e81312 94 *dT = DE0.write(DUMMY); //
asobhy 0:a355e511bc5d 95 }
asobhy 0:a355e511bc5d 96
asobhy 0:a355e511bc5d 97
asobhy 0:a355e511bc5d 98
asobhy 0:a355e511bc5d 99