ECE4333 - 2018 - Ahmed & Brandon / Mbed OS PlayBackFinal

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Drivers/DE0_driver.cpp@8:a0890fa79084, 2018-02-19 (annotated)

Committer:
asobhy
Date:
Mon Feb 19 17:42:33 2018 +0000
Revision:
8:a0890fa79084
Parent:
7:73fd05fe556a
Child:
9:fe56b888985c
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asobhy 8:a0890fa79084 1 /******************************************************************************/
asobhy 8:a0890fa79084 2 // ECE4333
asobhy 8:a0890fa79084 3 // LAB Partner 1: Ahmed Sobhy - ID: 3594449
asobhy 8:a0890fa79084 4 // LAB Partner 2: Brandon Kingman - ID: 3470444
asobhy 8:a0890fa79084 5 // Project: Autonomous Robot Design
asobhy 8:a0890fa79084 6 // Instructor: Prof. Chris Diduch
asobhy 8:a0890fa79084 7 /******************************************************************************/
asobhy 8:a0890fa79084 8 // filename: DE0_driver.cpp
asobhy 8:a0890fa79084 9 // file content description:
asobhy 8:a0890fa79084 10 // * function to initialize the hardware interface for communication
asobhy 8:a0890fa79084 11 // between the FPGA and LPC1768
asobhy 8:a0890fa79084 12 // * function to read required data from the DE0 (FPGA).
asobhy 8:a0890fa79084 13 /******************************************************************************/
asobhy 0:a355e511bc5d 14
asobhy 0:a355e511bc5d 15 #include "mbed.h"
asobhy 0:a355e511bc5d 16
asobhy 0:a355e511bc5d 17 #define DUMMY 0
asobhy 0:a355e511bc5d 18
asobhy 0:a355e511bc5d 19 SPI DE0(p5, p6, p7); // Configure pins and name SPI port.
asobhy 0:a355e511bc5d 20
asobhy 0:a355e511bc5d 21 void ResetDE0(void);
asobhy 0:a355e511bc5d 22 void RestartSpi(void);
asobhy 0:a355e511bc5d 23
asobhy 0:a355e511bc5d 24 DigitalOut IoReset(p15); // 0-1-0 reset for all SPI peripherals in the DE0 FPGA
asobhy 0:a355e511bc5d 25 DigitalOut SpiReset(p14); // 0-1-0 tells the DE0 SPI interace that the next word sent is a control word
asobhy 0:a355e511bc5d 26
asobhy 0:a355e511bc5d 27
asobhy 1:3e9684e81312 28 int SignExtend(int16_t x)
asobhy 1:3e9684e81312 29 {
asobhy 1:3e9684e81312 30 // if number is negative
asobhy 1:3e9684e81312 31 if(x&0x00008000) {
asobhy 1:3e9684e81312 32 // reserve the sign bit into the 32-bit number
asobhy 1:3e9684e81312 33 x = x|0xFFFF0000;
asobhy 1:3e9684e81312 34 }
asobhy 1:3e9684e81312 35 return x;
asobhy 1:3e9684e81312 36 }
asobhy 1:3e9684e81312 37
asobhy 1:3e9684e81312 38
asobhy 0:a355e511bc5d 39 // To reset all SPI peripheral on the FPGA:
asobhy 0:a355e511bc5d 40 void ResetDE0(void){
asobhy 0:a355e511bc5d 41 IoReset=0; // Reset all DE0 peripherals
asobhy 0:a355e511bc5d 42 IoReset=1;
asobhy 0:a355e511bc5d 43 wait_us(5);
asobhy 0:a355e511bc5d 44 IoReset=0;
asobhy 0:a355e511bc5d 45 }
asobhy 0:a355e511bc5d 46
asobhy 0:a355e511bc5d 47 // To reset the SPI channel in the slave and restart with a new SPI protocol.
asobhy 0:a355e511bc5d 48 void RestartSpi(void) {
asobhy 0:a355e511bc5d 49 // Restart DE0 SPI channel so the next word sent is interpreted as the Control Word
asobhy 0:a355e511bc5d 50 SpiReset=0;
asobhy 0:a355e511bc5d 51 SpiReset=1;
asobhy 0:a355e511bc5d 52 wait_us(5);
asobhy 0:a355e511bc5d 53 SpiReset=0;
asobhy 0:a355e511bc5d 54 }
asobhy 0:a355e511bc5d 55
asobhy 7:73fd05fe556a 56
asobhy 7:73fd05fe556a 57 /*******************************************************************************
asobhy 7:73fd05fe556a 58 * @brief This is the initialization function for the DE0 FPGA - communication
asobhy 7:73fd05fe556a 59 between the FPGA and MCU is done through SPI. The function
asobhy 7:73fd05fe556a 60 initializes the SPI channel to a bit rate of 500kbps
asobhy 7:73fd05fe556a 61 * @param none
asobhy 7:73fd05fe556a 62 * @return none
asobhy 7:73fd05fe556a 63 *******************************************************************************/
asobhy 0:a355e511bc5d 64 void DE0_init(void)
asobhy 0:a355e511bc5d 65 {
asobhy 0:a355e511bc5d 66 DE0.format(16,1); // Define SPI format: 16-bit words, mode 1 protocol.
asobhy 0:a355e511bc5d 67 DE0.frequency(500000); // Set SPI bit rate (Hz). Default is 1 MHz
asobhy 0:a355e511bc5d 68 ResetDE0();
asobhy 0:a355e511bc5d 69 }
asobhy 0:a355e511bc5d 70
asobhy 7:73fd05fe556a 71 /*******************************************************************************
asobhy 0:a355e511bc5d 72 Before an SPI data transaction with the DE0 FPGA can occur, a control word must
asobhy 0:a355e511bc5d 73 first be written to the slave that specifies:
asobhy 0:a355e511bc5d 74
asobhy 0:a355e511bc5d 75 i) the number of word transfers,
asobhy 0:a355e511bc5d 76 ii) the offset or starting address within the slave, and
asobhy 0:a355e511bc5d 77 iii) whether the transaction consists of ‘simultaneous read write’ or whether the
asobhy 0:a355e511bc5d 78 transactions are ‘read only’ (from the slave).
asobhy 0:a355e511bc5d 79
asobhy 0:a355e511bc5d 80 A control word need only be written once – if the same transactions are repeated.
asobhy 0:a355e511bc5d 81 Subsequent transactions use the protocol specified by the last control word that
asobhy 7:73fd05fe556a 82 was written. To change the transaction protocol a new control needs to be
asobhy 7:73fd05fe556a 83 written. To write a new control word, the SpiReset input must first be set then
asobhy 7:73fd05fe556a 84 cleared followed by a SPI write of a 16-bit word that is interpreted as the
asobhy 7:73fd05fe556a 85 control word by the slave.
asobhy 0:a355e511bc5d 86
asobhy 7:73fd05fe556a 87 The 16-bit control word format appears below.
asobhy 0:a355e511bc5d 88
asobhy 0:a355e511bc5d 89 1 7bits 8bits
asobhy 0:a355e511bc5d 90 rd | address offset | number of words
asobhy 0:a355e511bc5d 91
asobhy 0:a355e511bc5d 92 When RD = 1, no write operation occurs within the slave. Data on the MOSI is
asobhy 0:a355e511bc5d 93 ignored by the slave. When RD = 0, a simultaneous read + write of the slave
asobhy 0:a355e511bc5d 94 occurs.
asobhy 7:73fd05fe556a 95 *******************************************************************************/
asobhy 0:a355e511bc5d 96
asobhy 0:a355e511bc5d 97
asobhy 7:73fd05fe556a 98 /*******************************************************************************
asobhy 7:73fd05fe556a 99 * @brief This function reads the output from the FPGA through the SPI channel
asobhy 7:73fd05fe556a 100 * @param none
asobhy 7:73fd05fe556a 101 * @return none
asobhy 7:73fd05fe556a 102 *******************************************************************************/
asobhy 1:3e9684e81312 103 void DE0_read(uint16_t * id, int * dP, uint16_t * dT)
asobhy 0:a355e511bc5d 104 {
asobhy 0:a355e511bc5d 105 // To place SPI module into control mode, where the next word received by the
asobhy 0:a355e511bc5d 106 // slave is interpreted as a control word.
asobhy 0:a355e511bc5d 107 RestartSpi();
asobhy 0:a355e511bc5d 108
asobhy 0:a355e511bc5d 109 // rd = 1 (control if 1) address = 0 no of word = 2 - Specify a read only transactions of 2 words
asobhy 0:a355e511bc5d 110 *id = (uint16_t)DE0.write(0x8002);
asobhy 0:a355e511bc5d 111
asobhy 0:a355e511bc5d 112 // Read the two 16 bits registers from the FPGA
asobhy 1:3e9684e81312 113 *dP = SignExtend(DE0.write(DUMMY)); // A SPI read only transaction occurs.
asobhy 1:3e9684e81312 114 *dT = DE0.write(DUMMY); //
asobhy 0:a355e511bc5d 115 }
asobhy 0:a355e511bc5d 116