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SCB_Type Struct Reference
[System Control Block (SCB)]
Structure type to access the System Control Block (SCB). More...
#include <core_cm3.h>
Data Fields | |
| __I uint32_t | CPUID |
| __IO uint32_t | ICSR |
| __IO uint32_t | VTOR |
| __IO uint32_t | AIRCR |
| __IO uint32_t | SCR |
| __IO uint32_t | CCR |
| __IO uint8_t | SHP [12] |
| __IO uint32_t | SHCSR |
| __IO uint32_t | CFSR |
| __IO uint32_t | HFSR |
| __IO uint32_t | DFSR |
| __IO uint32_t | MMFAR |
| __IO uint32_t | BFAR |
| __IO uint32_t | AFSR |
| __I uint32_t | PFR [2] |
| __I uint32_t | DFR |
| __I uint32_t | ADR |
| __I uint32_t | MMFR [4] |
| __I uint32_t | ISAR [5] |
| __IO uint32_t | CPACR |
Detailed Description
Structure type to access the System Control Block (SCB).
Definition at line 311 of file core_cm3.h.
Field Documentation
| __I uint32_t ADR |
Offset: 0x04C (R/ ) Auxiliary Feature Register
Definition at line 329 of file core_cm3.h.
| __IO uint32_t AFSR |
Offset: 0x03C (R/W) Auxiliary Fault Status Register
Definition at line 326 of file core_cm3.h.
| __IO uint32_t AIRCR |
Offset: 0x00C (R/W) Application Interrupt and Reset Control Register
Definition at line 316 of file core_cm3.h.
| __IO uint32_t BFAR |
Offset: 0x038 (R/W) BusFault Address Register
Definition at line 325 of file core_cm3.h.
| __IO uint32_t CCR |
Offset: 0x014 (R/W) Configuration Control Register
Definition at line 318 of file core_cm3.h.
| __IO uint32_t CFSR |
Offset: 0x028 (R/W) Configurable Fault Status Register
Definition at line 321 of file core_cm3.h.
| __IO uint32_t CPACR |
Offset: 0x088 (R/W) Coprocessor Access Control Register
Definition at line 333 of file core_cm3.h.
| __I uint32_t CPUID |
Offset: 0x000 (R/ ) CPUID Base Register
Definition at line 313 of file core_cm3.h.
| __I uint32_t DFR |
Offset: 0x048 (R/ ) Debug Feature Register
Definition at line 328 of file core_cm3.h.
| __IO uint32_t DFSR |
Offset: 0x030 (R/W) Debug Fault Status Register
Definition at line 323 of file core_cm3.h.
| __IO uint32_t HFSR |
Offset: 0x02C (R/W) HardFault Status Register
Definition at line 322 of file core_cm3.h.
| __IO uint32_t ICSR |
Offset: 0x004 (R/W) Interrupt Control and State Register
Definition at line 314 of file core_cm3.h.
| __I uint32_t ISAR[5] |
Offset: 0x060 (R/ ) Instruction Set Attributes Register
Definition at line 331 of file core_cm3.h.
| __IO uint32_t MMFAR |
Offset: 0x034 (R/W) MemManage Fault Address Register
Definition at line 324 of file core_cm3.h.
| __I uint32_t MMFR[4] |
Offset: 0x050 (R/ ) Memory Model Feature Register
Definition at line 330 of file core_cm3.h.
| __I uint32_t PFR[2] |
Offset: 0x040 (R/ ) Processor Feature Register
Definition at line 327 of file core_cm3.h.
| __IO uint32_t SCR |
Offset: 0x010 (R/W) System Control Register
Definition at line 317 of file core_cm3.h.
| __IO uint32_t SHCSR |
Offset: 0x024 (R/W) System Handler Control and State Register
Definition at line 320 of file core_cm3.h.
| __IO uint8_t SHP[12] |
Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
Definition at line 319 of file core_cm3.h.
| __IO uint32_t VTOR |
Offset: 0x008 (R/W) Vector Table Offset Register
Definition at line 315 of file core_cm3.h.
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