Due Ingegneri Ed Un Controllore
Dependencies: X_NUCLEO_COMMON
Fork of
X_NUCLEO_IKS01A1-f2df
by 
Ant Robinson
X_NUCLEO_IKS01A1-f255a2c75ecb/Components/lps25h/lps25h.h@1:7f97780b8ad4, 2017-02-09 (annotated)
- Committer:
- Salvatore94
- Date:
- Thu Feb 09 16:40:33 2017 +0000
- Revision:
- 1:7f97780b8ad4
- Parent:
- 0:5a49275457c6
Per peppe;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| antseggs | 0:5a49275457c6 | 1 | /** |
| antseggs | 0:5a49275457c6 | 2 | ****************************************************************************** |
| antseggs | 0:5a49275457c6 | 3 | * @file lps25h.h |
| antseggs | 0:5a49275457c6 | 4 | * @author MEMS Application Team |
| antseggs | 0:5a49275457c6 | 5 | * @version V1.2.0 |
| antseggs | 0:5a49275457c6 | 6 | * @date 11-February-2015 |
| antseggs | 0:5a49275457c6 | 7 | * @brief This file contains definitions for the lps25h.c |
| antseggs | 0:5a49275457c6 | 8 | * firmware driver. |
| antseggs | 0:5a49275457c6 | 9 | ****************************************************************************** |
| antseggs | 0:5a49275457c6 | 10 | * @attention |
| antseggs | 0:5a49275457c6 | 11 | * |
| antseggs | 0:5a49275457c6 | 12 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| antseggs | 0:5a49275457c6 | 13 | * |
| antseggs | 0:5a49275457c6 | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| antseggs | 0:5a49275457c6 | 15 | * are permitted provided that the following conditions are met: |
| antseggs | 0:5a49275457c6 | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| antseggs | 0:5a49275457c6 | 17 | * this list of conditions and the following disclaimer. |
| antseggs | 0:5a49275457c6 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| antseggs | 0:5a49275457c6 | 19 | * this list of conditions and the following disclaimer in the documentation |
| antseggs | 0:5a49275457c6 | 20 | * and/or other materials provided with the distribution. |
| antseggs | 0:5a49275457c6 | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| antseggs | 0:5a49275457c6 | 22 | * may be used to endorse or promote products derived from this software |
| antseggs | 0:5a49275457c6 | 23 | * without specific prior written permission. |
| antseggs | 0:5a49275457c6 | 24 | * |
| antseggs | 0:5a49275457c6 | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| antseggs | 0:5a49275457c6 | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| antseggs | 0:5a49275457c6 | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| antseggs | 0:5a49275457c6 | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| antseggs | 0:5a49275457c6 | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| antseggs | 0:5a49275457c6 | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| antseggs | 0:5a49275457c6 | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| antseggs | 0:5a49275457c6 | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| antseggs | 0:5a49275457c6 | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| antseggs | 0:5a49275457c6 | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| antseggs | 0:5a49275457c6 | 35 | * |
| antseggs | 0:5a49275457c6 | 36 | ****************************************************************************** |
| antseggs | 0:5a49275457c6 | 37 | */ |
| antseggs | 0:5a49275457c6 | 38 | |
| antseggs | 0:5a49275457c6 | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| antseggs | 0:5a49275457c6 | 40 | #ifndef __LPS25H_H |
| antseggs | 0:5a49275457c6 | 41 | #define __LPS25H_H |
| antseggs | 0:5a49275457c6 | 42 | |
| antseggs | 0:5a49275457c6 | 43 | #ifdef __cplusplus |
| antseggs | 0:5a49275457c6 | 44 | extern "C" { |
| antseggs | 0:5a49275457c6 | 45 | #endif |
| antseggs | 0:5a49275457c6 | 46 | |
| antseggs | 0:5a49275457c6 | 47 | /* Includes ------------------------------------------------------------------*/ |
| antseggs | 0:5a49275457c6 | 48 | #include "pressure.h" |
| antseggs | 0:5a49275457c6 | 49 | |
| antseggs | 0:5a49275457c6 | 50 | /** @addtogroup BSP |
| antseggs | 0:5a49275457c6 | 51 | * @{ |
| antseggs | 0:5a49275457c6 | 52 | */ |
| antseggs | 0:5a49275457c6 | 53 | |
| antseggs | 0:5a49275457c6 | 54 | /** @addtogroup Components |
| antseggs | 0:5a49275457c6 | 55 | * @{ |
| antseggs | 0:5a49275457c6 | 56 | */ |
| antseggs | 0:5a49275457c6 | 57 | |
| antseggs | 0:5a49275457c6 | 58 | /** @addtogroup LPS25H |
| antseggs | 0:5a49275457c6 | 59 | * @{ |
| antseggs | 0:5a49275457c6 | 60 | */ |
| antseggs | 0:5a49275457c6 | 61 | |
| antseggs | 0:5a49275457c6 | 62 | /** @defgroup LPS25H_Exported_Defines LPS25H_Exported_Defines |
| antseggs | 0:5a49275457c6 | 63 | * @{ |
| antseggs | 0:5a49275457c6 | 64 | */ |
| antseggs | 0:5a49275457c6 | 65 | #ifndef NULL |
| antseggs | 0:5a49275457c6 | 66 | #define NULL (void *) 0 |
| antseggs | 0:5a49275457c6 | 67 | #endif |
| antseggs | 0:5a49275457c6 | 68 | |
| antseggs | 0:5a49275457c6 | 69 | |
| antseggs | 0:5a49275457c6 | 70 | /******************************************************************************/ |
| antseggs | 0:5a49275457c6 | 71 | /*************************** START REGISTER MAPPING **************************/ |
| antseggs | 0:5a49275457c6 | 72 | /******************************************************************************/ |
| antseggs | 0:5a49275457c6 | 73 | |
| antseggs | 0:5a49275457c6 | 74 | |
| antseggs | 0:5a49275457c6 | 75 | /** |
| antseggs | 0:5a49275457c6 | 76 | * @brief Reference pressure (LSB data) |
| antseggs | 0:5a49275457c6 | 77 | * \code |
| antseggs | 0:5a49275457c6 | 78 | * Read/write |
| antseggs | 0:5a49275457c6 | 79 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 80 | * 7:0 REF7-ODR0: Lower part of the reference pressure that |
| antseggs | 0:5a49275457c6 | 81 | * is sum to the sensor output pressure. |
| antseggs | 0:5a49275457c6 | 82 | * \endcode |
| antseggs | 0:5a49275457c6 | 83 | */ |
| antseggs | 0:5a49275457c6 | 84 | #define LPS25H_REF_P_XL_ADDR 0x08 |
| antseggs | 0:5a49275457c6 | 85 | |
| antseggs | 0:5a49275457c6 | 86 | /** |
| antseggs | 0:5a49275457c6 | 87 | * @brief Reference pressure (middle part) |
| antseggs | 0:5a49275457c6 | 88 | * \code |
| antseggs | 0:5a49275457c6 | 89 | * Read/write |
| antseggs | 0:5a49275457c6 | 90 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 91 | * 7:0 REF15-ODR8: Middle part of the reference pressure that |
| antseggs | 0:5a49275457c6 | 92 | * is sum to the sensor output pressure. |
| antseggs | 0:5a49275457c6 | 93 | * \endcode |
| antseggs | 0:5a49275457c6 | 94 | */ |
| antseggs | 0:5a49275457c6 | 95 | #define LPS25H_REF_P_L_ADDR 0x09 |
| antseggs | 0:5a49275457c6 | 96 | |
| antseggs | 0:5a49275457c6 | 97 | /** |
| antseggs | 0:5a49275457c6 | 98 | * @brief Reference pressure (MSB part) |
| antseggs | 0:5a49275457c6 | 99 | * \code |
| antseggs | 0:5a49275457c6 | 100 | * Read/write |
| antseggs | 0:5a49275457c6 | 101 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 102 | * 7:0 REF15-ODR8: Higher part of the reference pressure that |
| antseggs | 0:5a49275457c6 | 103 | * is sum to the sensor output pressure. |
| antseggs | 0:5a49275457c6 | 104 | * \endcode |
| antseggs | 0:5a49275457c6 | 105 | */ |
| antseggs | 0:5a49275457c6 | 106 | #define LPS25H_REF_P_H_ADDR 0x0A |
| antseggs | 0:5a49275457c6 | 107 | |
| antseggs | 0:5a49275457c6 | 108 | /** |
| antseggs | 0:5a49275457c6 | 109 | * @brief Device identifier register. |
| antseggs | 0:5a49275457c6 | 110 | * \code |
| antseggs | 0:5a49275457c6 | 111 | * Read |
| antseggs | 0:5a49275457c6 | 112 | * Default value: 0xBD |
| antseggs | 0:5a49275457c6 | 113 | * 7:0 This read-only register contains the device identifier that, |
| antseggs | 0:5a49275457c6 | 114 | for LPS25H, is set to 0xCA. |
| antseggs | 0:5a49275457c6 | 115 | * \endcode |
| antseggs | 0:5a49275457c6 | 116 | */ |
| antseggs | 0:5a49275457c6 | 117 | #define LPS25H_WHO_AM_I_ADDR 0x0F |
| antseggs | 0:5a49275457c6 | 118 | |
| antseggs | 0:5a49275457c6 | 119 | /** |
| antseggs | 0:5a49275457c6 | 120 | * @brief Pressure and temperature resolution mode register. |
| antseggs | 0:5a49275457c6 | 121 | * \code |
| antseggs | 0:5a49275457c6 | 122 | * Read |
| antseggs | 0:5a49275457c6 | 123 | * Default value: 0x05 |
| antseggs | 0:5a49275457c6 | 124 | * [7:4] Reserved |
| antseggs | 0:5a49275457c6 | 125 | * [3:2] AVGP1-0: select the pressure internal average. |
| antseggs | 0:5a49275457c6 | 126 | * [1:0] AVGT1-0: select the temperature internal average. |
| antseggs | 0:5a49275457c6 | 127 | * \endcode |
| antseggs | 0:5a49275457c6 | 128 | */ |
| antseggs | 0:5a49275457c6 | 129 | #define LPS25H_RES_CONF_ADDR 0x10 |
| antseggs | 0:5a49275457c6 | 130 | |
| antseggs | 0:5a49275457c6 | 131 | /** |
| antseggs | 0:5a49275457c6 | 132 | * @brief Pressure sensor control register 1 |
| antseggs | 0:5a49275457c6 | 133 | * \code |
| antseggs | 0:5a49275457c6 | 134 | * Read/write |
| antseggs | 0:5a49275457c6 | 135 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 136 | * 7 PD: power down control. 0 - disable; 1 - enable |
| antseggs | 0:5a49275457c6 | 137 | * 6:4 ODR2, ODR1, ODR0: output data rate selection. |
| antseggs | 0:5a49275457c6 | 138 | * ODR2 | ODR1 | ODR0 | Pressure output data-rate(Hz) | Temperature output data-rate(Hz) |
| antseggs | 0:5a49275457c6 | 139 | * ---------------------------------------------------------------------------------- |
| antseggs | 0:5a49275457c6 | 140 | * 0 | 0 | 0 | one shot | one shot |
| antseggs | 0:5a49275457c6 | 141 | * 0 | 0 | 1 | 1 | 1 |
| antseggs | 0:5a49275457c6 | 142 | * 0 | 1 | 0 | 7 | 7 |
| antseggs | 0:5a49275457c6 | 143 | * 0 | 1 | 1 | 12.5 | 12.5 |
| antseggs | 0:5a49275457c6 | 144 | * 1 | 0 | 0 | 25 | 25 |
| antseggs | 0:5a49275457c6 | 145 | * 1 | 0 | 1 | Reserved | Reserved |
| antseggs | 0:5a49275457c6 | 146 | * 1 | 1 | 0 | Reserved | Reserved |
| antseggs | 0:5a49275457c6 | 147 | * 1 | 1 | 1 | Reserved | Reserved |
| antseggs | 0:5a49275457c6 | 148 | * |
| antseggs | 0:5a49275457c6 | 149 | * 3 DIFF_EN: Interrupt circuit. 0 - disable; 1 - enable |
| antseggs | 0:5a49275457c6 | 150 | * 2 BDU: block data update. 0 - disable; 1 - enable |
| antseggs | 0:5a49275457c6 | 151 | * 1 DELTA_EN: delta pressure. 0 - disable; 1 - enable |
| antseggs | 0:5a49275457c6 | 152 | * 1 RESET_AZ: reset AutoZero. 0 - disable; 1 - enable ///////ALE REVIEW |
| antseggs | 0:5a49275457c6 | 153 | * 0 SIM: SPI Serial Interface Mode selection. 0 - SPI 4-wire; 1 - SPI 3-wire ///////ALE REVIEW |
| antseggs | 0:5a49275457c6 | 154 | * \endcode |
| antseggs | 0:5a49275457c6 | 155 | */ |
| antseggs | 0:5a49275457c6 | 156 | #define LPS25H_CTRL_REG1_ADDR 0x20 |
| antseggs | 0:5a49275457c6 | 157 | |
| antseggs | 0:5a49275457c6 | 158 | /** |
| antseggs | 0:5a49275457c6 | 159 | * @brief Pressure sensor control register 2 |
| antseggs | 0:5a49275457c6 | 160 | * \code |
| antseggs | 0:5a49275457c6 | 161 | * Read/write |
| antseggs | 0:5a49275457c6 | 162 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 163 | * 7 BOOT: Reboot memory content. 0: normal mode; 1: reboot memory content |
| antseggs | 0:5a49275457c6 | 164 | * 6 FIFO_EN: FIFO. 0: disable; 1: enable |
| antseggs | 0:5a49275457c6 | 165 | * 5 WTM_EN: FIFO Watermark level use. 0: disable; 1: enable |
| antseggs | 0:5a49275457c6 | 166 | * 4:3 Reserved. keep these bits at 0 |
| antseggs | 0:5a49275457c6 | 167 | * 2 SWRESET: Software reset. 0: normal mode; 1: SW reset. |
| antseggs | 0:5a49275457c6 | 168 | * 1 AUTO_ZERO: Autozero enable. 0: normal mode; 1: autozero enable. |
| antseggs | 0:5a49275457c6 | 169 | * 0 ONE_SHOT: One shot enable. 0: waiting for start of conversion; 1: start for a new dataset |
| antseggs | 0:5a49275457c6 | 170 | * \endcode |
| antseggs | 0:5a49275457c6 | 171 | */ |
| antseggs | 0:5a49275457c6 | 172 | #define LPS25H_CTRL_REG2_ADDR 0x21 |
| antseggs | 0:5a49275457c6 | 173 | |
| antseggs | 0:5a49275457c6 | 174 | /** |
| antseggs | 0:5a49275457c6 | 175 | * @brief Pressure sensor control register 3 |
| antseggs | 0:5a49275457c6 | 176 | * \code |
| antseggs | 0:5a49275457c6 | 177 | * Read/write |
| antseggs | 0:5a49275457c6 | 178 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 179 | * 7 INT_H_L: Interrupt. 0:active high; 1: active low. |
| antseggs | 0:5a49275457c6 | 180 | * 6 PP_OD: Push-Pull/OpenDrain selection on interrupt pads. 0: Push-pull; 1: open drain. |
| antseggs | 0:5a49275457c6 | 181 | * 5 Reserved |
| antseggs | 0:5a49275457c6 | 182 | * 4:3 INT2_S2, INT2_S1: INT2 output signal selection control bits. // TO DO |
| antseggs | 0:5a49275457c6 | 183 | * 1:0 INT1_S2, INT1_S1: data signal on INT1 pad control bits. |
| antseggs | 0:5a49275457c6 | 184 | * INT1(2)_S2 | INT1(2)_S1 | INT1(2) pin |
| antseggs | 0:5a49275457c6 | 185 | * ------------------------------------------------------ |
| antseggs | 0:5a49275457c6 | 186 | * 0 | 0 | Data signal |
| antseggs | 0:5a49275457c6 | 187 | * 0 | 1 | Pressure high (P_high) |
| antseggs | 0:5a49275457c6 | 188 | * 1 | 0 | Pressure low (P_low) |
| antseggs | 0:5a49275457c6 | 189 | * 1 | 1 | P_low OR P_high |
| antseggs | 0:5a49275457c6 | 190 | |
| antseggs | 0:5a49275457c6 | 191 | |
| antseggs | 0:5a49275457c6 | 192 | * \endcode |
| antseggs | 0:5a49275457c6 | 193 | */ |
| antseggs | 0:5a49275457c6 | 194 | #define LPS25H_CTRL_REG3_ADDR 0x22 |
| antseggs | 0:5a49275457c6 | 195 | |
| antseggs | 0:5a49275457c6 | 196 | /** |
| antseggs | 0:5a49275457c6 | 197 | * @brief Pressure sensor control register 4 |
| antseggs | 0:5a49275457c6 | 198 | * \code |
| antseggs | 0:5a49275457c6 | 199 | * Read/write |
| antseggs | 0:5a49275457c6 | 200 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 201 | * 7 P2_EMPTY: Empty Signal on INT2 pin. |
| antseggs | 0:5a49275457c6 | 202 | * 6 P2_WTM: Watermark Signal on INT2 pin. |
| antseggs | 0:5a49275457c6 | 203 | * 5 P2_Overrun:Overrun Signal on INT2 pin. |
| antseggs | 0:5a49275457c6 | 204 | * 4 P2_DRDY: Data Ready Signal on INT2 pin. |
| antseggs | 0:5a49275457c6 | 205 | * 3 P1_EMPTY: Empty Signal on INT1 pin. |
| antseggs | 0:5a49275457c6 | 206 | * 2 P1_WTM: Watermark Signal on INT1 pin. |
| antseggs | 0:5a49275457c6 | 207 | * 1 P1_Overrunn:Overrun Signal on INT1 pin. |
| antseggs | 0:5a49275457c6 | 208 | * 0 P1_DRDY: Data Ready Signal on INT1 pin. |
| antseggs | 0:5a49275457c6 | 209 | * \endcode |
| antseggs | 0:5a49275457c6 | 210 | */ |
| antseggs | 0:5a49275457c6 | 211 | #define LPS25H_CTRL_REG4_ADDR 0x23 |
| antseggs | 0:5a49275457c6 | 212 | |
| antseggs | 0:5a49275457c6 | 213 | /** |
| antseggs | 0:5a49275457c6 | 214 | * @brief Interrupt configuration Register |
| antseggs | 0:5a49275457c6 | 215 | * \code |
| antseggs | 0:5a49275457c6 | 216 | * Read/write |
| antseggs | 0:5a49275457c6 | 217 | * Default value: 0x00. |
| antseggs | 0:5a49275457c6 | 218 | * 7:3 Reserved. |
| antseggs | 0:5a49275457c6 | 219 | * 2 LIR: Latch Interrupt request into INT_SOURCE register. 0 - disable; 1 - enable |
| antseggs | 0:5a49275457c6 | 220 | * 1 PL_E: Enable interrupt generation on differential pressure low event. 0 - disable; 1 - enable |
| antseggs | 0:5a49275457c6 | 221 | * 0 PH_E: Enable interrupt generation on differential pressure high event. 0 - disable; 1 - enable |
| antseggs | 0:5a49275457c6 | 222 | * \endcode |
| antseggs | 0:5a49275457c6 | 223 | */ |
| antseggs | 0:5a49275457c6 | 224 | #define LPS25H_INT_CFG_REG_ADDR 0x24 |
| antseggs | 0:5a49275457c6 | 225 | |
| antseggs | 0:5a49275457c6 | 226 | /** |
| antseggs | 0:5a49275457c6 | 227 | * @brief Interrupt source Register |
| antseggs | 0:5a49275457c6 | 228 | * \code |
| antseggs | 0:5a49275457c6 | 229 | * Read |
| antseggs | 0:5a49275457c6 | 230 | * Default value: 0x00. |
| antseggs | 0:5a49275457c6 | 231 | * 7:3 0. |
| antseggs | 0:5a49275457c6 | 232 | * 2 IA: Interrupt Active.0: no interrupt has been generated; 1: one or more interrupt events have been generated. |
| antseggs | 0:5a49275457c6 | 233 | * 1 PL: Differential pressure Low. 0: no interrupt has been generated; 1: Low differential pressure event has occurred. |
| antseggs | 0:5a49275457c6 | 234 | * 0 PH: Differential pressure High. 0: no interrupt has been generated; 1: High differential pressure event has occurred. |
| antseggs | 0:5a49275457c6 | 235 | * \endcode |
| antseggs | 0:5a49275457c6 | 236 | */ |
| antseggs | 0:5a49275457c6 | 237 | #define LPS25H_INT_SOURCE_REG_ADDR 0x25 |
| antseggs | 0:5a49275457c6 | 238 | |
| antseggs | 0:5a49275457c6 | 239 | /** |
| antseggs | 0:5a49275457c6 | 240 | * @brief Threshold pressure (LSB) |
| antseggs | 0:5a49275457c6 | 241 | * \code |
| antseggs | 0:5a49275457c6 | 242 | * Read |
| antseggs | 0:5a49275457c6 | 243 | * Default value: 0x00. |
| antseggs | 0:5a49275457c6 | 244 | * 7:0 THS7-THS0: Low part of threshold value for pressure interrupt |
| antseggs | 0:5a49275457c6 | 245 | * generation. The complete threshold value is given by THS_P_H & THS_P_L and is |
| antseggs | 0:5a49275457c6 | 246 | * expressed as unsigned number. P_ths(mbar)=(THS_P_H & THS_P_L)[dec]/16. |
| antseggs | 0:5a49275457c6 | 247 | * \endcode |
| antseggs | 0:5a49275457c6 | 248 | */ |
| antseggs | 0:5a49275457c6 | 249 | #define LPS25H_THS_P_LOW_REG_ADDR 0x30 |
| antseggs | 0:5a49275457c6 | 250 | |
| antseggs | 0:5a49275457c6 | 251 | /** |
| antseggs | 0:5a49275457c6 | 252 | * @brief Threshold pressure (MSB) |
| antseggs | 0:5a49275457c6 | 253 | * \code |
| antseggs | 0:5a49275457c6 | 254 | * Read |
| antseggs | 0:5a49275457c6 | 255 | * Default value: 0x00. |
| antseggs | 0:5a49275457c6 | 256 | * 7:0 THS15-THS8: High part of threshold value for pressure interrupt |
| antseggs | 0:5a49275457c6 | 257 | * generation. The complete threshold value is given by THS_P_H & THS_P_L and is |
| antseggs | 0:5a49275457c6 | 258 | * expressed as unsigned number. P_ths(mbar)=(THS_P_H & THS_P_L)[dec]/16. |
| antseggs | 0:5a49275457c6 | 259 | * \endcode |
| antseggs | 0:5a49275457c6 | 260 | */ |
| antseggs | 0:5a49275457c6 | 261 | #define LPS25H_THS_P_HIGH_REG_ADDR 0x31 |
| antseggs | 0:5a49275457c6 | 262 | |
| antseggs | 0:5a49275457c6 | 263 | /** |
| antseggs | 0:5a49275457c6 | 264 | * @brief Status Register |
| antseggs | 0:5a49275457c6 | 265 | * \code |
| antseggs | 0:5a49275457c6 | 266 | * Read |
| antseggs | 0:5a49275457c6 | 267 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 268 | * 7:6 0 |
| antseggs | 0:5a49275457c6 | 269 | * 5 P_OR: Pressure data overrun. 0: no overrun has occurred; 1: new data for pressure has overwritten the previous one. |
| antseggs | 0:5a49275457c6 | 270 | * 4 T_OR: Temperature data overrun. 0: no overrun has occurred; 1: a new data for temperature has overwritten the previous one. |
| antseggs | 0:5a49275457c6 | 271 | * 3:2 0 |
| antseggs | 0:5a49275457c6 | 272 | * 1 P_DA: Pressure data available. 0: new data for pressure is not yet available; 1: new data for pressure is available. |
| antseggs | 0:5a49275457c6 | 273 | * 0 T_DA: Temperature data available. 0: new data for temperature is not yet available; 1: new data for temperature is available. |
| antseggs | 0:5a49275457c6 | 274 | * \endcode |
| antseggs | 0:5a49275457c6 | 275 | */ |
| antseggs | 0:5a49275457c6 | 276 | #define LPS25H_STATUS_REG_ADDR 0x27 |
| antseggs | 0:5a49275457c6 | 277 | |
| antseggs | 0:5a49275457c6 | 278 | /** |
| antseggs | 0:5a49275457c6 | 279 | * @brief Pressure data (LSB). |
| antseggs | 0:5a49275457c6 | 280 | * \code |
| antseggs | 0:5a49275457c6 | 281 | * Read |
| antseggs | 0:5a49275457c6 | 282 | * Default value: 0x00. |
| antseggs | 0:5a49275457c6 | 283 | * POUT7 - POUT0: Pressure data LSB (2's complement). |
| antseggs | 0:5a49275457c6 | 284 | * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & |
| antseggs | 0:5a49275457c6 | 285 | * PRESS_OUT_XL)[dec]/4096. |
| antseggs | 0:5a49275457c6 | 286 | * \endcode |
| antseggs | 0:5a49275457c6 | 287 | */ |
| antseggs | 0:5a49275457c6 | 288 | #define LPS25H_PRESS_POUT_XL_ADDR 0x28 |
| antseggs | 0:5a49275457c6 | 289 | |
| antseggs | 0:5a49275457c6 | 290 | /** |
| antseggs | 0:5a49275457c6 | 291 | * @brief Pressure data (Middle part). |
| antseggs | 0:5a49275457c6 | 292 | * \code |
| antseggs | 0:5a49275457c6 | 293 | * Read |
| antseggs | 0:5a49275457c6 | 294 | * Default value: 0x80. |
| antseggs | 0:5a49275457c6 | 295 | * POUT15 - POUT8: Pressure data middle part (2's complement). |
| antseggs | 0:5a49275457c6 | 296 | * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & |
| antseggs | 0:5a49275457c6 | 297 | * PRESS_OUT_XL)[dec]/4096. |
| antseggs | 0:5a49275457c6 | 298 | * \endcode |
| antseggs | 0:5a49275457c6 | 299 | */ |
| antseggs | 0:5a49275457c6 | 300 | #define LPS25H_PRESS_OUT_L_ADDR 0x29 |
| antseggs | 0:5a49275457c6 | 301 | |
| antseggs | 0:5a49275457c6 | 302 | /** |
| antseggs | 0:5a49275457c6 | 303 | * @brief Pressure data (MSB). |
| antseggs | 0:5a49275457c6 | 304 | * \code |
| antseggs | 0:5a49275457c6 | 305 | * Read |
| antseggs | 0:5a49275457c6 | 306 | * Default value: 0x2F. |
| antseggs | 0:5a49275457c6 | 307 | * POUT23 - POUT16: Pressure data MSB (2's complement). |
| antseggs | 0:5a49275457c6 | 308 | * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & |
| antseggs | 0:5a49275457c6 | 309 | * PRESS_OUT_XL)[dec]/4096. |
| antseggs | 0:5a49275457c6 | 310 | * \endcode |
| antseggs | 0:5a49275457c6 | 311 | */ |
| antseggs | 0:5a49275457c6 | 312 | #define LPS25H_PRESS_OUT_H_ADDR 0x2A |
| antseggs | 0:5a49275457c6 | 313 | |
| antseggs | 0:5a49275457c6 | 314 | /** |
| antseggs | 0:5a49275457c6 | 315 | * @brief Temperature data (LSB). |
| antseggs | 0:5a49275457c6 | 316 | * \code |
| antseggs | 0:5a49275457c6 | 317 | * Read |
| antseggs | 0:5a49275457c6 | 318 | * Default value: 0x00. |
| antseggs | 0:5a49275457c6 | 319 | * TOUT7 - TOUT0: temperature data LSB. |
| antseggs | 0:5a49275457c6 | 320 | * T(degC) = 42.5 + (Temp_OUTH & TEMP_OUT_L)[dec]/480. |
| antseggs | 0:5a49275457c6 | 321 | * \endcode |
| antseggs | 0:5a49275457c6 | 322 | */ |
| antseggs | 0:5a49275457c6 | 323 | #define LPS25H_TEMP_OUT_L_ADDR 0x2B |
| antseggs | 0:5a49275457c6 | 324 | |
| antseggs | 0:5a49275457c6 | 325 | /** |
| antseggs | 0:5a49275457c6 | 326 | * @brief Temperature data (MSB). |
| antseggs | 0:5a49275457c6 | 327 | * \code |
| antseggs | 0:5a49275457c6 | 328 | * Read |
| antseggs | 0:5a49275457c6 | 329 | * Default value: 0x00. |
| antseggs | 0:5a49275457c6 | 330 | * TOUT15 - TOUT8: temperature data MSB. |
| antseggs | 0:5a49275457c6 | 331 | * T(degC) = 42.5 + (Temp_OUTH & TEMP_OUT_L)[dec]/480. |
| antseggs | 0:5a49275457c6 | 332 | * \endcode |
| antseggs | 0:5a49275457c6 | 333 | */ |
| antseggs | 0:5a49275457c6 | 334 | #define LPS25H_TEMP_OUT_H_ADDR 0x2C |
| antseggs | 0:5a49275457c6 | 335 | |
| antseggs | 0:5a49275457c6 | 336 | /** |
| antseggs | 0:5a49275457c6 | 337 | * @brief FIFO control register |
| antseggs | 0:5a49275457c6 | 338 | * \code |
| antseggs | 0:5a49275457c6 | 339 | * Read/write |
| antseggs | 0:5a49275457c6 | 340 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 341 | * 7:5 F_MODE2, F_MODE1, F_MODE0: FIFO mode selection. |
| antseggs | 0:5a49275457c6 | 342 | * FM2 | FM1 | FM0 | FIFO MODE |
| antseggs | 0:5a49275457c6 | 343 | * --------------------------------------------------- |
| antseggs | 0:5a49275457c6 | 344 | * 0 | 0 | 0 | BYPASS MODE |
| antseggs | 0:5a49275457c6 | 345 | * 0 | 0 | 1 | FIFO MODE. Stops collecting data when full |
| antseggs | 0:5a49275457c6 | 346 | * 0 | 1 | 0 | STREAM MODE: Keep the newest measurements in the FIFO |
| antseggs | 0:5a49275457c6 | 347 | * 0 | 1 | 1 | STREAM MODE until trigger deasserted, then change to FIFO MODE |
| antseggs | 0:5a49275457c6 | 348 | * 1 | 0 | 0 | BYPASS MODE until trigger deasserted, then STREAM MODE |
| antseggs | 0:5a49275457c6 | 349 | * 1 | 0 | 1 | Reserved |
| antseggs | 0:5a49275457c6 | 350 | * 1 | 1 | 0 | FIFO_MEAN MODE: Fifo is used to generate a running average filtered pressure |
| antseggs | 0:5a49275457c6 | 351 | * 1 | 1 | 1 | BYPASS mode until trigger deasserted, then FIFO MODE |
| antseggs | 0:5a49275457c6 | 352 | * |
| antseggs | 0:5a49275457c6 | 353 | * 4:0 FIFO Mean Mode Sample size |
| antseggs | 0:5a49275457c6 | 354 | * WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | Sample Size |
| antseggs | 0:5a49275457c6 | 355 | * ---------------------------------------------------------------------------------- |
| antseggs | 0:5a49275457c6 | 356 | * 0 | 0 | 0 | 0 | 1 | 2 |
| antseggs | 0:5a49275457c6 | 357 | * 0 | 0 | 0 | 1 | 1 | 4 |
| antseggs | 0:5a49275457c6 | 358 | * 0 | 0 | 1 | 1 | 1 | 8 |
| antseggs | 0:5a49275457c6 | 359 | * 0 | 1 | 1 | 1 | 1 | 16 |
| antseggs | 0:5a49275457c6 | 360 | * 1 | 1 | 1 | 1 | 1 | 32 |
| antseggs | 0:5a49275457c6 | 361 | * other values operation not guaranteed |
| antseggs | 0:5a49275457c6 | 362 | * \endcode |
| antseggs | 0:5a49275457c6 | 363 | */ |
| antseggs | 0:5a49275457c6 | 364 | #define LPS25H_CTRL_FIFO_ADDR 0x2E |
| antseggs | 0:5a49275457c6 | 365 | |
| antseggs | 0:5a49275457c6 | 366 | /** |
| antseggs | 0:5a49275457c6 | 367 | * @brief FIFO Status register |
| antseggs | 0:5a49275457c6 | 368 | * \code |
| antseggs | 0:5a49275457c6 | 369 | * Read/write |
| antseggs | 0:5a49275457c6 | 370 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 371 | * 7 WTM_FIFO: Watermark status. 0:FIFO filling is lower than watermark level; 1: FIFO is equal or higher than watermark level. |
| antseggs | 0:5a49275457c6 | 372 | * 6 FULL_FIFO: Overrun bit status. 0 - FIFO not full; 1 -FIFO is full. |
| antseggs | 0:5a49275457c6 | 373 | * 5 EMPTY_FIFO: Empty FIFO bit. 0 - FIFO not empty; 1 -FIFO is empty. |
| antseggs | 0:5a49275457c6 | 374 | * 4:0 DIFF_POINT4...0: FIFOsStored data level. |
| antseggs | 0:5a49275457c6 | 375 | * \endcode |
| antseggs | 0:5a49275457c6 | 376 | */ |
| antseggs | 0:5a49275457c6 | 377 | #define LPS25H_STATUS_FIFO_ADDR 0x2F |
| antseggs | 0:5a49275457c6 | 378 | |
| antseggs | 0:5a49275457c6 | 379 | /** |
| antseggs | 0:5a49275457c6 | 380 | * @brief Pressure offset register |
| antseggs | 0:5a49275457c6 | 381 | * \code |
| antseggs | 0:5a49275457c6 | 382 | * Read/write |
| antseggs | 0:5a49275457c6 | 383 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 384 | * 7:0 RPDS15...8:Pressure Offset for 1 point calibration after soldering. |
| antseggs | 0:5a49275457c6 | 385 | * \endcode |
| antseggs | 0:5a49275457c6 | 386 | */ |
| antseggs | 0:5a49275457c6 | 387 | #define LPS25H_RPDS_TRIM_L_ADDR 0x39 |
| antseggs | 0:5a49275457c6 | 388 | |
| antseggs | 0:5a49275457c6 | 389 | /** |
| antseggs | 0:5a49275457c6 | 390 | * @brief Pressure offset register |
| antseggs | 0:5a49275457c6 | 391 | * \code |
| antseggs | 0:5a49275457c6 | 392 | * Read/write |
| antseggs | 0:5a49275457c6 | 393 | * Default value: 0x00 |
| antseggs | 0:5a49275457c6 | 394 | * 7:0 RPDS23...16:Pressure Offset for 1 point calibration after soldering. |
| antseggs | 0:5a49275457c6 | 395 | * \endcode |
| antseggs | 0:5a49275457c6 | 396 | */ |
| antseggs | 0:5a49275457c6 | 397 | #define LPS25H_RPDS_TRIM_H_ADDR 0x3A |
| antseggs | 0:5a49275457c6 | 398 | |
| antseggs | 0:5a49275457c6 | 399 | /******************************************************************************/ |
| antseggs | 0:5a49275457c6 | 400 | /**************************** END REGISTER MAPPING ***************************/ |
| antseggs | 0:5a49275457c6 | 401 | /******************************************************************************/ |
| antseggs | 0:5a49275457c6 | 402 | |
| antseggs | 0:5a49275457c6 | 403 | /** |
| antseggs | 0:5a49275457c6 | 404 | * @brief Multiple Byte. Mask for enabling multiple byte read/write command. |
| antseggs | 0:5a49275457c6 | 405 | */ |
| antseggs | 0:5a49275457c6 | 406 | #define LPS25H_I2C_MULTIPLEBYTE_CMD ((uint8_t)0x80) |
| antseggs | 0:5a49275457c6 | 407 | |
| antseggs | 0:5a49275457c6 | 408 | /** |
| antseggs | 0:5a49275457c6 | 409 | * @brief Device Address |
| antseggs | 0:5a49275457c6 | 410 | */ |
| antseggs | 0:5a49275457c6 | 411 | #define LPS25H_ADDRESS_LOW 0xB8 |
| antseggs | 0:5a49275457c6 | 412 | #define LPS25H_ADDRESS_HIGH 0xBA |
| antseggs | 0:5a49275457c6 | 413 | |
| antseggs | 0:5a49275457c6 | 414 | |
| antseggs | 0:5a49275457c6 | 415 | /** |
| antseggs | 0:5a49275457c6 | 416 | * @brief Device Identifier. Default value of the WHO_AM_I register. |
| antseggs | 0:5a49275457c6 | 417 | */ |
| antseggs | 0:5a49275457c6 | 418 | #define I_AM_LPS25H ((uint8_t)0xBD) |
| antseggs | 0:5a49275457c6 | 419 | |
| antseggs | 0:5a49275457c6 | 420 | /** @defgroup LPS25H_Power_Mode_Selection_CTRL_REG1 LPS25H_Power_Mode_Selection_CTRL_REG1 |
| antseggs | 0:5a49275457c6 | 421 | * @{ |
| antseggs | 0:5a49275457c6 | 422 | */ |
| antseggs | 0:5a49275457c6 | 423 | #define LPS25H_MODE_POWERDOWN ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 424 | #define LPS25H_MODE_ACTIVE ((uint8_t)0x80) |
| antseggs | 0:5a49275457c6 | 425 | |
| antseggs | 0:5a49275457c6 | 426 | #define LPS25H_MODE_MASK ((uint8_t)0x80) |
| antseggs | 0:5a49275457c6 | 427 | /** |
| antseggs | 0:5a49275457c6 | 428 | * @} |
| antseggs | 0:5a49275457c6 | 429 | */ |
| antseggs | 0:5a49275457c6 | 430 | |
| antseggs | 0:5a49275457c6 | 431 | /** @defgroup LPS25H_Output_Data_Rate_Selection_CTRL_REG1 LPS25H_Output_Data_Rate_Selection_CTRL_REG1 |
| antseggs | 0:5a49275457c6 | 432 | * @{ |
| antseggs | 0:5a49275457c6 | 433 | */ |
| antseggs | 0:5a49275457c6 | 434 | #define LPS25H_ODR_ONE_SHOT ((uint8_t)0x00) /*!< Output Data Rate: P - one shot, T - one shot */ |
| antseggs | 0:5a49275457c6 | 435 | #define LPS25H_ODR_1Hz ((uint8_t)0x10) /*!< Output Data Rate: P - 1Hz, T - 1Hz */ |
| antseggs | 0:5a49275457c6 | 436 | #define LPS25H_ODR_7Hz ((uint8_t)0x20) /*!< Output Data Rate: P - 7Hz, T - 7Hz */ |
| antseggs | 0:5a49275457c6 | 437 | #define LPS25H_ODR_12_5Hz ((uint8_t)0x30) /*!< Output Data Rate: P - 12.5Hz, T - 12.5Hz */ |
| antseggs | 0:5a49275457c6 | 438 | #define LPS25H_ODR_25Hz ((uint8_t)0x40) /*!< Output Data Rate: P - 25Hz, T - 25Hz */ |
| antseggs | 0:5a49275457c6 | 439 | |
| antseggs | 0:5a49275457c6 | 440 | #define LPS25H_ODR_MASK ((uint8_t)0x70) |
| antseggs | 0:5a49275457c6 | 441 | /** |
| antseggs | 0:5a49275457c6 | 442 | * @} |
| antseggs | 0:5a49275457c6 | 443 | */ |
| antseggs | 0:5a49275457c6 | 444 | |
| antseggs | 0:5a49275457c6 | 445 | /** @defgroup LPS25H_Interrupt_Circuit_Enable_CTRL_REG1 LPS25H_Interrupt_Circuit_Enable_CTRL_REG1 |
| antseggs | 0:5a49275457c6 | 446 | * @{ |
| antseggs | 0:5a49275457c6 | 447 | */ |
| antseggs | 0:5a49275457c6 | 448 | #define LPS25H_DIFF_DISABLE ((uint8_t)0x00) /*!< interrupt circuit enabled */ |
| antseggs | 0:5a49275457c6 | 449 | #define LPS25H_DIFF_ENABLE ((uint8_t)0x08) /*!< interrupt generation disabled */ |
| antseggs | 0:5a49275457c6 | 450 | |
| antseggs | 0:5a49275457c6 | 451 | #define LPS25H_DIFF_EN_MASK ((uint8_t)0x08) |
| antseggs | 0:5a49275457c6 | 452 | /** |
| antseggs | 0:5a49275457c6 | 453 | * @} |
| antseggs | 0:5a49275457c6 | 454 | */ |
| antseggs | 0:5a49275457c6 | 455 | |
| antseggs | 0:5a49275457c6 | 456 | /** @defgroup LPS25H_Block_Data_Update_CTRL_REG1 LPS25H_Block_Data_Update_CTRL_REG1 |
| antseggs | 0:5a49275457c6 | 457 | * @{ |
| antseggs | 0:5a49275457c6 | 458 | */ |
| antseggs | 0:5a49275457c6 | 459 | #define LPS25H_BDU_CONT ((uint8_t)0x00) /*!< continuous update */ |
| antseggs | 0:5a49275457c6 | 460 | #define LPS25H_BDU_READ ((uint8_t)0x04) /*!< output registers not updated until MSB and LSB reading */ |
| antseggs | 0:5a49275457c6 | 461 | |
| antseggs | 0:5a49275457c6 | 462 | #define LPS25H_BDU_MASK ((uint8_t)0x04) |
| antseggs | 0:5a49275457c6 | 463 | /** |
| antseggs | 0:5a49275457c6 | 464 | * @} |
| antseggs | 0:5a49275457c6 | 465 | */ |
| antseggs | 0:5a49275457c6 | 466 | |
| antseggs | 0:5a49275457c6 | 467 | /** @defgroup LPS25H_SPI_Serial_Interface_Mode_Selection_CTRL_REG1 LPS25H_SPI_Serial_Interface_Mode_Selection_CTRL_REG1 |
| antseggs | 0:5a49275457c6 | 468 | * @{ |
| antseggs | 0:5a49275457c6 | 469 | */ |
| antseggs | 0:5a49275457c6 | 470 | #define LPS25H_SPI_SIM_4W ((uint8_t)0x00) /*!< 4-wire interface */ |
| antseggs | 0:5a49275457c6 | 471 | #define LPS25H_SPI_SIM_3W ((uint8_t)0x01) /*!< 3-wire interface */ |
| antseggs | 0:5a49275457c6 | 472 | |
| antseggs | 0:5a49275457c6 | 473 | #define LPS25H_SPI_SIM_MASK ((uint8_t)0x01) |
| antseggs | 0:5a49275457c6 | 474 | /** |
| antseggs | 0:5a49275457c6 | 475 | * @} |
| antseggs | 0:5a49275457c6 | 476 | */ |
| antseggs | 0:5a49275457c6 | 477 | |
| antseggs | 0:5a49275457c6 | 478 | /** @defgroup LPS25H_Refresh_Registers_Flash_Memory_CTRL_REG2 LPS25H_Refresh_Registers_Flash_Memory_CTRL_REG2 |
| antseggs | 0:5a49275457c6 | 479 | * @{ |
| antseggs | 0:5a49275457c6 | 480 | */ |
| antseggs | 0:5a49275457c6 | 481 | #define LPS25H_NORMAL_MODE ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 482 | #define LPS25H_RESET_MEMORY ((uint8_t)0x80) |
| antseggs | 0:5a49275457c6 | 483 | |
| antseggs | 0:5a49275457c6 | 484 | #define LPS25H_RESET_MEMORY_MASK ((uint8_t)0x80) |
| antseggs | 0:5a49275457c6 | 485 | /** |
| antseggs | 0:5a49275457c6 | 486 | * @} |
| antseggs | 0:5a49275457c6 | 487 | */ |
| antseggs | 0:5a49275457c6 | 488 | |
| antseggs | 0:5a49275457c6 | 489 | /** @defgroup LPS25H_Pressure_Resolution_Selection_RES_CONF LPS25H_Pressure_Resolution_Selection_RES_CONF |
| antseggs | 0:5a49275457c6 | 490 | * @{ |
| antseggs | 0:5a49275457c6 | 491 | */ |
| antseggs | 0:5a49275457c6 | 492 | #define LPS25H_P_RES_AVG_8 ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 493 | #define LPS25H_P_RES_AVG_32 ((uint8_t)0x01) |
| antseggs | 0:5a49275457c6 | 494 | #define LPS25H_P_RES_AVG_128 ((uint8_t)0x02) |
| antseggs | 0:5a49275457c6 | 495 | #define LPS25H_P_RES_AVG_512 ((uint8_t)0x03) |
| antseggs | 0:5a49275457c6 | 496 | |
| antseggs | 0:5a49275457c6 | 497 | #define LPS25H_P_RES_MASK ((uint8_t)0x03) |
| antseggs | 0:5a49275457c6 | 498 | /** |
| antseggs | 0:5a49275457c6 | 499 | * @} |
| antseggs | 0:5a49275457c6 | 500 | */ |
| antseggs | 0:5a49275457c6 | 501 | |
| antseggs | 0:5a49275457c6 | 502 | /** @defgroup LPS25H_Temperature_Resolution_Selection_RES_CONF LPS25H_Temperature_Resolution_Selection_RES_CONF |
| antseggs | 0:5a49275457c6 | 503 | * @{ |
| antseggs | 0:5a49275457c6 | 504 | */ |
| antseggs | 0:5a49275457c6 | 505 | #define LPS25H_T_RES_AVG_8 ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 506 | #define LPS25H_T_RES_AVG_16 ((uint8_t)0x04) |
| antseggs | 0:5a49275457c6 | 507 | #define LPS25H_T_RES_AVG_32 ((uint8_t)0x08) |
| antseggs | 0:5a49275457c6 | 508 | #define LPS25H_T_RES_AVG_64 ((uint8_t)0x0C) |
| antseggs | 0:5a49275457c6 | 509 | |
| antseggs | 0:5a49275457c6 | 510 | #define LPS25H_T_RES_MASK ((uint8_t)0x0C) |
| antseggs | 0:5a49275457c6 | 511 | /** |
| antseggs | 0:5a49275457c6 | 512 | * @} |
| antseggs | 0:5a49275457c6 | 513 | */ |
| antseggs | 0:5a49275457c6 | 514 | |
| antseggs | 0:5a49275457c6 | 515 | #define LPS25H_SA0_LOW ((uint8_t)0x00) |
| antseggs | 0:5a49275457c6 | 516 | #define LPS25H_SA0_HIGH ((uint8_t)0x01) |
| antseggs | 0:5a49275457c6 | 517 | |
| antseggs | 0:5a49275457c6 | 518 | /** |
| antseggs | 0:5a49275457c6 | 519 | * @} |
| antseggs | 0:5a49275457c6 | 520 | */ |
| antseggs | 0:5a49275457c6 | 521 | |
| antseggs | 0:5a49275457c6 | 522 | /** @defgroup LPS25H_Imported_Functions LPS25H_Imported_Functions |
| antseggs | 0:5a49275457c6 | 523 | * @{ |
| antseggs | 0:5a49275457c6 | 524 | */ |
| antseggs | 0:5a49275457c6 | 525 | /* Pressure sensor IO functions */ |
| antseggs | 0:5a49275457c6 | 526 | extern PRESSURE_StatusTypeDef LPS25H_IO_Init(void); |
| antseggs | 0:5a49275457c6 | 527 | extern PRESSURE_StatusTypeDef LPS25H_IO_Write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, |
| antseggs | 0:5a49275457c6 | 528 | uint16_t NumByteToWrite); |
| antseggs | 0:5a49275457c6 | 529 | extern PRESSURE_StatusTypeDef LPS25H_IO_Read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, |
| antseggs | 0:5a49275457c6 | 530 | uint16_t NumByteToRead); |
| antseggs | 0:5a49275457c6 | 531 | extern void LPS25H_IO_ITConfig( void ); |
| antseggs | 0:5a49275457c6 | 532 | |
| antseggs | 0:5a49275457c6 | 533 | /** |
| antseggs | 0:5a49275457c6 | 534 | * @} |
| antseggs | 0:5a49275457c6 | 535 | */ |
| antseggs | 0:5a49275457c6 | 536 | |
| antseggs | 0:5a49275457c6 | 537 | /* ------------------------------------------------------- */ |
| antseggs | 0:5a49275457c6 | 538 | /* Here you should declare the internal struct of */ |
| antseggs | 0:5a49275457c6 | 539 | /* extended features of LPS25H. See the example of */ |
| antseggs | 0:5a49275457c6 | 540 | /* LSM6DS3 in lsm6ds3.h */ |
| antseggs | 0:5a49275457c6 | 541 | /* ------------------------------------------------------- */ |
| antseggs | 0:5a49275457c6 | 542 | |
| antseggs | 0:5a49275457c6 | 543 | /** @addtogroup LPS25H_Exported_Variables LPS25H_Exported_Variables |
| antseggs | 0:5a49275457c6 | 544 | * @{ |
| antseggs | 0:5a49275457c6 | 545 | */ |
| antseggs | 0:5a49275457c6 | 546 | /* Pressure sensor driver structure */ |
| antseggs | 0:5a49275457c6 | 547 | extern PRESSURE_DrvTypeDef LPS25HDrv; |
| antseggs | 0:5a49275457c6 | 548 | extern PRESSURE_DrvExtTypeDef LPS25HDrv_ext; |
| antseggs | 0:5a49275457c6 | 549 | |
| antseggs | 0:5a49275457c6 | 550 | /** |
| antseggs | 0:5a49275457c6 | 551 | * @} |
| antseggs | 0:5a49275457c6 | 552 | */ |
| antseggs | 0:5a49275457c6 | 553 | |
| antseggs | 0:5a49275457c6 | 554 | /** |
| antseggs | 0:5a49275457c6 | 555 | * @} |
| antseggs | 0:5a49275457c6 | 556 | */ |
| antseggs | 0:5a49275457c6 | 557 | |
| antseggs | 0:5a49275457c6 | 558 | /** |
| antseggs | 0:5a49275457c6 | 559 | * @} |
| antseggs | 0:5a49275457c6 | 560 | */ |
| antseggs | 0:5a49275457c6 | 561 | |
| antseggs | 0:5a49275457c6 | 562 | /** |
| antseggs | 0:5a49275457c6 | 563 | * @} |
| antseggs | 0:5a49275457c6 | 564 | */ |
| antseggs | 0:5a49275457c6 | 565 | |
| antseggs | 0:5a49275457c6 | 566 | #ifdef __cplusplus |
| antseggs | 0:5a49275457c6 | 567 | } |
| antseggs | 0:5a49275457c6 | 568 | #endif |
| antseggs | 0:5a49275457c6 | 569 | |
| antseggs | 0:5a49275457c6 | 570 | #endif /* __LPS25H_H */ |
| antseggs | 0:5a49275457c6 | 571 | |
| antseggs | 0:5a49275457c6 | 572 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |