20160814
Fork of RF24 by
RF24.cpp@8:6827b6f0283b, 2016-07-28 (annotated)
- Committer:
- adam_z
- Date:
- Thu Jul 28 08:10:31 2016 +0000
- Revision:
- 8:6827b6f0283b
- Parent:
- 6:5cc7136648d1
RF24 lib modified from https://developer.mbed.org/users/akashvibhute/code/RF24/docs/tip/RF24_8cpp_source.html
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
akashvibhute | 0:bb74812ac6bb | 1 | /* |
akashvibhute | 0:bb74812ac6bb | 2 | Copyright (C) 2011 J. Coliz <maniacbug@ymail.com> |
akashvibhute | 0:bb74812ac6bb | 3 | |
akashvibhute | 0:bb74812ac6bb | 4 | This program is free software; you can redistribute it and/or |
akashvibhute | 0:bb74812ac6bb | 5 | modify it under the terms of the GNU General Public License |
akashvibhute | 0:bb74812ac6bb | 6 | version 2 as published by the Free Software Foundation. |
akashvibhute | 0:bb74812ac6bb | 7 | */ |
akashvibhute | 6:5cc7136648d1 | 8 | |
akashvibhute | 3:e94be00fd19e | 9 | /* |
akashvibhute | 3:e94be00fd19e | 10 | * Mbed support added by Akash Vibhute <akash.roboticist@gmail.com> |
akashvibhute | 3:e94be00fd19e | 11 | * Porting completed on Nov/05/2015 |
akashvibhute | 3:e94be00fd19e | 12 | * |
akashvibhute | 6:5cc7136648d1 | 13 | * Updated 1: Synced with TMRh20's RF24 library on Nov/04/2015 from https://github.com/TMRh20 |
akashvibhute | 6:5cc7136648d1 | 14 | * Updated 2: Synced with TMRh20's RF24 library on Apr/18/2015 from https://github.com/TMRh20 |
akashvibhute | 3:e94be00fd19e | 15 | * |
akashvibhute | 3:e94be00fd19e | 16 | */ |
akashvibhute | 6:5cc7136648d1 | 17 | |
akashvibhute | 2:3bdf0d9bb71f | 18 | #include "nRF24L01.h" |
akashvibhute | 2:3bdf0d9bb71f | 19 | #include "RF24_config.h" |
akashvibhute | 0:bb74812ac6bb | 20 | #include "RF24.h" |
akashvibhute | 0:bb74812ac6bb | 21 | |
akashvibhute | 0:bb74812ac6bb | 22 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 23 | |
akashvibhute | 2:3bdf0d9bb71f | 24 | void RF24::csn(bool mode) |
akashvibhute | 0:bb74812ac6bb | 25 | { |
akashvibhute | 6:5cc7136648d1 | 26 | |
akashvibhute | 6:5cc7136648d1 | 27 | csn_pin = mode; |
akashvibhute | 6:5cc7136648d1 | 28 | |
adam_z | 8:6827b6f0283b | 29 | |
akashvibhute | 0:bb74812ac6bb | 30 | } |
akashvibhute | 0:bb74812ac6bb | 31 | |
akashvibhute | 0:bb74812ac6bb | 32 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 33 | |
akashvibhute | 2:3bdf0d9bb71f | 34 | void RF24::ce(bool level) |
akashvibhute | 0:bb74812ac6bb | 35 | { |
akashvibhute | 6:5cc7136648d1 | 36 | ce_pin = level; |
akashvibhute | 6:5cc7136648d1 | 37 | |
akashvibhute | 0:bb74812ac6bb | 38 | } |
akashvibhute | 0:bb74812ac6bb | 39 | |
akashvibhute | 0:bb74812ac6bb | 40 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 41 | |
akashvibhute | 6:5cc7136648d1 | 42 | inline void RF24::beginTransaction() { |
akashvibhute | 6:5cc7136648d1 | 43 | |
akashvibhute | 6:5cc7136648d1 | 44 | |
akashvibhute | 6:5cc7136648d1 | 45 | csn(LOW); |
akashvibhute | 6:5cc7136648d1 | 46 | } |
akashvibhute | 2:3bdf0d9bb71f | 47 | |
akashvibhute | 2:3bdf0d9bb71f | 48 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 49 | |
akashvibhute | 6:5cc7136648d1 | 50 | inline void RF24::endTransaction() { |
akashvibhute | 6:5cc7136648d1 | 51 | csn(HIGH); |
akashvibhute | 6:5cc7136648d1 | 52 | |
akashvibhute | 6:5cc7136648d1 | 53 | |
akashvibhute | 6:5cc7136648d1 | 54 | |
akashvibhute | 6:5cc7136648d1 | 55 | } |
akashvibhute | 2:3bdf0d9bb71f | 56 | |
akashvibhute | 2:3bdf0d9bb71f | 57 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 58 | |
akashvibhute | 0:bb74812ac6bb | 59 | uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len) |
akashvibhute | 0:bb74812ac6bb | 60 | { |
akashvibhute | 6:5cc7136648d1 | 61 | uint8_t status; |
akashvibhute | 0:bb74812ac6bb | 62 | |
akashvibhute | 6:5cc7136648d1 | 63 | |
akashvibhute | 3:e94be00fd19e | 64 | |
akashvibhute | 6:5cc7136648d1 | 65 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 66 | status = spi.write( R_REGISTER | ( REGISTER_MASK & reg ) ); |
akashvibhute | 6:5cc7136648d1 | 67 | while ( len-- ){ |
akashvibhute | 6:5cc7136648d1 | 68 | *buf++ = spi.write(0xff); |
akashvibhute | 6:5cc7136648d1 | 69 | } |
akashvibhute | 6:5cc7136648d1 | 70 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 71 | |
akashvibhute | 6:5cc7136648d1 | 72 | |
akashvibhute | 6:5cc7136648d1 | 73 | |
akashvibhute | 6:5cc7136648d1 | 74 | return status; |
akashvibhute | 0:bb74812ac6bb | 75 | } |
akashvibhute | 0:bb74812ac6bb | 76 | |
akashvibhute | 0:bb74812ac6bb | 77 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 78 | |
akashvibhute | 0:bb74812ac6bb | 79 | uint8_t RF24::read_register(uint8_t reg) |
akashvibhute | 0:bb74812ac6bb | 80 | { |
akashvibhute | 6:5cc7136648d1 | 81 | uint8_t result; |
akashvibhute | 6:5cc7136648d1 | 82 | |
akashvibhute | 0:bb74812ac6bb | 83 | |
akashvibhute | 6:5cc7136648d1 | 84 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 85 | spi.write( R_REGISTER | ( REGISTER_MASK & reg ) ); |
akashvibhute | 6:5cc7136648d1 | 86 | result = spi.write(0xff); |
akashvibhute | 6:5cc7136648d1 | 87 | endTransaction(); |
akashvibhute | 3:e94be00fd19e | 88 | |
akashvibhute | 6:5cc7136648d1 | 89 | |
akashvibhute | 6:5cc7136648d1 | 90 | |
akashvibhute | 6:5cc7136648d1 | 91 | return result; |
akashvibhute | 0:bb74812ac6bb | 92 | } |
akashvibhute | 0:bb74812ac6bb | 93 | |
akashvibhute | 0:bb74812ac6bb | 94 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 95 | |
akashvibhute | 0:bb74812ac6bb | 96 | uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len) |
akashvibhute | 0:bb74812ac6bb | 97 | { |
akashvibhute | 6:5cc7136648d1 | 98 | uint8_t status; |
adam_z | 8:6827b6f0283b | 99 | |
akashvibhute | 3:e94be00fd19e | 100 | |
akashvibhute | 6:5cc7136648d1 | 101 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 102 | status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) ); |
akashvibhute | 6:5cc7136648d1 | 103 | while ( len-- ) |
akashvibhute | 6:5cc7136648d1 | 104 | spi.write(*buf++); |
akashvibhute | 6:5cc7136648d1 | 105 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 106 | |
akashvibhute | 6:5cc7136648d1 | 107 | |
akashvibhute | 6:5cc7136648d1 | 108 | |
akashvibhute | 6:5cc7136648d1 | 109 | return status; |
akashvibhute | 0:bb74812ac6bb | 110 | } |
akashvibhute | 0:bb74812ac6bb | 111 | |
akashvibhute | 0:bb74812ac6bb | 112 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 113 | |
akashvibhute | 0:bb74812ac6bb | 114 | uint8_t RF24::write_register(uint8_t reg, uint8_t value) |
akashvibhute | 0:bb74812ac6bb | 115 | { |
akashvibhute | 6:5cc7136648d1 | 116 | uint8_t status; |
akashvibhute | 2:3bdf0d9bb71f | 117 | |
akashvibhute | 6:5cc7136648d1 | 118 | IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"),reg,value)); |
akashvibhute | 2:3bdf0d9bb71f | 119 | |
akashvibhute | 6:5cc7136648d1 | 120 | |
akashvibhute | 6:5cc7136648d1 | 121 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 122 | status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) ); |
akashvibhute | 6:5cc7136648d1 | 123 | spi.write(value); |
akashvibhute | 6:5cc7136648d1 | 124 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 125 | |
akashvibhute | 6:5cc7136648d1 | 126 | |
akashvibhute | 6:5cc7136648d1 | 127 | |
akashvibhute | 6:5cc7136648d1 | 128 | return status; |
akashvibhute | 2:3bdf0d9bb71f | 129 | } |
akashvibhute | 2:3bdf0d9bb71f | 130 | |
akashvibhute | 2:3bdf0d9bb71f | 131 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 132 | |
akashvibhute | 6:5cc7136648d1 | 133 | uint8_t RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t writeType) |
akashvibhute | 2:3bdf0d9bb71f | 134 | { |
akashvibhute | 6:5cc7136648d1 | 135 | uint8_t status; |
akashvibhute | 6:5cc7136648d1 | 136 | const uint8_t* current = reinterpret_cast<const uint8_t*>(buf); |
akashvibhute | 2:3bdf0d9bb71f | 137 | |
akashvibhute | 6:5cc7136648d1 | 138 | data_len = rf24_min(data_len, payload_size); |
akashvibhute | 6:5cc7136648d1 | 139 | uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len; |
akashvibhute | 6:5cc7136648d1 | 140 | |
akashvibhute | 6:5cc7136648d1 | 141 | //printf("[Writing %u bytes %u blanks]",data_len,blank_len); |
akashvibhute | 6:5cc7136648d1 | 142 | IF_SERIAL_DEBUG( printf("[Writing %u bytes %u blanks]\n",data_len,blank_len); ); |
akashvibhute | 6:5cc7136648d1 | 143 | |
akashvibhute | 6:5cc7136648d1 | 144 | |
akashvibhute | 6:5cc7136648d1 | 145 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 146 | status = spi.write( writeType ); |
akashvibhute | 6:5cc7136648d1 | 147 | while ( data_len-- ) { |
akashvibhute | 6:5cc7136648d1 | 148 | spi.write(*current++); |
akashvibhute | 6:5cc7136648d1 | 149 | } |
akashvibhute | 6:5cc7136648d1 | 150 | while ( blank_len-- ) { |
akashvibhute | 6:5cc7136648d1 | 151 | spi.write(0); |
akashvibhute | 6:5cc7136648d1 | 152 | } |
akashvibhute | 6:5cc7136648d1 | 153 | endTransaction(); |
akashvibhute | 3:e94be00fd19e | 154 | |
akashvibhute | 6:5cc7136648d1 | 155 | |
akashvibhute | 6:5cc7136648d1 | 156 | |
akashvibhute | 6:5cc7136648d1 | 157 | return status; |
akashvibhute | 0:bb74812ac6bb | 158 | } |
akashvibhute | 0:bb74812ac6bb | 159 | |
akashvibhute | 0:bb74812ac6bb | 160 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 161 | |
akashvibhute | 2:3bdf0d9bb71f | 162 | uint8_t RF24::read_payload(void* buf, uint8_t data_len) |
akashvibhute | 0:bb74812ac6bb | 163 | { |
akashvibhute | 6:5cc7136648d1 | 164 | uint8_t status; |
akashvibhute | 6:5cc7136648d1 | 165 | uint8_t* current = reinterpret_cast<uint8_t*>(buf); |
akashvibhute | 2:3bdf0d9bb71f | 166 | |
akashvibhute | 6:5cc7136648d1 | 167 | if(data_len > payload_size) data_len = payload_size; |
akashvibhute | 6:5cc7136648d1 | 168 | uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len; |
akashvibhute | 6:5cc7136648d1 | 169 | |
akashvibhute | 6:5cc7136648d1 | 170 | //printf("[Reading %u bytes %u blanks]",data_len,blank_len); |
akashvibhute | 0:bb74812ac6bb | 171 | |
akashvibhute | 6:5cc7136648d1 | 172 | IF_SERIAL_DEBUG( printf("[Reading %u bytes %u blanks]\n",data_len,blank_len); ); |
akashvibhute | 6:5cc7136648d1 | 173 | |
akashvibhute | 6:5cc7136648d1 | 174 | |
akashvibhute | 3:e94be00fd19e | 175 | |
akashvibhute | 6:5cc7136648d1 | 176 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 177 | status = spi.write( R_RX_PAYLOAD ); |
akashvibhute | 6:5cc7136648d1 | 178 | while ( data_len-- ) { |
akashvibhute | 6:5cc7136648d1 | 179 | *current++ = spi.write(0xFF); |
akashvibhute | 6:5cc7136648d1 | 180 | } |
akashvibhute | 6:5cc7136648d1 | 181 | while ( blank_len-- ) { |
akashvibhute | 6:5cc7136648d1 | 182 | spi.write(0xff); |
akashvibhute | 6:5cc7136648d1 | 183 | } |
akashvibhute | 6:5cc7136648d1 | 184 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 185 | |
akashvibhute | 6:5cc7136648d1 | 186 | |
akashvibhute | 6:5cc7136648d1 | 187 | |
akashvibhute | 6:5cc7136648d1 | 188 | return status; |
akashvibhute | 0:bb74812ac6bb | 189 | } |
akashvibhute | 0:bb74812ac6bb | 190 | |
akashvibhute | 0:bb74812ac6bb | 191 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 192 | |
akashvibhute | 0:bb74812ac6bb | 193 | uint8_t RF24::flush_rx(void) |
akashvibhute | 0:bb74812ac6bb | 194 | { |
akashvibhute | 6:5cc7136648d1 | 195 | return spiTrans( FLUSH_RX ); |
akashvibhute | 0:bb74812ac6bb | 196 | } |
akashvibhute | 0:bb74812ac6bb | 197 | |
akashvibhute | 0:bb74812ac6bb | 198 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 199 | |
akashvibhute | 0:bb74812ac6bb | 200 | uint8_t RF24::flush_tx(void) |
akashvibhute | 0:bb74812ac6bb | 201 | { |
akashvibhute | 6:5cc7136648d1 | 202 | return spiTrans( FLUSH_TX ); |
akashvibhute | 2:3bdf0d9bb71f | 203 | } |
akashvibhute | 2:3bdf0d9bb71f | 204 | |
akashvibhute | 2:3bdf0d9bb71f | 205 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 206 | |
akashvibhute | 6:5cc7136648d1 | 207 | uint8_t RF24::spiTrans(uint8_t cmd){ |
akashvibhute | 0:bb74812ac6bb | 208 | |
akashvibhute | 6:5cc7136648d1 | 209 | uint8_t status; |
akashvibhute | 6:5cc7136648d1 | 210 | |
akashvibhute | 6:5cc7136648d1 | 211 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 212 | status = spi.write( cmd ); |
akashvibhute | 6:5cc7136648d1 | 213 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 214 | |
akashvibhute | 6:5cc7136648d1 | 215 | return status; |
akashvibhute | 0:bb74812ac6bb | 216 | } |
akashvibhute | 0:bb74812ac6bb | 217 | |
akashvibhute | 0:bb74812ac6bb | 218 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 219 | |
akashvibhute | 0:bb74812ac6bb | 220 | uint8_t RF24::get_status(void) |
akashvibhute | 0:bb74812ac6bb | 221 | { |
akashvibhute | 6:5cc7136648d1 | 222 | return spiTrans(NOP); |
akashvibhute | 0:bb74812ac6bb | 223 | } |
akashvibhute | 0:bb74812ac6bb | 224 | |
akashvibhute | 0:bb74812ac6bb | 225 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 226 | #if !defined (MINIMAL) |
akashvibhute | 0:bb74812ac6bb | 227 | void RF24::print_status(uint8_t status) |
akashvibhute | 0:bb74812ac6bb | 228 | { |
akashvibhute | 6:5cc7136648d1 | 229 | printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"), |
akashvibhute | 0:bb74812ac6bb | 230 | status, |
akashvibhute | 0:bb74812ac6bb | 231 | (status & _BV(RX_DR))?1:0, |
akashvibhute | 0:bb74812ac6bb | 232 | (status & _BV(TX_DS))?1:0, |
akashvibhute | 0:bb74812ac6bb | 233 | (status & _BV(MAX_RT))?1:0, |
akashvibhute | 6:5cc7136648d1 | 234 | ((status >> RX_P_NO) & 0b111), |
akashvibhute | 0:bb74812ac6bb | 235 | (status & _BV(TX_FULL))?1:0 |
akashvibhute | 0:bb74812ac6bb | 236 | ); |
akashvibhute | 0:bb74812ac6bb | 237 | } |
akashvibhute | 0:bb74812ac6bb | 238 | |
akashvibhute | 0:bb74812ac6bb | 239 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 240 | |
akashvibhute | 0:bb74812ac6bb | 241 | void RF24::print_observe_tx(uint8_t value) |
akashvibhute | 0:bb74812ac6bb | 242 | { |
akashvibhute | 6:5cc7136648d1 | 243 | printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"), |
akashvibhute | 0:bb74812ac6bb | 244 | value, |
akashvibhute | 6:5cc7136648d1 | 245 | (value >> PLOS_CNT) & 0b1111, |
akashvibhute | 6:5cc7136648d1 | 246 | (value >> ARC_CNT) & 0b1111 |
akashvibhute | 0:bb74812ac6bb | 247 | ); |
akashvibhute | 0:bb74812ac6bb | 248 | } |
akashvibhute | 0:bb74812ac6bb | 249 | |
akashvibhute | 0:bb74812ac6bb | 250 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 251 | |
akashvibhute | 0:bb74812ac6bb | 252 | void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty) |
akashvibhute | 0:bb74812ac6bb | 253 | { |
akashvibhute | 6:5cc7136648d1 | 254 | //char extra_tab = strlen_P(name) < 8 ? '\t' : 0; |
akashvibhute | 6:5cc7136648d1 | 255 | //printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab); |
akashvibhute | 6:5cc7136648d1 | 256 | |
akashvibhute | 6:5cc7136648d1 | 257 | |
akashvibhute | 6:5cc7136648d1 | 258 | |
akashvibhute | 6:5cc7136648d1 | 259 | printf_P(PSTR(PRIPSTR"\t ="),name); |
akashvibhute | 6:5cc7136648d1 | 260 | |
akashvibhute | 6:5cc7136648d1 | 261 | while (qty--) |
akashvibhute | 6:5cc7136648d1 | 262 | printf_P(PSTR(" 0x%02x"),read_register(reg++)); |
akashvibhute | 6:5cc7136648d1 | 263 | printf_P(PSTR("\r\n")); |
akashvibhute | 0:bb74812ac6bb | 264 | } |
akashvibhute | 0:bb74812ac6bb | 265 | |
akashvibhute | 0:bb74812ac6bb | 266 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 267 | |
akashvibhute | 0:bb74812ac6bb | 268 | void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty) |
akashvibhute | 0:bb74812ac6bb | 269 | { |
akashvibhute | 0:bb74812ac6bb | 270 | |
akashvibhute | 6:5cc7136648d1 | 271 | |
akashvibhute | 6:5cc7136648d1 | 272 | |
akashvibhute | 6:5cc7136648d1 | 273 | |
akashvibhute | 6:5cc7136648d1 | 274 | printf_P(PSTR(PRIPSTR"\t ="),name); |
akashvibhute | 6:5cc7136648d1 | 275 | |
akashvibhute | 6:5cc7136648d1 | 276 | while (qty--) |
akashvibhute | 6:5cc7136648d1 | 277 | { |
akashvibhute | 6:5cc7136648d1 | 278 | uint8_t buffer[addr_width]; |
akashvibhute | 6:5cc7136648d1 | 279 | read_register(reg++,buffer,sizeof buffer); |
akashvibhute | 0:bb74812ac6bb | 280 | |
akashvibhute | 6:5cc7136648d1 | 281 | printf_P(PSTR(" 0x")); |
akashvibhute | 6:5cc7136648d1 | 282 | uint8_t* bufptr = buffer + sizeof buffer; |
akashvibhute | 6:5cc7136648d1 | 283 | while( --bufptr >= buffer ) |
akashvibhute | 6:5cc7136648d1 | 284 | printf_P(PSTR("%02x"),*bufptr); |
akashvibhute | 6:5cc7136648d1 | 285 | } |
akashvibhute | 3:e94be00fd19e | 286 | |
akashvibhute | 6:5cc7136648d1 | 287 | printf_P(PSTR("\r\n")); |
akashvibhute | 2:3bdf0d9bb71f | 288 | } |
akashvibhute | 2:3bdf0d9bb71f | 289 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 290 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 291 | RF24::RF24(PinName mosi, PinName miso, PinName sck, PinName _cepin, PinName _csnpin): |
akashvibhute | 6:5cc7136648d1 | 292 | spi(mosi, miso, sck), ce_pin(_cepin), csn_pin(_csnpin), p_variant(true), |
akashvibhute | 6:5cc7136648d1 | 293 | payload_size(32), dynamic_payloads_enabled(false), addr_width(5) |
akashvibhute | 2:3bdf0d9bb71f | 294 | { |
akashvibhute | 6:5cc7136648d1 | 295 | pipe0_reading_address[0]=0; |
akashvibhute | 6:5cc7136648d1 | 296 | |
akashvibhute | 6:5cc7136648d1 | 297 | //spi.frequency(10000000/5); // 2Mbit, 1/5th the maximum transfer rate for the spi bus |
adam_z | 8:6827b6f0283b | 298 | spi.frequency(10000000/5); |
akashvibhute | 6:5cc7136648d1 | 299 | //spi.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0 |
akashvibhute | 6:5cc7136648d1 | 300 | spi.format(8,0); |
akashvibhute | 6:5cc7136648d1 | 301 | wait_ms(10); |
akashvibhute | 0:bb74812ac6bb | 302 | } |
akashvibhute | 0:bb74812ac6bb | 303 | |
akashvibhute | 2:3bdf0d9bb71f | 304 | |
akashvibhute | 2:3bdf0d9bb71f | 305 | |
akashvibhute | 0:bb74812ac6bb | 306 | |
akashvibhute | 2:3bdf0d9bb71f | 307 | |
akashvibhute | 2:3bdf0d9bb71f | 308 | |
akashvibhute | 2:3bdf0d9bb71f | 309 | |
akashvibhute | 0:bb74812ac6bb | 310 | |
akashvibhute | 0:bb74812ac6bb | 311 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 312 | |
akashvibhute | 0:bb74812ac6bb | 313 | void RF24::setChannel(uint8_t channel) |
akashvibhute | 0:bb74812ac6bb | 314 | { |
akashvibhute | 6:5cc7136648d1 | 315 | const uint8_t max_channel = 125; |
akashvibhute | 6:5cc7136648d1 | 316 | write_register(RF_CH,rf24_min(channel,max_channel)); |
akashvibhute | 0:bb74812ac6bb | 317 | } |
akashvibhute | 0:bb74812ac6bb | 318 | |
akashvibhute | 2:3bdf0d9bb71f | 319 | uint8_t RF24::getChannel() |
akashvibhute | 2:3bdf0d9bb71f | 320 | { |
akashvibhute | 6:5cc7136648d1 | 321 | |
akashvibhute | 6:5cc7136648d1 | 322 | return read_register(RF_CH); |
akashvibhute | 2:3bdf0d9bb71f | 323 | } |
akashvibhute | 0:bb74812ac6bb | 324 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 325 | |
akashvibhute | 0:bb74812ac6bb | 326 | void RF24::setPayloadSize(uint8_t size) |
akashvibhute | 0:bb74812ac6bb | 327 | { |
akashvibhute | 6:5cc7136648d1 | 328 | payload_size = rf24_min(size,32); |
akashvibhute | 0:bb74812ac6bb | 329 | } |
akashvibhute | 0:bb74812ac6bb | 330 | |
akashvibhute | 0:bb74812ac6bb | 331 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 332 | |
akashvibhute | 0:bb74812ac6bb | 333 | uint8_t RF24::getPayloadSize(void) |
akashvibhute | 0:bb74812ac6bb | 334 | { |
akashvibhute | 6:5cc7136648d1 | 335 | return payload_size; |
akashvibhute | 0:bb74812ac6bb | 336 | } |
akashvibhute | 0:bb74812ac6bb | 337 | |
akashvibhute | 0:bb74812ac6bb | 338 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 339 | |
akashvibhute | 2:3bdf0d9bb71f | 340 | #if !defined (MINIMAL) |
akashvibhute | 2:3bdf0d9bb71f | 341 | |
akashvibhute | 2:3bdf0d9bb71f | 342 | static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS"; |
akashvibhute | 2:3bdf0d9bb71f | 343 | static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS"; |
akashvibhute | 2:3bdf0d9bb71f | 344 | static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS"; |
akashvibhute | 2:3bdf0d9bb71f | 345 | static const char * const rf24_datarate_e_str_P[] PROGMEM = { |
akashvibhute | 6:5cc7136648d1 | 346 | rf24_datarate_e_str_0, |
akashvibhute | 6:5cc7136648d1 | 347 | rf24_datarate_e_str_1, |
akashvibhute | 6:5cc7136648d1 | 348 | rf24_datarate_e_str_2, |
akashvibhute | 0:bb74812ac6bb | 349 | }; |
akashvibhute | 2:3bdf0d9bb71f | 350 | static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01"; |
akashvibhute | 2:3bdf0d9bb71f | 351 | static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+"; |
akashvibhute | 2:3bdf0d9bb71f | 352 | static const char * const rf24_model_e_str_P[] PROGMEM = { |
akashvibhute | 6:5cc7136648d1 | 353 | rf24_model_e_str_0, |
akashvibhute | 6:5cc7136648d1 | 354 | rf24_model_e_str_1, |
akashvibhute | 0:bb74812ac6bb | 355 | }; |
akashvibhute | 2:3bdf0d9bb71f | 356 | static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled"; |
akashvibhute | 2:3bdf0d9bb71f | 357 | static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits"; |
akashvibhute | 2:3bdf0d9bb71f | 358 | static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ; |
akashvibhute | 2:3bdf0d9bb71f | 359 | static const char * const rf24_crclength_e_str_P[] PROGMEM = { |
akashvibhute | 6:5cc7136648d1 | 360 | rf24_crclength_e_str_0, |
akashvibhute | 6:5cc7136648d1 | 361 | rf24_crclength_e_str_1, |
akashvibhute | 6:5cc7136648d1 | 362 | rf24_crclength_e_str_2, |
akashvibhute | 0:bb74812ac6bb | 363 | }; |
akashvibhute | 2:3bdf0d9bb71f | 364 | static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN"; |
akashvibhute | 2:3bdf0d9bb71f | 365 | static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW"; |
akashvibhute | 2:3bdf0d9bb71f | 366 | static const char rf24_pa_dbm_e_str_2[] PROGMEM = "PA_HIGH"; |
akashvibhute | 2:3bdf0d9bb71f | 367 | static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_MAX"; |
akashvibhute | 2:3bdf0d9bb71f | 368 | static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = { |
akashvibhute | 6:5cc7136648d1 | 369 | rf24_pa_dbm_e_str_0, |
akashvibhute | 6:5cc7136648d1 | 370 | rf24_pa_dbm_e_str_1, |
akashvibhute | 6:5cc7136648d1 | 371 | rf24_pa_dbm_e_str_2, |
akashvibhute | 6:5cc7136648d1 | 372 | rf24_pa_dbm_e_str_3, |
akashvibhute | 0:bb74812ac6bb | 373 | }; |
akashvibhute | 0:bb74812ac6bb | 374 | |
akashvibhute | 6:5cc7136648d1 | 375 | |
akashvibhute | 6:5cc7136648d1 | 376 | |
akashvibhute | 6:5cc7136648d1 | 377 | |
akashvibhute | 6:5cc7136648d1 | 378 | |
akashvibhute | 6:5cc7136648d1 | 379 | |
akashvibhute | 6:5cc7136648d1 | 380 | |
akashvibhute | 6:5cc7136648d1 | 381 | |
akashvibhute | 6:5cc7136648d1 | 382 | |
akashvibhute | 6:5cc7136648d1 | 383 | |
akashvibhute | 6:5cc7136648d1 | 384 | |
akashvibhute | 6:5cc7136648d1 | 385 | |
akashvibhute | 6:5cc7136648d1 | 386 | |
akashvibhute | 6:5cc7136648d1 | 387 | |
akashvibhute | 0:bb74812ac6bb | 388 | void RF24::printDetails(void) |
akashvibhute | 0:bb74812ac6bb | 389 | { |
akashvibhute | 6:5cc7136648d1 | 390 | |
akashvibhute | 6:5cc7136648d1 | 391 | |
akashvibhute | 6:5cc7136648d1 | 392 | print_status(get_status()); |
akashvibhute | 6:5cc7136648d1 | 393 | |
akashvibhute | 6:5cc7136648d1 | 394 | print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2); |
akashvibhute | 6:5cc7136648d1 | 395 | print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4); |
akashvibhute | 6:5cc7136648d1 | 396 | print_address_register(PSTR("TX_ADDR\t"),TX_ADDR); |
akashvibhute | 0:bb74812ac6bb | 397 | |
akashvibhute | 6:5cc7136648d1 | 398 | print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6); |
akashvibhute | 6:5cc7136648d1 | 399 | print_byte_register(PSTR("EN_AA\t"),EN_AA); |
akashvibhute | 6:5cc7136648d1 | 400 | print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR); |
akashvibhute | 6:5cc7136648d1 | 401 | print_byte_register(PSTR("RF_CH\t"),RF_CH); |
akashvibhute | 6:5cc7136648d1 | 402 | print_byte_register(PSTR("RF_SETUP"),RF_SETUP); |
akashvibhute | 6:5cc7136648d1 | 403 | print_byte_register(PSTR("CONFIG\t"),NRF_CONFIG); |
akashvibhute | 6:5cc7136648d1 | 404 | print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2); |
akashvibhute | 6:5cc7136648d1 | 405 | |
akashvibhute | 6:5cc7136648d1 | 406 | printf_P(PSTR("Data Rate\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_datarate_e_str_P[getDataRate()])); |
akashvibhute | 6:5cc7136648d1 | 407 | printf_P(PSTR("Model\t\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_model_e_str_P[isPVariant()])); |
akashvibhute | 6:5cc7136648d1 | 408 | printf_P(PSTR("CRC Length\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_crclength_e_str_P[getCRCLength()])); |
akashvibhute | 6:5cc7136648d1 | 409 | printf_P(PSTR("PA Power\t = " PRIPSTR "\r\n"), pgm_read_word(&rf24_pa_dbm_e_str_P[getPALevel()])); |
akashvibhute | 2:3bdf0d9bb71f | 410 | |
akashvibhute | 0:bb74812ac6bb | 411 | } |
akashvibhute | 0:bb74812ac6bb | 412 | |
akashvibhute | 2:3bdf0d9bb71f | 413 | #endif |
akashvibhute | 0:bb74812ac6bb | 414 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 415 | |
akashvibhute | 2:3bdf0d9bb71f | 416 | bool RF24::begin(void) |
akashvibhute | 0:bb74812ac6bb | 417 | { |
akashvibhute | 6:5cc7136648d1 | 418 | |
akashvibhute | 6:5cc7136648d1 | 419 | uint8_t setup=0; |
akashvibhute | 6:5cc7136648d1 | 420 | |
akashvibhute | 6:5cc7136648d1 | 421 | mainTimer.start(); |
akashvibhute | 6:5cc7136648d1 | 422 | |
akashvibhute | 6:5cc7136648d1 | 423 | ce(LOW); |
akashvibhute | 6:5cc7136648d1 | 424 | csn(HIGH); |
akashvibhute | 6:5cc7136648d1 | 425 | |
akashvibhute | 6:5cc7136648d1 | 426 | wait_ms(100); |
akashvibhute | 6:5cc7136648d1 | 427 | |
akashvibhute | 6:5cc7136648d1 | 428 | |
akashvibhute | 6:5cc7136648d1 | 429 | |
akashvibhute | 6:5cc7136648d1 | 430 | |
akashvibhute | 6:5cc7136648d1 | 431 | // Must allow the radio time to settle else configuration bits will not necessarily stick. |
akashvibhute | 6:5cc7136648d1 | 432 | // This is actually only required following power up but some settling time also appears to |
akashvibhute | 6:5cc7136648d1 | 433 | // be required after resets too. For full coverage, we'll always assume the worst. |
akashvibhute | 6:5cc7136648d1 | 434 | // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped. |
akashvibhute | 6:5cc7136648d1 | 435 | // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure. |
akashvibhute | 6:5cc7136648d1 | 436 | // WARNING: Delay is based on P-variant whereby non-P *may* require different timing. |
akashvibhute | 6:5cc7136648d1 | 437 | wait_ms( 5 ) ; |
akashvibhute | 0:bb74812ac6bb | 438 | |
akashvibhute | 6:5cc7136648d1 | 439 | // Reset NRF_CONFIG and enable 16-bit CRC. |
akashvibhute | 6:5cc7136648d1 | 440 | write_register( NRF_CONFIG, 0b00001100 ) ; |
akashvibhute | 6:5cc7136648d1 | 441 | |
akashvibhute | 6:5cc7136648d1 | 442 | // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier |
akashvibhute | 6:5cc7136648d1 | 443 | // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet |
akashvibhute | 6:5cc7136648d1 | 444 | // sizes must never be used. See documentation for a more complete explanation. |
akashvibhute | 6:5cc7136648d1 | 445 | setRetries(5,15); |
akashvibhute | 6:5cc7136648d1 | 446 | |
akashvibhute | 6:5cc7136648d1 | 447 | // Reset value is MAX |
akashvibhute | 6:5cc7136648d1 | 448 | //setPALevel( RF24_PA_MAX ) ; |
akashvibhute | 0:bb74812ac6bb | 449 | |
akashvibhute | 6:5cc7136648d1 | 450 | // check for connected module and if this is a p nRF24l01 variant |
akashvibhute | 6:5cc7136648d1 | 451 | // |
akashvibhute | 6:5cc7136648d1 | 452 | if( setDataRate( RF24_250KBPS ) ) |
akashvibhute | 6:5cc7136648d1 | 453 | { |
akashvibhute | 6:5cc7136648d1 | 454 | p_variant = true ; |
akashvibhute | 6:5cc7136648d1 | 455 | } |
akashvibhute | 6:5cc7136648d1 | 456 | setup = read_register(RF_SETUP); |
akashvibhute | 6:5cc7136648d1 | 457 | /*if( setup == 0b00001110 ) // register default for nRF24L01P |
akashvibhute | 6:5cc7136648d1 | 458 | { |
akashvibhute | 6:5cc7136648d1 | 459 | p_variant = true ; |
akashvibhute | 6:5cc7136648d1 | 460 | }*/ |
akashvibhute | 6:5cc7136648d1 | 461 | |
akashvibhute | 6:5cc7136648d1 | 462 | // Then set the data rate to the slowest (and most reliable) speed supported by all |
akashvibhute | 6:5cc7136648d1 | 463 | // hardware. |
akashvibhute | 6:5cc7136648d1 | 464 | //setDataRate( RF24_1MBPS ) ; |
adam_z | 8:6827b6f0283b | 465 | setDataRate( RF24_1MBPS ) ; |
akashvibhute | 0:bb74812ac6bb | 466 | |
akashvibhute | 6:5cc7136648d1 | 467 | // Initialize CRC and request 2-byte (16bit) CRC |
adam_z | 8:6827b6f0283b | 468 | setCRCLength( RF24_CRC_16 ) ; |
akashvibhute | 2:3bdf0d9bb71f | 469 | |
akashvibhute | 6:5cc7136648d1 | 470 | // Disable dynamic payloads, to match dynamic_payloads_enabled setting - Reset value is 0 |
akashvibhute | 6:5cc7136648d1 | 471 | toggle_features(); |
akashvibhute | 6:5cc7136648d1 | 472 | write_register(FEATURE,0 ); |
akashvibhute | 6:5cc7136648d1 | 473 | write_register(DYNPD,0); |
akashvibhute | 6:5cc7136648d1 | 474 | |
akashvibhute | 6:5cc7136648d1 | 475 | // Reset current status |
akashvibhute | 6:5cc7136648d1 | 476 | // Notice reset and flush is the last thing we do |
akashvibhute | 6:5cc7136648d1 | 477 | write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); |
akashvibhute | 0:bb74812ac6bb | 478 | |
akashvibhute | 6:5cc7136648d1 | 479 | // Set up default configuration. Callers can always change it later. |
akashvibhute | 6:5cc7136648d1 | 480 | // This channel should be universally safe and not bleed over into adjacent |
akashvibhute | 6:5cc7136648d1 | 481 | // spectrum. |
akashvibhute | 6:5cc7136648d1 | 482 | setChannel(76); |
akashvibhute | 0:bb74812ac6bb | 483 | |
akashvibhute | 6:5cc7136648d1 | 484 | // Flush buffers |
akashvibhute | 6:5cc7136648d1 | 485 | flush_rx(); |
akashvibhute | 6:5cc7136648d1 | 486 | flush_tx(); |
akashvibhute | 2:3bdf0d9bb71f | 487 | |
akashvibhute | 6:5cc7136648d1 | 488 | powerUp(); //Power up by default when begin() is called |
akashvibhute | 2:3bdf0d9bb71f | 489 | |
akashvibhute | 6:5cc7136648d1 | 490 | // Enable PTX, do not write CE high so radio will remain in standby I mode ( 130us max to transition to RX or TX instead of 1500us from powerUp ) |
akashvibhute | 6:5cc7136648d1 | 491 | // PTX should use only 22uA of power |
akashvibhute | 6:5cc7136648d1 | 492 | write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) ); |
akashvibhute | 6:5cc7136648d1 | 493 | printDetails(); |
akashvibhute | 6:5cc7136648d1 | 494 | // if setup is 0 or ff then there was no response from module |
akashvibhute | 6:5cc7136648d1 | 495 | return ( setup != 0 && setup != 0xff ); |
akashvibhute | 0:bb74812ac6bb | 496 | } |
akashvibhute | 0:bb74812ac6bb | 497 | |
akashvibhute | 0:bb74812ac6bb | 498 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 499 | |
akashvibhute | 0:bb74812ac6bb | 500 | void RF24::startListening(void) |
akashvibhute | 0:bb74812ac6bb | 501 | { |
akashvibhute | 6:5cc7136648d1 | 502 | |
akashvibhute | 6:5cc7136648d1 | 503 | |
akashvibhute | 6:5cc7136648d1 | 504 | |
akashvibhute | 6:5cc7136648d1 | 505 | write_register(NRF_CONFIG, read_register(NRF_CONFIG) | _BV(PRIM_RX)); |
akashvibhute | 6:5cc7136648d1 | 506 | write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); |
akashvibhute | 6:5cc7136648d1 | 507 | ce(HIGH); |
akashvibhute | 6:5cc7136648d1 | 508 | // Restore the pipe0 adddress, if exists |
akashvibhute | 6:5cc7136648d1 | 509 | if (pipe0_reading_address[0] > 0){ |
akashvibhute | 6:5cc7136648d1 | 510 | write_register(RX_ADDR_P0, pipe0_reading_address, addr_width); |
akashvibhute | 6:5cc7136648d1 | 511 | }else{ |
akashvibhute | 6:5cc7136648d1 | 512 | closeReadingPipe(0); |
akashvibhute | 6:5cc7136648d1 | 513 | } |
akashvibhute | 0:bb74812ac6bb | 514 | |
akashvibhute | 6:5cc7136648d1 | 515 | // Flush buffers |
akashvibhute | 6:5cc7136648d1 | 516 | //flush_rx(); |
akashvibhute | 6:5cc7136648d1 | 517 | if(read_register(FEATURE) & _BV(EN_ACK_PAY)){ |
akashvibhute | 6:5cc7136648d1 | 518 | flush_tx(); |
akashvibhute | 6:5cc7136648d1 | 519 | } |
akashvibhute | 0:bb74812ac6bb | 520 | |
akashvibhute | 6:5cc7136648d1 | 521 | // Go! |
akashvibhute | 6:5cc7136648d1 | 522 | //delayMicroseconds(100); |
akashvibhute | 0:bb74812ac6bb | 523 | } |
akashvibhute | 0:bb74812ac6bb | 524 | |
akashvibhute | 0:bb74812ac6bb | 525 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 526 | static const uint8_t child_pipe_enable[] PROGMEM = |
akashvibhute | 6:5cc7136648d1 | 527 | { |
akashvibhute | 6:5cc7136648d1 | 528 | ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5 |
akashvibhute | 2:3bdf0d9bb71f | 529 | }; |
akashvibhute | 0:bb74812ac6bb | 530 | |
akashvibhute | 0:bb74812ac6bb | 531 | void RF24::stopListening(void) |
akashvibhute | 6:5cc7136648d1 | 532 | { |
akashvibhute | 6:5cc7136648d1 | 533 | ce(LOW); |
akashvibhute | 2:3bdf0d9bb71f | 534 | |
akashvibhute | 6:5cc7136648d1 | 535 | wait_us(txRxDelay); |
akashvibhute | 6:5cc7136648d1 | 536 | |
akashvibhute | 6:5cc7136648d1 | 537 | if(read_register(FEATURE) & _BV(EN_ACK_PAY)){ |
akashvibhute | 6:5cc7136648d1 | 538 | wait_us(txRxDelay); //200 |
akashvibhute | 6:5cc7136648d1 | 539 | flush_tx(); |
akashvibhute | 6:5cc7136648d1 | 540 | } |
akashvibhute | 6:5cc7136648d1 | 541 | //flush_rx(); |
akashvibhute | 6:5cc7136648d1 | 542 | write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) ); |
akashvibhute | 6:5cc7136648d1 | 543 | |
akashvibhute | 6:5cc7136648d1 | 544 | |
akashvibhute | 6:5cc7136648d1 | 545 | write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0]))); // Enable RX on pipe0 |
akashvibhute | 6:5cc7136648d1 | 546 | |
akashvibhute | 6:5cc7136648d1 | 547 | //delayMicroseconds(100); |
akashvibhute | 2:3bdf0d9bb71f | 548 | |
akashvibhute | 0:bb74812ac6bb | 549 | } |
akashvibhute | 0:bb74812ac6bb | 550 | |
akashvibhute | 0:bb74812ac6bb | 551 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 552 | |
akashvibhute | 0:bb74812ac6bb | 553 | void RF24::powerDown(void) |
akashvibhute | 0:bb74812ac6bb | 554 | { |
akashvibhute | 6:5cc7136648d1 | 555 | ce(LOW); // Guarantee CE is low on powerDown |
akashvibhute | 6:5cc7136648d1 | 556 | write_register(NRF_CONFIG,read_register(NRF_CONFIG) & ~_BV(PWR_UP)); |
akashvibhute | 0:bb74812ac6bb | 557 | } |
akashvibhute | 0:bb74812ac6bb | 558 | |
akashvibhute | 0:bb74812ac6bb | 559 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 560 | |
akashvibhute | 2:3bdf0d9bb71f | 561 | //Power up now. Radio will not power down unless instructed by MCU for config changes etc. |
akashvibhute | 0:bb74812ac6bb | 562 | void RF24::powerUp(void) |
akashvibhute | 0:bb74812ac6bb | 563 | { |
akashvibhute | 6:5cc7136648d1 | 564 | uint8_t cfg = read_register(NRF_CONFIG); |
akashvibhute | 2:3bdf0d9bb71f | 565 | |
akashvibhute | 6:5cc7136648d1 | 566 | // if not powered up then power up and wait for the radio to initialize |
akashvibhute | 6:5cc7136648d1 | 567 | if (!(cfg & _BV(PWR_UP))){ |
akashvibhute | 6:5cc7136648d1 | 568 | write_register(NRF_CONFIG, cfg | _BV(PWR_UP)); |
akashvibhute | 2:3bdf0d9bb71f | 569 | |
akashvibhute | 6:5cc7136648d1 | 570 | // For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode. |
akashvibhute | 6:5cc7136648d1 | 571 | // There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before |
akashvibhute | 6:5cc7136648d1 | 572 | // the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet |
akashvibhute | 6:5cc7136648d1 | 573 | wait_ms(5); |
akashvibhute | 6:5cc7136648d1 | 574 | } |
akashvibhute | 0:bb74812ac6bb | 575 | } |
akashvibhute | 0:bb74812ac6bb | 576 | |
akashvibhute | 0:bb74812ac6bb | 577 | /******************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 578 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 579 | void RF24::errNotify(){ |
akashvibhute | 6:5cc7136648d1 | 580 | #if defined (SERIAL_DEBUG) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 581 | printf_P(PSTR("RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n")); |
akashvibhute | 6:5cc7136648d1 | 582 | #endif |
akashvibhute | 6:5cc7136648d1 | 583 | #if defined (FAILURE_HANDLING) |
akashvibhute | 6:5cc7136648d1 | 584 | failureDetected = 1; |
akashvibhute | 6:5cc7136648d1 | 585 | #else |
akashvibhute | 6:5cc7136648d1 | 586 | wait_ms(5000); |
akashvibhute | 6:5cc7136648d1 | 587 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 588 | } |
akashvibhute | 2:3bdf0d9bb71f | 589 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 590 | /******************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 591 | |
akashvibhute | 2:3bdf0d9bb71f | 592 | //Similar to the previous write, clears the interrupt flags |
akashvibhute | 2:3bdf0d9bb71f | 593 | bool RF24::write( const void* buf, uint8_t len, const bool multicast ) |
akashvibhute | 2:3bdf0d9bb71f | 594 | { |
akashvibhute | 6:5cc7136648d1 | 595 | //Start Writing |
akashvibhute | 6:5cc7136648d1 | 596 | startFastWrite(buf,len,multicast); |
akashvibhute | 3:e94be00fd19e | 597 | |
akashvibhute | 6:5cc7136648d1 | 598 | //Wait until complete or failed |
akashvibhute | 6:5cc7136648d1 | 599 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 600 | uint32_t timer = mainTimer.read_ms(); |
akashvibhute | 6:5cc7136648d1 | 601 | #endif |
akashvibhute | 6:5cc7136648d1 | 602 | |
akashvibhute | 6:5cc7136648d1 | 603 | while( ! ( get_status() & ( _BV(TX_DS) | _BV(MAX_RT) ))) { |
akashvibhute | 6:5cc7136648d1 | 604 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 605 | if(mainTimer.read_ms() - timer > 95){ |
akashvibhute | 6:5cc7136648d1 | 606 | errNotify(); |
akashvibhute | 6:5cc7136648d1 | 607 | #if defined (FAILURE_HANDLING) |
akashvibhute | 6:5cc7136648d1 | 608 | return 0; |
akashvibhute | 6:5cc7136648d1 | 609 | #else |
akashvibhute | 6:5cc7136648d1 | 610 | wait_ms(100); |
akashvibhute | 6:5cc7136648d1 | 611 | #endif |
akashvibhute | 6:5cc7136648d1 | 612 | } |
akashvibhute | 6:5cc7136648d1 | 613 | #endif |
akashvibhute | 6:5cc7136648d1 | 614 | } |
akashvibhute | 6:5cc7136648d1 | 615 | |
akashvibhute | 6:5cc7136648d1 | 616 | ce(LOW); |
akashvibhute | 3:e94be00fd19e | 617 | |
akashvibhute | 6:5cc7136648d1 | 618 | uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); |
akashvibhute | 0:bb74812ac6bb | 619 | |
akashvibhute | 6:5cc7136648d1 | 620 | //Max retries exceeded |
akashvibhute | 6:5cc7136648d1 | 621 | if( status & _BV(MAX_RT)){ |
akashvibhute | 6:5cc7136648d1 | 622 | flush_tx(); //Only going to be 1 packet int the FIFO at a time using this method, so just flush |
akashvibhute | 6:5cc7136648d1 | 623 | return 0; |
akashvibhute | 6:5cc7136648d1 | 624 | } |
akashvibhute | 6:5cc7136648d1 | 625 | //TX OK 1 or 0 |
akashvibhute | 6:5cc7136648d1 | 626 | return 1; |
akashvibhute | 2:3bdf0d9bb71f | 627 | } |
akashvibhute | 0:bb74812ac6bb | 628 | |
akashvibhute | 6:5cc7136648d1 | 629 | bool RF24::write( const void* buf, uint8_t len ){ |
akashvibhute | 6:5cc7136648d1 | 630 | return write(buf,len,0); |
akashvibhute | 0:bb74812ac6bb | 631 | } |
akashvibhute | 0:bb74812ac6bb | 632 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 633 | |
akashvibhute | 2:3bdf0d9bb71f | 634 | //For general use, the interrupt flags are not important to clear |
akashvibhute | 2:3bdf0d9bb71f | 635 | bool RF24::writeBlocking( const void* buf, uint8_t len, uint32_t timeout ) |
akashvibhute | 2:3bdf0d9bb71f | 636 | { |
akashvibhute | 6:5cc7136648d1 | 637 | //Block until the FIFO is NOT full. |
akashvibhute | 6:5cc7136648d1 | 638 | //Keep track of the MAX retries and set auto-retry if seeing failures |
akashvibhute | 6:5cc7136648d1 | 639 | //This way the FIFO will fill up and allow blocking until packets go through |
akashvibhute | 6:5cc7136648d1 | 640 | //The radio will auto-clear everything in the FIFO as long as CE remains high |
akashvibhute | 2:3bdf0d9bb71f | 641 | |
akashvibhute | 6:5cc7136648d1 | 642 | uint32_t timer = mainTimer.read_ms(); //Get the time that the payload transmission started |
akashvibhute | 2:3bdf0d9bb71f | 643 | |
akashvibhute | 6:5cc7136648d1 | 644 | while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or timeout |
akashvibhute | 2:3bdf0d9bb71f | 645 | |
akashvibhute | 6:5cc7136648d1 | 646 | if( get_status() & _BV(MAX_RT)){ //If MAX Retries have been reached |
akashvibhute | 6:5cc7136648d1 | 647 | reUseTX(); //Set re-transmit and clear the MAX_RT interrupt flag |
akashvibhute | 6:5cc7136648d1 | 648 | if(mainTimer.read_ms() - timer > timeout){ return 0; } //If this payload has exceeded the user-defined timeout, exit and return 0 |
akashvibhute | 6:5cc7136648d1 | 649 | } |
akashvibhute | 6:5cc7136648d1 | 650 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 651 | if(mainTimer.read_ms() - timer > (timeout+95) ){ |
akashvibhute | 6:5cc7136648d1 | 652 | errNotify(); |
akashvibhute | 6:5cc7136648d1 | 653 | #if defined (FAILURE_HANDLING) |
akashvibhute | 6:5cc7136648d1 | 654 | return 0; |
akashvibhute | 6:5cc7136648d1 | 655 | #endif |
akashvibhute | 6:5cc7136648d1 | 656 | } |
akashvibhute | 6:5cc7136648d1 | 657 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 658 | |
akashvibhute | 6:5cc7136648d1 | 659 | } |
akashvibhute | 2:3bdf0d9bb71f | 660 | |
akashvibhute | 6:5cc7136648d1 | 661 | //Start Writing |
akashvibhute | 6:5cc7136648d1 | 662 | startFastWrite(buf,len,0); //Write the payload if a buffer is clear |
akashvibhute | 6:5cc7136648d1 | 663 | |
akashvibhute | 6:5cc7136648d1 | 664 | return 1; //Return 1 to indicate successful transmission |
akashvibhute | 2:3bdf0d9bb71f | 665 | } |
akashvibhute | 2:3bdf0d9bb71f | 666 | |
akashvibhute | 2:3bdf0d9bb71f | 667 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 668 | |
akashvibhute | 6:5cc7136648d1 | 669 | void RF24::reUseTX(){ |
akashvibhute | 6:5cc7136648d1 | 670 | write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag |
akashvibhute | 6:5cc7136648d1 | 671 | spiTrans( REUSE_TX_PL ); |
akashvibhute | 6:5cc7136648d1 | 672 | ce(LOW); //Re-Transfer packet |
akashvibhute | 6:5cc7136648d1 | 673 | ce(HIGH); |
akashvibhute | 2:3bdf0d9bb71f | 674 | } |
akashvibhute | 2:3bdf0d9bb71f | 675 | |
akashvibhute | 2:3bdf0d9bb71f | 676 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 677 | |
akashvibhute | 2:3bdf0d9bb71f | 678 | bool RF24::writeFast( const void* buf, uint8_t len, const bool multicast ) |
akashvibhute | 0:bb74812ac6bb | 679 | { |
akashvibhute | 6:5cc7136648d1 | 680 | //Block until the FIFO is NOT full. |
akashvibhute | 6:5cc7136648d1 | 681 | //Keep track of the MAX retries and set auto-retry if seeing failures |
akashvibhute | 6:5cc7136648d1 | 682 | //Return 0 so the user can control the retrys and set a timer or failure counter if required |
akashvibhute | 6:5cc7136648d1 | 683 | //The radio will auto-clear everything in the FIFO as long as CE remains high |
akashvibhute | 2:3bdf0d9bb71f | 684 | |
akashvibhute | 6:5cc7136648d1 | 685 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 686 | uint32_t timer = mainTimer.read_ms(); |
akashvibhute | 6:5cc7136648d1 | 687 | #endif |
akashvibhute | 6:5cc7136648d1 | 688 | |
akashvibhute | 6:5cc7136648d1 | 689 | while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or fail |
akashvibhute | 2:3bdf0d9bb71f | 690 | |
akashvibhute | 6:5cc7136648d1 | 691 | if( get_status() & _BV(MAX_RT)){ |
akashvibhute | 6:5cc7136648d1 | 692 | //reUseTX(); //Set re-transmit |
akashvibhute | 6:5cc7136648d1 | 693 | write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag |
akashvibhute | 6:5cc7136648d1 | 694 | return 0; //Return 0. The previous payload has been retransmitted |
akashvibhute | 6:5cc7136648d1 | 695 | //From the user perspective, if you get a 0, just keep trying to send the same payload |
akashvibhute | 6:5cc7136648d1 | 696 | } |
akashvibhute | 6:5cc7136648d1 | 697 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 698 | if(mainTimer.read_ms() - timer > 95 ){ |
akashvibhute | 6:5cc7136648d1 | 699 | errNotify(); |
akashvibhute | 6:5cc7136648d1 | 700 | #if defined (FAILURE_HANDLING) |
akashvibhute | 6:5cc7136648d1 | 701 | return 0; |
akashvibhute | 6:5cc7136648d1 | 702 | #endif |
akashvibhute | 6:5cc7136648d1 | 703 | } |
akashvibhute | 6:5cc7136648d1 | 704 | #endif |
akashvibhute | 6:5cc7136648d1 | 705 | } |
akashvibhute | 6:5cc7136648d1 | 706 | //Start Writing |
akashvibhute | 6:5cc7136648d1 | 707 | startFastWrite(buf,len,multicast); |
akashvibhute | 2:3bdf0d9bb71f | 708 | |
akashvibhute | 6:5cc7136648d1 | 709 | return 1; |
akashvibhute | 2:3bdf0d9bb71f | 710 | } |
akashvibhute | 2:3bdf0d9bb71f | 711 | |
akashvibhute | 6:5cc7136648d1 | 712 | bool RF24::writeFast( const void* buf, uint8_t len ){ |
akashvibhute | 6:5cc7136648d1 | 713 | return writeFast(buf,len,0); |
akashvibhute | 2:3bdf0d9bb71f | 714 | } |
akashvibhute | 2:3bdf0d9bb71f | 715 | |
akashvibhute | 2:3bdf0d9bb71f | 716 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 717 | |
akashvibhute | 2:3bdf0d9bb71f | 718 | //Per the documentation, we want to set PTX Mode when not listening. Then all we do is write data and set CE high |
akashvibhute | 2:3bdf0d9bb71f | 719 | //In this mode, if we can keep the FIFO buffers loaded, packets will transmit immediately (no 130us delay) |
akashvibhute | 2:3bdf0d9bb71f | 720 | //Otherwise we enter Standby-II mode, which is still faster than standby mode |
akashvibhute | 2:3bdf0d9bb71f | 721 | //Also, we remove the need to keep writing the config register over and over and delaying for 150 us each time if sending a stream of data |
akashvibhute | 2:3bdf0d9bb71f | 722 | |
akashvibhute | 6:5cc7136648d1 | 723 | void RF24::startFastWrite( const void* buf, uint8_t len, const bool multicast, bool startTx){ //TMRh20 |
akashvibhute | 2:3bdf0d9bb71f | 724 | |
akashvibhute | 6:5cc7136648d1 | 725 | //write_payload( buf,len); |
akashvibhute | 6:5cc7136648d1 | 726 | write_payload( buf, len,multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ; |
akashvibhute | 6:5cc7136648d1 | 727 | if(startTx){ |
akashvibhute | 6:5cc7136648d1 | 728 | ce(HIGH); |
akashvibhute | 6:5cc7136648d1 | 729 | } |
akashvibhute | 6:5cc7136648d1 | 730 | |
akashvibhute | 2:3bdf0d9bb71f | 731 | } |
akashvibhute | 2:3bdf0d9bb71f | 732 | |
akashvibhute | 2:3bdf0d9bb71f | 733 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 734 | |
akashvibhute | 2:3bdf0d9bb71f | 735 | //Added the original startWrite back in so users can still use interrupts, ack payloads, etc |
akashvibhute | 2:3bdf0d9bb71f | 736 | //Allows the library to pass all tests |
akashvibhute | 6:5cc7136648d1 | 737 | void RF24::startWrite( const void* buf, uint8_t len, const bool multicast ){ |
akashvibhute | 2:3bdf0d9bb71f | 738 | |
akashvibhute | 6:5cc7136648d1 | 739 | // Send the payload |
akashvibhute | 2:3bdf0d9bb71f | 740 | |
akashvibhute | 6:5cc7136648d1 | 741 | //write_payload( buf, len ); |
akashvibhute | 6:5cc7136648d1 | 742 | write_payload( buf, len,multicast? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ; |
akashvibhute | 6:5cc7136648d1 | 743 | ce(HIGH); |
akashvibhute | 6:5cc7136648d1 | 744 | |
akashvibhute | 6:5cc7136648d1 | 745 | wait_us(10); |
akashvibhute | 6:5cc7136648d1 | 746 | |
akashvibhute | 6:5cc7136648d1 | 747 | ce(LOW); |
akashvibhute | 2:3bdf0d9bb71f | 748 | |
akashvibhute | 2:3bdf0d9bb71f | 749 | |
akashvibhute | 2:3bdf0d9bb71f | 750 | } |
akashvibhute | 2:3bdf0d9bb71f | 751 | |
akashvibhute | 2:3bdf0d9bb71f | 752 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 753 | |
akashvibhute | 6:5cc7136648d1 | 754 | bool RF24::rxFifoFull(){ |
akashvibhute | 6:5cc7136648d1 | 755 | return read_register(FIFO_STATUS) & _BV(RX_FULL); |
akashvibhute | 6:5cc7136648d1 | 756 | } |
akashvibhute | 6:5cc7136648d1 | 757 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 758 | |
akashvibhute | 6:5cc7136648d1 | 759 | bool RF24::txStandBy(){ |
akashvibhute | 6:5cc7136648d1 | 760 | |
akashvibhute | 6:5cc7136648d1 | 761 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 762 | uint32_t timeout = mainTimer.read_ms(); |
akashvibhute | 6:5cc7136648d1 | 763 | #endif |
akashvibhute | 6:5cc7136648d1 | 764 | while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){ |
akashvibhute | 6:5cc7136648d1 | 765 | if( get_status() & _BV(MAX_RT)){ |
akashvibhute | 6:5cc7136648d1 | 766 | write_register(NRF_STATUS,_BV(MAX_RT) ); |
akashvibhute | 6:5cc7136648d1 | 767 | ce(LOW); |
akashvibhute | 6:5cc7136648d1 | 768 | flush_tx(); //Non blocking, flush the data |
akashvibhute | 6:5cc7136648d1 | 769 | return 0; |
akashvibhute | 6:5cc7136648d1 | 770 | } |
akashvibhute | 6:5cc7136648d1 | 771 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 772 | if( mainTimer.read_ms() - timeout > 95){ |
akashvibhute | 6:5cc7136648d1 | 773 | errNotify(); |
akashvibhute | 6:5cc7136648d1 | 774 | #if defined (FAILURE_HANDLING) |
akashvibhute | 6:5cc7136648d1 | 775 | return 0; |
akashvibhute | 6:5cc7136648d1 | 776 | #endif |
akashvibhute | 6:5cc7136648d1 | 777 | } |
akashvibhute | 6:5cc7136648d1 | 778 | #endif |
akashvibhute | 6:5cc7136648d1 | 779 | } |
akashvibhute | 6:5cc7136648d1 | 780 | |
akashvibhute | 6:5cc7136648d1 | 781 | ce(LOW); //Set STANDBY-I mode |
akashvibhute | 6:5cc7136648d1 | 782 | return 1; |
akashvibhute | 6:5cc7136648d1 | 783 | } |
akashvibhute | 6:5cc7136648d1 | 784 | |
akashvibhute | 6:5cc7136648d1 | 785 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 786 | |
akashvibhute | 6:5cc7136648d1 | 787 | bool RF24::txStandBy(uint32_t timeout, bool startTx){ |
akashvibhute | 2:3bdf0d9bb71f | 788 | |
akashvibhute | 6:5cc7136648d1 | 789 | if(startTx){ |
akashvibhute | 6:5cc7136648d1 | 790 | stopListening(); |
akashvibhute | 6:5cc7136648d1 | 791 | ce(HIGH); |
akashvibhute | 6:5cc7136648d1 | 792 | } |
akashvibhute | 6:5cc7136648d1 | 793 | uint32_t start = mainTimer.read_ms(); |
akashvibhute | 6:5cc7136648d1 | 794 | |
akashvibhute | 6:5cc7136648d1 | 795 | while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){ |
akashvibhute | 6:5cc7136648d1 | 796 | if( get_status() & _BV(MAX_RT)){ |
akashvibhute | 6:5cc7136648d1 | 797 | write_register(NRF_STATUS,_BV(MAX_RT) ); |
akashvibhute | 6:5cc7136648d1 | 798 | ce(LOW); //Set re-transmit |
akashvibhute | 6:5cc7136648d1 | 799 | ce(HIGH); |
akashvibhute | 6:5cc7136648d1 | 800 | if(mainTimer.read_ms() - start >= timeout){ |
akashvibhute | 6:5cc7136648d1 | 801 | ce(LOW); flush_tx(); return 0; |
akashvibhute | 6:5cc7136648d1 | 802 | } |
akashvibhute | 6:5cc7136648d1 | 803 | } |
akashvibhute | 6:5cc7136648d1 | 804 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 805 | if( mainTimer.read_ms() - start > (timeout+95)){ |
akashvibhute | 6:5cc7136648d1 | 806 | errNotify(); |
akashvibhute | 6:5cc7136648d1 | 807 | #if defined (FAILURE_HANDLING) |
akashvibhute | 6:5cc7136648d1 | 808 | return 0; |
akashvibhute | 6:5cc7136648d1 | 809 | #endif |
akashvibhute | 6:5cc7136648d1 | 810 | } |
akashvibhute | 6:5cc7136648d1 | 811 | #endif |
akashvibhute | 6:5cc7136648d1 | 812 | } |
akashvibhute | 6:5cc7136648d1 | 813 | |
akashvibhute | 6:5cc7136648d1 | 814 | |
akashvibhute | 6:5cc7136648d1 | 815 | ce(LOW); //Set STANDBY-I mode |
akashvibhute | 6:5cc7136648d1 | 816 | return 1; |
akashvibhute | 6:5cc7136648d1 | 817 | |
akashvibhute | 6:5cc7136648d1 | 818 | } |
akashvibhute | 6:5cc7136648d1 | 819 | |
akashvibhute | 6:5cc7136648d1 | 820 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 821 | |
akashvibhute | 6:5cc7136648d1 | 822 | void RF24::maskIRQ(bool tx, bool fail, bool rx){ |
akashvibhute | 6:5cc7136648d1 | 823 | |
akashvibhute | 6:5cc7136648d1 | 824 | uint8_t config = read_register(NRF_CONFIG); |
akashvibhute | 6:5cc7136648d1 | 825 | /* clear the interrupt flags */ |
akashvibhute | 6:5cc7136648d1 | 826 | config &= ~(1 << MASK_MAX_RT | 1 << MASK_TX_DS | 1 << MASK_RX_DR); |
akashvibhute | 6:5cc7136648d1 | 827 | /* set the specified interrupt flags */ |
akashvibhute | 6:5cc7136648d1 | 828 | config |= fail << MASK_MAX_RT | tx << MASK_TX_DS | rx << MASK_RX_DR; |
akashvibhute | 6:5cc7136648d1 | 829 | write_register(NRF_CONFIG, config); |
akashvibhute | 0:bb74812ac6bb | 830 | } |
akashvibhute | 0:bb74812ac6bb | 831 | |
akashvibhute | 0:bb74812ac6bb | 832 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 833 | |
akashvibhute | 0:bb74812ac6bb | 834 | uint8_t RF24::getDynamicPayloadSize(void) |
akashvibhute | 0:bb74812ac6bb | 835 | { |
akashvibhute | 6:5cc7136648d1 | 836 | uint8_t result = 0; |
akashvibhute | 0:bb74812ac6bb | 837 | |
akashvibhute | 6:5cc7136648d1 | 838 | |
akashvibhute | 6:5cc7136648d1 | 839 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 840 | spi.write( R_RX_PL_WID ); |
akashvibhute | 6:5cc7136648d1 | 841 | result = spi.write(0xff); |
akashvibhute | 6:5cc7136648d1 | 842 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 843 | |
akashvibhute | 0:bb74812ac6bb | 844 | |
akashvibhute | 6:5cc7136648d1 | 845 | if(result > 32) { flush_rx(); wait_ms(2); return 0; } |
akashvibhute | 6:5cc7136648d1 | 846 | return result; |
akashvibhute | 0:bb74812ac6bb | 847 | } |
akashvibhute | 0:bb74812ac6bb | 848 | |
akashvibhute | 0:bb74812ac6bb | 849 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 850 | |
akashvibhute | 0:bb74812ac6bb | 851 | bool RF24::available(void) |
akashvibhute | 0:bb74812ac6bb | 852 | { |
akashvibhute | 6:5cc7136648d1 | 853 | return available(NULL); |
akashvibhute | 0:bb74812ac6bb | 854 | } |
akashvibhute | 0:bb74812ac6bb | 855 | |
akashvibhute | 0:bb74812ac6bb | 856 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 857 | |
akashvibhute | 0:bb74812ac6bb | 858 | bool RF24::available(uint8_t* pipe_num) |
akashvibhute | 0:bb74812ac6bb | 859 | { |
akashvibhute | 6:5cc7136648d1 | 860 | if (!( read_register(FIFO_STATUS) & _BV(RX_EMPTY) )){ |
akashvibhute | 0:bb74812ac6bb | 861 | |
akashvibhute | 6:5cc7136648d1 | 862 | // If the caller wants the pipe number, include that |
akashvibhute | 6:5cc7136648d1 | 863 | if ( pipe_num ){ |
akashvibhute | 6:5cc7136648d1 | 864 | uint8_t status = get_status(); |
akashvibhute | 6:5cc7136648d1 | 865 | *pipe_num = ( status >> RX_P_NO ) & 0b111; |
akashvibhute | 6:5cc7136648d1 | 866 | } |
akashvibhute | 6:5cc7136648d1 | 867 | return 1; |
akashvibhute | 6:5cc7136648d1 | 868 | } |
akashvibhute | 3:e94be00fd19e | 869 | |
akashvibhute | 6:5cc7136648d1 | 870 | |
akashvibhute | 6:5cc7136648d1 | 871 | return 0; |
akashvibhute | 6:5cc7136648d1 | 872 | |
akashvibhute | 6:5cc7136648d1 | 873 | |
akashvibhute | 0:bb74812ac6bb | 874 | } |
akashvibhute | 0:bb74812ac6bb | 875 | |
akashvibhute | 0:bb74812ac6bb | 876 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 877 | |
akashvibhute | 6:5cc7136648d1 | 878 | void RF24::read( void* buf, uint8_t len ){ |
akashvibhute | 2:3bdf0d9bb71f | 879 | |
akashvibhute | 6:5cc7136648d1 | 880 | // Fetch the payload |
akashvibhute | 6:5cc7136648d1 | 881 | read_payload( buf, len ); |
akashvibhute | 0:bb74812ac6bb | 882 | |
akashvibhute | 6:5cc7136648d1 | 883 | //Clear the two possible interrupt flags with one command |
akashvibhute | 6:5cc7136648d1 | 884 | write_register(NRF_STATUS,_BV(RX_DR) | _BV(MAX_RT) | _BV(TX_DS) ); |
akashvibhute | 6:5cc7136648d1 | 885 | |
akashvibhute | 0:bb74812ac6bb | 886 | } |
akashvibhute | 0:bb74812ac6bb | 887 | |
akashvibhute | 0:bb74812ac6bb | 888 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 889 | |
akashvibhute | 0:bb74812ac6bb | 890 | void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready) |
akashvibhute | 0:bb74812ac6bb | 891 | { |
akashvibhute | 6:5cc7136648d1 | 892 | // Read the status & reset the status in one easy call |
akashvibhute | 6:5cc7136648d1 | 893 | // Or is that such a good idea? |
akashvibhute | 6:5cc7136648d1 | 894 | uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); |
akashvibhute | 0:bb74812ac6bb | 895 | |
akashvibhute | 6:5cc7136648d1 | 896 | // Report to the user what happened |
akashvibhute | 6:5cc7136648d1 | 897 | tx_ok = status & _BV(TX_DS); |
akashvibhute | 6:5cc7136648d1 | 898 | tx_fail = status & _BV(MAX_RT); |
akashvibhute | 6:5cc7136648d1 | 899 | rx_ready = status & _BV(RX_DR); |
akashvibhute | 0:bb74812ac6bb | 900 | } |
akashvibhute | 0:bb74812ac6bb | 901 | |
akashvibhute | 0:bb74812ac6bb | 902 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 903 | |
akashvibhute | 0:bb74812ac6bb | 904 | void RF24::openWritingPipe(uint64_t value) |
akashvibhute | 0:bb74812ac6bb | 905 | { |
akashvibhute | 6:5cc7136648d1 | 906 | // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+) |
akashvibhute | 6:5cc7136648d1 | 907 | // expects it LSB first too, so we're good. |
akashvibhute | 0:bb74812ac6bb | 908 | |
akashvibhute | 6:5cc7136648d1 | 909 | write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width); |
akashvibhute | 6:5cc7136648d1 | 910 | write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width); |
akashvibhute | 6:5cc7136648d1 | 911 | |
akashvibhute | 6:5cc7136648d1 | 912 | |
akashvibhute | 6:5cc7136648d1 | 913 | //const uint8_t max_payload_size = 32; |
akashvibhute | 6:5cc7136648d1 | 914 | //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size)); |
akashvibhute | 6:5cc7136648d1 | 915 | write_register(RX_PW_P0,payload_size); |
akashvibhute | 0:bb74812ac6bb | 916 | } |
akashvibhute | 0:bb74812ac6bb | 917 | |
akashvibhute | 0:bb74812ac6bb | 918 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 919 | void RF24::openWritingPipe(const uint8_t *address) |
akashvibhute | 2:3bdf0d9bb71f | 920 | { |
akashvibhute | 6:5cc7136648d1 | 921 | // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+) |
akashvibhute | 6:5cc7136648d1 | 922 | // expects it LSB first too, so we're good. |
akashvibhute | 0:bb74812ac6bb | 923 | |
akashvibhute | 6:5cc7136648d1 | 924 | write_register(RX_ADDR_P0,address, addr_width); |
akashvibhute | 6:5cc7136648d1 | 925 | write_register(TX_ADDR, address, addr_width); |
akashvibhute | 2:3bdf0d9bb71f | 926 | |
akashvibhute | 6:5cc7136648d1 | 927 | //const uint8_t max_payload_size = 32; |
akashvibhute | 6:5cc7136648d1 | 928 | //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size)); |
akashvibhute | 6:5cc7136648d1 | 929 | write_register(RX_PW_P0,payload_size); |
akashvibhute | 2:3bdf0d9bb71f | 930 | } |
akashvibhute | 2:3bdf0d9bb71f | 931 | |
akashvibhute | 2:3bdf0d9bb71f | 932 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 933 | static const uint8_t child_pipe[] PROGMEM = |
akashvibhute | 6:5cc7136648d1 | 934 | { |
akashvibhute | 6:5cc7136648d1 | 935 | RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5 |
akashvibhute | 0:bb74812ac6bb | 936 | }; |
akashvibhute | 6:5cc7136648d1 | 937 | static const uint8_t child_payload_size[] PROGMEM = |
akashvibhute | 6:5cc7136648d1 | 938 | { |
akashvibhute | 6:5cc7136648d1 | 939 | RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5 |
akashvibhute | 0:bb74812ac6bb | 940 | }; |
akashvibhute | 2:3bdf0d9bb71f | 941 | |
akashvibhute | 0:bb74812ac6bb | 942 | |
akashvibhute | 0:bb74812ac6bb | 943 | void RF24::openReadingPipe(uint8_t child, uint64_t address) |
akashvibhute | 0:bb74812ac6bb | 944 | { |
akashvibhute | 6:5cc7136648d1 | 945 | // If this is pipe 0, cache the address. This is needed because |
akashvibhute | 6:5cc7136648d1 | 946 | // openWritingPipe() will overwrite the pipe 0 address, so |
akashvibhute | 6:5cc7136648d1 | 947 | // startListening() will have to restore it. |
akashvibhute | 6:5cc7136648d1 | 948 | if (child == 0){ |
akashvibhute | 6:5cc7136648d1 | 949 | memcpy(pipe0_reading_address,&address,addr_width); |
akashvibhute | 6:5cc7136648d1 | 950 | } |
akashvibhute | 0:bb74812ac6bb | 951 | |
akashvibhute | 6:5cc7136648d1 | 952 | if (child <= 6) |
akashvibhute | 6:5cc7136648d1 | 953 | { |
akashvibhute | 6:5cc7136648d1 | 954 | // For pipes 2-5, only write the LSB |
akashvibhute | 6:5cc7136648d1 | 955 | if ( child < 2 ) |
akashvibhute | 6:5cc7136648d1 | 956 | write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width); |
akashvibhute | 6:5cc7136648d1 | 957 | else |
akashvibhute | 6:5cc7136648d1 | 958 | write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1); |
akashvibhute | 0:bb74812ac6bb | 959 | |
akashvibhute | 6:5cc7136648d1 | 960 | write_register(pgm_read_byte(&child_payload_size[child]),payload_size); |
akashvibhute | 0:bb74812ac6bb | 961 | |
akashvibhute | 6:5cc7136648d1 | 962 | // Note it would be more efficient to set all of the bits for all open |
akashvibhute | 6:5cc7136648d1 | 963 | // pipes at once. However, I thought it would make the calling code |
akashvibhute | 6:5cc7136648d1 | 964 | // more simple to do it this way. |
akashvibhute | 6:5cc7136648d1 | 965 | write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child]))); |
akashvibhute | 6:5cc7136648d1 | 966 | } |
akashvibhute | 2:3bdf0d9bb71f | 967 | } |
akashvibhute | 2:3bdf0d9bb71f | 968 | |
akashvibhute | 2:3bdf0d9bb71f | 969 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 970 | void RF24::setAddressWidth(uint8_t a_width){ |
akashvibhute | 2:3bdf0d9bb71f | 971 | |
akashvibhute | 6:5cc7136648d1 | 972 | if(a_width -= 2){ |
akashvibhute | 6:5cc7136648d1 | 973 | write_register(SETUP_AW,a_width%4); |
akashvibhute | 6:5cc7136648d1 | 974 | addr_width = (a_width%4) + 2; |
akashvibhute | 6:5cc7136648d1 | 975 | } |
akashvibhute | 6:5cc7136648d1 | 976 | |
akashvibhute | 2:3bdf0d9bb71f | 977 | } |
akashvibhute | 2:3bdf0d9bb71f | 978 | |
akashvibhute | 2:3bdf0d9bb71f | 979 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 980 | |
akashvibhute | 2:3bdf0d9bb71f | 981 | void RF24::openReadingPipe(uint8_t child, const uint8_t *address) |
akashvibhute | 2:3bdf0d9bb71f | 982 | { |
akashvibhute | 6:5cc7136648d1 | 983 | // If this is pipe 0, cache the address. This is needed because |
akashvibhute | 6:5cc7136648d1 | 984 | // openWritingPipe() will overwrite the pipe 0 address, so |
akashvibhute | 6:5cc7136648d1 | 985 | // startListening() will have to restore it. |
akashvibhute | 6:5cc7136648d1 | 986 | if (child == 0){ |
akashvibhute | 6:5cc7136648d1 | 987 | memcpy(pipe0_reading_address,address,addr_width); |
akashvibhute | 6:5cc7136648d1 | 988 | } |
akashvibhute | 6:5cc7136648d1 | 989 | if (child <= 6) |
akashvibhute | 6:5cc7136648d1 | 990 | { |
akashvibhute | 6:5cc7136648d1 | 991 | // For pipes 2-5, only write the LSB |
akashvibhute | 6:5cc7136648d1 | 992 | if ( child < 2 ){ |
akashvibhute | 6:5cc7136648d1 | 993 | write_register(pgm_read_byte(&child_pipe[child]), address, addr_width); |
akashvibhute | 6:5cc7136648d1 | 994 | }else{ |
akashvibhute | 6:5cc7136648d1 | 995 | write_register(pgm_read_byte(&child_pipe[child]), address, 1); |
akashvibhute | 6:5cc7136648d1 | 996 | } |
akashvibhute | 6:5cc7136648d1 | 997 | write_register(pgm_read_byte(&child_payload_size[child]),payload_size); |
akashvibhute | 2:3bdf0d9bb71f | 998 | |
akashvibhute | 6:5cc7136648d1 | 999 | // Note it would be more efficient to set all of the bits for all open |
akashvibhute | 6:5cc7136648d1 | 1000 | // pipes at once. However, I thought it would make the calling code |
akashvibhute | 6:5cc7136648d1 | 1001 | // more simple to do it this way. |
akashvibhute | 6:5cc7136648d1 | 1002 | write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child]))); |
akashvibhute | 6:5cc7136648d1 | 1003 | |
akashvibhute | 6:5cc7136648d1 | 1004 | } |
akashvibhute | 2:3bdf0d9bb71f | 1005 | } |
akashvibhute | 2:3bdf0d9bb71f | 1006 | |
akashvibhute | 2:3bdf0d9bb71f | 1007 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 1008 | |
akashvibhute | 2:3bdf0d9bb71f | 1009 | void RF24::closeReadingPipe( uint8_t pipe ) |
akashvibhute | 2:3bdf0d9bb71f | 1010 | { |
akashvibhute | 6:5cc7136648d1 | 1011 | write_register(EN_RXADDR,read_register(EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe]))); |
akashvibhute | 0:bb74812ac6bb | 1012 | } |
akashvibhute | 0:bb74812ac6bb | 1013 | |
akashvibhute | 0:bb74812ac6bb | 1014 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1015 | |
akashvibhute | 0:bb74812ac6bb | 1016 | void RF24::toggle_features(void) |
akashvibhute | 0:bb74812ac6bb | 1017 | { |
akashvibhute | 2:3bdf0d9bb71f | 1018 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 1019 | spi.write( ACTIVATE ); |
akashvibhute | 2:3bdf0d9bb71f | 1020 | spi.write( 0x73 ); |
akashvibhute | 6:5cc7136648d1 | 1021 | endTransaction(); |
akashvibhute | 0:bb74812ac6bb | 1022 | } |
akashvibhute | 0:bb74812ac6bb | 1023 | |
akashvibhute | 0:bb74812ac6bb | 1024 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1025 | |
akashvibhute | 0:bb74812ac6bb | 1026 | void RF24::enableDynamicPayloads(void) |
akashvibhute | 0:bb74812ac6bb | 1027 | { |
akashvibhute | 6:5cc7136648d1 | 1028 | // Enable dynamic payload throughout the system |
akashvibhute | 0:bb74812ac6bb | 1029 | |
akashvibhute | 2:3bdf0d9bb71f | 1030 | //toggle_features(); |
akashvibhute | 0:bb74812ac6bb | 1031 | write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) ); |
akashvibhute | 2:3bdf0d9bb71f | 1032 | |
akashvibhute | 6:5cc7136648d1 | 1033 | |
akashvibhute | 6:5cc7136648d1 | 1034 | IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE))); |
akashvibhute | 0:bb74812ac6bb | 1035 | |
akashvibhute | 6:5cc7136648d1 | 1036 | // Enable dynamic payload on all pipes |
akashvibhute | 6:5cc7136648d1 | 1037 | // |
akashvibhute | 6:5cc7136648d1 | 1038 | // Not sure the use case of only having dynamic payload on certain |
akashvibhute | 6:5cc7136648d1 | 1039 | // pipes, so the library does not support it. |
akashvibhute | 6:5cc7136648d1 | 1040 | write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0)); |
akashvibhute | 0:bb74812ac6bb | 1041 | |
akashvibhute | 6:5cc7136648d1 | 1042 | dynamic_payloads_enabled = true; |
akashvibhute | 0:bb74812ac6bb | 1043 | } |
akashvibhute | 0:bb74812ac6bb | 1044 | |
akashvibhute | 0:bb74812ac6bb | 1045 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1046 | |
akashvibhute | 0:bb74812ac6bb | 1047 | void RF24::enableAckPayload(void) |
akashvibhute | 0:bb74812ac6bb | 1048 | { |
akashvibhute | 6:5cc7136648d1 | 1049 | // |
akashvibhute | 6:5cc7136648d1 | 1050 | // enable ack payload and dynamic payload features |
akashvibhute | 6:5cc7136648d1 | 1051 | // |
akashvibhute | 0:bb74812ac6bb | 1052 | |
akashvibhute | 2:3bdf0d9bb71f | 1053 | //toggle_features(); |
akashvibhute | 2:3bdf0d9bb71f | 1054 | write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) ); |
akashvibhute | 0:bb74812ac6bb | 1055 | |
akashvibhute | 6:5cc7136648d1 | 1056 | IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE))); |
akashvibhute | 0:bb74812ac6bb | 1057 | |
akashvibhute | 6:5cc7136648d1 | 1058 | // |
akashvibhute | 6:5cc7136648d1 | 1059 | // Enable dynamic payload on pipes 0 & 1 |
akashvibhute | 6:5cc7136648d1 | 1060 | // |
akashvibhute | 0:bb74812ac6bb | 1061 | |
akashvibhute | 6:5cc7136648d1 | 1062 | write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0)); |
akashvibhute | 6:5cc7136648d1 | 1063 | dynamic_payloads_enabled = true; |
akashvibhute | 2:3bdf0d9bb71f | 1064 | } |
akashvibhute | 2:3bdf0d9bb71f | 1065 | |
akashvibhute | 2:3bdf0d9bb71f | 1066 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 1067 | |
akashvibhute | 6:5cc7136648d1 | 1068 | void RF24::enableDynamicAck(void){ |
akashvibhute | 6:5cc7136648d1 | 1069 | // |
akashvibhute | 6:5cc7136648d1 | 1070 | // enable dynamic ack features |
akashvibhute | 6:5cc7136648d1 | 1071 | // |
akashvibhute | 2:3bdf0d9bb71f | 1072 | //toggle_features(); |
akashvibhute | 2:3bdf0d9bb71f | 1073 | write_register(FEATURE,read_register(FEATURE) | _BV(EN_DYN_ACK) ); |
akashvibhute | 2:3bdf0d9bb71f | 1074 | |
akashvibhute | 6:5cc7136648d1 | 1075 | IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE))); |
akashvibhute | 2:3bdf0d9bb71f | 1076 | |
akashvibhute | 2:3bdf0d9bb71f | 1077 | |
akashvibhute | 0:bb74812ac6bb | 1078 | } |
akashvibhute | 0:bb74812ac6bb | 1079 | |
akashvibhute | 0:bb74812ac6bb | 1080 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1081 | |
akashvibhute | 0:bb74812ac6bb | 1082 | void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len) |
akashvibhute | 0:bb74812ac6bb | 1083 | { |
akashvibhute | 6:5cc7136648d1 | 1084 | const uint8_t* current = reinterpret_cast<const uint8_t*>(buf); |
akashvibhute | 0:bb74812ac6bb | 1085 | |
akashvibhute | 6:5cc7136648d1 | 1086 | uint8_t data_len = rf24_min(len,32); |
akashvibhute | 2:3bdf0d9bb71f | 1087 | |
adam_z | 8:6827b6f0283b | 1088 | |
akashvibhute | 6:5cc7136648d1 | 1089 | |
akashvibhute | 6:5cc7136648d1 | 1090 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 1091 | spi.write(W_ACK_PAYLOAD | ( pipe & 0b111 ) ); |
akashvibhute | 2:3bdf0d9bb71f | 1092 | |
akashvibhute | 6:5cc7136648d1 | 1093 | while ( data_len-- ) |
akashvibhute | 6:5cc7136648d1 | 1094 | spi.write(*current++); |
akashvibhute | 6:5cc7136648d1 | 1095 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 1096 | |
akashvibhute | 6:5cc7136648d1 | 1097 | |
akashvibhute | 0:bb74812ac6bb | 1098 | |
akashvibhute | 0:bb74812ac6bb | 1099 | } |
akashvibhute | 0:bb74812ac6bb | 1100 | |
akashvibhute | 0:bb74812ac6bb | 1101 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1102 | |
akashvibhute | 0:bb74812ac6bb | 1103 | bool RF24::isAckPayloadAvailable(void) |
akashvibhute | 0:bb74812ac6bb | 1104 | { |
akashvibhute | 6:5cc7136648d1 | 1105 | return ! (read_register(FIFO_STATUS) & _BV(RX_EMPTY)); |
akashvibhute | 0:bb74812ac6bb | 1106 | } |
akashvibhute | 0:bb74812ac6bb | 1107 | |
akashvibhute | 0:bb74812ac6bb | 1108 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1109 | |
akashvibhute | 0:bb74812ac6bb | 1110 | bool RF24::isPVariant(void) |
akashvibhute | 0:bb74812ac6bb | 1111 | { |
akashvibhute | 6:5cc7136648d1 | 1112 | return p_variant ; |
akashvibhute | 0:bb74812ac6bb | 1113 | } |
akashvibhute | 0:bb74812ac6bb | 1114 | |
akashvibhute | 0:bb74812ac6bb | 1115 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1116 | |
akashvibhute | 0:bb74812ac6bb | 1117 | void RF24::setAutoAck(bool enable) |
akashvibhute | 0:bb74812ac6bb | 1118 | { |
akashvibhute | 6:5cc7136648d1 | 1119 | if ( enable ) |
akashvibhute | 6:5cc7136648d1 | 1120 | write_register(EN_AA, 0b111111); |
akashvibhute | 6:5cc7136648d1 | 1121 | else |
akashvibhute | 6:5cc7136648d1 | 1122 | write_register(EN_AA, 0); |
akashvibhute | 0:bb74812ac6bb | 1123 | } |
akashvibhute | 0:bb74812ac6bb | 1124 | |
akashvibhute | 0:bb74812ac6bb | 1125 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1126 | |
akashvibhute | 0:bb74812ac6bb | 1127 | void RF24::setAutoAck( uint8_t pipe, bool enable ) |
akashvibhute | 0:bb74812ac6bb | 1128 | { |
akashvibhute | 6:5cc7136648d1 | 1129 | if ( pipe <= 6 ) |
akashvibhute | 6:5cc7136648d1 | 1130 | { |
akashvibhute | 6:5cc7136648d1 | 1131 | uint8_t en_aa = read_register( EN_AA ) ; |
akashvibhute | 6:5cc7136648d1 | 1132 | if( enable ) |
akashvibhute | 6:5cc7136648d1 | 1133 | { |
akashvibhute | 6:5cc7136648d1 | 1134 | en_aa |= _BV(pipe) ; |
akashvibhute | 0:bb74812ac6bb | 1135 | } |
akashvibhute | 6:5cc7136648d1 | 1136 | else |
akashvibhute | 6:5cc7136648d1 | 1137 | { |
akashvibhute | 6:5cc7136648d1 | 1138 | en_aa &= ~_BV(pipe) ; |
akashvibhute | 6:5cc7136648d1 | 1139 | } |
akashvibhute | 6:5cc7136648d1 | 1140 | write_register( EN_AA, en_aa ) ; |
akashvibhute | 6:5cc7136648d1 | 1141 | } |
akashvibhute | 0:bb74812ac6bb | 1142 | } |
akashvibhute | 0:bb74812ac6bb | 1143 | |
akashvibhute | 0:bb74812ac6bb | 1144 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1145 | |
akashvibhute | 0:bb74812ac6bb | 1146 | bool RF24::testCarrier(void) |
akashvibhute | 0:bb74812ac6bb | 1147 | { |
akashvibhute | 6:5cc7136648d1 | 1148 | return ( read_register(CD) & 1 ); |
akashvibhute | 0:bb74812ac6bb | 1149 | } |
akashvibhute | 0:bb74812ac6bb | 1150 | |
akashvibhute | 0:bb74812ac6bb | 1151 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1152 | |
akashvibhute | 0:bb74812ac6bb | 1153 | bool RF24::testRPD(void) |
akashvibhute | 0:bb74812ac6bb | 1154 | { |
akashvibhute | 6:5cc7136648d1 | 1155 | return ( read_register(RPD) & 1 ) ; |
akashvibhute | 0:bb74812ac6bb | 1156 | } |
akashvibhute | 0:bb74812ac6bb | 1157 | |
akashvibhute | 0:bb74812ac6bb | 1158 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1159 | |
akashvibhute | 2:3bdf0d9bb71f | 1160 | void RF24::setPALevel(uint8_t level) |
akashvibhute | 0:bb74812ac6bb | 1161 | { |
akashvibhute | 2:3bdf0d9bb71f | 1162 | |
akashvibhute | 6:5cc7136648d1 | 1163 | uint8_t setup = read_register(RF_SETUP) & 0b11111000; |
akashvibhute | 0:bb74812ac6bb | 1164 | |
akashvibhute | 6:5cc7136648d1 | 1165 | if(level > 3){ // If invalid level, go to max PA |
akashvibhute | 6:5cc7136648d1 | 1166 | level = (RF24_PA_MAX << 1) + 1; // +1 to support the SI24R1 chip extra bit |
akashvibhute | 6:5cc7136648d1 | 1167 | }else{ |
akashvibhute | 6:5cc7136648d1 | 1168 | level = (level << 1) + 1; // Else set level as requested |
akashvibhute | 6:5cc7136648d1 | 1169 | } |
akashvibhute | 0:bb74812ac6bb | 1170 | |
akashvibhute | 2:3bdf0d9bb71f | 1171 | |
akashvibhute | 6:5cc7136648d1 | 1172 | write_register( RF_SETUP, setup |= level ) ; // Write it to the chip |
akashvibhute | 0:bb74812ac6bb | 1173 | } |
akashvibhute | 0:bb74812ac6bb | 1174 | |
akashvibhute | 0:bb74812ac6bb | 1175 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1176 | |
akashvibhute | 2:3bdf0d9bb71f | 1177 | uint8_t RF24::getPALevel(void) |
akashvibhute | 0:bb74812ac6bb | 1178 | { |
akashvibhute | 0:bb74812ac6bb | 1179 | |
akashvibhute | 6:5cc7136648d1 | 1180 | return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH))) >> 1 ; |
akashvibhute | 0:bb74812ac6bb | 1181 | } |
akashvibhute | 0:bb74812ac6bb | 1182 | |
akashvibhute | 0:bb74812ac6bb | 1183 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1184 | |
akashvibhute | 0:bb74812ac6bb | 1185 | bool RF24::setDataRate(rf24_datarate_e speed) |
akashvibhute | 0:bb74812ac6bb | 1186 | { |
akashvibhute | 6:5cc7136648d1 | 1187 | bool result = false; |
akashvibhute | 6:5cc7136648d1 | 1188 | uint8_t setup = read_register(RF_SETUP) ; |
akashvibhute | 0:bb74812ac6bb | 1189 | |
akashvibhute | 6:5cc7136648d1 | 1190 | // HIGH and LOW '00' is 1Mbs - our default |
akashvibhute | 6:5cc7136648d1 | 1191 | setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ; |
akashvibhute | 6:5cc7136648d1 | 1192 | |
akashvibhute | 6:5cc7136648d1 | 1193 | |
akashvibhute | 6:5cc7136648d1 | 1194 | |
akashvibhute | 6:5cc7136648d1 | 1195 | |
akashvibhute | 2:3bdf0d9bb71f | 1196 | txRxDelay=85; |
akashvibhute | 2:3bdf0d9bb71f | 1197 | |
akashvibhute | 6:5cc7136648d1 | 1198 | if( speed == RF24_250KBPS ) |
akashvibhute | 6:5cc7136648d1 | 1199 | { |
akashvibhute | 6:5cc7136648d1 | 1200 | // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0 |
akashvibhute | 6:5cc7136648d1 | 1201 | // Making it '10'. |
akashvibhute | 6:5cc7136648d1 | 1202 | setup |= _BV( RF_DR_LOW ) ; |
akashvibhute | 6:5cc7136648d1 | 1203 | |
akashvibhute | 6:5cc7136648d1 | 1204 | |
akashvibhute | 6:5cc7136648d1 | 1205 | |
akashvibhute | 6:5cc7136648d1 | 1206 | txRxDelay=155; |
akashvibhute | 6:5cc7136648d1 | 1207 | |
akashvibhute | 6:5cc7136648d1 | 1208 | } |
akashvibhute | 6:5cc7136648d1 | 1209 | else |
akashvibhute | 6:5cc7136648d1 | 1210 | { |
akashvibhute | 6:5cc7136648d1 | 1211 | // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1 |
akashvibhute | 6:5cc7136648d1 | 1212 | // Making it '01' |
akashvibhute | 6:5cc7136648d1 | 1213 | if ( speed == RF24_2MBPS ) |
akashvibhute | 6:5cc7136648d1 | 1214 | { |
akashvibhute | 6:5cc7136648d1 | 1215 | setup |= _BV(RF_DR_HIGH); |
akashvibhute | 6:5cc7136648d1 | 1216 | |
akashvibhute | 6:5cc7136648d1 | 1217 | |
akashvibhute | 6:5cc7136648d1 | 1218 | //txRxDelay=65; |
akashvibhute | 6:5cc7136648d1 | 1219 | txRxDelay=15; //mbed works fine with this latency |
akashvibhute | 6:5cc7136648d1 | 1220 | |
akashvibhute | 0:bb74812ac6bb | 1221 | } |
akashvibhute | 6:5cc7136648d1 | 1222 | } |
akashvibhute | 6:5cc7136648d1 | 1223 | write_register(RF_SETUP,setup); |
akashvibhute | 0:bb74812ac6bb | 1224 | |
akashvibhute | 6:5cc7136648d1 | 1225 | // Verify our result |
akashvibhute | 6:5cc7136648d1 | 1226 | if ( read_register(RF_SETUP) == setup ) |
akashvibhute | 6:5cc7136648d1 | 1227 | { |
akashvibhute | 6:5cc7136648d1 | 1228 | result = true; |
akashvibhute | 6:5cc7136648d1 | 1229 | } |
akashvibhute | 6:5cc7136648d1 | 1230 | return result; |
akashvibhute | 0:bb74812ac6bb | 1231 | } |
akashvibhute | 0:bb74812ac6bb | 1232 | |
akashvibhute | 0:bb74812ac6bb | 1233 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1234 | |
akashvibhute | 0:bb74812ac6bb | 1235 | rf24_datarate_e RF24::getDataRate( void ) |
akashvibhute | 0:bb74812ac6bb | 1236 | { |
akashvibhute | 6:5cc7136648d1 | 1237 | rf24_datarate_e result ; |
akashvibhute | 6:5cc7136648d1 | 1238 | uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)); |
akashvibhute | 2:3bdf0d9bb71f | 1239 | |
akashvibhute | 6:5cc7136648d1 | 1240 | // switch uses RAM (evil!) |
akashvibhute | 6:5cc7136648d1 | 1241 | // Order matters in our case below |
akashvibhute | 6:5cc7136648d1 | 1242 | if ( dr == _BV(RF_DR_LOW) ) |
akashvibhute | 6:5cc7136648d1 | 1243 | { |
akashvibhute | 6:5cc7136648d1 | 1244 | // '10' = 250KBPS |
akashvibhute | 6:5cc7136648d1 | 1245 | result = RF24_250KBPS ; |
akashvibhute | 6:5cc7136648d1 | 1246 | } |
akashvibhute | 6:5cc7136648d1 | 1247 | else if ( dr == _BV(RF_DR_HIGH) ) |
akashvibhute | 6:5cc7136648d1 | 1248 | { |
akashvibhute | 6:5cc7136648d1 | 1249 | // '01' = 2MBPS |
akashvibhute | 6:5cc7136648d1 | 1250 | result = RF24_2MBPS ; |
akashvibhute | 6:5cc7136648d1 | 1251 | } |
akashvibhute | 6:5cc7136648d1 | 1252 | else |
akashvibhute | 6:5cc7136648d1 | 1253 | { |
akashvibhute | 6:5cc7136648d1 | 1254 | // '00' = 1MBPS |
akashvibhute | 6:5cc7136648d1 | 1255 | result = RF24_1MBPS ; |
akashvibhute | 6:5cc7136648d1 | 1256 | } |
akashvibhute | 6:5cc7136648d1 | 1257 | return result ; |
akashvibhute | 0:bb74812ac6bb | 1258 | } |
akashvibhute | 0:bb74812ac6bb | 1259 | |
akashvibhute | 0:bb74812ac6bb | 1260 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1261 | |
akashvibhute | 0:bb74812ac6bb | 1262 | void RF24::setCRCLength(rf24_crclength_e length) |
akashvibhute | 0:bb74812ac6bb | 1263 | { |
akashvibhute | 6:5cc7136648d1 | 1264 | uint8_t config = read_register(NRF_CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ; |
akashvibhute | 2:3bdf0d9bb71f | 1265 | |
akashvibhute | 6:5cc7136648d1 | 1266 | // switch uses RAM (evil!) |
akashvibhute | 6:5cc7136648d1 | 1267 | if ( length == RF24_CRC_DISABLED ) |
akashvibhute | 6:5cc7136648d1 | 1268 | { |
akashvibhute | 6:5cc7136648d1 | 1269 | // Do nothing, we turned it off above. |
akashvibhute | 6:5cc7136648d1 | 1270 | } |
akashvibhute | 6:5cc7136648d1 | 1271 | else if ( length == RF24_CRC_8 ) |
akashvibhute | 6:5cc7136648d1 | 1272 | { |
akashvibhute | 6:5cc7136648d1 | 1273 | config |= _BV(EN_CRC); |
akashvibhute | 6:5cc7136648d1 | 1274 | } |
akashvibhute | 6:5cc7136648d1 | 1275 | else |
akashvibhute | 6:5cc7136648d1 | 1276 | { |
akashvibhute | 6:5cc7136648d1 | 1277 | config |= _BV(EN_CRC); |
akashvibhute | 6:5cc7136648d1 | 1278 | config |= _BV( CRCO ); |
akashvibhute | 6:5cc7136648d1 | 1279 | } |
akashvibhute | 6:5cc7136648d1 | 1280 | write_register( NRF_CONFIG, config ) ; |
akashvibhute | 0:bb74812ac6bb | 1281 | } |
akashvibhute | 0:bb74812ac6bb | 1282 | |
akashvibhute | 0:bb74812ac6bb | 1283 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1284 | |
akashvibhute | 0:bb74812ac6bb | 1285 | rf24_crclength_e RF24::getCRCLength(void) |
akashvibhute | 0:bb74812ac6bb | 1286 | { |
akashvibhute | 6:5cc7136648d1 | 1287 | rf24_crclength_e result = RF24_CRC_DISABLED; |
akashvibhute | 6:5cc7136648d1 | 1288 | |
akashvibhute | 6:5cc7136648d1 | 1289 | uint8_t config = read_register(NRF_CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ; |
akashvibhute | 6:5cc7136648d1 | 1290 | uint8_t AA = read_register(EN_AA); |
akashvibhute | 6:5cc7136648d1 | 1291 | |
akashvibhute | 6:5cc7136648d1 | 1292 | if ( config & _BV(EN_CRC ) || AA) |
akashvibhute | 6:5cc7136648d1 | 1293 | { |
akashvibhute | 6:5cc7136648d1 | 1294 | if ( config & _BV(CRCO) ) |
akashvibhute | 6:5cc7136648d1 | 1295 | result = RF24_CRC_16; |
akashvibhute | 6:5cc7136648d1 | 1296 | else |
akashvibhute | 6:5cc7136648d1 | 1297 | result = RF24_CRC_8; |
akashvibhute | 6:5cc7136648d1 | 1298 | } |
akashvibhute | 0:bb74812ac6bb | 1299 | |
akashvibhute | 6:5cc7136648d1 | 1300 | return result; |
akashvibhute | 0:bb74812ac6bb | 1301 | } |
akashvibhute | 0:bb74812ac6bb | 1302 | |
akashvibhute | 0:bb74812ac6bb | 1303 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1304 | |
akashvibhute | 0:bb74812ac6bb | 1305 | void RF24::disableCRC( void ) |
akashvibhute | 0:bb74812ac6bb | 1306 | { |
akashvibhute | 6:5cc7136648d1 | 1307 | uint8_t disable = read_register(NRF_CONFIG) & ~_BV(EN_CRC) ; |
akashvibhute | 6:5cc7136648d1 | 1308 | write_register( NRF_CONFIG, disable ) ; |
akashvibhute | 0:bb74812ac6bb | 1309 | } |
akashvibhute | 0:bb74812ac6bb | 1310 | |
akashvibhute | 0:bb74812ac6bb | 1311 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1312 | void RF24::setRetries(uint8_t delay, uint8_t count) |
akashvibhute | 0:bb74812ac6bb | 1313 | { |
akashvibhute | 6:5cc7136648d1 | 1314 | write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC); |
akashvibhute | 0:bb74812ac6bb | 1315 | } |
akashvibhute | 6:5cc7136648d1 | 1316 |