MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/dma_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /***************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file dma_api.c
sahilmgandhi 18:6a4db94011d3 3 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 4 * @section License
sahilmgandhi 18:6a4db94011d3 5 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
sahilmgandhi 18:6a4db94011d3 6 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * SPDX-License-Identifier: Apache-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Licensed under the Apache License, Version 2.0 (the "License"); you may
sahilmgandhi 18:6a4db94011d3 11 * not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 12 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 17 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
sahilmgandhi 18:6a4db94011d3 18 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 19 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 20 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 25 #include "dma_api_HAL.h"
sahilmgandhi 18:6a4db94011d3 26 #include "em_device.h"
sahilmgandhi 18:6a4db94011d3 27 #include "em_cmu.h"
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 #ifdef DMA_PRESENT
sahilmgandhi 18:6a4db94011d3 30 #include "em_dma.h"
sahilmgandhi 18:6a4db94011d3 31 #endif
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 #ifdef LDMA_PRESENT
sahilmgandhi 18:6a4db94011d3 34 #include "em_ldma.h"
sahilmgandhi 18:6a4db94011d3 35 #endif
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 /** DMA control block array, requires proper alignment. */
sahilmgandhi 18:6a4db94011d3 38 #ifdef DMA_PRESENT
sahilmgandhi 18:6a4db94011d3 39 #if defined (__ICCARM__)
sahilmgandhi 18:6a4db94011d3 40 #pragma data_alignment=DMACTRL_ALIGNMENT
sahilmgandhi 18:6a4db94011d3 41 DMA_DESCRIPTOR_TypeDef dmaControlBlock[DMACTRL_CH_CNT * 2];
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 #elif defined (__CC_ARM)
sahilmgandhi 18:6a4db94011d3 44 DMA_DESCRIPTOR_TypeDef dmaControlBlock[DMACTRL_CH_CNT * 2] __attribute__ ((aligned(DMACTRL_ALIGNMENT)));
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 #elif defined (__GNUC__)
sahilmgandhi 18:6a4db94011d3 47 DMA_DESCRIPTOR_TypeDef dmaControlBlock[DMACTRL_CH_CNT * 2] __attribute__ ((aligned(DMACTRL_ALIGNMENT), section("dma")));
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 #else
sahilmgandhi 18:6a4db94011d3 50 #error Undefined toolkit, need to define alignment
sahilmgandhi 18:6a4db94011d3 51 #endif
sahilmgandhi 18:6a4db94011d3 52 #endif /* DMA_PRESENT */
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 uint32_t channels = 0; // Bit vector of taken channels
sahilmgandhi 18:6a4db94011d3 55 bool enabled = false;
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 void dma_init(void)
sahilmgandhi 18:6a4db94011d3 58 {
sahilmgandhi 18:6a4db94011d3 59 if (enabled) return;
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 #if defined DMA_PRESENT
sahilmgandhi 18:6a4db94011d3 62 CMU_ClockEnable(cmuClock_DMA, true);
sahilmgandhi 18:6a4db94011d3 63 CMU_ClockEnable(cmuClock_HFPER, true); // FIXME: DMA is clocked via HFCORECLK, why HFPERCLK?
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 DMA_Init_TypeDef dmaInit;
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 dmaInit.hprot = 0;
sahilmgandhi 18:6a4db94011d3 68 dmaInit.controlBlock = dmaControlBlock;
sahilmgandhi 18:6a4db94011d3 69 DMA_Init(&dmaInit);
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 #elif defined LDMA_PRESENT
sahilmgandhi 18:6a4db94011d3 72 CMU_ClockEnable(cmuClock_LDMA, true);
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 LDMA_Init_t ldmaInit;
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 ldmaInit.ldmaInitCtrlNumFixed = 0; /* All channels round-robin */
sahilmgandhi 18:6a4db94011d3 77 ldmaInit.ldmaInitCtrlSyncPrsClrEn = 0; /* Do not allow PRS to clear SYNCTRIG */
sahilmgandhi 18:6a4db94011d3 78 ldmaInit.ldmaInitCtrlSyncPrsSetEn = 0; /* Do not allow PRS to set SYNCTRIG */
sahilmgandhi 18:6a4db94011d3 79 ldmaInit.ldmaInitIrqPriority = 2; /* IRQ Priority */
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 LDMA_Init(&ldmaInit);
sahilmgandhi 18:6a4db94011d3 82 #else
sahilmgandhi 18:6a4db94011d3 83 #error "Unrecognized DMA peripheral"
sahilmgandhi 18:6a4db94011d3 84 #endif
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 enabled = true;
sahilmgandhi 18:6a4db94011d3 87 }
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 int dma_channel_allocate(uint32_t capabilities)
sahilmgandhi 18:6a4db94011d3 90 {
sahilmgandhi 18:6a4db94011d3 91 int i;
sahilmgandhi 18:6a4db94011d3 92 // Check if 2d copy is required
sahilmgandhi 18:6a4db94011d3 93 if (DMA_CAP_2DCOPY & capabilities) {
sahilmgandhi 18:6a4db94011d3 94 if (channels & 1) {
sahilmgandhi 18:6a4db94011d3 95 // Channel already in use
sahilmgandhi 18:6a4db94011d3 96 return DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 97 } else {
sahilmgandhi 18:6a4db94011d3 98 channels |= 1 << 0;
sahilmgandhi 18:6a4db94011d3 99 return 0;
sahilmgandhi 18:6a4db94011d3 100 }
sahilmgandhi 18:6a4db94011d3 101 }
sahilmgandhi 18:6a4db94011d3 102 for (i = 1; i < DMA_CHAN_COUNT; i++) {
sahilmgandhi 18:6a4db94011d3 103 if ((channels & (1 << i)) == 0) {
sahilmgandhi 18:6a4db94011d3 104 // Channel available
sahilmgandhi 18:6a4db94011d3 105 channels |= 1 << i;
sahilmgandhi 18:6a4db94011d3 106 return i;
sahilmgandhi 18:6a4db94011d3 107 }
sahilmgandhi 18:6a4db94011d3 108 }
sahilmgandhi 18:6a4db94011d3 109 // Check if channel 0 is available
sahilmgandhi 18:6a4db94011d3 110 if ((channels & 1 ) == 0) {
sahilmgandhi 18:6a4db94011d3 111 channels |= 1 << 0;
sahilmgandhi 18:6a4db94011d3 112 return 0;
sahilmgandhi 18:6a4db94011d3 113 }
sahilmgandhi 18:6a4db94011d3 114 // Couldn't find a channel.
sahilmgandhi 18:6a4db94011d3 115 return DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 116 }
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 int dma_channel_free(int channelid)
sahilmgandhi 18:6a4db94011d3 119 {
sahilmgandhi 18:6a4db94011d3 120 if( channelid >= 0 ) {
sahilmgandhi 18:6a4db94011d3 121 channels &= ~(1 << channelid);
sahilmgandhi 18:6a4db94011d3 122 }
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 return 0;
sahilmgandhi 18:6a4db94011d3 125 }
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 #ifdef LDMA_PRESENT
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 /* LDMA emlib API extensions */
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 typedef struct {
sahilmgandhi 18:6a4db94011d3 132 LDMAx_CBFunc_t callback;
sahilmgandhi 18:6a4db94011d3 133 void *userdata;
sahilmgandhi 18:6a4db94011d3 134 } LDMA_InternCallback_t;
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 static LDMA_InternCallback_t ldmaCallback[DMA_CHAN_COUNT];
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 void LDMAx_StartTransfer( int ch,
sahilmgandhi 18:6a4db94011d3 139 LDMA_TransferCfg_t *transfer,
sahilmgandhi 18:6a4db94011d3 140 LDMA_Descriptor_t *descriptor,
sahilmgandhi 18:6a4db94011d3 141 LDMAx_CBFunc_t cbFunc,
sahilmgandhi 18:6a4db94011d3 142 void *userData )
sahilmgandhi 18:6a4db94011d3 143 {
sahilmgandhi 18:6a4db94011d3 144 ldmaCallback[ch].callback = cbFunc;
sahilmgandhi 18:6a4db94011d3 145 ldmaCallback[ch].userdata = userData;
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 LDMA_StartTransfer(ch, transfer, descriptor);
sahilmgandhi 18:6a4db94011d3 148 }
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150 void LDMA_IRQHandler( void )
sahilmgandhi 18:6a4db94011d3 151 {
sahilmgandhi 18:6a4db94011d3 152 uint32_t pending, chnum, chmask;
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 /* Get all pending and enabled interrupts */
sahilmgandhi 18:6a4db94011d3 155 pending = LDMA->IF;
sahilmgandhi 18:6a4db94011d3 156 pending &= LDMA->IEN;
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 /* Check for LDMA error */
sahilmgandhi 18:6a4db94011d3 159 if ( pending & LDMA_IF_ERROR )
sahilmgandhi 18:6a4db94011d3 160 {
sahilmgandhi 18:6a4db94011d3 161 /* Loop here to enable the debugger to see what has happened */
sahilmgandhi 18:6a4db94011d3 162 while (1)
sahilmgandhi 18:6a4db94011d3 163 ;
sahilmgandhi 18:6a4db94011d3 164 }
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 /* Iterate over all LDMA channels. */
sahilmgandhi 18:6a4db94011d3 167 for ( chnum = 0, chmask = 1;
sahilmgandhi 18:6a4db94011d3 168 chnum < DMA_CHAN_COUNT;
sahilmgandhi 18:6a4db94011d3 169 chnum++, chmask <<= 1 )
sahilmgandhi 18:6a4db94011d3 170 {
sahilmgandhi 18:6a4db94011d3 171 if ( pending & chmask )
sahilmgandhi 18:6a4db94011d3 172 {
sahilmgandhi 18:6a4db94011d3 173 /* Clear interrupt flag. */
sahilmgandhi 18:6a4db94011d3 174 LDMA->IFC = chmask;
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 /* Do more stuff here, execute callbacks etc. */
sahilmgandhi 18:6a4db94011d3 177 if ( ldmaCallback[chnum].callback )
sahilmgandhi 18:6a4db94011d3 178 {
sahilmgandhi 18:6a4db94011d3 179 ldmaCallback[chnum].callback(chnum, false, ldmaCallback[chnum].userdata);
sahilmgandhi 18:6a4db94011d3 180 }
sahilmgandhi 18:6a4db94011d3 181 }
sahilmgandhi 18:6a4db94011d3 182 }
sahilmgandhi 18:6a4db94011d3 183 }
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 /***************************************************************************//**
sahilmgandhi 18:6a4db94011d3 186 * @brief
sahilmgandhi 18:6a4db94011d3 187 * Check if LDMA channel is enabled.
sahilmgandhi 18:6a4db94011d3 188 *
sahilmgandhi 18:6a4db94011d3 189 * @param[in] ch
sahilmgandhi 18:6a4db94011d3 190 * LDMA channel to check.
sahilmgandhi 18:6a4db94011d3 191 *
sahilmgandhi 18:6a4db94011d3 192 * @return
sahilmgandhi 18:6a4db94011d3 193 * true if channel is enabled, false if not.
sahilmgandhi 18:6a4db94011d3 194 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 195 bool LDMAx_ChannelEnabled( int ch )
sahilmgandhi 18:6a4db94011d3 196 {
sahilmgandhi 18:6a4db94011d3 197 EFM_ASSERT(ch < DMA_CHAN_COUNT);
sahilmgandhi 18:6a4db94011d3 198 uint32_t chMask = 1 << ch;
sahilmgandhi 18:6a4db94011d3 199 return (bool)(LDMA->CHEN & chMask);
sahilmgandhi 18:6a4db94011d3 200 }
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 #endif /* LDMA_PRESENT */