MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file efr32mg1p_wdog.h
sahilmgandhi 18:6a4db94011d3 3 * @brief EFR32MG1P_WDOG register and bit field definitions
sahilmgandhi 18:6a4db94011d3 4 * @version 5.1.2
sahilmgandhi 18:6a4db94011d3 5 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 6 * @section License
sahilmgandhi 18:6a4db94011d3 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Permission is granted to anyone to use this software for any purpose,
sahilmgandhi 18:6a4db94011d3 11 * including commercial applications, and to alter it and redistribute it
sahilmgandhi 18:6a4db94011d3 12 * freely, subject to the following restrictions:
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * 1. The origin of this software must not be misrepresented; you must not
sahilmgandhi 18:6a4db94011d3 15 * claim that you wrote the original software.@n
sahilmgandhi 18:6a4db94011d3 16 * 2. Altered source versions must be plainly marked as such, and must not be
sahilmgandhi 18:6a4db94011d3 17 * misrepresented as being the original software.@n
sahilmgandhi 18:6a4db94011d3 18 * 3. This notice may not be removed or altered from any source distribution.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
sahilmgandhi 18:6a4db94011d3 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
sahilmgandhi 18:6a4db94011d3 22 * providing the Software "AS IS", with no express or implied warranties of any
sahilmgandhi 18:6a4db94011d3 23 * kind, including, but not limited to, any implied warranties of
sahilmgandhi 18:6a4db94011d3 24 * merchantability or fitness for any particular purpose or warranties against
sahilmgandhi 18:6a4db94011d3 25 * infringement of any proprietary rights of a third party.
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
sahilmgandhi 18:6a4db94011d3 28 * incidental, or special damages, or any other relief, or for any claim by
sahilmgandhi 18:6a4db94011d3 29 * any third party, arising from your use of this Software.
sahilmgandhi 18:6a4db94011d3 30 *
sahilmgandhi 18:6a4db94011d3 31 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 32 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 33 * @addtogroup Parts
sahilmgandhi 18:6a4db94011d3 34 * @{
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 36 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 37 * @defgroup EFR32MG1P_WDOG
sahilmgandhi 18:6a4db94011d3 38 * @{
sahilmgandhi 18:6a4db94011d3 39 * @brief EFR32MG1P_WDOG Register Declaration
sahilmgandhi 18:6a4db94011d3 40 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 41 typedef struct
sahilmgandhi 18:6a4db94011d3 42 {
sahilmgandhi 18:6a4db94011d3 43 __IOM uint32_t CTRL; /**< Control Register */
sahilmgandhi 18:6a4db94011d3 44 __IOM uint32_t CMD; /**< Command Register */
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 WDOG_PCH_TypeDef PCH[2]; /**< PCH */
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 uint32_t RESERVED0[2]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 51 __IM uint32_t IF; /**< Watchdog Interrupt Flags */
sahilmgandhi 18:6a4db94011d3 52 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
sahilmgandhi 18:6a4db94011d3 53 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
sahilmgandhi 18:6a4db94011d3 54 __IOM uint32_t IEN; /**< Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 55 } WDOG_TypeDef; /** @} */
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 58 * @defgroup EFR32MG1P_WDOG_BitFields
sahilmgandhi 18:6a4db94011d3 59 * @{
sahilmgandhi 18:6a4db94011d3 60 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 /* Bit fields for WDOG CTRL */
sahilmgandhi 18:6a4db94011d3 63 #define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 64 #define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 65 #define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */
sahilmgandhi 18:6a4db94011d3 66 #define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */
sahilmgandhi 18:6a4db94011d3 67 #define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */
sahilmgandhi 18:6a4db94011d3 68 #define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 69 #define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 70 #define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
sahilmgandhi 18:6a4db94011d3 71 #define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */
sahilmgandhi 18:6a4db94011d3 72 #define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */
sahilmgandhi 18:6a4db94011d3 73 #define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 74 #define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 75 #define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */
sahilmgandhi 18:6a4db94011d3 76 #define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */
sahilmgandhi 18:6a4db94011d3 77 #define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */
sahilmgandhi 18:6a4db94011d3 78 #define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 79 #define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 80 #define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */
sahilmgandhi 18:6a4db94011d3 81 #define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */
sahilmgandhi 18:6a4db94011d3 82 #define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */
sahilmgandhi 18:6a4db94011d3 83 #define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 84 #define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 85 #define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */
sahilmgandhi 18:6a4db94011d3 86 #define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */
sahilmgandhi 18:6a4db94011d3 87 #define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */
sahilmgandhi 18:6a4db94011d3 88 #define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 89 #define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 90 #define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */
sahilmgandhi 18:6a4db94011d3 91 #define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */
sahilmgandhi 18:6a4db94011d3 92 #define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */
sahilmgandhi 18:6a4db94011d3 93 #define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 94 #define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 95 #define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */
sahilmgandhi 18:6a4db94011d3 96 #define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */
sahilmgandhi 18:6a4db94011d3 97 #define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */
sahilmgandhi 18:6a4db94011d3 98 #define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 99 #define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 100 #define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */
sahilmgandhi 18:6a4db94011d3 101 #define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */
sahilmgandhi 18:6a4db94011d3 102 #define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 103 #define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 104 #define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */
sahilmgandhi 18:6a4db94011d3 105 #define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */
sahilmgandhi 18:6a4db94011d3 106 #define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 107 #define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 108 #define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 109 #define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 110 #define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 111 #define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 112 #define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 113 #define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 114 #define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */
sahilmgandhi 18:6a4db94011d3 115 #define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */
sahilmgandhi 18:6a4db94011d3 116 #define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 117 #define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 118 #define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */
sahilmgandhi 18:6a4db94011d3 119 #define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */
sahilmgandhi 18:6a4db94011d3 120 #define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 121 #define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 122 #define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */
sahilmgandhi 18:6a4db94011d3 123 #define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */
sahilmgandhi 18:6a4db94011d3 124 #define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */
sahilmgandhi 18:6a4db94011d3 125 #define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 126 #define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 127 #define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 128 #define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 129 #define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 130 #define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 131 #define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */
sahilmgandhi 18:6a4db94011d3 132 #define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */
sahilmgandhi 18:6a4db94011d3 133 #define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */
sahilmgandhi 18:6a4db94011d3 134 #define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 135 #define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 136 #define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 137 #define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 138 #define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 139 #define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 /* Bit fields for WDOG CMD */
sahilmgandhi 18:6a4db94011d3 142 #define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */
sahilmgandhi 18:6a4db94011d3 143 #define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */
sahilmgandhi 18:6a4db94011d3 144 #define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */
sahilmgandhi 18:6a4db94011d3 145 #define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */
sahilmgandhi 18:6a4db94011d3 146 #define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */
sahilmgandhi 18:6a4db94011d3 147 #define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */
sahilmgandhi 18:6a4db94011d3 148 #define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */
sahilmgandhi 18:6a4db94011d3 149 #define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */
sahilmgandhi 18:6a4db94011d3 150 #define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */
sahilmgandhi 18:6a4db94011d3 151 #define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */
sahilmgandhi 18:6a4db94011d3 152 #define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 /* Bit fields for WDOG SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 155 #define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 156 #define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 157 #define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
sahilmgandhi 18:6a4db94011d3 158 #define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 159 #define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */
sahilmgandhi 18:6a4db94011d3 160 #define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 161 #define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 162 #define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
sahilmgandhi 18:6a4db94011d3 163 #define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */
sahilmgandhi 18:6a4db94011d3 164 #define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */
sahilmgandhi 18:6a4db94011d3 165 #define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 166 #define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 167 #define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */
sahilmgandhi 18:6a4db94011d3 168 #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 169 #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 170 #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 171 #define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 172 #define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */
sahilmgandhi 18:6a4db94011d3 173 #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 174 #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 175 #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 176 #define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 /* Bit fields for WDOG PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 179 #define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 180 #define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL /**< Mask for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 181 #define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */
sahilmgandhi 18:6a4db94011d3 182 #define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL /**< Bit mask for WDOG_PRSSEL */
sahilmgandhi 18:6a4db94011d3 183 #define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 184 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 185 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 186 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 187 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 188 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 189 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 190 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 191 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 192 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 193 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 194 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 195 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 196 #define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 197 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 198 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 199 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 200 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 201 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 202 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 203 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 204 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 205 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 206 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 207 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 208 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 209 #define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS missing event will trigger a watchdog reset */
sahilmgandhi 18:6a4db94011d3 210 #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */
sahilmgandhi 18:6a4db94011d3 211 #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */
sahilmgandhi 18:6a4db94011d3 212 #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 213 #define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 /* Bit fields for WDOG IF */
sahilmgandhi 18:6a4db94011d3 216 #define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */
sahilmgandhi 18:6a4db94011d3 217 #define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */
sahilmgandhi 18:6a4db94011d3 218 #define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 219 #define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
sahilmgandhi 18:6a4db94011d3 220 #define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
sahilmgandhi 18:6a4db94011d3 221 #define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
sahilmgandhi 18:6a4db94011d3 222 #define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */
sahilmgandhi 18:6a4db94011d3 223 #define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 224 #define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
sahilmgandhi 18:6a4db94011d3 225 #define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
sahilmgandhi 18:6a4db94011d3 226 #define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
sahilmgandhi 18:6a4db94011d3 227 #define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */
sahilmgandhi 18:6a4db94011d3 228 #define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 229 #define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
sahilmgandhi 18:6a4db94011d3 230 #define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
sahilmgandhi 18:6a4db94011d3 231 #define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
sahilmgandhi 18:6a4db94011d3 232 #define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */
sahilmgandhi 18:6a4db94011d3 233 #define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 234 #define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
sahilmgandhi 18:6a4db94011d3 235 #define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
sahilmgandhi 18:6a4db94011d3 236 #define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
sahilmgandhi 18:6a4db94011d3 237 #define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */
sahilmgandhi 18:6a4db94011d3 238 #define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 239 #define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
sahilmgandhi 18:6a4db94011d3 240 #define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
sahilmgandhi 18:6a4db94011d3 241 #define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
sahilmgandhi 18:6a4db94011d3 242 #define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 /* Bit fields for WDOG IFS */
sahilmgandhi 18:6a4db94011d3 245 #define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */
sahilmgandhi 18:6a4db94011d3 246 #define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */
sahilmgandhi 18:6a4db94011d3 247 #define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 248 #define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
sahilmgandhi 18:6a4db94011d3 249 #define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
sahilmgandhi 18:6a4db94011d3 250 #define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
sahilmgandhi 18:6a4db94011d3 251 #define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */
sahilmgandhi 18:6a4db94011d3 252 #define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 253 #define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
sahilmgandhi 18:6a4db94011d3 254 #define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
sahilmgandhi 18:6a4db94011d3 255 #define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
sahilmgandhi 18:6a4db94011d3 256 #define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */
sahilmgandhi 18:6a4db94011d3 257 #define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 258 #define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
sahilmgandhi 18:6a4db94011d3 259 #define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
sahilmgandhi 18:6a4db94011d3 260 #define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
sahilmgandhi 18:6a4db94011d3 261 #define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */
sahilmgandhi 18:6a4db94011d3 262 #define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 263 #define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
sahilmgandhi 18:6a4db94011d3 264 #define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
sahilmgandhi 18:6a4db94011d3 265 #define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
sahilmgandhi 18:6a4db94011d3 266 #define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */
sahilmgandhi 18:6a4db94011d3 267 #define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 268 #define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
sahilmgandhi 18:6a4db94011d3 269 #define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
sahilmgandhi 18:6a4db94011d3 270 #define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
sahilmgandhi 18:6a4db94011d3 271 #define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 /* Bit fields for WDOG IFC */
sahilmgandhi 18:6a4db94011d3 274 #define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */
sahilmgandhi 18:6a4db94011d3 275 #define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */
sahilmgandhi 18:6a4db94011d3 276 #define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 277 #define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
sahilmgandhi 18:6a4db94011d3 278 #define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
sahilmgandhi 18:6a4db94011d3 279 #define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
sahilmgandhi 18:6a4db94011d3 280 #define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */
sahilmgandhi 18:6a4db94011d3 281 #define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 282 #define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
sahilmgandhi 18:6a4db94011d3 283 #define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
sahilmgandhi 18:6a4db94011d3 284 #define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
sahilmgandhi 18:6a4db94011d3 285 #define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */
sahilmgandhi 18:6a4db94011d3 286 #define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 287 #define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
sahilmgandhi 18:6a4db94011d3 288 #define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
sahilmgandhi 18:6a4db94011d3 289 #define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
sahilmgandhi 18:6a4db94011d3 290 #define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */
sahilmgandhi 18:6a4db94011d3 291 #define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 292 #define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
sahilmgandhi 18:6a4db94011d3 293 #define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
sahilmgandhi 18:6a4db94011d3 294 #define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
sahilmgandhi 18:6a4db94011d3 295 #define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */
sahilmgandhi 18:6a4db94011d3 296 #define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 297 #define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
sahilmgandhi 18:6a4db94011d3 298 #define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
sahilmgandhi 18:6a4db94011d3 299 #define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
sahilmgandhi 18:6a4db94011d3 300 #define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 /* Bit fields for WDOG IEN */
sahilmgandhi 18:6a4db94011d3 303 #define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */
sahilmgandhi 18:6a4db94011d3 304 #define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */
sahilmgandhi 18:6a4db94011d3 305 #define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 306 #define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
sahilmgandhi 18:6a4db94011d3 307 #define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
sahilmgandhi 18:6a4db94011d3 308 #define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
sahilmgandhi 18:6a4db94011d3 309 #define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */
sahilmgandhi 18:6a4db94011d3 310 #define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 311 #define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
sahilmgandhi 18:6a4db94011d3 312 #define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
sahilmgandhi 18:6a4db94011d3 313 #define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
sahilmgandhi 18:6a4db94011d3 314 #define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */
sahilmgandhi 18:6a4db94011d3 315 #define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 316 #define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
sahilmgandhi 18:6a4db94011d3 317 #define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
sahilmgandhi 18:6a4db94011d3 318 #define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
sahilmgandhi 18:6a4db94011d3 319 #define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */
sahilmgandhi 18:6a4db94011d3 320 #define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 321 #define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
sahilmgandhi 18:6a4db94011d3 322 #define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
sahilmgandhi 18:6a4db94011d3 323 #define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
sahilmgandhi 18:6a4db94011d3 324 #define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */
sahilmgandhi 18:6a4db94011d3 325 #define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 326 #define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
sahilmgandhi 18:6a4db94011d3 327 #define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
sahilmgandhi 18:6a4db94011d3 328 #define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
sahilmgandhi 18:6a4db94011d3 329 #define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 /** @} End of group EFR32MG1P_WDOG */
sahilmgandhi 18:6a4db94011d3 332 /** @} End of group Parts */
sahilmgandhi 18:6a4db94011d3 333