MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_msc.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file efr32mg1p_msc.h
sahilmgandhi 18:6a4db94011d3 3 * @brief EFR32MG1P_MSC register and bit field definitions
sahilmgandhi 18:6a4db94011d3 4 * @version 5.1.2
sahilmgandhi 18:6a4db94011d3 5 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 6 * @section License
sahilmgandhi 18:6a4db94011d3 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Permission is granted to anyone to use this software for any purpose,
sahilmgandhi 18:6a4db94011d3 11 * including commercial applications, and to alter it and redistribute it
sahilmgandhi 18:6a4db94011d3 12 * freely, subject to the following restrictions:
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * 1. The origin of this software must not be misrepresented; you must not
sahilmgandhi 18:6a4db94011d3 15 * claim that you wrote the original software.@n
sahilmgandhi 18:6a4db94011d3 16 * 2. Altered source versions must be plainly marked as such, and must not be
sahilmgandhi 18:6a4db94011d3 17 * misrepresented as being the original software.@n
sahilmgandhi 18:6a4db94011d3 18 * 3. This notice may not be removed or altered from any source distribution.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
sahilmgandhi 18:6a4db94011d3 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
sahilmgandhi 18:6a4db94011d3 22 * providing the Software "AS IS", with no express or implied warranties of any
sahilmgandhi 18:6a4db94011d3 23 * kind, including, but not limited to, any implied warranties of
sahilmgandhi 18:6a4db94011d3 24 * merchantability or fitness for any particular purpose or warranties against
sahilmgandhi 18:6a4db94011d3 25 * infringement of any proprietary rights of a third party.
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
sahilmgandhi 18:6a4db94011d3 28 * incidental, or special damages, or any other relief, or for any claim by
sahilmgandhi 18:6a4db94011d3 29 * any third party, arising from your use of this Software.
sahilmgandhi 18:6a4db94011d3 30 *
sahilmgandhi 18:6a4db94011d3 31 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 32 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 33 * @addtogroup Parts
sahilmgandhi 18:6a4db94011d3 34 * @{
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 36 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 37 * @defgroup EFR32MG1P_MSC
sahilmgandhi 18:6a4db94011d3 38 * @{
sahilmgandhi 18:6a4db94011d3 39 * @brief EFR32MG1P_MSC Register Declaration
sahilmgandhi 18:6a4db94011d3 40 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 41 typedef struct
sahilmgandhi 18:6a4db94011d3 42 {
sahilmgandhi 18:6a4db94011d3 43 __IOM uint32_t CTRL; /**< Memory System Control Register */
sahilmgandhi 18:6a4db94011d3 44 __IOM uint32_t READCTRL; /**< Read Control Register */
sahilmgandhi 18:6a4db94011d3 45 __IOM uint32_t WRITECTRL; /**< Write Control Register */
sahilmgandhi 18:6a4db94011d3 46 __IOM uint32_t WRITECMD; /**< Write Command Register */
sahilmgandhi 18:6a4db94011d3 47 __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
sahilmgandhi 18:6a4db94011d3 48 uint32_t RESERVED0[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 49 __IOM uint32_t WDATA; /**< Write Data Register */
sahilmgandhi 18:6a4db94011d3 50 __IM uint32_t STATUS; /**< Status Register */
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 uint32_t RESERVED1[4]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 53 __IM uint32_t IF; /**< Interrupt Flag Register */
sahilmgandhi 18:6a4db94011d3 54 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
sahilmgandhi 18:6a4db94011d3 55 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
sahilmgandhi 18:6a4db94011d3 56 __IOM uint32_t IEN; /**< Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 57 __IOM uint32_t LOCK; /**< Configuration Lock Register */
sahilmgandhi 18:6a4db94011d3 58 __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */
sahilmgandhi 18:6a4db94011d3 59 __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
sahilmgandhi 18:6a4db94011d3 60 __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 uint32_t RESERVED2[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 63 __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 uint32_t RESERVED3[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 66 __IOM uint32_t STARTUP; /**< Startup Control */
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 uint32_t RESERVED4[5]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 69 __IOM uint32_t CMD; /**< Command Register */
sahilmgandhi 18:6a4db94011d3 70 } MSC_TypeDef; /** @} */
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 73 * @defgroup EFR32MG1P_MSC_BitFields
sahilmgandhi 18:6a4db94011d3 74 * @{
sahilmgandhi 18:6a4db94011d3 75 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 /* Bit fields for MSC CTRL */
sahilmgandhi 18:6a4db94011d3 78 #define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
sahilmgandhi 18:6a4db94011d3 79 #define _MSC_CTRL_MASK 0x0000000FUL /**< Mask for MSC_CTRL */
sahilmgandhi 18:6a4db94011d3 80 #define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */
sahilmgandhi 18:6a4db94011d3 81 #define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */
sahilmgandhi 18:6a4db94011d3 82 #define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */
sahilmgandhi 18:6a4db94011d3 83 #define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */
sahilmgandhi 18:6a4db94011d3 84 #define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */
sahilmgandhi 18:6a4db94011d3 85 #define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */
sahilmgandhi 18:6a4db94011d3 86 #define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */
sahilmgandhi 18:6a4db94011d3 87 #define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */
sahilmgandhi 18:6a4db94011d3 88 #define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
sahilmgandhi 18:6a4db94011d3 89 #define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */
sahilmgandhi 18:6a4db94011d3 90 #define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up On Demand During Wake Up */
sahilmgandhi 18:6a4db94011d3 91 #define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */
sahilmgandhi 18:6a4db94011d3 92 #define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */
sahilmgandhi 18:6a4db94011d3 93 #define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
sahilmgandhi 18:6a4db94011d3 94 #define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */
sahilmgandhi 18:6a4db94011d3 95 #define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */
sahilmgandhi 18:6a4db94011d3 96 #define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */
sahilmgandhi 18:6a4db94011d3 97 #define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */
sahilmgandhi 18:6a4db94011d3 98 #define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
sahilmgandhi 18:6a4db94011d3 99 #define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 /* Bit fields for MSC READCTRL */
sahilmgandhi 18:6a4db94011d3 102 #define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 103 #define _MSC_READCTRL_MASK 0x13000338UL /**< Mask for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 104 #define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */
sahilmgandhi 18:6a4db94011d3 105 #define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */
sahilmgandhi 18:6a4db94011d3 106 #define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */
sahilmgandhi 18:6a4db94011d3 107 #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 108 #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 109 #define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */
sahilmgandhi 18:6a4db94011d3 110 #define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */
sahilmgandhi 18:6a4db94011d3 111 #define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */
sahilmgandhi 18:6a4db94011d3 112 #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 113 #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 114 #define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */
sahilmgandhi 18:6a4db94011d3 115 #define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */
sahilmgandhi 18:6a4db94011d3 116 #define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */
sahilmgandhi 18:6a4db94011d3 117 #define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 118 #define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 119 #define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */
sahilmgandhi 18:6a4db94011d3 120 #define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */
sahilmgandhi 18:6a4db94011d3 121 #define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */
sahilmgandhi 18:6a4db94011d3 122 #define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 123 #define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 124 #define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */
sahilmgandhi 18:6a4db94011d3 125 #define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */
sahilmgandhi 18:6a4db94011d3 126 #define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */
sahilmgandhi 18:6a4db94011d3 127 #define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 128 #define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 129 #define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */
sahilmgandhi 18:6a4db94011d3 130 #define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */
sahilmgandhi 18:6a4db94011d3 131 #define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 132 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 133 #define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 134 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 135 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 136 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 137 #define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */
sahilmgandhi 18:6a4db94011d3 138 #define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */
sahilmgandhi 18:6a4db94011d3 139 #define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */
sahilmgandhi 18:6a4db94011d3 140 #define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 141 #define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 /* Bit fields for MSC WRITECTRL */
sahilmgandhi 18:6a4db94011d3 144 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
sahilmgandhi 18:6a4db94011d3 145 #define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */
sahilmgandhi 18:6a4db94011d3 146 #define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
sahilmgandhi 18:6a4db94011d3 147 #define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
sahilmgandhi 18:6a4db94011d3 148 #define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
sahilmgandhi 18:6a4db94011d3 149 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
sahilmgandhi 18:6a4db94011d3 150 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
sahilmgandhi 18:6a4db94011d3 151 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
sahilmgandhi 18:6a4db94011d3 152 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
sahilmgandhi 18:6a4db94011d3 153 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
sahilmgandhi 18:6a4db94011d3 154 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
sahilmgandhi 18:6a4db94011d3 155 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 /* Bit fields for MSC WRITECMD */
sahilmgandhi 18:6a4db94011d3 158 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 159 #define _MSC_WRITECMD_MASK 0x0000113FUL /**< Mask for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 160 #define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */
sahilmgandhi 18:6a4db94011d3 161 #define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
sahilmgandhi 18:6a4db94011d3 162 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
sahilmgandhi 18:6a4db94011d3 163 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 164 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 165 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
sahilmgandhi 18:6a4db94011d3 166 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
sahilmgandhi 18:6a4db94011d3 167 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
sahilmgandhi 18:6a4db94011d3 168 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 169 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 170 #define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
sahilmgandhi 18:6a4db94011d3 171 #define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
sahilmgandhi 18:6a4db94011d3 172 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
sahilmgandhi 18:6a4db94011d3 173 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 174 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 175 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */
sahilmgandhi 18:6a4db94011d3 176 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */
sahilmgandhi 18:6a4db94011d3 177 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */
sahilmgandhi 18:6a4db94011d3 178 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 179 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 180 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */
sahilmgandhi 18:6a4db94011d3 181 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */
sahilmgandhi 18:6a4db94011d3 182 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
sahilmgandhi 18:6a4db94011d3 183 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 184 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 185 #define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */
sahilmgandhi 18:6a4db94011d3 186 #define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
sahilmgandhi 18:6a4db94011d3 187 #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
sahilmgandhi 18:6a4db94011d3 188 #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 189 #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 190 #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */
sahilmgandhi 18:6a4db94011d3 191 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
sahilmgandhi 18:6a4db94011d3 192 #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
sahilmgandhi 18:6a4db94011d3 193 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 194 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 195 #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */
sahilmgandhi 18:6a4db94011d3 196 #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
sahilmgandhi 18:6a4db94011d3 197 #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
sahilmgandhi 18:6a4db94011d3 198 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 199 #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 /* Bit fields for MSC ADDRB */
sahilmgandhi 18:6a4db94011d3 202 #define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
sahilmgandhi 18:6a4db94011d3 203 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
sahilmgandhi 18:6a4db94011d3 204 #define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
sahilmgandhi 18:6a4db94011d3 205 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
sahilmgandhi 18:6a4db94011d3 206 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
sahilmgandhi 18:6a4db94011d3 207 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 /* Bit fields for MSC WDATA */
sahilmgandhi 18:6a4db94011d3 210 #define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
sahilmgandhi 18:6a4db94011d3 211 #define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
sahilmgandhi 18:6a4db94011d3 212 #define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */
sahilmgandhi 18:6a4db94011d3 213 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */
sahilmgandhi 18:6a4db94011d3 214 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
sahilmgandhi 18:6a4db94011d3 215 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
sahilmgandhi 18:6a4db94011d3 216
sahilmgandhi 18:6a4db94011d3 217 /* Bit fields for MSC STATUS */
sahilmgandhi 18:6a4db94011d3 218 #define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 219 #define _MSC_STATUS_MASK 0x0000007FUL /**< Mask for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 220 #define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
sahilmgandhi 18:6a4db94011d3 221 #define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
sahilmgandhi 18:6a4db94011d3 222 #define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
sahilmgandhi 18:6a4db94011d3 223 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 224 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 225 #define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
sahilmgandhi 18:6a4db94011d3 226 #define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
sahilmgandhi 18:6a4db94011d3 227 #define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
sahilmgandhi 18:6a4db94011d3 228 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 229 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 230 #define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
sahilmgandhi 18:6a4db94011d3 231 #define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
sahilmgandhi 18:6a4db94011d3 232 #define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
sahilmgandhi 18:6a4db94011d3 233 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 234 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 235 #define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
sahilmgandhi 18:6a4db94011d3 236 #define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
sahilmgandhi 18:6a4db94011d3 237 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
sahilmgandhi 18:6a4db94011d3 238 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 239 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 240 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */
sahilmgandhi 18:6a4db94011d3 241 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */
sahilmgandhi 18:6a4db94011d3 242 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */
sahilmgandhi 18:6a4db94011d3 243 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 244 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 245 #define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */
sahilmgandhi 18:6a4db94011d3 246 #define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */
sahilmgandhi 18:6a4db94011d3 247 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */
sahilmgandhi 18:6a4db94011d3 248 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 249 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 250 #define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */
sahilmgandhi 18:6a4db94011d3 251 #define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */
sahilmgandhi 18:6a4db94011d3 252 #define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */
sahilmgandhi 18:6a4db94011d3 253 #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 254 #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 /* Bit fields for MSC IF */
sahilmgandhi 18:6a4db94011d3 257 #define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
sahilmgandhi 18:6a4db94011d3 258 #define _MSC_IF_MASK 0x0000003FUL /**< Mask for MSC_IF */
sahilmgandhi 18:6a4db94011d3 259 #define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */
sahilmgandhi 18:6a4db94011d3 260 #define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
sahilmgandhi 18:6a4db94011d3 261 #define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
sahilmgandhi 18:6a4db94011d3 262 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
sahilmgandhi 18:6a4db94011d3 263 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
sahilmgandhi 18:6a4db94011d3 264 #define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */
sahilmgandhi 18:6a4db94011d3 265 #define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
sahilmgandhi 18:6a4db94011d3 266 #define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
sahilmgandhi 18:6a4db94011d3 267 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
sahilmgandhi 18:6a4db94011d3 268 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
sahilmgandhi 18:6a4db94011d3 269 #define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 270 #define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
sahilmgandhi 18:6a4db94011d3 271 #define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
sahilmgandhi 18:6a4db94011d3 272 #define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
sahilmgandhi 18:6a4db94011d3 273 #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */
sahilmgandhi 18:6a4db94011d3 274 #define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 275 #define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
sahilmgandhi 18:6a4db94011d3 276 #define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
sahilmgandhi 18:6a4db94011d3 277 #define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
sahilmgandhi 18:6a4db94011d3 278 #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */
sahilmgandhi 18:6a4db94011d3 279 #define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */
sahilmgandhi 18:6a4db94011d3 280 #define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
sahilmgandhi 18:6a4db94011d3 281 #define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
sahilmgandhi 18:6a4db94011d3 282 #define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
sahilmgandhi 18:6a4db94011d3 283 #define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */
sahilmgandhi 18:6a4db94011d3 284 #define MSC_IF_ICACHERR (0x1UL << 5) /**< iCache RAM Parity Error Flag */
sahilmgandhi 18:6a4db94011d3 285 #define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
sahilmgandhi 18:6a4db94011d3 286 #define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
sahilmgandhi 18:6a4db94011d3 287 #define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
sahilmgandhi 18:6a4db94011d3 288 #define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 /* Bit fields for MSC IFS */
sahilmgandhi 18:6a4db94011d3 291 #define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 292 #define _MSC_IFS_MASK 0x0000003FUL /**< Mask for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 293 #define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 294 #define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
sahilmgandhi 18:6a4db94011d3 295 #define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
sahilmgandhi 18:6a4db94011d3 296 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 297 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 298 #define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 299 #define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
sahilmgandhi 18:6a4db94011d3 300 #define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
sahilmgandhi 18:6a4db94011d3 301 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 302 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 303 #define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 304 #define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
sahilmgandhi 18:6a4db94011d3 305 #define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
sahilmgandhi 18:6a4db94011d3 306 #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 307 #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 308 #define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 309 #define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
sahilmgandhi 18:6a4db94011d3 310 #define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
sahilmgandhi 18:6a4db94011d3 311 #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 312 #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 313 #define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 314 #define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
sahilmgandhi 18:6a4db94011d3 315 #define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
sahilmgandhi 18:6a4db94011d3 316 #define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 317 #define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 318 #define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 319 #define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
sahilmgandhi 18:6a4db94011d3 320 #define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
sahilmgandhi 18:6a4db94011d3 321 #define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 322 #define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 /* Bit fields for MSC IFC */
sahilmgandhi 18:6a4db94011d3 325 #define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 326 #define _MSC_IFC_MASK 0x0000003FUL /**< Mask for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 327 #define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 328 #define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
sahilmgandhi 18:6a4db94011d3 329 #define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
sahilmgandhi 18:6a4db94011d3 330 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 331 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 332 #define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 333 #define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
sahilmgandhi 18:6a4db94011d3 334 #define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
sahilmgandhi 18:6a4db94011d3 335 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 336 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 337 #define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 338 #define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
sahilmgandhi 18:6a4db94011d3 339 #define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
sahilmgandhi 18:6a4db94011d3 340 #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 341 #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 342 #define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 343 #define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
sahilmgandhi 18:6a4db94011d3 344 #define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
sahilmgandhi 18:6a4db94011d3 345 #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 346 #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 347 #define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 348 #define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
sahilmgandhi 18:6a4db94011d3 349 #define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
sahilmgandhi 18:6a4db94011d3 350 #define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 351 #define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 352 #define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 353 #define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
sahilmgandhi 18:6a4db94011d3 354 #define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
sahilmgandhi 18:6a4db94011d3 355 #define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 356 #define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 /* Bit fields for MSC IEN */
sahilmgandhi 18:6a4db94011d3 359 #define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 360 #define _MSC_IEN_MASK 0x0000003FUL /**< Mask for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 361 #define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 362 #define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
sahilmgandhi 18:6a4db94011d3 363 #define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
sahilmgandhi 18:6a4db94011d3 364 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 365 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 366 #define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 367 #define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
sahilmgandhi 18:6a4db94011d3 368 #define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
sahilmgandhi 18:6a4db94011d3 369 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 370 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 371 #define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 372 #define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
sahilmgandhi 18:6a4db94011d3 373 #define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
sahilmgandhi 18:6a4db94011d3 374 #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 375 #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 376 #define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 377 #define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
sahilmgandhi 18:6a4db94011d3 378 #define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
sahilmgandhi 18:6a4db94011d3 379 #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 380 #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 381 #define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 382 #define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
sahilmgandhi 18:6a4db94011d3 383 #define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
sahilmgandhi 18:6a4db94011d3 384 #define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 385 #define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 386 #define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 387 #define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
sahilmgandhi 18:6a4db94011d3 388 #define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
sahilmgandhi 18:6a4db94011d3 389 #define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 390 #define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 /* Bit fields for MSC LOCK */
sahilmgandhi 18:6a4db94011d3 393 #define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
sahilmgandhi 18:6a4db94011d3 394 #define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
sahilmgandhi 18:6a4db94011d3 395 #define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 396 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 397 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
sahilmgandhi 18:6a4db94011d3 398 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
sahilmgandhi 18:6a4db94011d3 399 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
sahilmgandhi 18:6a4db94011d3 400 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
sahilmgandhi 18:6a4db94011d3 401 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
sahilmgandhi 18:6a4db94011d3 402 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
sahilmgandhi 18:6a4db94011d3 403 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
sahilmgandhi 18:6a4db94011d3 404 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
sahilmgandhi 18:6a4db94011d3 405 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
sahilmgandhi 18:6a4db94011d3 406 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
sahilmgandhi 18:6a4db94011d3 407
sahilmgandhi 18:6a4db94011d3 408 /* Bit fields for MSC CACHECMD */
sahilmgandhi 18:6a4db94011d3 409 #define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */
sahilmgandhi 18:6a4db94011d3 410 #define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */
sahilmgandhi 18:6a4db94011d3 411 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */
sahilmgandhi 18:6a4db94011d3 412 #define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */
sahilmgandhi 18:6a4db94011d3 413 #define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */
sahilmgandhi 18:6a4db94011d3 414 #define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
sahilmgandhi 18:6a4db94011d3 415 #define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */
sahilmgandhi 18:6a4db94011d3 416 #define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
sahilmgandhi 18:6a4db94011d3 417 #define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */
sahilmgandhi 18:6a4db94011d3 418 #define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */
sahilmgandhi 18:6a4db94011d3 419 #define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
sahilmgandhi 18:6a4db94011d3 420 #define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */
sahilmgandhi 18:6a4db94011d3 421 #define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
sahilmgandhi 18:6a4db94011d3 422 #define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */
sahilmgandhi 18:6a4db94011d3 423 #define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */
sahilmgandhi 18:6a4db94011d3 424 #define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
sahilmgandhi 18:6a4db94011d3 425 #define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 /* Bit fields for MSC CACHEHITS */
sahilmgandhi 18:6a4db94011d3 428 #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */
sahilmgandhi 18:6a4db94011d3 429 #define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */
sahilmgandhi 18:6a4db94011d3 430 #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */
sahilmgandhi 18:6a4db94011d3 431 #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */
sahilmgandhi 18:6a4db94011d3 432 #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */
sahilmgandhi 18:6a4db94011d3 433 #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
sahilmgandhi 18:6a4db94011d3 434
sahilmgandhi 18:6a4db94011d3 435 /* Bit fields for MSC CACHEMISSES */
sahilmgandhi 18:6a4db94011d3 436 #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */
sahilmgandhi 18:6a4db94011d3 437 #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */
sahilmgandhi 18:6a4db94011d3 438 #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */
sahilmgandhi 18:6a4db94011d3 439 #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */
sahilmgandhi 18:6a4db94011d3 440 #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */
sahilmgandhi 18:6a4db94011d3 441 #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443 /* Bit fields for MSC MASSLOCK */
sahilmgandhi 18:6a4db94011d3 444 #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */
sahilmgandhi 18:6a4db94011d3 445 #define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
sahilmgandhi 18:6a4db94011d3 446 #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 447 #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 448 #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
sahilmgandhi 18:6a4db94011d3 449 #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
sahilmgandhi 18:6a4db94011d3 450 #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
sahilmgandhi 18:6a4db94011d3 451 #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
sahilmgandhi 18:6a4db94011d3 452 #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
sahilmgandhi 18:6a4db94011d3 453 #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
sahilmgandhi 18:6a4db94011d3 454 #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
sahilmgandhi 18:6a4db94011d3 455 #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
sahilmgandhi 18:6a4db94011d3 456 #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
sahilmgandhi 18:6a4db94011d3 457 #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
sahilmgandhi 18:6a4db94011d3 458
sahilmgandhi 18:6a4db94011d3 459 /* Bit fields for MSC STARTUP */
sahilmgandhi 18:6a4db94011d3 460 #define _MSC_STARTUP_RESETVALUE 0x1300104DUL /**< Default value for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 461 #define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 462 #define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */
sahilmgandhi 18:6a4db94011d3 463 #define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */
sahilmgandhi 18:6a4db94011d3 464 #define _MSC_STARTUP_STDLY0_DEFAULT 0x0000004DUL /**< Mode DEFAULT for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 465 #define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 466 #define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */
sahilmgandhi 18:6a4db94011d3 467 #define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */
sahilmgandhi 18:6a4db94011d3 468 #define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 469 #define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 470 #define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */
sahilmgandhi 18:6a4db94011d3 471 #define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */
sahilmgandhi 18:6a4db94011d3 472 #define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */
sahilmgandhi 18:6a4db94011d3 473 #define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 474 #define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 475 #define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */
sahilmgandhi 18:6a4db94011d3 476 #define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */
sahilmgandhi 18:6a4db94011d3 477 #define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */
sahilmgandhi 18:6a4db94011d3 478 #define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 479 #define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 480 #define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */
sahilmgandhi 18:6a4db94011d3 481 #define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */
sahilmgandhi 18:6a4db94011d3 482 #define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */
sahilmgandhi 18:6a4db94011d3 483 #define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 484 #define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 485 #define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */
sahilmgandhi 18:6a4db94011d3 486 #define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */
sahilmgandhi 18:6a4db94011d3 487 #define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 488 #define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */
sahilmgandhi 18:6a4db94011d3 489
sahilmgandhi 18:6a4db94011d3 490 /* Bit fields for MSC CMD */
sahilmgandhi 18:6a4db94011d3 491 #define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */
sahilmgandhi 18:6a4db94011d3 492 #define _MSC_CMD_MASK 0x00000001UL /**< Mask for MSC_CMD */
sahilmgandhi 18:6a4db94011d3 493 #define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */
sahilmgandhi 18:6a4db94011d3 494 #define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */
sahilmgandhi 18:6a4db94011d3 495 #define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */
sahilmgandhi 18:6a4db94011d3 496 #define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
sahilmgandhi 18:6a4db94011d3 497 #define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
sahilmgandhi 18:6a4db94011d3 498
sahilmgandhi 18:6a4db94011d3 499 /** @} End of group EFR32MG1P_MSC */
sahilmgandhi 18:6a4db94011d3 500 /** @} End of group Parts */
sahilmgandhi 18:6a4db94011d3 501