Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /***************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file PeripheralNames.h
sahilmgandhi 18:6a4db94011d3 3 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 4 * @section License
sahilmgandhi 18:6a4db94011d3 5 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
sahilmgandhi 18:6a4db94011d3 6 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * SPDX-License-Identifier: Apache-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Licensed under the Apache License, Version 2.0 (the "License"); you may
sahilmgandhi 18:6a4db94011d3 11 * not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 12 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 17 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
sahilmgandhi 18:6a4db94011d3 18 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 19 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 20 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 23 #ifndef MBED_PERIPHERALNAMES_H
sahilmgandhi 18:6a4db94011d3 24 #define MBED_PERIPHERALNAMES_H
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #include "em_adc.h"
sahilmgandhi 18:6a4db94011d3 27 #include "em_usart.h"
sahilmgandhi 18:6a4db94011d3 28 #include "em_i2c.h"
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 31 extern "C" {
sahilmgandhi 18:6a4db94011d3 32 #endif
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 typedef enum {
sahilmgandhi 18:6a4db94011d3 35 ADC_0 = ADC0_BASE
sahilmgandhi 18:6a4db94011d3 36 } ADCName;
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 typedef enum {
sahilmgandhi 18:6a4db94011d3 39 I2C_0 = I2C0_BASE,
sahilmgandhi 18:6a4db94011d3 40 } I2CName;
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 typedef enum {
sahilmgandhi 18:6a4db94011d3 43 PWM_CH0 = 0,
sahilmgandhi 18:6a4db94011d3 44 PWM_CH1 = 1,
sahilmgandhi 18:6a4db94011d3 45 PWM_CH2 = 2,
sahilmgandhi 18:6a4db94011d3 46 PWM_CH3 = 3
sahilmgandhi 18:6a4db94011d3 47 } PWMName;
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 typedef enum {
sahilmgandhi 18:6a4db94011d3 50 USART_0 = USART0_BASE,
sahilmgandhi 18:6a4db94011d3 51 USART_1 = USART1_BASE,
sahilmgandhi 18:6a4db94011d3 52 LEUART_0 = LEUART0_BASE,
sahilmgandhi 18:6a4db94011d3 53 } UARTName;
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 typedef enum {
sahilmgandhi 18:6a4db94011d3 56 SPI_0 = USART0_BASE,
sahilmgandhi 18:6a4db94011d3 57 SPI_1 = USART1_BASE,
sahilmgandhi 18:6a4db94011d3 58 } SPIName;
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 61 }
sahilmgandhi 18:6a4db94011d3 62 #endif
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 #endif