MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_stm32f7xx.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file system_stm32f7xx.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.2.0
sahilmgandhi 18:6a4db94011d3 6 * @date 30-December-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * This file provides two functions and one global variable to be called from
sahilmgandhi 18:6a4db94011d3 10 * user application:
sahilmgandhi 18:6a4db94011d3 11 * - SystemInit(): This function is called at startup just after reset and
sahilmgandhi 18:6a4db94011d3 12 * before branch to main program. This call is made inside
sahilmgandhi 18:6a4db94011d3 13 * the "startup_stm32f7xx.s" file.
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
sahilmgandhi 18:6a4db94011d3 16 * by the user application to setup the SysTick
sahilmgandhi 18:6a4db94011d3 17 * timer or configure other parameters.
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
sahilmgandhi 18:6a4db94011d3 20 * be called whenever the core clock is changed
sahilmgandhi 18:6a4db94011d3 21 * during program execution.
sahilmgandhi 18:6a4db94011d3 22 *
sahilmgandhi 18:6a4db94011d3 23 * This file configures the system clock as follows:
sahilmgandhi 18:6a4db94011d3 24 *-----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 25 * System clock source | [1] PLL_HSE_XTAL | [2] PLL_HSI if [1] fails
sahilmgandhi 18:6a4db94011d3 26 * | (external 25MHz xtal) | (internal 16MHz clock)
sahilmgandhi 18:6a4db94011d3 27 *-----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 28 * SYSCLK(MHz) | 216 | 216
sahilmgandhi 18:6a4db94011d3 29 *-----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 30 * AHBCLK (MHz) | 216 | 216
sahilmgandhi 18:6a4db94011d3 31 *-----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 32 * APB1CLK (MHz) | 54 | 54
sahilmgandhi 18:6a4db94011d3 33 *-----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 34 * APB2CLK (MHz) | 108 | 108
sahilmgandhi 18:6a4db94011d3 35 *-----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 36 * USB capable | YES | NO
sahilmgandhi 18:6a4db94011d3 37 * with 48 MHz precise clock | |
sahilmgandhi 18:6a4db94011d3 38 *-----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 39 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 40 * @attention
sahilmgandhi 18:6a4db94011d3 41 *
sahilmgandhi 18:6a4db94011d3 42 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 43 *
sahilmgandhi 18:6a4db94011d3 44 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 45 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 46 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 47 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 48 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 49 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 50 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 51 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 52 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 53 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 54 *
sahilmgandhi 18:6a4db94011d3 55 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 56 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 58 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 62 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 65 *
sahilmgandhi 18:6a4db94011d3 66 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 67 */
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 /** @addtogroup CMSIS
sahilmgandhi 18:6a4db94011d3 70 * @{
sahilmgandhi 18:6a4db94011d3 71 */
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 /** @addtogroup stm32f7xx_system
sahilmgandhi 18:6a4db94011d3 74 * @{
sahilmgandhi 18:6a4db94011d3 75 */
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 /** @addtogroup STM32F7xx_System_Private_Includes
sahilmgandhi 18:6a4db94011d3 78 * @{
sahilmgandhi 18:6a4db94011d3 79 */
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 #include "stm32f7xx.h"
sahilmgandhi 18:6a4db94011d3 82 #include "hal_tick.h"
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 HAL_StatusTypeDef HAL_Init(void);
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 #if !defined (HSE_VALUE)
sahilmgandhi 18:6a4db94011d3 87 #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
sahilmgandhi 18:6a4db94011d3 88 #endif /* HSE_VALUE */
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 #if !defined (HSI_VALUE)
sahilmgandhi 18:6a4db94011d3 91 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
sahilmgandhi 18:6a4db94011d3 92 #endif /* HSI_VALUE */
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 /**
sahilmgandhi 18:6a4db94011d3 95 * @}
sahilmgandhi 18:6a4db94011d3 96 */
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /** @addtogroup STM32F7xx_System_Private_TypesDefinitions
sahilmgandhi 18:6a4db94011d3 99 * @{
sahilmgandhi 18:6a4db94011d3 100 */
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 /**
sahilmgandhi 18:6a4db94011d3 103 * @}
sahilmgandhi 18:6a4db94011d3 104 */
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 /** @addtogroup STM32F7xx_System_Private_Defines
sahilmgandhi 18:6a4db94011d3 107 * @{
sahilmgandhi 18:6a4db94011d3 108 */
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 /************************* Miscellaneous Configuration ************************/
sahilmgandhi 18:6a4db94011d3 111 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
sahilmgandhi 18:6a4db94011d3 112 on STMicroelectronics EVAL/Discovery boards as data memory */
sahilmgandhi 18:6a4db94011d3 113 /*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
sahilmgandhi 18:6a4db94011d3 114 need to be added in the project preprocessor to avoid SDRAM multiple configuration
sahilmgandhi 18:6a4db94011d3 115 (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
sahilmgandhi 18:6a4db94011d3 116 /* #define DATA_IN_ExtSRAM */
sahilmgandhi 18:6a4db94011d3 117 /* #define DATA_IN_ExtSDRAM */
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 /*!< Uncomment the following line if you need to relocate your vector Table in
sahilmgandhi 18:6a4db94011d3 120 Internal SRAM. */
sahilmgandhi 18:6a4db94011d3 121 /* #define VECT_TAB_SRAM */
sahilmgandhi 18:6a4db94011d3 122 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
sahilmgandhi 18:6a4db94011d3 123 This value must be a multiple of 0x200. */
sahilmgandhi 18:6a4db94011d3 124 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 /**
sahilmgandhi 18:6a4db94011d3 127 * @}
sahilmgandhi 18:6a4db94011d3 128 */
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 /** @addtogroup STM32F7xx_System_Private_Macros
sahilmgandhi 18:6a4db94011d3 131 * @{
sahilmgandhi 18:6a4db94011d3 132 */
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
sahilmgandhi 18:6a4db94011d3 135 #define USE_PLL_HSE_EXTC (0) /* Use external clock --> NOT USED ON THIS BOARD */
sahilmgandhi 18:6a4db94011d3 136 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 /**
sahilmgandhi 18:6a4db94011d3 139 * @}
sahilmgandhi 18:6a4db94011d3 140 */
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 /** @addtogroup STM32F7xx_System_Private_Variables
sahilmgandhi 18:6a4db94011d3 143 * @{
sahilmgandhi 18:6a4db94011d3 144 */
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 /* This variable is updated in three ways:
sahilmgandhi 18:6a4db94011d3 147 1) by calling CMSIS function SystemCoreClockUpdate()
sahilmgandhi 18:6a4db94011d3 148 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
sahilmgandhi 18:6a4db94011d3 149 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
sahilmgandhi 18:6a4db94011d3 150 Note: If you use this function to configure the system clock; then there
sahilmgandhi 18:6a4db94011d3 151 is no need to call the 2 first functions listed above, since SystemCoreClock
sahilmgandhi 18:6a4db94011d3 152 variable is updated automatically.
sahilmgandhi 18:6a4db94011d3 153 */
sahilmgandhi 18:6a4db94011d3 154 uint32_t SystemCoreClock = HSI_VALUE;
sahilmgandhi 18:6a4db94011d3 155 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
sahilmgandhi 18:6a4db94011d3 156 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 /**
sahilmgandhi 18:6a4db94011d3 159 * @}
sahilmgandhi 18:6a4db94011d3 160 */
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
sahilmgandhi 18:6a4db94011d3 163 * @{
sahilmgandhi 18:6a4db94011d3 164 */
sahilmgandhi 18:6a4db94011d3 165 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
sahilmgandhi 18:6a4db94011d3 166 static void SystemInit_ExtMemCtl(void);
sahilmgandhi 18:6a4db94011d3 167 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
sahilmgandhi 18:6a4db94011d3 170 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
sahilmgandhi 18:6a4db94011d3 171 #endif
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 uint8_t SetSysClock_PLL_HSI(void);
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 /**
sahilmgandhi 18:6a4db94011d3 176 * @}
sahilmgandhi 18:6a4db94011d3 177 */
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 /** @addtogroup STM32F7xx_System_Private_Functions
sahilmgandhi 18:6a4db94011d3 180 * @{
sahilmgandhi 18:6a4db94011d3 181 */
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 /**
sahilmgandhi 18:6a4db94011d3 184 * @brief Setup the microcontroller system
sahilmgandhi 18:6a4db94011d3 185 * Initialize the Embedded Flash Interface, the PLL and update the
sahilmgandhi 18:6a4db94011d3 186 * SystemFrequency variable.
sahilmgandhi 18:6a4db94011d3 187 * @param None
sahilmgandhi 18:6a4db94011d3 188 * @retval None
sahilmgandhi 18:6a4db94011d3 189 */
sahilmgandhi 18:6a4db94011d3 190 void SystemInit(void)
sahilmgandhi 18:6a4db94011d3 191 {
sahilmgandhi 18:6a4db94011d3 192 /* FPU settings ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 193 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sahilmgandhi 18:6a4db94011d3 194 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
sahilmgandhi 18:6a4db94011d3 195 #endif
sahilmgandhi 18:6a4db94011d3 196 /* Reset the RCC clock configuration to the default reset state ------------*/
sahilmgandhi 18:6a4db94011d3 197 /* Set HSION bit */
sahilmgandhi 18:6a4db94011d3 198 RCC->CR |= (uint32_t)0x00000001;
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 /* Reset CFGR register */
sahilmgandhi 18:6a4db94011d3 201 RCC->CFGR = 0x00000000;
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 /* Reset HSEON, CSSON and PLLON bits */
sahilmgandhi 18:6a4db94011d3 204 RCC->CR &= (uint32_t)0xFEF6FFFF;
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 /* Reset PLLCFGR register */
sahilmgandhi 18:6a4db94011d3 207 RCC->PLLCFGR = 0x24003010;
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 /* Reset HSEBYP bit */
sahilmgandhi 18:6a4db94011d3 210 RCC->CR &= (uint32_t)0xFFFBFFFF;
sahilmgandhi 18:6a4db94011d3 211
sahilmgandhi 18:6a4db94011d3 212 /* Disable all interrupts */
sahilmgandhi 18:6a4db94011d3 213 RCC->CIR = 0x00000000;
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
sahilmgandhi 18:6a4db94011d3 216 SystemInit_ExtMemCtl();
sahilmgandhi 18:6a4db94011d3 217 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 /* Configure the Vector Table location add offset address ------------------*/
sahilmgandhi 18:6a4db94011d3 220 #ifdef VECT_TAB_SRAM
sahilmgandhi 18:6a4db94011d3 221 SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
sahilmgandhi 18:6a4db94011d3 222 #else
sahilmgandhi 18:6a4db94011d3 223 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
sahilmgandhi 18:6a4db94011d3 224 #endif
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 /* Configure the Cube driver */
sahilmgandhi 18:6a4db94011d3 227 SystemCoreClock = HSI_VALUE; // At this stage the HSI is used as system clock
sahilmgandhi 18:6a4db94011d3 228 HAL_Init();
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 // Enable CPU L1-Cache
sahilmgandhi 18:6a4db94011d3 231 SCB_EnableICache();
sahilmgandhi 18:6a4db94011d3 232 SCB_EnableDCache();
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 /* Configure the System clock source, PLL Multiplier and Divider factors,
sahilmgandhi 18:6a4db94011d3 235 AHB/APBx prescalers and Flash settings */
sahilmgandhi 18:6a4db94011d3 236 SetSysClock();
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /* Reset the timer to avoid issues after the RAM initialization */
sahilmgandhi 18:6a4db94011d3 239 TIM_MST_RESET_ON;
sahilmgandhi 18:6a4db94011d3 240 TIM_MST_RESET_OFF;
sahilmgandhi 18:6a4db94011d3 241 }
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 /**
sahilmgandhi 18:6a4db94011d3 244 * @brief Update SystemCoreClock variable according to Clock Register Values.
sahilmgandhi 18:6a4db94011d3 245 * The SystemCoreClock variable contains the core clock (HCLK), it can
sahilmgandhi 18:6a4db94011d3 246 * be used by the user application to setup the SysTick timer or configure
sahilmgandhi 18:6a4db94011d3 247 * other parameters.
sahilmgandhi 18:6a4db94011d3 248 *
sahilmgandhi 18:6a4db94011d3 249 * @note Each time the core clock (HCLK) changes, this function must be called
sahilmgandhi 18:6a4db94011d3 250 * to update SystemCoreClock variable value. Otherwise, any configuration
sahilmgandhi 18:6a4db94011d3 251 * based on this variable will be incorrect.
sahilmgandhi 18:6a4db94011d3 252 *
sahilmgandhi 18:6a4db94011d3 253 * @note - The system frequency computed by this function is not the real
sahilmgandhi 18:6a4db94011d3 254 * frequency in the chip. It is calculated based on the predefined
sahilmgandhi 18:6a4db94011d3 255 * constant and the selected clock source:
sahilmgandhi 18:6a4db94011d3 256 *
sahilmgandhi 18:6a4db94011d3 257 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
sahilmgandhi 18:6a4db94011d3 258 *
sahilmgandhi 18:6a4db94011d3 259 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
sahilmgandhi 18:6a4db94011d3 260 *
sahilmgandhi 18:6a4db94011d3 261 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
sahilmgandhi 18:6a4db94011d3 262 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
sahilmgandhi 18:6a4db94011d3 263 *
sahilmgandhi 18:6a4db94011d3 264 * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
sahilmgandhi 18:6a4db94011d3 265 * 16 MHz) but the real value may vary depending on the variations
sahilmgandhi 18:6a4db94011d3 266 * in voltage and temperature.
sahilmgandhi 18:6a4db94011d3 267 *
sahilmgandhi 18:6a4db94011d3 268 * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
sahilmgandhi 18:6a4db94011d3 269 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
sahilmgandhi 18:6a4db94011d3 270 * frequency of the crystal used. Otherwise, this function may
sahilmgandhi 18:6a4db94011d3 271 * have wrong result.
sahilmgandhi 18:6a4db94011d3 272 *
sahilmgandhi 18:6a4db94011d3 273 * - The result of this function could be not correct when using fractional
sahilmgandhi 18:6a4db94011d3 274 * value for HSE crystal.
sahilmgandhi 18:6a4db94011d3 275 *
sahilmgandhi 18:6a4db94011d3 276 * @param None
sahilmgandhi 18:6a4db94011d3 277 * @retval None
sahilmgandhi 18:6a4db94011d3 278 */
sahilmgandhi 18:6a4db94011d3 279 void SystemCoreClockUpdate(void)
sahilmgandhi 18:6a4db94011d3 280 {
sahilmgandhi 18:6a4db94011d3 281 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 /* Get SYSCLK source -------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 284 tmp = RCC->CFGR & RCC_CFGR_SWS;
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 switch (tmp)
sahilmgandhi 18:6a4db94011d3 287 {
sahilmgandhi 18:6a4db94011d3 288 case 0x00: /* HSI used as system clock source */
sahilmgandhi 18:6a4db94011d3 289 SystemCoreClock = HSI_VALUE;
sahilmgandhi 18:6a4db94011d3 290 break;
sahilmgandhi 18:6a4db94011d3 291 case 0x04: /* HSE used as system clock source */
sahilmgandhi 18:6a4db94011d3 292 SystemCoreClock = HSE_VALUE;
sahilmgandhi 18:6a4db94011d3 293 break;
sahilmgandhi 18:6a4db94011d3 294 case 0x08: /* PLL used as system clock source */
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
sahilmgandhi 18:6a4db94011d3 297 SYSCLK = PLL_VCO / PLL_P
sahilmgandhi 18:6a4db94011d3 298 */
sahilmgandhi 18:6a4db94011d3 299 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
sahilmgandhi 18:6a4db94011d3 300 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 if (pllsource != 0)
sahilmgandhi 18:6a4db94011d3 303 {
sahilmgandhi 18:6a4db94011d3 304 /* HSE used as PLL clock source */
sahilmgandhi 18:6a4db94011d3 305 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
sahilmgandhi 18:6a4db94011d3 306 }
sahilmgandhi 18:6a4db94011d3 307 else
sahilmgandhi 18:6a4db94011d3 308 {
sahilmgandhi 18:6a4db94011d3 309 /* HSI used as PLL clock source */
sahilmgandhi 18:6a4db94011d3 310 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
sahilmgandhi 18:6a4db94011d3 311 }
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
sahilmgandhi 18:6a4db94011d3 314 SystemCoreClock = pllvco/pllp;
sahilmgandhi 18:6a4db94011d3 315 break;
sahilmgandhi 18:6a4db94011d3 316 default:
sahilmgandhi 18:6a4db94011d3 317 SystemCoreClock = HSI_VALUE;
sahilmgandhi 18:6a4db94011d3 318 break;
sahilmgandhi 18:6a4db94011d3 319 }
sahilmgandhi 18:6a4db94011d3 320 /* Compute HCLK frequency --------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 321 /* Get HCLK prescaler */
sahilmgandhi 18:6a4db94011d3 322 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
sahilmgandhi 18:6a4db94011d3 323 /* HCLK frequency */
sahilmgandhi 18:6a4db94011d3 324 SystemCoreClock >>= tmp;
sahilmgandhi 18:6a4db94011d3 325 }
sahilmgandhi 18:6a4db94011d3 326
sahilmgandhi 18:6a4db94011d3 327 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
sahilmgandhi 18:6a4db94011d3 328 /**
sahilmgandhi 18:6a4db94011d3 329 * @brief Setup the external memory controller.
sahilmgandhi 18:6a4db94011d3 330 * Called in startup_stm32f7xx.s before jump to main.
sahilmgandhi 18:6a4db94011d3 331 * This function configures the external memories (SRAM/SDRAM)
sahilmgandhi 18:6a4db94011d3 332 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
sahilmgandhi 18:6a4db94011d3 333 * @param None
sahilmgandhi 18:6a4db94011d3 334 * @retval None
sahilmgandhi 18:6a4db94011d3 335 */
sahilmgandhi 18:6a4db94011d3 336 void SystemInit_ExtMemCtl(void)
sahilmgandhi 18:6a4db94011d3 337 {
sahilmgandhi 18:6a4db94011d3 338 __IO uint32_t tmp = 0;
sahilmgandhi 18:6a4db94011d3 339 #if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
sahilmgandhi 18:6a4db94011d3 340 register uint32_t tmpreg = 0, timeout = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 341 register uint32_t index;
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
sahilmgandhi 18:6a4db94011d3 344 clock */
sahilmgandhi 18:6a4db94011d3 345 RCC->AHB1ENR |= 0x000001F8;
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 /* Delay after an RCC peripheral clock enabling */
sahilmgandhi 18:6a4db94011d3 348 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 /* Connect PDx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 351 GPIOD->AFR[0] = 0x00CCC0CC;
sahilmgandhi 18:6a4db94011d3 352 GPIOD->AFR[1] = 0xCCCCCCCC;
sahilmgandhi 18:6a4db94011d3 353 /* Configure PDx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 354 GPIOD->MODER = 0xAAAA0A8A;
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 /* Configure PDx pins speed to 100 MHz */
sahilmgandhi 18:6a4db94011d3 357 GPIOD->OSPEEDR = 0xFFFF0FCF;
sahilmgandhi 18:6a4db94011d3 358 /* Configure PDx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 359 GPIOD->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 360 /* No pull-up, pull-down for PDx pins */
sahilmgandhi 18:6a4db94011d3 361 GPIOD->PUPDR = 0x55550545;
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 /* Connect PEx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 364 GPIOE->AFR[0] = 0xC00CC0CC;
sahilmgandhi 18:6a4db94011d3 365 GPIOE->AFR[1] = 0xCCCCCCCC;
sahilmgandhi 18:6a4db94011d3 366 /* Configure PEx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 367 GPIOE->MODER = 0xAAAA828A;
sahilmgandhi 18:6a4db94011d3 368 /* Configure PEx pins speed to 50 MHz */
sahilmgandhi 18:6a4db94011d3 369 GPIOE->OSPEEDR = 0xFFFFC3CF;
sahilmgandhi 18:6a4db94011d3 370 /* Configure PEx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 371 GPIOE->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 372 /* No pull-up, pull-down for PEx pins */
sahilmgandhi 18:6a4db94011d3 373 GPIOE->PUPDR = 0x55554145;
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375 /* Connect PFx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 376 GPIOF->AFR[0] = 0x00CCCCCC;
sahilmgandhi 18:6a4db94011d3 377 GPIOF->AFR[1] = 0xCCCCC000;
sahilmgandhi 18:6a4db94011d3 378 /* Configure PFx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 379 GPIOF->MODER = 0xAA800AAA;
sahilmgandhi 18:6a4db94011d3 380 /* Configure PFx pins speed to 50 MHz */
sahilmgandhi 18:6a4db94011d3 381 GPIOF->OSPEEDR = 0xFF800FFF;
sahilmgandhi 18:6a4db94011d3 382 /* Configure PFx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 383 GPIOF->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 384 /* No pull-up, pull-down for PFx pins */
sahilmgandhi 18:6a4db94011d3 385 GPIOF->PUPDR = 0x55400555;
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 /* Connect PGx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 388 GPIOG->AFR[0] = 0x00CC00CC;
sahilmgandhi 18:6a4db94011d3 389 GPIOG->AFR[1] = 0xC00000CC;
sahilmgandhi 18:6a4db94011d3 390 /* Configure PGx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 391 GPIOG->MODER = 0x80220AAA;
sahilmgandhi 18:6a4db94011d3 392 /* Configure PGx pins speed to 50 MHz */
sahilmgandhi 18:6a4db94011d3 393 GPIOG->OSPEEDR = 0x80320FFF;
sahilmgandhi 18:6a4db94011d3 394 /* Configure PGx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 395 GPIOG->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 396 /* No pull-up, pull-down for PGx pins */
sahilmgandhi 18:6a4db94011d3 397 GPIOG->PUPDR = 0x40110555;
sahilmgandhi 18:6a4db94011d3 398
sahilmgandhi 18:6a4db94011d3 399 /* Connect PHx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 400 GPIOH->AFR[0] = 0x00C0CC00;
sahilmgandhi 18:6a4db94011d3 401 GPIOH->AFR[1] = 0xCCCCCCCC;
sahilmgandhi 18:6a4db94011d3 402 /* Configure PHx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 403 GPIOH->MODER = 0xAAAA08A0;
sahilmgandhi 18:6a4db94011d3 404 /* Configure PHx pins speed to 50 MHz */
sahilmgandhi 18:6a4db94011d3 405 GPIOH->OSPEEDR = 0xAAAA08A0;
sahilmgandhi 18:6a4db94011d3 406 /* Configure PHx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 407 GPIOH->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 408 /* No pull-up, pull-down for PHx pins */
sahilmgandhi 18:6a4db94011d3 409 GPIOH->PUPDR = 0x55550450;
sahilmgandhi 18:6a4db94011d3 410
sahilmgandhi 18:6a4db94011d3 411 /* Connect PIx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 412 GPIOI->AFR[0] = 0xCCCCCCCC;
sahilmgandhi 18:6a4db94011d3 413 GPIOI->AFR[1] = 0x00000CC0;
sahilmgandhi 18:6a4db94011d3 414 /* Configure PIx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 415 GPIOI->MODER = 0x0028AAAA;
sahilmgandhi 18:6a4db94011d3 416 /* Configure PIx pins speed to 50 MHz */
sahilmgandhi 18:6a4db94011d3 417 GPIOI->OSPEEDR = 0x0028AAAA;
sahilmgandhi 18:6a4db94011d3 418 /* Configure PIx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 419 GPIOI->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 420 /* No pull-up, pull-down for PIx pins */
sahilmgandhi 18:6a4db94011d3 421 GPIOI->PUPDR = 0x00145555;
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 /*-- FMC Configuration ------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 424 /* Enable the FMC interface clock */
sahilmgandhi 18:6a4db94011d3 425 RCC->AHB3ENR |= 0x00000001;
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 /* Delay after an RCC peripheral clock enabling */
sahilmgandhi 18:6a4db94011d3 428 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 /* Configure and enable Bank1_SRAM2 */
sahilmgandhi 18:6a4db94011d3 431 FMC_Bank1->BTCR[4] = 0x00001091;
sahilmgandhi 18:6a4db94011d3 432 FMC_Bank1->BTCR[5] = 0x00110212;
sahilmgandhi 18:6a4db94011d3 433 FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
sahilmgandhi 18:6a4db94011d3 434
sahilmgandhi 18:6a4db94011d3 435 /* Configure and enable SDRAM bank1 */
sahilmgandhi 18:6a4db94011d3 436 FMC_Bank5_6->SDCR[0] = 0x000019E5;
sahilmgandhi 18:6a4db94011d3 437 FMC_Bank5_6->SDTR[0] = 0x01116361;
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 /* SDRAM initialization sequence */
sahilmgandhi 18:6a4db94011d3 440 /* Clock enable command */
sahilmgandhi 18:6a4db94011d3 441 FMC_Bank5_6->SDCMR = 0x00000011;
sahilmgandhi 18:6a4db94011d3 442 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi 18:6a4db94011d3 443 while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi 18:6a4db94011d3 444 {
sahilmgandhi 18:6a4db94011d3 445 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi 18:6a4db94011d3 446 }
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 /* Delay */
sahilmgandhi 18:6a4db94011d3 449 for (index = 0; index<1000; index++);
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 /* PALL command */
sahilmgandhi 18:6a4db94011d3 452 FMC_Bank5_6->SDCMR = 0x00000012;
sahilmgandhi 18:6a4db94011d3 453 timeout = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 454 while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi 18:6a4db94011d3 455 {
sahilmgandhi 18:6a4db94011d3 456 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi 18:6a4db94011d3 457 }
sahilmgandhi 18:6a4db94011d3 458
sahilmgandhi 18:6a4db94011d3 459 /* Auto refresh command */
sahilmgandhi 18:6a4db94011d3 460 FMC_Bank5_6->SDCMR = 0x000000F3;
sahilmgandhi 18:6a4db94011d3 461 timeout = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 462 while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi 18:6a4db94011d3 463 {
sahilmgandhi 18:6a4db94011d3 464 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi 18:6a4db94011d3 465 }
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 /* MRD register program */
sahilmgandhi 18:6a4db94011d3 468 FMC_Bank5_6->SDCMR = 0x00046014;
sahilmgandhi 18:6a4db94011d3 469 timeout = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 470 while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi 18:6a4db94011d3 471 {
sahilmgandhi 18:6a4db94011d3 472 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi 18:6a4db94011d3 473 }
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /* Set refresh count */
sahilmgandhi 18:6a4db94011d3 476 tmpreg = FMC_Bank5_6->SDRTR;
sahilmgandhi 18:6a4db94011d3 477 FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 /* Disable write protection */
sahilmgandhi 18:6a4db94011d3 480 tmpreg = FMC_Bank5_6->SDCR[0];
sahilmgandhi 18:6a4db94011d3 481 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 #elif defined (DATA_IN_ExtSDRAM)
sahilmgandhi 18:6a4db94011d3 484 register uint32_t tmpreg = 0, timeout = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 485 register uint32_t index;
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
sahilmgandhi 18:6a4db94011d3 488 clock */
sahilmgandhi 18:6a4db94011d3 489 RCC->AHB1ENR |= 0x000001F8;
sahilmgandhi 18:6a4db94011d3 490
sahilmgandhi 18:6a4db94011d3 491 /* Delay after an RCC peripheral clock enabling */
sahilmgandhi 18:6a4db94011d3 492 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 /* Connect PDx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 495 GPIOD->AFR[0] = 0x000000CC;
sahilmgandhi 18:6a4db94011d3 496 GPIOD->AFR[1] = 0xCC000CCC;
sahilmgandhi 18:6a4db94011d3 497 /* Configure PDx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 498 GPIOD->MODER = 0xA02A000A;
sahilmgandhi 18:6a4db94011d3 499 /* Configure PDx pins speed to 50 MHz */
sahilmgandhi 18:6a4db94011d3 500 GPIOD->OSPEEDR = 0xA02A000A;
sahilmgandhi 18:6a4db94011d3 501 /* Configure PDx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 502 GPIOD->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 503 /* No pull-up, pull-down for PDx pins */
sahilmgandhi 18:6a4db94011d3 504 GPIOD->PUPDR = 0x50150005;
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 /* Connect PEx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 507 GPIOE->AFR[0] = 0xC00000CC;
sahilmgandhi 18:6a4db94011d3 508 GPIOE->AFR[1] = 0xCCCCCCCC;
sahilmgandhi 18:6a4db94011d3 509 /* Configure PEx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 510 GPIOE->MODER = 0xAAAA800A;
sahilmgandhi 18:6a4db94011d3 511 /* Configure PEx pins speed to 50 MHz */
sahilmgandhi 18:6a4db94011d3 512 GPIOE->OSPEEDR = 0xAAAA800A;
sahilmgandhi 18:6a4db94011d3 513 /* Configure PEx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 514 GPIOE->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 515 /* No pull-up, pull-down for PEx pins */
sahilmgandhi 18:6a4db94011d3 516 GPIOE->PUPDR = 0x55554005;
sahilmgandhi 18:6a4db94011d3 517
sahilmgandhi 18:6a4db94011d3 518 /* Connect PFx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 519 GPIOF->AFR[0] = 0x00CCCCCC;
sahilmgandhi 18:6a4db94011d3 520 GPIOF->AFR[1] = 0xCCCCC000;
sahilmgandhi 18:6a4db94011d3 521 /* Configure PFx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 522 GPIOF->MODER = 0xAA800AAA;
sahilmgandhi 18:6a4db94011d3 523 /* Configure PFx pins speed to 50 MHz */
sahilmgandhi 18:6a4db94011d3 524 GPIOF->OSPEEDR = 0xAA800AAA;
sahilmgandhi 18:6a4db94011d3 525 /* Configure PFx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 526 GPIOF->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 527 /* No pull-up, pull-down for PFx pins */
sahilmgandhi 18:6a4db94011d3 528 GPIOF->PUPDR = 0x55400555;
sahilmgandhi 18:6a4db94011d3 529
sahilmgandhi 18:6a4db94011d3 530 /* Connect PGx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 531 GPIOG->AFR[0] = 0x00CC00CC;
sahilmgandhi 18:6a4db94011d3 532 GPIOG->AFR[1] = 0xC000000C;
sahilmgandhi 18:6a4db94011d3 533 /* Configure PGx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 534 GPIOG->MODER = 0x80020A0A;
sahilmgandhi 18:6a4db94011d3 535 /* Configure PGx pins speed to 50 MHz */
sahilmgandhi 18:6a4db94011d3 536 GPIOG->OSPEEDR = 0x80020A0A;
sahilmgandhi 18:6a4db94011d3 537 /* Configure PGx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 538 GPIOG->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 539 /* No pull-up, pull-down for PGx pins */
sahilmgandhi 18:6a4db94011d3 540 GPIOG->PUPDR = 0x40010505;
sahilmgandhi 18:6a4db94011d3 541
sahilmgandhi 18:6a4db94011d3 542 /* Connect PHx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 543 GPIOH->AFR[0] = 0x00C0CC00;
sahilmgandhi 18:6a4db94011d3 544 GPIOH->AFR[1] = 0xCCCCCCCC;
sahilmgandhi 18:6a4db94011d3 545 /* Configure PHx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 546 GPIOH->MODER = 0xAAAA08A0;
sahilmgandhi 18:6a4db94011d3 547 /* Configure PHx pins speed to 50 MHz */
sahilmgandhi 18:6a4db94011d3 548 GPIOH->OSPEEDR = 0xAAAA08A0;
sahilmgandhi 18:6a4db94011d3 549 /* Configure PHx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 550 GPIOH->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 551 /* No pull-up, pull-down for PHx pins */
sahilmgandhi 18:6a4db94011d3 552 GPIOH->PUPDR = 0x55550450;
sahilmgandhi 18:6a4db94011d3 553
sahilmgandhi 18:6a4db94011d3 554 /* Connect PIx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 555 GPIOI->AFR[0] = 0xCCCCCCCC;
sahilmgandhi 18:6a4db94011d3 556 GPIOI->AFR[1] = 0x00000CC0;
sahilmgandhi 18:6a4db94011d3 557 /* Configure PIx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 558 GPIOI->MODER = 0x0028AAAA;
sahilmgandhi 18:6a4db94011d3 559 /* Configure PIx pins speed to 50 MHz */
sahilmgandhi 18:6a4db94011d3 560 GPIOI->OSPEEDR = 0x0028AAAA;
sahilmgandhi 18:6a4db94011d3 561 /* Configure PIx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 562 GPIOI->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 563 /* No pull-up, pull-down for PIx pins */
sahilmgandhi 18:6a4db94011d3 564 GPIOI->PUPDR = 0x00145555;
sahilmgandhi 18:6a4db94011d3 565
sahilmgandhi 18:6a4db94011d3 566 /*-- FMC Configuration ------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 567 /* Enable the FMC interface clock */
sahilmgandhi 18:6a4db94011d3 568 RCC->AHB3ENR |= 0x00000001;
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 /* Delay after an RCC peripheral clock enabling */
sahilmgandhi 18:6a4db94011d3 571 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 /* Configure and enable SDRAM bank1 */
sahilmgandhi 18:6a4db94011d3 574 FMC_Bank5_6->SDCR[0] = 0x000019E5;
sahilmgandhi 18:6a4db94011d3 575 FMC_Bank5_6->SDTR[0] = 0x01116361;
sahilmgandhi 18:6a4db94011d3 576
sahilmgandhi 18:6a4db94011d3 577 /* SDRAM initialization sequence */
sahilmgandhi 18:6a4db94011d3 578 /* Clock enable command */
sahilmgandhi 18:6a4db94011d3 579 FMC_Bank5_6->SDCMR = 0x00000011;
sahilmgandhi 18:6a4db94011d3 580 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi 18:6a4db94011d3 581 while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi 18:6a4db94011d3 582 {
sahilmgandhi 18:6a4db94011d3 583 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi 18:6a4db94011d3 584 }
sahilmgandhi 18:6a4db94011d3 585
sahilmgandhi 18:6a4db94011d3 586 /* Delay */
sahilmgandhi 18:6a4db94011d3 587 for (index = 0; index<1000; index++);
sahilmgandhi 18:6a4db94011d3 588
sahilmgandhi 18:6a4db94011d3 589 /* PALL command */
sahilmgandhi 18:6a4db94011d3 590 FMC_Bank5_6->SDCMR = 0x00000012;
sahilmgandhi 18:6a4db94011d3 591 timeout = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 592 while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi 18:6a4db94011d3 593 {
sahilmgandhi 18:6a4db94011d3 594 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi 18:6a4db94011d3 595 }
sahilmgandhi 18:6a4db94011d3 596
sahilmgandhi 18:6a4db94011d3 597 /* Auto refresh command */
sahilmgandhi 18:6a4db94011d3 598 FMC_Bank5_6->SDCMR = 0x000000F3;
sahilmgandhi 18:6a4db94011d3 599 timeout = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 600 while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi 18:6a4db94011d3 601 {
sahilmgandhi 18:6a4db94011d3 602 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi 18:6a4db94011d3 603 }
sahilmgandhi 18:6a4db94011d3 604
sahilmgandhi 18:6a4db94011d3 605 /* MRD register program */
sahilmgandhi 18:6a4db94011d3 606 FMC_Bank5_6->SDCMR = 0x00046014;
sahilmgandhi 18:6a4db94011d3 607 timeout = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 608 while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi 18:6a4db94011d3 609 {
sahilmgandhi 18:6a4db94011d3 610 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi 18:6a4db94011d3 611 }
sahilmgandhi 18:6a4db94011d3 612
sahilmgandhi 18:6a4db94011d3 613 /* Set refresh count */
sahilmgandhi 18:6a4db94011d3 614 tmpreg = FMC_Bank5_6->SDRTR;
sahilmgandhi 18:6a4db94011d3 615 FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
sahilmgandhi 18:6a4db94011d3 616
sahilmgandhi 18:6a4db94011d3 617 /* Disable write protection */
sahilmgandhi 18:6a4db94011d3 618 tmpreg = FMC_Bank5_6->SDCR[0];
sahilmgandhi 18:6a4db94011d3 619 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
sahilmgandhi 18:6a4db94011d3 620
sahilmgandhi 18:6a4db94011d3 621 #elif defined(DATA_IN_ExtSRAM)
sahilmgandhi 18:6a4db94011d3 622 /*-- GPIOs Configuration -----------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 623 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
sahilmgandhi 18:6a4db94011d3 624 RCC->AHB1ENR |= 0x00000078;
sahilmgandhi 18:6a4db94011d3 625
sahilmgandhi 18:6a4db94011d3 626 /* Delay after an RCC peripheral clock enabling */
sahilmgandhi 18:6a4db94011d3 627 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
sahilmgandhi 18:6a4db94011d3 628
sahilmgandhi 18:6a4db94011d3 629 /* Connect PDx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 630 GPIOD->AFR[0] = 0x00CCC0CC;
sahilmgandhi 18:6a4db94011d3 631 GPIOD->AFR[1] = 0xCCCCCCCC;
sahilmgandhi 18:6a4db94011d3 632 /* Configure PDx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 633 GPIOD->MODER = 0xAAAA0A8A;
sahilmgandhi 18:6a4db94011d3 634 /* Configure PDx pins speed to 100 MHz */
sahilmgandhi 18:6a4db94011d3 635 GPIOD->OSPEEDR = 0xFFFF0FCF;
sahilmgandhi 18:6a4db94011d3 636 /* Configure PDx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 637 GPIOD->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 638 /* No pull-up, pull-down for PDx pins */
sahilmgandhi 18:6a4db94011d3 639 GPIOD->PUPDR = 0x55550545;
sahilmgandhi 18:6a4db94011d3 640
sahilmgandhi 18:6a4db94011d3 641 /* Connect PEx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 642 GPIOE->AFR[0] = 0xC00CC0CC;
sahilmgandhi 18:6a4db94011d3 643 GPIOE->AFR[1] = 0xCCCCCCCC;
sahilmgandhi 18:6a4db94011d3 644 /* Configure PEx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 645 GPIOE->MODER = 0xAAAA828A;
sahilmgandhi 18:6a4db94011d3 646 /* Configure PEx pins speed to 100 MHz */
sahilmgandhi 18:6a4db94011d3 647 GPIOE->OSPEEDR = 0xFFFFC3CF;
sahilmgandhi 18:6a4db94011d3 648 /* Configure PEx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 649 GPIOE->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 650 /* No pull-up, pull-down for PEx pins */
sahilmgandhi 18:6a4db94011d3 651 GPIOE->PUPDR = 0x55554145;
sahilmgandhi 18:6a4db94011d3 652
sahilmgandhi 18:6a4db94011d3 653 /* Connect PFx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 654 GPIOF->AFR[0] = 0x00CCCCCC;
sahilmgandhi 18:6a4db94011d3 655 GPIOF->AFR[1] = 0xCCCC0000;
sahilmgandhi 18:6a4db94011d3 656 /* Configure PFx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 657 GPIOF->MODER = 0xAA000AAA;
sahilmgandhi 18:6a4db94011d3 658 /* Configure PFx pins speed to 100 MHz */
sahilmgandhi 18:6a4db94011d3 659 GPIOF->OSPEEDR = 0xFF000FFF;
sahilmgandhi 18:6a4db94011d3 660 /* Configure PFx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 661 GPIOF->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 662 /* No pull-up, pull-down for PFx pins */
sahilmgandhi 18:6a4db94011d3 663 GPIOF->PUPDR = 0x55000555;
sahilmgandhi 18:6a4db94011d3 664
sahilmgandhi 18:6a4db94011d3 665 /* Connect PGx pins to FMC Alternate function */
sahilmgandhi 18:6a4db94011d3 666 GPIOG->AFR[0] = 0x00CCCCCC;
sahilmgandhi 18:6a4db94011d3 667 GPIOG->AFR[1] = 0x000000C0;
sahilmgandhi 18:6a4db94011d3 668 /* Configure PGx pins in Alternate function mode */
sahilmgandhi 18:6a4db94011d3 669 GPIOG->MODER = 0x00200AAA;
sahilmgandhi 18:6a4db94011d3 670 /* Configure PGx pins speed to 100 MHz */
sahilmgandhi 18:6a4db94011d3 671 GPIOG->OSPEEDR = 0x00300FFF;
sahilmgandhi 18:6a4db94011d3 672 /* Configure PGx pins Output type to push-pull */
sahilmgandhi 18:6a4db94011d3 673 GPIOG->OTYPER = 0x00000000;
sahilmgandhi 18:6a4db94011d3 674 /* No pull-up, pull-down for PGx pins */
sahilmgandhi 18:6a4db94011d3 675 GPIOG->PUPDR = 0x00100555;
sahilmgandhi 18:6a4db94011d3 676
sahilmgandhi 18:6a4db94011d3 677 /*-- FMC/FSMC Configuration --------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 678 /* Enable the FMC/FSMC interface clock */
sahilmgandhi 18:6a4db94011d3 679 RCC->AHB3ENR |= 0x00000001;
sahilmgandhi 18:6a4db94011d3 680
sahilmgandhi 18:6a4db94011d3 681 /* Delay after an RCC peripheral clock enabling */
sahilmgandhi 18:6a4db94011d3 682 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
sahilmgandhi 18:6a4db94011d3 683
sahilmgandhi 18:6a4db94011d3 684 /* Configure and enable Bank1_SRAM2 */
sahilmgandhi 18:6a4db94011d3 685 FMC_Bank1->BTCR[4] = 0x00001091;
sahilmgandhi 18:6a4db94011d3 686 FMC_Bank1->BTCR[5] = 0x00110212;
sahilmgandhi 18:6a4db94011d3 687 FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
sahilmgandhi 18:6a4db94011d3 688
sahilmgandhi 18:6a4db94011d3 689 #endif /* DATA_IN_ExtSRAM */
sahilmgandhi 18:6a4db94011d3 690
sahilmgandhi 18:6a4db94011d3 691 (void)(tmp);
sahilmgandhi 18:6a4db94011d3 692 }
sahilmgandhi 18:6a4db94011d3 693 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
sahilmgandhi 18:6a4db94011d3 694
sahilmgandhi 18:6a4db94011d3 695 /**
sahilmgandhi 18:6a4db94011d3 696 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
sahilmgandhi 18:6a4db94011d3 697 * AHB/APBx prescalers and Flash settings
sahilmgandhi 18:6a4db94011d3 698 * @note This function should be called only once the RCC clock configuration
sahilmgandhi 18:6a4db94011d3 699 * is reset to the default reset state (done in SystemInit() function).
sahilmgandhi 18:6a4db94011d3 700 * @param None
sahilmgandhi 18:6a4db94011d3 701 * @retval None
sahilmgandhi 18:6a4db94011d3 702 */
sahilmgandhi 18:6a4db94011d3 703 void SetSysClock(void)
sahilmgandhi 18:6a4db94011d3 704 {
sahilmgandhi 18:6a4db94011d3 705 /* 1- Try to start with HSE and external clock */
sahilmgandhi 18:6a4db94011d3 706 #if USE_PLL_HSE_EXTC != 0
sahilmgandhi 18:6a4db94011d3 707 if (SetSysClock_PLL_HSE(1) == 0)
sahilmgandhi 18:6a4db94011d3 708 #endif
sahilmgandhi 18:6a4db94011d3 709 {
sahilmgandhi 18:6a4db94011d3 710 /* 2- If fail try to start with HSE and external xtal */
sahilmgandhi 18:6a4db94011d3 711 #if USE_PLL_HSE_XTAL != 0
sahilmgandhi 18:6a4db94011d3 712 if (SetSysClock_PLL_HSE(0) == 0)
sahilmgandhi 18:6a4db94011d3 713 #endif
sahilmgandhi 18:6a4db94011d3 714 {
sahilmgandhi 18:6a4db94011d3 715 /* 3- If fail start with HSI clock */
sahilmgandhi 18:6a4db94011d3 716 if (SetSysClock_PLL_HSI() == 0)
sahilmgandhi 18:6a4db94011d3 717 {
sahilmgandhi 18:6a4db94011d3 718 while(1)
sahilmgandhi 18:6a4db94011d3 719 {
sahilmgandhi 18:6a4db94011d3 720 // [TODO] Put something here to tell the user that a problem occured...
sahilmgandhi 18:6a4db94011d3 721 }
sahilmgandhi 18:6a4db94011d3 722 }
sahilmgandhi 18:6a4db94011d3 723 }
sahilmgandhi 18:6a4db94011d3 724 }
sahilmgandhi 18:6a4db94011d3 725
sahilmgandhi 18:6a4db94011d3 726 // Output clock on MCO2 pin(PC9) for debugging purpose
sahilmgandhi 18:6a4db94011d3 727 // Can be visualized on CN8 connector pin 4
sahilmgandhi 18:6a4db94011d3 728 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
sahilmgandhi 18:6a4db94011d3 729 }
sahilmgandhi 18:6a4db94011d3 730
sahilmgandhi 18:6a4db94011d3 731 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
sahilmgandhi 18:6a4db94011d3 732 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 733 /* PLL (clocked by HSE) used as System clock source */
sahilmgandhi 18:6a4db94011d3 734 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 735 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
sahilmgandhi 18:6a4db94011d3 736 {
sahilmgandhi 18:6a4db94011d3 737 RCC_ClkInitTypeDef RCC_ClkInitStruct;
sahilmgandhi 18:6a4db94011d3 738 RCC_OscInitTypeDef RCC_OscInitStruct;
sahilmgandhi 18:6a4db94011d3 739 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
sahilmgandhi 18:6a4db94011d3 740
sahilmgandhi 18:6a4db94011d3 741 // Enable power clock
sahilmgandhi 18:6a4db94011d3 742 __PWR_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 743
sahilmgandhi 18:6a4db94011d3 744 // Enable HSE oscillator and activate PLL with HSE as source
sahilmgandhi 18:6a4db94011d3 745 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
sahilmgandhi 18:6a4db94011d3 746 if (bypass == 0)
sahilmgandhi 18:6a4db94011d3 747 {
sahilmgandhi 18:6a4db94011d3 748 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
sahilmgandhi 18:6a4db94011d3 749 }
sahilmgandhi 18:6a4db94011d3 750 else
sahilmgandhi 18:6a4db94011d3 751 {
sahilmgandhi 18:6a4db94011d3 752 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */
sahilmgandhi 18:6a4db94011d3 753 }
sahilmgandhi 18:6a4db94011d3 754 // Warning: this configuration is for a 25 MHz xtal clock only
sahilmgandhi 18:6a4db94011d3 755 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
sahilmgandhi 18:6a4db94011d3 756 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
sahilmgandhi 18:6a4db94011d3 757 RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25)
sahilmgandhi 18:6a4db94011d3 758 RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
sahilmgandhi 18:6a4db94011d3 759 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
sahilmgandhi 18:6a4db94011d3 760 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
sahilmgandhi 18:6a4db94011d3 761 RCC_OscInitStruct.PLL.PLLR = 2;
sahilmgandhi 18:6a4db94011d3 762
sahilmgandhi 18:6a4db94011d3 763 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 764 {
sahilmgandhi 18:6a4db94011d3 765 return 0; // FAIL
sahilmgandhi 18:6a4db94011d3 766 }
sahilmgandhi 18:6a4db94011d3 767
sahilmgandhi 18:6a4db94011d3 768 // Activate the OverDrive to reach the 216 MHz Frequency
sahilmgandhi 18:6a4db94011d3 769 if (HAL_PWREx_EnableOverDrive() != HAL_OK)
sahilmgandhi 18:6a4db94011d3 770 {
sahilmgandhi 18:6a4db94011d3 771 return 0; // FAIL
sahilmgandhi 18:6a4db94011d3 772 }
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 /* Select PLLSAI output as USB clock source */
sahilmgandhi 18:6a4db94011d3 775 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
sahilmgandhi 18:6a4db94011d3 776 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP;
sahilmgandhi 18:6a4db94011d3 777 PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
sahilmgandhi 18:6a4db94011d3 778 PeriphClkInitStruct.PLLSAI.PLLSAIQ = 7;
sahilmgandhi 18:6a4db94011d3 779 PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
sahilmgandhi 18:6a4db94011d3 780 if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 781 {
sahilmgandhi 18:6a4db94011d3 782 return 0; // FAIL
sahilmgandhi 18:6a4db94011d3 783 }
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
sahilmgandhi 18:6a4db94011d3 786 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
sahilmgandhi 18:6a4db94011d3 787 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
sahilmgandhi 18:6a4db94011d3 788 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
sahilmgandhi 18:6a4db94011d3 789 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
sahilmgandhi 18:6a4db94011d3 790 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
sahilmgandhi 18:6a4db94011d3 791
sahilmgandhi 18:6a4db94011d3 792 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 793 {
sahilmgandhi 18:6a4db94011d3 794 return 0; // FAIL
sahilmgandhi 18:6a4db94011d3 795 }
sahilmgandhi 18:6a4db94011d3 796
sahilmgandhi 18:6a4db94011d3 797 return 1; // OK
sahilmgandhi 18:6a4db94011d3 798 }
sahilmgandhi 18:6a4db94011d3 799 #endif
sahilmgandhi 18:6a4db94011d3 800
sahilmgandhi 18:6a4db94011d3 801 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 802 /* PLL (clocked by HSI) used as System clock source */
sahilmgandhi 18:6a4db94011d3 803 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 804 uint8_t SetSysClock_PLL_HSI(void)
sahilmgandhi 18:6a4db94011d3 805 {
sahilmgandhi 18:6a4db94011d3 806 RCC_ClkInitTypeDef RCC_ClkInitStruct;
sahilmgandhi 18:6a4db94011d3 807 RCC_OscInitTypeDef RCC_OscInitStruct;
sahilmgandhi 18:6a4db94011d3 808
sahilmgandhi 18:6a4db94011d3 809 // Enable CPU L1-Cache
sahilmgandhi 18:6a4db94011d3 810 SCB_EnableICache();
sahilmgandhi 18:6a4db94011d3 811 SCB_EnableDCache();
sahilmgandhi 18:6a4db94011d3 812
sahilmgandhi 18:6a4db94011d3 813 // Enable power clock
sahilmgandhi 18:6a4db94011d3 814 __PWR_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 815
sahilmgandhi 18:6a4db94011d3 816 // Enable HSI oscillator and activate PLL with HSI as source
sahilmgandhi 18:6a4db94011d3 817 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
sahilmgandhi 18:6a4db94011d3 818 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
sahilmgandhi 18:6a4db94011d3 819 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
sahilmgandhi 18:6a4db94011d3 820 RCC_OscInitStruct.HSICalibrationValue = 16;
sahilmgandhi 18:6a4db94011d3 821 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
sahilmgandhi 18:6a4db94011d3 822 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
sahilmgandhi 18:6a4db94011d3 823 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
sahilmgandhi 18:6a4db94011d3 824 RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
sahilmgandhi 18:6a4db94011d3 825 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
sahilmgandhi 18:6a4db94011d3 826 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
sahilmgandhi 18:6a4db94011d3 827 RCC_OscInitStruct.PLL.PLLR = 2;
sahilmgandhi 18:6a4db94011d3 828
sahilmgandhi 18:6a4db94011d3 829 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 830 {
sahilmgandhi 18:6a4db94011d3 831 return 0; // FAIL
sahilmgandhi 18:6a4db94011d3 832 }
sahilmgandhi 18:6a4db94011d3 833
sahilmgandhi 18:6a4db94011d3 834 // Activate the OverDrive to reach the 216 MHz Frequency
sahilmgandhi 18:6a4db94011d3 835 if (HAL_PWREx_EnableOverDrive() != HAL_OK)
sahilmgandhi 18:6a4db94011d3 836 {
sahilmgandhi 18:6a4db94011d3 837 return 0; // FAIL
sahilmgandhi 18:6a4db94011d3 838 }
sahilmgandhi 18:6a4db94011d3 839
sahilmgandhi 18:6a4db94011d3 840 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
sahilmgandhi 18:6a4db94011d3 841 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
sahilmgandhi 18:6a4db94011d3 842 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
sahilmgandhi 18:6a4db94011d3 843 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
sahilmgandhi 18:6a4db94011d3 844 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
sahilmgandhi 18:6a4db94011d3 845 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
sahilmgandhi 18:6a4db94011d3 846
sahilmgandhi 18:6a4db94011d3 847 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 848 {
sahilmgandhi 18:6a4db94011d3 849 return 0; // FAIL
sahilmgandhi 18:6a4db94011d3 850 }
sahilmgandhi 18:6a4db94011d3 851
sahilmgandhi 18:6a4db94011d3 852 return 1; // OK
sahilmgandhi 18:6a4db94011d3 853 }
sahilmgandhi 18:6a4db94011d3 854
sahilmgandhi 18:6a4db94011d3 855 /**
sahilmgandhi 18:6a4db94011d3 856 * @}
sahilmgandhi 18:6a4db94011d3 857 */
sahilmgandhi 18:6a4db94011d3 858
sahilmgandhi 18:6a4db94011d3 859 /**
sahilmgandhi 18:6a4db94011d3 860 * @}
sahilmgandhi 18:6a4db94011d3 861 */
sahilmgandhi 18:6a4db94011d3 862
sahilmgandhi 18:6a4db94011d3 863 /**
sahilmgandhi 18:6a4db94011d3 864 * @}
sahilmgandhi 18:6a4db94011d3 865 */
sahilmgandhi 18:6a4db94011d3 866 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/