MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_nor.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of NOR HAL module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32F4xx_HAL_NOR_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32F4xx_HAL_NOR_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
sahilmgandhi 18:6a4db94011d3 48 defined(STM32F412Vx)
sahilmgandhi 18:6a4db94011d3 49 #include "stm32f4xx_ll_fsmc.h"
sahilmgandhi 18:6a4db94011d3 50 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
sahilmgandhi 18:6a4db94011d3 53 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 54 #include "stm32f4xx_ll_fmc.h"
sahilmgandhi 18:6a4db94011d3 55 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 58 * @{
sahilmgandhi 18:6a4db94011d3 59 */
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 /** @addtogroup NOR
sahilmgandhi 18:6a4db94011d3 62 * @{
sahilmgandhi 18:6a4db94011d3 63 */
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
sahilmgandhi 18:6a4db94011d3 66 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
sahilmgandhi 18:6a4db94011d3 67 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
sahilmgandhi 18:6a4db94011d3 68 defined(STM32F412Vx)
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 /* Exported typedef ----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 71 /** @defgroup NOR_Exported_Types NOR Exported Types
sahilmgandhi 18:6a4db94011d3 72 * @{
sahilmgandhi 18:6a4db94011d3 73 */
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 /**
sahilmgandhi 18:6a4db94011d3 76 * @brief HAL SRAM State structures definition
sahilmgandhi 18:6a4db94011d3 77 */
sahilmgandhi 18:6a4db94011d3 78 typedef enum
sahilmgandhi 18:6a4db94011d3 79 {
sahilmgandhi 18:6a4db94011d3 80 HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
sahilmgandhi 18:6a4db94011d3 81 HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
sahilmgandhi 18:6a4db94011d3 82 HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
sahilmgandhi 18:6a4db94011d3 83 HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
sahilmgandhi 18:6a4db94011d3 84 HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
sahilmgandhi 18:6a4db94011d3 85 }HAL_NOR_StateTypeDef;
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 /**
sahilmgandhi 18:6a4db94011d3 88 * @brief FMC NOR Status typedef
sahilmgandhi 18:6a4db94011d3 89 */
sahilmgandhi 18:6a4db94011d3 90 typedef enum
sahilmgandhi 18:6a4db94011d3 91 {
sahilmgandhi 18:6a4db94011d3 92 HAL_NOR_STATUS_SUCCESS = 0U,
sahilmgandhi 18:6a4db94011d3 93 HAL_NOR_STATUS_ONGOING,
sahilmgandhi 18:6a4db94011d3 94 HAL_NOR_STATUS_ERROR,
sahilmgandhi 18:6a4db94011d3 95 HAL_NOR_STATUS_TIMEOUT
sahilmgandhi 18:6a4db94011d3 96 }HAL_NOR_StatusTypeDef;
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /**
sahilmgandhi 18:6a4db94011d3 99 * @brief FMC NOR ID typedef
sahilmgandhi 18:6a4db94011d3 100 */
sahilmgandhi 18:6a4db94011d3 101 typedef struct
sahilmgandhi 18:6a4db94011d3 102 {
sahilmgandhi 18:6a4db94011d3 103 uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 uint16_t Device_Code1;
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 uint16_t Device_Code2;
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
sahilmgandhi 18:6a4db94011d3 110 These codes can be accessed by performing read operations with specific
sahilmgandhi 18:6a4db94011d3 111 control signals and addresses set.They can also be accessed by issuing
sahilmgandhi 18:6a4db94011d3 112 an Auto Select command */
sahilmgandhi 18:6a4db94011d3 113 }NOR_IDTypeDef;
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 /**
sahilmgandhi 18:6a4db94011d3 116 * @brief FMC NOR CFI typedef
sahilmgandhi 18:6a4db94011d3 117 */
sahilmgandhi 18:6a4db94011d3 118 typedef struct
sahilmgandhi 18:6a4db94011d3 119 {
sahilmgandhi 18:6a4db94011d3 120 /*!< Defines the information stored in the memory's Common flash interface
sahilmgandhi 18:6a4db94011d3 121 which contains a description of various electrical and timing parameters,
sahilmgandhi 18:6a4db94011d3 122 density information and functions supported by the memory */
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 uint16_t CFI_1;
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 uint16_t CFI_2;
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 uint16_t CFI_3;
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 uint16_t CFI_4;
sahilmgandhi 18:6a4db94011d3 131 }NOR_CFITypeDef;
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 /**
sahilmgandhi 18:6a4db94011d3 134 * @brief NOR handle Structure definition
sahilmgandhi 18:6a4db94011d3 135 */
sahilmgandhi 18:6a4db94011d3 136 typedef struct
sahilmgandhi 18:6a4db94011d3 137 {
sahilmgandhi 18:6a4db94011d3 138 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 HAL_LockTypeDef Lock; /*!< NOR locking object */
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 }NOR_HandleTypeDef;
sahilmgandhi 18:6a4db94011d3 149 /**
sahilmgandhi 18:6a4db94011d3 150 * @}
sahilmgandhi 18:6a4db94011d3 151 */
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 154 /* Exported macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 155 /** @defgroup NOR_Exported_Macros NOR Exported Macros
sahilmgandhi 18:6a4db94011d3 156 * @{
sahilmgandhi 18:6a4db94011d3 157 */
sahilmgandhi 18:6a4db94011d3 158 /** @brief Reset NOR handle state
sahilmgandhi 18:6a4db94011d3 159 * @param __HANDLE__: specifies the NOR handle.
sahilmgandhi 18:6a4db94011d3 160 * @retval None
sahilmgandhi 18:6a4db94011d3 161 */
sahilmgandhi 18:6a4db94011d3 162 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 163 /**
sahilmgandhi 18:6a4db94011d3 164 * @}
sahilmgandhi 18:6a4db94011d3 165 */
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 168 /** @addtogroup NOR_Exported_Functions
sahilmgandhi 18:6a4db94011d3 169 * @{
sahilmgandhi 18:6a4db94011d3 170 */
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 /** @addtogroup NOR_Exported_Functions_Group1
sahilmgandhi 18:6a4db94011d3 173 * @{
sahilmgandhi 18:6a4db94011d3 174 */
sahilmgandhi 18:6a4db94011d3 175 /* Initialization/de-initialization functions ********************************/
sahilmgandhi 18:6a4db94011d3 176 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
sahilmgandhi 18:6a4db94011d3 177 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
sahilmgandhi 18:6a4db94011d3 178 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
sahilmgandhi 18:6a4db94011d3 179 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
sahilmgandhi 18:6a4db94011d3 180 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 181 /**
sahilmgandhi 18:6a4db94011d3 182 * @}
sahilmgandhi 18:6a4db94011d3 183 */
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 /** @addtogroup NOR_Exported_Functions_Group2
sahilmgandhi 18:6a4db94011d3 186 * @{
sahilmgandhi 18:6a4db94011d3 187 */
sahilmgandhi 18:6a4db94011d3 188 /* I/O operation functions ***************************************************/
sahilmgandhi 18:6a4db94011d3 189 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
sahilmgandhi 18:6a4db94011d3 190 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
sahilmgandhi 18:6a4db94011d3 191 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
sahilmgandhi 18:6a4db94011d3 192 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
sahilmgandhi 18:6a4db94011d3 195 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
sahilmgandhi 18:6a4db94011d3 198 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
sahilmgandhi 18:6a4db94011d3 199 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
sahilmgandhi 18:6a4db94011d3 200 /**
sahilmgandhi 18:6a4db94011d3 201 * @}
sahilmgandhi 18:6a4db94011d3 202 */
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204 /** @addtogroup NOR_Exported_Functions_Group3
sahilmgandhi 18:6a4db94011d3 205 * @{
sahilmgandhi 18:6a4db94011d3 206 */
sahilmgandhi 18:6a4db94011d3 207 /* NOR Control functions *****************************************************/
sahilmgandhi 18:6a4db94011d3 208 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
sahilmgandhi 18:6a4db94011d3 209 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
sahilmgandhi 18:6a4db94011d3 210 /**
sahilmgandhi 18:6a4db94011d3 211 * @}
sahilmgandhi 18:6a4db94011d3 212 */
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 /** @addtogroup NOR_Exported_Functions_Group4
sahilmgandhi 18:6a4db94011d3 215 * @{
sahilmgandhi 18:6a4db94011d3 216 */
sahilmgandhi 18:6a4db94011d3 217 /* NOR State functions ********************************************************/
sahilmgandhi 18:6a4db94011d3 218 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
sahilmgandhi 18:6a4db94011d3 219 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 220 /**
sahilmgandhi 18:6a4db94011d3 221 * @}
sahilmgandhi 18:6a4db94011d3 222 */
sahilmgandhi 18:6a4db94011d3 223
sahilmgandhi 18:6a4db94011d3 224 /**
sahilmgandhi 18:6a4db94011d3 225 * @}
sahilmgandhi 18:6a4db94011d3 226 */
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 229 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 230 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 231 /** @defgroup NOR_Private_Constants NOR Private Constants
sahilmgandhi 18:6a4db94011d3 232 * @{
sahilmgandhi 18:6a4db94011d3 233 */
sahilmgandhi 18:6a4db94011d3 234 /* NOR device IDs addresses */
sahilmgandhi 18:6a4db94011d3 235 #define MC_ADDRESS ((uint16_t)0x0000U)
sahilmgandhi 18:6a4db94011d3 236 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
sahilmgandhi 18:6a4db94011d3 237 #define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
sahilmgandhi 18:6a4db94011d3 238 #define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 /* NOR CFI IDs addresses */
sahilmgandhi 18:6a4db94011d3 241 #define CFI1_ADDRESS ((uint16_t)0x0061U)
sahilmgandhi 18:6a4db94011d3 242 #define CFI2_ADDRESS ((uint16_t)0x0062U)
sahilmgandhi 18:6a4db94011d3 243 #define CFI3_ADDRESS ((uint16_t)0x0063U)
sahilmgandhi 18:6a4db94011d3 244 #define CFI4_ADDRESS ((uint16_t)0x0064U)
sahilmgandhi 18:6a4db94011d3 245
sahilmgandhi 18:6a4db94011d3 246 /* NOR operation wait timeout */
sahilmgandhi 18:6a4db94011d3 247 #define NOR_TMEOUT ((uint16_t)0xFFFFU)
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 /* NOR memory data width */
sahilmgandhi 18:6a4db94011d3 250 #define NOR_MEMORY_8B ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 251 #define NOR_MEMORY_16B ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 /* NOR memory device read/write start address */
sahilmgandhi 18:6a4db94011d3 254 #define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
sahilmgandhi 18:6a4db94011d3 255 #define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
sahilmgandhi 18:6a4db94011d3 256 #define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
sahilmgandhi 18:6a4db94011d3 257 #define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
sahilmgandhi 18:6a4db94011d3 258 /**
sahilmgandhi 18:6a4db94011d3 259 * @}
sahilmgandhi 18:6a4db94011d3 260 */
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 263 /** @defgroup NOR_Private_Macros NOR Private Macros
sahilmgandhi 18:6a4db94011d3 264 * @{
sahilmgandhi 18:6a4db94011d3 265 */
sahilmgandhi 18:6a4db94011d3 266 /**
sahilmgandhi 18:6a4db94011d3 267 * @brief NOR memory address shifting.
sahilmgandhi 18:6a4db94011d3 268 * @param __NOR_ADDRESS__: NOR base address
sahilmgandhi 18:6a4db94011d3 269 * @param NOR_MEMORY_WIDTH: NOR memory width
sahilmgandhi 18:6a4db94011d3 270 * @param ADDRESS: NOR memory address
sahilmgandhi 18:6a4db94011d3 271 * @retval NOR shifted address value
sahilmgandhi 18:6a4db94011d3 272 */
sahilmgandhi 18:6a4db94011d3 273 #define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_16B)? ((uint32_t)((__NOR_ADDRESS__) + (2U * (ADDRESS)))):\
sahilmgandhi 18:6a4db94011d3 274 ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS))))
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 /**
sahilmgandhi 18:6a4db94011d3 277 * @brief NOR memory write data to specified address.
sahilmgandhi 18:6a4db94011d3 278 * @param ADDRESS: NOR memory address
sahilmgandhi 18:6a4db94011d3 279 * @param DATA: Data to write
sahilmgandhi 18:6a4db94011d3 280 * @retval None
sahilmgandhi 18:6a4db94011d3 281 */
sahilmgandhi 18:6a4db94011d3 282 #define NOR_WRITE(ADDRESS, DATA) (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA))
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 /**
sahilmgandhi 18:6a4db94011d3 285 * @}
sahilmgandhi 18:6a4db94011d3 286 */
sahilmgandhi 18:6a4db94011d3 287 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
sahilmgandhi 18:6a4db94011d3 288 STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
sahilmgandhi 18:6a4db94011d3 289 STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
sahilmgandhi 18:6a4db94011d3 290 STM32F412Vx */
sahilmgandhi 18:6a4db94011d3 291 /**
sahilmgandhi 18:6a4db94011d3 292 * @}
sahilmgandhi 18:6a4db94011d3 293 */
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 /**
sahilmgandhi 18:6a4db94011d3 296 * @}
sahilmgandhi 18:6a4db94011d3 297 */
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 300 }
sahilmgandhi 18:6a4db94011d3 301 #endif
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 #endif /* __STM32F4xx_HAL_NOR_H */
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/