MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_cortex.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of CORTEX HAL module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32F4xx_HAL_CORTEX_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32F4xx_HAL_CORTEX_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 #include "stm32f4xx_hal_def.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 50 * @{
sahilmgandhi 18:6a4db94011d3 51 */
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /** @addtogroup CORTEX
sahilmgandhi 18:6a4db94011d3 54 * @{
sahilmgandhi 18:6a4db94011d3 55 */
sahilmgandhi 18:6a4db94011d3 56 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 57 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
sahilmgandhi 18:6a4db94011d3 58 * @{
sahilmgandhi 18:6a4db94011d3 59 */
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 #if (__MPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 62 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
sahilmgandhi 18:6a4db94011d3 63 * @brief MPU Region initialization structure
sahilmgandhi 18:6a4db94011d3 64 * @{
sahilmgandhi 18:6a4db94011d3 65 */
sahilmgandhi 18:6a4db94011d3 66 typedef struct
sahilmgandhi 18:6a4db94011d3 67 {
sahilmgandhi 18:6a4db94011d3 68 uint8_t Enable; /*!< Specifies the status of the region.
sahilmgandhi 18:6a4db94011d3 69 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
sahilmgandhi 18:6a4db94011d3 70 uint8_t Number; /*!< Specifies the number of the region to protect.
sahilmgandhi 18:6a4db94011d3 71 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
sahilmgandhi 18:6a4db94011d3 72 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
sahilmgandhi 18:6a4db94011d3 73 uint8_t Size; /*!< Specifies the size of the region to protect.
sahilmgandhi 18:6a4db94011d3 74 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
sahilmgandhi 18:6a4db94011d3 75 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
sahilmgandhi 18:6a4db94011d3 76 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
sahilmgandhi 18:6a4db94011d3 77 uint8_t TypeExtField; /*!< Specifies the TEX field level.
sahilmgandhi 18:6a4db94011d3 78 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
sahilmgandhi 18:6a4db94011d3 79 uint8_t AccessPermission; /*!< Specifies the region access permission type.
sahilmgandhi 18:6a4db94011d3 80 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
sahilmgandhi 18:6a4db94011d3 81 uint8_t DisableExec; /*!< Specifies the instruction access status.
sahilmgandhi 18:6a4db94011d3 82 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
sahilmgandhi 18:6a4db94011d3 83 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
sahilmgandhi 18:6a4db94011d3 84 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
sahilmgandhi 18:6a4db94011d3 85 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
sahilmgandhi 18:6a4db94011d3 86 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
sahilmgandhi 18:6a4db94011d3 87 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
sahilmgandhi 18:6a4db94011d3 88 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
sahilmgandhi 18:6a4db94011d3 89 }MPU_Region_InitTypeDef;
sahilmgandhi 18:6a4db94011d3 90 /**
sahilmgandhi 18:6a4db94011d3 91 * @}
sahilmgandhi 18:6a4db94011d3 92 */
sahilmgandhi 18:6a4db94011d3 93 #endif /* __MPU_PRESENT */
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 /**
sahilmgandhi 18:6a4db94011d3 96 * @}
sahilmgandhi 18:6a4db94011d3 97 */
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
sahilmgandhi 18:6a4db94011d3 102 * @{
sahilmgandhi 18:6a4db94011d3 103 */
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
sahilmgandhi 18:6a4db94011d3 106 * @{
sahilmgandhi 18:6a4db94011d3 107 */
sahilmgandhi 18:6a4db94011d3 108 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
sahilmgandhi 18:6a4db94011d3 109 4 bits for subpriority */
sahilmgandhi 18:6a4db94011d3 110 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
sahilmgandhi 18:6a4db94011d3 111 3 bits for subpriority */
sahilmgandhi 18:6a4db94011d3 112 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
sahilmgandhi 18:6a4db94011d3 113 2 bits for subpriority */
sahilmgandhi 18:6a4db94011d3 114 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
sahilmgandhi 18:6a4db94011d3 115 1 bits for subpriority */
sahilmgandhi 18:6a4db94011d3 116 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
sahilmgandhi 18:6a4db94011d3 117 0 bits for subpriority */
sahilmgandhi 18:6a4db94011d3 118 /**
sahilmgandhi 18:6a4db94011d3 119 * @}
sahilmgandhi 18:6a4db94011d3 120 */
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
sahilmgandhi 18:6a4db94011d3 123 * @{
sahilmgandhi 18:6a4db94011d3 124 */
sahilmgandhi 18:6a4db94011d3 125 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 126 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /**
sahilmgandhi 18:6a4db94011d3 129 * @}
sahilmgandhi 18:6a4db94011d3 130 */
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 #if (__MPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 133 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
sahilmgandhi 18:6a4db94011d3 134 * @{
sahilmgandhi 18:6a4db94011d3 135 */
sahilmgandhi 18:6a4db94011d3 136 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 137 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
sahilmgandhi 18:6a4db94011d3 138 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
sahilmgandhi 18:6a4db94011d3 139 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
sahilmgandhi 18:6a4db94011d3 140 /**
sahilmgandhi 18:6a4db94011d3 141 * @}
sahilmgandhi 18:6a4db94011d3 142 */
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
sahilmgandhi 18:6a4db94011d3 145 * @{
sahilmgandhi 18:6a4db94011d3 146 */
sahilmgandhi 18:6a4db94011d3 147 #define MPU_REGION_ENABLE ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 148 #define MPU_REGION_DISABLE ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 149 /**
sahilmgandhi 18:6a4db94011d3 150 * @}
sahilmgandhi 18:6a4db94011d3 151 */
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
sahilmgandhi 18:6a4db94011d3 154 * @{
sahilmgandhi 18:6a4db94011d3 155 */
sahilmgandhi 18:6a4db94011d3 156 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 157 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 158 /**
sahilmgandhi 18:6a4db94011d3 159 * @}
sahilmgandhi 18:6a4db94011d3 160 */
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
sahilmgandhi 18:6a4db94011d3 163 * @{
sahilmgandhi 18:6a4db94011d3 164 */
sahilmgandhi 18:6a4db94011d3 165 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 166 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 167 /**
sahilmgandhi 18:6a4db94011d3 168 * @}
sahilmgandhi 18:6a4db94011d3 169 */
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
sahilmgandhi 18:6a4db94011d3 172 * @{
sahilmgandhi 18:6a4db94011d3 173 */
sahilmgandhi 18:6a4db94011d3 174 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 175 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 176 /**
sahilmgandhi 18:6a4db94011d3 177 * @}
sahilmgandhi 18:6a4db94011d3 178 */
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
sahilmgandhi 18:6a4db94011d3 181 * @{
sahilmgandhi 18:6a4db94011d3 182 */
sahilmgandhi 18:6a4db94011d3 183 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 184 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 185 /**
sahilmgandhi 18:6a4db94011d3 186 * @}
sahilmgandhi 18:6a4db94011d3 187 */
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
sahilmgandhi 18:6a4db94011d3 190 * @{
sahilmgandhi 18:6a4db94011d3 191 */
sahilmgandhi 18:6a4db94011d3 192 #define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 193 #define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 194 #define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
sahilmgandhi 18:6a4db94011d3 195 /**
sahilmgandhi 18:6a4db94011d3 196 * @}
sahilmgandhi 18:6a4db94011d3 197 */
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
sahilmgandhi 18:6a4db94011d3 200 * @{
sahilmgandhi 18:6a4db94011d3 201 */
sahilmgandhi 18:6a4db94011d3 202 #define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
sahilmgandhi 18:6a4db94011d3 203 #define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
sahilmgandhi 18:6a4db94011d3 204 #define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
sahilmgandhi 18:6a4db94011d3 205 #define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
sahilmgandhi 18:6a4db94011d3 206 #define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
sahilmgandhi 18:6a4db94011d3 207 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
sahilmgandhi 18:6a4db94011d3 208 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
sahilmgandhi 18:6a4db94011d3 209 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
sahilmgandhi 18:6a4db94011d3 210 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
sahilmgandhi 18:6a4db94011d3 211 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
sahilmgandhi 18:6a4db94011d3 212 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
sahilmgandhi 18:6a4db94011d3 213 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
sahilmgandhi 18:6a4db94011d3 214 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
sahilmgandhi 18:6a4db94011d3 215 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
sahilmgandhi 18:6a4db94011d3 216 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
sahilmgandhi 18:6a4db94011d3 217 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
sahilmgandhi 18:6a4db94011d3 218 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
sahilmgandhi 18:6a4db94011d3 219 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
sahilmgandhi 18:6a4db94011d3 220 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
sahilmgandhi 18:6a4db94011d3 221 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
sahilmgandhi 18:6a4db94011d3 222 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
sahilmgandhi 18:6a4db94011d3 223 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
sahilmgandhi 18:6a4db94011d3 224 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
sahilmgandhi 18:6a4db94011d3 225 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
sahilmgandhi 18:6a4db94011d3 226 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
sahilmgandhi 18:6a4db94011d3 227 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
sahilmgandhi 18:6a4db94011d3 228 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
sahilmgandhi 18:6a4db94011d3 229 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
sahilmgandhi 18:6a4db94011d3 230 /**
sahilmgandhi 18:6a4db94011d3 231 * @}
sahilmgandhi 18:6a4db94011d3 232 */
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
sahilmgandhi 18:6a4db94011d3 235 * @{
sahilmgandhi 18:6a4db94011d3 236 */
sahilmgandhi 18:6a4db94011d3 237 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 238 #define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 239 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
sahilmgandhi 18:6a4db94011d3 240 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
sahilmgandhi 18:6a4db94011d3 241 #define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
sahilmgandhi 18:6a4db94011d3 242 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
sahilmgandhi 18:6a4db94011d3 243 /**
sahilmgandhi 18:6a4db94011d3 244 * @}
sahilmgandhi 18:6a4db94011d3 245 */
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
sahilmgandhi 18:6a4db94011d3 248 * @{
sahilmgandhi 18:6a4db94011d3 249 */
sahilmgandhi 18:6a4db94011d3 250 #define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 251 #define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 252 #define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
sahilmgandhi 18:6a4db94011d3 253 #define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
sahilmgandhi 18:6a4db94011d3 254 #define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
sahilmgandhi 18:6a4db94011d3 255 #define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
sahilmgandhi 18:6a4db94011d3 256 #define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
sahilmgandhi 18:6a4db94011d3 257 #define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
sahilmgandhi 18:6a4db94011d3 258 /**
sahilmgandhi 18:6a4db94011d3 259 * @}
sahilmgandhi 18:6a4db94011d3 260 */
sahilmgandhi 18:6a4db94011d3 261 #endif /* __MPU_PRESENT */
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 /**
sahilmgandhi 18:6a4db94011d3 264 * @}
sahilmgandhi 18:6a4db94011d3 265 */
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 /* Exported Macros -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 271 /** @addtogroup CORTEX_Exported_Functions
sahilmgandhi 18:6a4db94011d3 272 * @{
sahilmgandhi 18:6a4db94011d3 273 */
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 /** @addtogroup CORTEX_Exported_Functions_Group1
sahilmgandhi 18:6a4db94011d3 276 * @{
sahilmgandhi 18:6a4db94011d3 277 */
sahilmgandhi 18:6a4db94011d3 278 /* Initialization and de-initialization functions *****************************/
sahilmgandhi 18:6a4db94011d3 279 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
sahilmgandhi 18:6a4db94011d3 280 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
sahilmgandhi 18:6a4db94011d3 281 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
sahilmgandhi 18:6a4db94011d3 282 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
sahilmgandhi 18:6a4db94011d3 283 void HAL_NVIC_SystemReset(void);
sahilmgandhi 18:6a4db94011d3 284 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
sahilmgandhi 18:6a4db94011d3 285 /**
sahilmgandhi 18:6a4db94011d3 286 * @}
sahilmgandhi 18:6a4db94011d3 287 */
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 /** @addtogroup CORTEX_Exported_Functions_Group2
sahilmgandhi 18:6a4db94011d3 290 * @{
sahilmgandhi 18:6a4db94011d3 291 */
sahilmgandhi 18:6a4db94011d3 292 /* Peripheral Control functions ***********************************************/
sahilmgandhi 18:6a4db94011d3 293 #if (__MPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 294 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
sahilmgandhi 18:6a4db94011d3 295 #endif /* __MPU_PRESENT */
sahilmgandhi 18:6a4db94011d3 296 uint32_t HAL_NVIC_GetPriorityGrouping(void);
sahilmgandhi 18:6a4db94011d3 297 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
sahilmgandhi 18:6a4db94011d3 298 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
sahilmgandhi 18:6a4db94011d3 299 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
sahilmgandhi 18:6a4db94011d3 300 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
sahilmgandhi 18:6a4db94011d3 301 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
sahilmgandhi 18:6a4db94011d3 302 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
sahilmgandhi 18:6a4db94011d3 303 void HAL_SYSTICK_IRQHandler(void);
sahilmgandhi 18:6a4db94011d3 304 void HAL_SYSTICK_Callback(void);
sahilmgandhi 18:6a4db94011d3 305 /**
sahilmgandhi 18:6a4db94011d3 306 * @}
sahilmgandhi 18:6a4db94011d3 307 */
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 /**
sahilmgandhi 18:6a4db94011d3 310 * @}
sahilmgandhi 18:6a4db94011d3 311 */
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 314 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 315 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 316 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 317 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
sahilmgandhi 18:6a4db94011d3 318 * @{
sahilmgandhi 18:6a4db94011d3 319 */
sahilmgandhi 18:6a4db94011d3 320 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
sahilmgandhi 18:6a4db94011d3 321 ((GROUP) == NVIC_PRIORITYGROUP_1) || \
sahilmgandhi 18:6a4db94011d3 322 ((GROUP) == NVIC_PRIORITYGROUP_2) || \
sahilmgandhi 18:6a4db94011d3 323 ((GROUP) == NVIC_PRIORITYGROUP_3) || \
sahilmgandhi 18:6a4db94011d3 324 ((GROUP) == NVIC_PRIORITYGROUP_4))
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
sahilmgandhi 18:6a4db94011d3 331
sahilmgandhi 18:6a4db94011d3 332 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
sahilmgandhi 18:6a4db94011d3 333 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 #if (__MPU_PRESENT == 1U)
sahilmgandhi 18:6a4db94011d3 336 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
sahilmgandhi 18:6a4db94011d3 337 ((STATE) == MPU_REGION_DISABLE))
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
sahilmgandhi 18:6a4db94011d3 340 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
sahilmgandhi 18:6a4db94011d3 343 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
sahilmgandhi 18:6a4db94011d3 346 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
sahilmgandhi 18:6a4db94011d3 349 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
sahilmgandhi 18:6a4db94011d3 352 ((TYPE) == MPU_TEX_LEVEL1) || \
sahilmgandhi 18:6a4db94011d3 353 ((TYPE) == MPU_TEX_LEVEL2))
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
sahilmgandhi 18:6a4db94011d3 356 ((TYPE) == MPU_REGION_PRIV_RW) || \
sahilmgandhi 18:6a4db94011d3 357 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
sahilmgandhi 18:6a4db94011d3 358 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
sahilmgandhi 18:6a4db94011d3 359 ((TYPE) == MPU_REGION_PRIV_RO) || \
sahilmgandhi 18:6a4db94011d3 360 ((TYPE) == MPU_REGION_PRIV_RO_URO))
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
sahilmgandhi 18:6a4db94011d3 363 ((NUMBER) == MPU_REGION_NUMBER1) || \
sahilmgandhi 18:6a4db94011d3 364 ((NUMBER) == MPU_REGION_NUMBER2) || \
sahilmgandhi 18:6a4db94011d3 365 ((NUMBER) == MPU_REGION_NUMBER3) || \
sahilmgandhi 18:6a4db94011d3 366 ((NUMBER) == MPU_REGION_NUMBER4) || \
sahilmgandhi 18:6a4db94011d3 367 ((NUMBER) == MPU_REGION_NUMBER5) || \
sahilmgandhi 18:6a4db94011d3 368 ((NUMBER) == MPU_REGION_NUMBER6) || \
sahilmgandhi 18:6a4db94011d3 369 ((NUMBER) == MPU_REGION_NUMBER7))
sahilmgandhi 18:6a4db94011d3 370
sahilmgandhi 18:6a4db94011d3 371 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
sahilmgandhi 18:6a4db94011d3 372 ((SIZE) == MPU_REGION_SIZE_64B) || \
sahilmgandhi 18:6a4db94011d3 373 ((SIZE) == MPU_REGION_SIZE_128B) || \
sahilmgandhi 18:6a4db94011d3 374 ((SIZE) == MPU_REGION_SIZE_256B) || \
sahilmgandhi 18:6a4db94011d3 375 ((SIZE) == MPU_REGION_SIZE_512B) || \
sahilmgandhi 18:6a4db94011d3 376 ((SIZE) == MPU_REGION_SIZE_1KB) || \
sahilmgandhi 18:6a4db94011d3 377 ((SIZE) == MPU_REGION_SIZE_2KB) || \
sahilmgandhi 18:6a4db94011d3 378 ((SIZE) == MPU_REGION_SIZE_4KB) || \
sahilmgandhi 18:6a4db94011d3 379 ((SIZE) == MPU_REGION_SIZE_8KB) || \
sahilmgandhi 18:6a4db94011d3 380 ((SIZE) == MPU_REGION_SIZE_16KB) || \
sahilmgandhi 18:6a4db94011d3 381 ((SIZE) == MPU_REGION_SIZE_32KB) || \
sahilmgandhi 18:6a4db94011d3 382 ((SIZE) == MPU_REGION_SIZE_64KB) || \
sahilmgandhi 18:6a4db94011d3 383 ((SIZE) == MPU_REGION_SIZE_128KB) || \
sahilmgandhi 18:6a4db94011d3 384 ((SIZE) == MPU_REGION_SIZE_256KB) || \
sahilmgandhi 18:6a4db94011d3 385 ((SIZE) == MPU_REGION_SIZE_512KB) || \
sahilmgandhi 18:6a4db94011d3 386 ((SIZE) == MPU_REGION_SIZE_1MB) || \
sahilmgandhi 18:6a4db94011d3 387 ((SIZE) == MPU_REGION_SIZE_2MB) || \
sahilmgandhi 18:6a4db94011d3 388 ((SIZE) == MPU_REGION_SIZE_4MB) || \
sahilmgandhi 18:6a4db94011d3 389 ((SIZE) == MPU_REGION_SIZE_8MB) || \
sahilmgandhi 18:6a4db94011d3 390 ((SIZE) == MPU_REGION_SIZE_16MB) || \
sahilmgandhi 18:6a4db94011d3 391 ((SIZE) == MPU_REGION_SIZE_32MB) || \
sahilmgandhi 18:6a4db94011d3 392 ((SIZE) == MPU_REGION_SIZE_64MB) || \
sahilmgandhi 18:6a4db94011d3 393 ((SIZE) == MPU_REGION_SIZE_128MB) || \
sahilmgandhi 18:6a4db94011d3 394 ((SIZE) == MPU_REGION_SIZE_256MB) || \
sahilmgandhi 18:6a4db94011d3 395 ((SIZE) == MPU_REGION_SIZE_512MB) || \
sahilmgandhi 18:6a4db94011d3 396 ((SIZE) == MPU_REGION_SIZE_1GB) || \
sahilmgandhi 18:6a4db94011d3 397 ((SIZE) == MPU_REGION_SIZE_2GB) || \
sahilmgandhi 18:6a4db94011d3 398 ((SIZE) == MPU_REGION_SIZE_4GB))
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
sahilmgandhi 18:6a4db94011d3 401 #endif /* __MPU_PRESENT */
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 /**
sahilmgandhi 18:6a4db94011d3 404 * @}
sahilmgandhi 18:6a4db94011d3 405 */
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 408 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
sahilmgandhi 18:6a4db94011d3 409 * @brief CORTEX private functions
sahilmgandhi 18:6a4db94011d3 410 * @{
sahilmgandhi 18:6a4db94011d3 411 */
sahilmgandhi 18:6a4db94011d3 412
sahilmgandhi 18:6a4db94011d3 413 #if (__MPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 414 /**
sahilmgandhi 18:6a4db94011d3 415 * @brief Disables the MPU
sahilmgandhi 18:6a4db94011d3 416 * @retval None
sahilmgandhi 18:6a4db94011d3 417 */
sahilmgandhi 18:6a4db94011d3 418 __STATIC_INLINE void HAL_MPU_Disable(void)
sahilmgandhi 18:6a4db94011d3 419 {
sahilmgandhi 18:6a4db94011d3 420 /* Disable fault exceptions */
sahilmgandhi 18:6a4db94011d3 421 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 /* Disable the MPU */
sahilmgandhi 18:6a4db94011d3 424 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
sahilmgandhi 18:6a4db94011d3 425 }
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 /**
sahilmgandhi 18:6a4db94011d3 428 * @brief Enables the MPU
sahilmgandhi 18:6a4db94011d3 429 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
sahilmgandhi 18:6a4db94011d3 430 * NMI, FAULTMASK and privileged access to the default memory
sahilmgandhi 18:6a4db94011d3 431 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 432 * @arg MPU_HFNMI_PRIVDEF_NONE
sahilmgandhi 18:6a4db94011d3 433 * @arg MPU_HARDFAULT_NMI
sahilmgandhi 18:6a4db94011d3 434 * @arg MPU_PRIVILEGED_DEFAULT
sahilmgandhi 18:6a4db94011d3 435 * @arg MPU_HFNMI_PRIVDEF
sahilmgandhi 18:6a4db94011d3 436 * @retval None
sahilmgandhi 18:6a4db94011d3 437 */
sahilmgandhi 18:6a4db94011d3 438 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
sahilmgandhi 18:6a4db94011d3 439 {
sahilmgandhi 18:6a4db94011d3 440 /* Enable the MPU */
sahilmgandhi 18:6a4db94011d3 441 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443 /* Enable fault exceptions */
sahilmgandhi 18:6a4db94011d3 444 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
sahilmgandhi 18:6a4db94011d3 445 }
sahilmgandhi 18:6a4db94011d3 446 #endif /* __MPU_PRESENT */
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 /**
sahilmgandhi 18:6a4db94011d3 449 * @}
sahilmgandhi 18:6a4db94011d3 450 */
sahilmgandhi 18:6a4db94011d3 451
sahilmgandhi 18:6a4db94011d3 452 /**
sahilmgandhi 18:6a4db94011d3 453 * @}
sahilmgandhi 18:6a4db94011d3 454 */
sahilmgandhi 18:6a4db94011d3 455
sahilmgandhi 18:6a4db94011d3 456 /**
sahilmgandhi 18:6a4db94011d3 457 * @}
sahilmgandhi 18:6a4db94011d3 458 */
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 461 }
sahilmgandhi 18:6a4db94011d3 462 #endif
sahilmgandhi 18:6a4db94011d3 463
sahilmgandhi 18:6a4db94011d3 464 #endif /* __STM32F4xx_HAL_CORTEX_H */
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/