Mouse code for the MacroRat
mbed-dev/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/nvic_addr.h@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* mbed Microcontroller Library |
sahilmgandhi | 18:6a4db94011d3 | 2 | * Copyright (c) 2017-2017 ARM Limited |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
sahilmgandhi | 18:6a4db94011d3 | 5 | * you may not use this file except in compliance with the License. |
sahilmgandhi | 18:6a4db94011d3 | 6 | * You may obtain a copy of the License at |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * Unless required by applicable law or agreed to in writing, software |
sahilmgandhi | 18:6a4db94011d3 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
sahilmgandhi | 18:6a4db94011d3 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
sahilmgandhi | 18:6a4db94011d3 | 13 | * See the License for the specific language governing permissions and |
sahilmgandhi | 18:6a4db94011d3 | 14 | * limitations under the License. |
sahilmgandhi | 18:6a4db94011d3 | 15 | */ |
sahilmgandhi | 18:6a4db94011d3 | 16 | #ifndef NVIC_ADDR_H |
sahilmgandhi | 18:6a4db94011d3 | 17 | #define NVIC_ADDR_H |
sahilmgandhi | 18:6a4db94011d3 | 18 | |
sahilmgandhi | 18:6a4db94011d3 | 19 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 20 | extern "C" { |
sahilmgandhi | 18:6a4db94011d3 | 21 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 22 | |
sahilmgandhi | 18:6a4db94011d3 | 23 | #if defined(__ICCARM__) |
sahilmgandhi | 18:6a4db94011d3 | 24 | #pragma section=".intvec" |
sahilmgandhi | 18:6a4db94011d3 | 25 | #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec")) |
sahilmgandhi | 18:6a4db94011d3 | 26 | #elif defined(__CC_ARM) |
sahilmgandhi | 18:6a4db94011d3 | 27 | extern uint32_t Load$$LR$$LR_IROM1$$Base[]; |
sahilmgandhi | 18:6a4db94011d3 | 28 | #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base) |
sahilmgandhi | 18:6a4db94011d3 | 29 | #elif defined(__GNUC__) |
sahilmgandhi | 18:6a4db94011d3 | 30 | extern uint32_t g_pfnVectors[]; |
sahilmgandhi | 18:6a4db94011d3 | 31 | #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)g_pfnVectors) |
sahilmgandhi | 18:6a4db94011d3 | 32 | #else |
sahilmgandhi | 18:6a4db94011d3 | 33 | #error "Flash vector address not set for this toolchain" |
sahilmgandhi | 18:6a4db94011d3 | 34 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 35 | |
sahilmgandhi | 18:6a4db94011d3 | 36 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 37 | } |
sahilmgandhi | 18:6a4db94011d3 | 38 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 39 | |
sahilmgandhi | 18:6a4db94011d3 | 40 | #endif |