MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f407xx.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V2.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 22-April-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * This file contains:
sahilmgandhi 18:6a4db94011d3 10 * - Data structures and the address mapping for all peripherals
sahilmgandhi 18:6a4db94011d3 11 * - peripherals registers declarations and bits definition
sahilmgandhi 18:6a4db94011d3 12 * - Macros to access peripheral’s registers hardware
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 15 * @attention
sahilmgandhi 18:6a4db94011d3 16 *
sahilmgandhi 18:6a4db94011d3 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 20 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 21 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 22 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 24 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 25 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 27 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 28 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 29 *
sahilmgandhi 18:6a4db94011d3 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 40 *
sahilmgandhi 18:6a4db94011d3 41 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 42 */
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 /** @addtogroup CMSIS
sahilmgandhi 18:6a4db94011d3 45 * @{
sahilmgandhi 18:6a4db94011d3 46 */
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 /** @addtogroup stm32f407xx
sahilmgandhi 18:6a4db94011d3 49 * @{
sahilmgandhi 18:6a4db94011d3 50 */
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 #ifndef __STM32F407xx_H
sahilmgandhi 18:6a4db94011d3 53 #define __STM32F407xx_H
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 56 extern "C" {
sahilmgandhi 18:6a4db94011d3 57 #endif /* __cplusplus */
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 /** @addtogroup Configuration_section_for_CMSIS
sahilmgandhi 18:6a4db94011d3 61 * @{
sahilmgandhi 18:6a4db94011d3 62 */
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /**
sahilmgandhi 18:6a4db94011d3 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
sahilmgandhi 18:6a4db94011d3 66 */
sahilmgandhi 18:6a4db94011d3 67 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
sahilmgandhi 18:6a4db94011d3 68 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
sahilmgandhi 18:6a4db94011d3 69 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
sahilmgandhi 18:6a4db94011d3 70 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 71 #ifndef __FPU_PRESENT
sahilmgandhi 18:6a4db94011d3 72 #define __FPU_PRESENT 1U /*!< FPU present */
sahilmgandhi 18:6a4db94011d3 73 #endif /* __FPU_PRESENT */
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 /**
sahilmgandhi 18:6a4db94011d3 76 * @}
sahilmgandhi 18:6a4db94011d3 77 */
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 /** @addtogroup Peripheral_interrupt_number_definition
sahilmgandhi 18:6a4db94011d3 80 * @{
sahilmgandhi 18:6a4db94011d3 81 */
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 /**
sahilmgandhi 18:6a4db94011d3 84 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
sahilmgandhi 18:6a4db94011d3 85 * in @ref Library_configuration_section
sahilmgandhi 18:6a4db94011d3 86 */
sahilmgandhi 18:6a4db94011d3 87 typedef enum
sahilmgandhi 18:6a4db94011d3 88 {
sahilmgandhi 18:6a4db94011d3 89 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
sahilmgandhi 18:6a4db94011d3 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
sahilmgandhi 18:6a4db94011d3 91 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
sahilmgandhi 18:6a4db94011d3 92 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 93 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 94 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
sahilmgandhi 18:6a4db94011d3 95 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
sahilmgandhi 18:6a4db94011d3 96 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
sahilmgandhi 18:6a4db94011d3 97 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
sahilmgandhi 18:6a4db94011d3 98 /****** STM32 specific Interrupt Numbers **********************************************************************/
sahilmgandhi 18:6a4db94011d3 99 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
sahilmgandhi 18:6a4db94011d3 100 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
sahilmgandhi 18:6a4db94011d3 101 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
sahilmgandhi 18:6a4db94011d3 102 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
sahilmgandhi 18:6a4db94011d3 103 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
sahilmgandhi 18:6a4db94011d3 104 RCC_IRQn = 5, /*!< RCC global Interrupt */
sahilmgandhi 18:6a4db94011d3 105 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
sahilmgandhi 18:6a4db94011d3 106 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
sahilmgandhi 18:6a4db94011d3 107 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
sahilmgandhi 18:6a4db94011d3 108 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
sahilmgandhi 18:6a4db94011d3 109 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
sahilmgandhi 18:6a4db94011d3 110 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
sahilmgandhi 18:6a4db94011d3 111 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 112 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 113 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 114 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
sahilmgandhi 18:6a4db94011d3 115 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
sahilmgandhi 18:6a4db94011d3 116 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
sahilmgandhi 18:6a4db94011d3 117 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
sahilmgandhi 18:6a4db94011d3 118 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
sahilmgandhi 18:6a4db94011d3 119 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
sahilmgandhi 18:6a4db94011d3 120 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
sahilmgandhi 18:6a4db94011d3 121 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
sahilmgandhi 18:6a4db94011d3 122 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
sahilmgandhi 18:6a4db94011d3 123 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
sahilmgandhi 18:6a4db94011d3 124 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
sahilmgandhi 18:6a4db94011d3 125 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
sahilmgandhi 18:6a4db94011d3 126 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
sahilmgandhi 18:6a4db94011d3 127 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 128 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 129 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
sahilmgandhi 18:6a4db94011d3 130 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
sahilmgandhi 18:6a4db94011d3 131 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
sahilmgandhi 18:6a4db94011d3 132 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
sahilmgandhi 18:6a4db94011d3 133 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
sahilmgandhi 18:6a4db94011d3 134 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 135 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 136 USART1_IRQn = 37, /*!< USART1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 137 USART2_IRQn = 38, /*!< USART2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 138 USART3_IRQn = 39, /*!< USART3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 139 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
sahilmgandhi 18:6a4db94011d3 140 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
sahilmgandhi 18:6a4db94011d3 141 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
sahilmgandhi 18:6a4db94011d3 142 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
sahilmgandhi 18:6a4db94011d3 143 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
sahilmgandhi 18:6a4db94011d3 144 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
sahilmgandhi 18:6a4db94011d3 145 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
sahilmgandhi 18:6a4db94011d3 146 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
sahilmgandhi 18:6a4db94011d3 147 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
sahilmgandhi 18:6a4db94011d3 148 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
sahilmgandhi 18:6a4db94011d3 149 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
sahilmgandhi 18:6a4db94011d3 150 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 151 UART4_IRQn = 52, /*!< UART4 global Interrupt */
sahilmgandhi 18:6a4db94011d3 152 UART5_IRQn = 53, /*!< UART5 global Interrupt */
sahilmgandhi 18:6a4db94011d3 153 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
sahilmgandhi 18:6a4db94011d3 154 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
sahilmgandhi 18:6a4db94011d3 155 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
sahilmgandhi 18:6a4db94011d3 156 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 157 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 158 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 159 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
sahilmgandhi 18:6a4db94011d3 160 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
sahilmgandhi 18:6a4db94011d3 161 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
sahilmgandhi 18:6a4db94011d3 162 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
sahilmgandhi 18:6a4db94011d3 163 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
sahilmgandhi 18:6a4db94011d3 164 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
sahilmgandhi 18:6a4db94011d3 165 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
sahilmgandhi 18:6a4db94011d3 166 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
sahilmgandhi 18:6a4db94011d3 167 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
sahilmgandhi 18:6a4db94011d3 168 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
sahilmgandhi 18:6a4db94011d3 169 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
sahilmgandhi 18:6a4db94011d3 170 USART6_IRQn = 71, /*!< USART6 global interrupt */
sahilmgandhi 18:6a4db94011d3 171 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
sahilmgandhi 18:6a4db94011d3 172 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
sahilmgandhi 18:6a4db94011d3 173 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
sahilmgandhi 18:6a4db94011d3 174 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
sahilmgandhi 18:6a4db94011d3 175 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
sahilmgandhi 18:6a4db94011d3 176 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
sahilmgandhi 18:6a4db94011d3 177 DCMI_IRQn = 78, /*!< DCMI global interrupt */
sahilmgandhi 18:6a4db94011d3 178 HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
sahilmgandhi 18:6a4db94011d3 179 FPU_IRQn = 81 /*!< FPU global interrupt */
sahilmgandhi 18:6a4db94011d3 180 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 /**
sahilmgandhi 18:6a4db94011d3 183 * @}
sahilmgandhi 18:6a4db94011d3 184 */
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 187 #include "system_stm32f4xx.h"
sahilmgandhi 18:6a4db94011d3 188 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 /** @addtogroup Peripheral_registers_structures
sahilmgandhi 18:6a4db94011d3 191 * @{
sahilmgandhi 18:6a4db94011d3 192 */
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 /**
sahilmgandhi 18:6a4db94011d3 195 * @brief Analog to Digital Converter
sahilmgandhi 18:6a4db94011d3 196 */
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 typedef struct
sahilmgandhi 18:6a4db94011d3 199 {
sahilmgandhi 18:6a4db94011d3 200 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 201 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 202 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 203 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 204 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 205 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 206 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 207 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 208 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 209 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 210 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 211 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 212 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 213 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 214 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
sahilmgandhi 18:6a4db94011d3 215 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 216 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 217 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 218 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 219 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 220 } ADC_TypeDef;
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 typedef struct
sahilmgandhi 18:6a4db94011d3 223 {
sahilmgandhi 18:6a4db94011d3 224 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
sahilmgandhi 18:6a4db94011d3 225 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
sahilmgandhi 18:6a4db94011d3 226 __IO uint32_t CDR; /*!< ADC common regular data register for dual
sahilmgandhi 18:6a4db94011d3 227 AND triple modes, Address offset: ADC1 base address + 0x308 */
sahilmgandhi 18:6a4db94011d3 228 } ADC_Common_TypeDef;
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 /**
sahilmgandhi 18:6a4db94011d3 232 * @brief Controller Area Network TxMailBox
sahilmgandhi 18:6a4db94011d3 233 */
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 typedef struct
sahilmgandhi 18:6a4db94011d3 236 {
sahilmgandhi 18:6a4db94011d3 237 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
sahilmgandhi 18:6a4db94011d3 238 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
sahilmgandhi 18:6a4db94011d3 239 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
sahilmgandhi 18:6a4db94011d3 240 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
sahilmgandhi 18:6a4db94011d3 241 } CAN_TxMailBox_TypeDef;
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 /**
sahilmgandhi 18:6a4db94011d3 244 * @brief Controller Area Network FIFOMailBox
sahilmgandhi 18:6a4db94011d3 245 */
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 typedef struct
sahilmgandhi 18:6a4db94011d3 248 {
sahilmgandhi 18:6a4db94011d3 249 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
sahilmgandhi 18:6a4db94011d3 250 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
sahilmgandhi 18:6a4db94011d3 251 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
sahilmgandhi 18:6a4db94011d3 252 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
sahilmgandhi 18:6a4db94011d3 253 } CAN_FIFOMailBox_TypeDef;
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 /**
sahilmgandhi 18:6a4db94011d3 256 * @brief Controller Area Network FilterRegister
sahilmgandhi 18:6a4db94011d3 257 */
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 typedef struct
sahilmgandhi 18:6a4db94011d3 260 {
sahilmgandhi 18:6a4db94011d3 261 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
sahilmgandhi 18:6a4db94011d3 262 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
sahilmgandhi 18:6a4db94011d3 263 } CAN_FilterRegister_TypeDef;
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /**
sahilmgandhi 18:6a4db94011d3 266 * @brief Controller Area Network
sahilmgandhi 18:6a4db94011d3 267 */
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 typedef struct
sahilmgandhi 18:6a4db94011d3 270 {
sahilmgandhi 18:6a4db94011d3 271 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 272 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 273 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 274 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 275 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 276 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 277 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 278 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 279 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
sahilmgandhi 18:6a4db94011d3 280 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
sahilmgandhi 18:6a4db94011d3 281 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
sahilmgandhi 18:6a4db94011d3 282 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
sahilmgandhi 18:6a4db94011d3 283 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
sahilmgandhi 18:6a4db94011d3 284 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
sahilmgandhi 18:6a4db94011d3 285 uint32_t RESERVED2; /*!< Reserved, 0x208 */
sahilmgandhi 18:6a4db94011d3 286 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
sahilmgandhi 18:6a4db94011d3 287 uint32_t RESERVED3; /*!< Reserved, 0x210 */
sahilmgandhi 18:6a4db94011d3 288 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
sahilmgandhi 18:6a4db94011d3 289 uint32_t RESERVED4; /*!< Reserved, 0x218 */
sahilmgandhi 18:6a4db94011d3 290 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
sahilmgandhi 18:6a4db94011d3 291 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
sahilmgandhi 18:6a4db94011d3 292 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
sahilmgandhi 18:6a4db94011d3 293 } CAN_TypeDef;
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 /**
sahilmgandhi 18:6a4db94011d3 296 * @brief CRC calculation unit
sahilmgandhi 18:6a4db94011d3 297 */
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 typedef struct
sahilmgandhi 18:6a4db94011d3 300 {
sahilmgandhi 18:6a4db94011d3 301 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 302 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 303 uint8_t RESERVED0; /*!< Reserved, 0x05 */
sahilmgandhi 18:6a4db94011d3 304 uint16_t RESERVED1; /*!< Reserved, 0x06 */
sahilmgandhi 18:6a4db94011d3 305 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 306 } CRC_TypeDef;
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308 /**
sahilmgandhi 18:6a4db94011d3 309 * @brief Digital to Analog Converter
sahilmgandhi 18:6a4db94011d3 310 */
sahilmgandhi 18:6a4db94011d3 311
sahilmgandhi 18:6a4db94011d3 312 typedef struct
sahilmgandhi 18:6a4db94011d3 313 {
sahilmgandhi 18:6a4db94011d3 314 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 315 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 316 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 317 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 318 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 319 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 320 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 321 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 322 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 323 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 324 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 325 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 326 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 327 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 328 } DAC_TypeDef;
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 /**
sahilmgandhi 18:6a4db94011d3 331 * @brief Debug MCU
sahilmgandhi 18:6a4db94011d3 332 */
sahilmgandhi 18:6a4db94011d3 333
sahilmgandhi 18:6a4db94011d3 334 typedef struct
sahilmgandhi 18:6a4db94011d3 335 {
sahilmgandhi 18:6a4db94011d3 336 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 337 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 338 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 339 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 340 }DBGMCU_TypeDef;
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 /**
sahilmgandhi 18:6a4db94011d3 343 * @brief DCMI
sahilmgandhi 18:6a4db94011d3 344 */
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 typedef struct
sahilmgandhi 18:6a4db94011d3 347 {
sahilmgandhi 18:6a4db94011d3 348 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 349 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 350 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 351 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 352 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 353 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 354 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 355 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 356 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 357 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 358 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 359 } DCMI_TypeDef;
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 /**
sahilmgandhi 18:6a4db94011d3 362 * @brief DMA Controller
sahilmgandhi 18:6a4db94011d3 363 */
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365 typedef struct
sahilmgandhi 18:6a4db94011d3 366 {
sahilmgandhi 18:6a4db94011d3 367 __IO uint32_t CR; /*!< DMA stream x configuration register */
sahilmgandhi 18:6a4db94011d3 368 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
sahilmgandhi 18:6a4db94011d3 369 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
sahilmgandhi 18:6a4db94011d3 370 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
sahilmgandhi 18:6a4db94011d3 371 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
sahilmgandhi 18:6a4db94011d3 372 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
sahilmgandhi 18:6a4db94011d3 373 } DMA_Stream_TypeDef;
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375 typedef struct
sahilmgandhi 18:6a4db94011d3 376 {
sahilmgandhi 18:6a4db94011d3 377 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 378 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 379 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 380 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 381 } DMA_TypeDef;
sahilmgandhi 18:6a4db94011d3 382
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 /**
sahilmgandhi 18:6a4db94011d3 385 * @brief Ethernet MAC
sahilmgandhi 18:6a4db94011d3 386 */
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 typedef struct
sahilmgandhi 18:6a4db94011d3 389 {
sahilmgandhi 18:6a4db94011d3 390 __IO uint32_t MACCR;
sahilmgandhi 18:6a4db94011d3 391 __IO uint32_t MACFFR;
sahilmgandhi 18:6a4db94011d3 392 __IO uint32_t MACHTHR;
sahilmgandhi 18:6a4db94011d3 393 __IO uint32_t MACHTLR;
sahilmgandhi 18:6a4db94011d3 394 __IO uint32_t MACMIIAR;
sahilmgandhi 18:6a4db94011d3 395 __IO uint32_t MACMIIDR;
sahilmgandhi 18:6a4db94011d3 396 __IO uint32_t MACFCR;
sahilmgandhi 18:6a4db94011d3 397 __IO uint32_t MACVLANTR; /* 8 */
sahilmgandhi 18:6a4db94011d3 398 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 399 __IO uint32_t MACRWUFFR; /* 11 */
sahilmgandhi 18:6a4db94011d3 400 __IO uint32_t MACPMTCSR;
sahilmgandhi 18:6a4db94011d3 401 uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 402 __IO uint32_t MACSR; /* 15 */
sahilmgandhi 18:6a4db94011d3 403 __IO uint32_t MACIMR;
sahilmgandhi 18:6a4db94011d3 404 __IO uint32_t MACA0HR;
sahilmgandhi 18:6a4db94011d3 405 __IO uint32_t MACA0LR;
sahilmgandhi 18:6a4db94011d3 406 __IO uint32_t MACA1HR;
sahilmgandhi 18:6a4db94011d3 407 __IO uint32_t MACA1LR;
sahilmgandhi 18:6a4db94011d3 408 __IO uint32_t MACA2HR;
sahilmgandhi 18:6a4db94011d3 409 __IO uint32_t MACA2LR;
sahilmgandhi 18:6a4db94011d3 410 __IO uint32_t MACA3HR;
sahilmgandhi 18:6a4db94011d3 411 __IO uint32_t MACA3LR; /* 24 */
sahilmgandhi 18:6a4db94011d3 412 uint32_t RESERVED2[40];
sahilmgandhi 18:6a4db94011d3 413 __IO uint32_t MMCCR; /* 65 */
sahilmgandhi 18:6a4db94011d3 414 __IO uint32_t MMCRIR;
sahilmgandhi 18:6a4db94011d3 415 __IO uint32_t MMCTIR;
sahilmgandhi 18:6a4db94011d3 416 __IO uint32_t MMCRIMR;
sahilmgandhi 18:6a4db94011d3 417 __IO uint32_t MMCTIMR; /* 69 */
sahilmgandhi 18:6a4db94011d3 418 uint32_t RESERVED3[14];
sahilmgandhi 18:6a4db94011d3 419 __IO uint32_t MMCTGFSCCR; /* 84 */
sahilmgandhi 18:6a4db94011d3 420 __IO uint32_t MMCTGFMSCCR;
sahilmgandhi 18:6a4db94011d3 421 uint32_t RESERVED4[5];
sahilmgandhi 18:6a4db94011d3 422 __IO uint32_t MMCTGFCR;
sahilmgandhi 18:6a4db94011d3 423 uint32_t RESERVED5[10];
sahilmgandhi 18:6a4db94011d3 424 __IO uint32_t MMCRFCECR;
sahilmgandhi 18:6a4db94011d3 425 __IO uint32_t MMCRFAECR;
sahilmgandhi 18:6a4db94011d3 426 uint32_t RESERVED6[10];
sahilmgandhi 18:6a4db94011d3 427 __IO uint32_t MMCRGUFCR;
sahilmgandhi 18:6a4db94011d3 428 uint32_t RESERVED7[334];
sahilmgandhi 18:6a4db94011d3 429 __IO uint32_t PTPTSCR;
sahilmgandhi 18:6a4db94011d3 430 __IO uint32_t PTPSSIR;
sahilmgandhi 18:6a4db94011d3 431 __IO uint32_t PTPTSHR;
sahilmgandhi 18:6a4db94011d3 432 __IO uint32_t PTPTSLR;
sahilmgandhi 18:6a4db94011d3 433 __IO uint32_t PTPTSHUR;
sahilmgandhi 18:6a4db94011d3 434 __IO uint32_t PTPTSLUR;
sahilmgandhi 18:6a4db94011d3 435 __IO uint32_t PTPTSAR;
sahilmgandhi 18:6a4db94011d3 436 __IO uint32_t PTPTTHR;
sahilmgandhi 18:6a4db94011d3 437 __IO uint32_t PTPTTLR;
sahilmgandhi 18:6a4db94011d3 438 __IO uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 439 __IO uint32_t PTPTSSR;
sahilmgandhi 18:6a4db94011d3 440 uint32_t RESERVED9[565];
sahilmgandhi 18:6a4db94011d3 441 __IO uint32_t DMABMR;
sahilmgandhi 18:6a4db94011d3 442 __IO uint32_t DMATPDR;
sahilmgandhi 18:6a4db94011d3 443 __IO uint32_t DMARPDR;
sahilmgandhi 18:6a4db94011d3 444 __IO uint32_t DMARDLAR;
sahilmgandhi 18:6a4db94011d3 445 __IO uint32_t DMATDLAR;
sahilmgandhi 18:6a4db94011d3 446 __IO uint32_t DMASR;
sahilmgandhi 18:6a4db94011d3 447 __IO uint32_t DMAOMR;
sahilmgandhi 18:6a4db94011d3 448 __IO uint32_t DMAIER;
sahilmgandhi 18:6a4db94011d3 449 __IO uint32_t DMAMFBOCR;
sahilmgandhi 18:6a4db94011d3 450 __IO uint32_t DMARSWTR;
sahilmgandhi 18:6a4db94011d3 451 uint32_t RESERVED10[8];
sahilmgandhi 18:6a4db94011d3 452 __IO uint32_t DMACHTDR;
sahilmgandhi 18:6a4db94011d3 453 __IO uint32_t DMACHRDR;
sahilmgandhi 18:6a4db94011d3 454 __IO uint32_t DMACHTBAR;
sahilmgandhi 18:6a4db94011d3 455 __IO uint32_t DMACHRBAR;
sahilmgandhi 18:6a4db94011d3 456 } ETH_TypeDef;
sahilmgandhi 18:6a4db94011d3 457
sahilmgandhi 18:6a4db94011d3 458 /**
sahilmgandhi 18:6a4db94011d3 459 * @brief External Interrupt/Event Controller
sahilmgandhi 18:6a4db94011d3 460 */
sahilmgandhi 18:6a4db94011d3 461
sahilmgandhi 18:6a4db94011d3 462 typedef struct
sahilmgandhi 18:6a4db94011d3 463 {
sahilmgandhi 18:6a4db94011d3 464 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 465 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 466 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 467 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 468 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 469 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 470 } EXTI_TypeDef;
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 /**
sahilmgandhi 18:6a4db94011d3 473 * @brief FLASH Registers
sahilmgandhi 18:6a4db94011d3 474 */
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 typedef struct
sahilmgandhi 18:6a4db94011d3 477 {
sahilmgandhi 18:6a4db94011d3 478 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 479 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 480 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 481 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 482 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 483 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 484 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 485 } FLASH_TypeDef;
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488 /**
sahilmgandhi 18:6a4db94011d3 489 * @brief Flexible Static Memory Controller
sahilmgandhi 18:6a4db94011d3 490 */
sahilmgandhi 18:6a4db94011d3 491
sahilmgandhi 18:6a4db94011d3 492 typedef struct
sahilmgandhi 18:6a4db94011d3 493 {
sahilmgandhi 18:6a4db94011d3 494 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
sahilmgandhi 18:6a4db94011d3 495 } FSMC_Bank1_TypeDef;
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 /**
sahilmgandhi 18:6a4db94011d3 498 * @brief Flexible Static Memory Controller Bank1E
sahilmgandhi 18:6a4db94011d3 499 */
sahilmgandhi 18:6a4db94011d3 500
sahilmgandhi 18:6a4db94011d3 501 typedef struct
sahilmgandhi 18:6a4db94011d3 502 {
sahilmgandhi 18:6a4db94011d3 503 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
sahilmgandhi 18:6a4db94011d3 504 } FSMC_Bank1E_TypeDef;
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 /**
sahilmgandhi 18:6a4db94011d3 507 * @brief Flexible Static Memory Controller Bank2
sahilmgandhi 18:6a4db94011d3 508 */
sahilmgandhi 18:6a4db94011d3 509
sahilmgandhi 18:6a4db94011d3 510 typedef struct
sahilmgandhi 18:6a4db94011d3 511 {
sahilmgandhi 18:6a4db94011d3 512 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 513 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
sahilmgandhi 18:6a4db94011d3 514 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
sahilmgandhi 18:6a4db94011d3 515 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
sahilmgandhi 18:6a4db94011d3 516 uint32_t RESERVED0; /*!< Reserved, 0x70 */
sahilmgandhi 18:6a4db94011d3 517 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
sahilmgandhi 18:6a4db94011d3 518 uint32_t RESERVED1; /*!< Reserved, 0x78 */
sahilmgandhi 18:6a4db94011d3 519 uint32_t RESERVED2; /*!< Reserved, 0x7C */
sahilmgandhi 18:6a4db94011d3 520 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 521 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 522 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
sahilmgandhi 18:6a4db94011d3 523 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
sahilmgandhi 18:6a4db94011d3 524 uint32_t RESERVED3; /*!< Reserved, 0x90 */
sahilmgandhi 18:6a4db94011d3 525 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
sahilmgandhi 18:6a4db94011d3 526 } FSMC_Bank2_3_TypeDef;
sahilmgandhi 18:6a4db94011d3 527
sahilmgandhi 18:6a4db94011d3 528 /**
sahilmgandhi 18:6a4db94011d3 529 * @brief Flexible Static Memory Controller Bank4
sahilmgandhi 18:6a4db94011d3 530 */
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 typedef struct
sahilmgandhi 18:6a4db94011d3 533 {
sahilmgandhi 18:6a4db94011d3 534 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
sahilmgandhi 18:6a4db94011d3 535 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
sahilmgandhi 18:6a4db94011d3 536 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
sahilmgandhi 18:6a4db94011d3 537 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
sahilmgandhi 18:6a4db94011d3 538 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
sahilmgandhi 18:6a4db94011d3 539 } FSMC_Bank4_TypeDef;
sahilmgandhi 18:6a4db94011d3 540
sahilmgandhi 18:6a4db94011d3 541
sahilmgandhi 18:6a4db94011d3 542 /**
sahilmgandhi 18:6a4db94011d3 543 * @brief General Purpose I/O
sahilmgandhi 18:6a4db94011d3 544 */
sahilmgandhi 18:6a4db94011d3 545
sahilmgandhi 18:6a4db94011d3 546 typedef struct
sahilmgandhi 18:6a4db94011d3 547 {
sahilmgandhi 18:6a4db94011d3 548 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 549 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 550 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 551 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 552 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 553 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 554 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 555 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 556 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
sahilmgandhi 18:6a4db94011d3 557 } GPIO_TypeDef;
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559 /**
sahilmgandhi 18:6a4db94011d3 560 * @brief System configuration controller
sahilmgandhi 18:6a4db94011d3 561 */
sahilmgandhi 18:6a4db94011d3 562
sahilmgandhi 18:6a4db94011d3 563 typedef struct
sahilmgandhi 18:6a4db94011d3 564 {
sahilmgandhi 18:6a4db94011d3 565 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 566 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 567 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
sahilmgandhi 18:6a4db94011d3 568 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
sahilmgandhi 18:6a4db94011d3 569 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 570 } SYSCFG_TypeDef;
sahilmgandhi 18:6a4db94011d3 571
sahilmgandhi 18:6a4db94011d3 572 /**
sahilmgandhi 18:6a4db94011d3 573 * @brief Inter-integrated Circuit Interface
sahilmgandhi 18:6a4db94011d3 574 */
sahilmgandhi 18:6a4db94011d3 575
sahilmgandhi 18:6a4db94011d3 576 typedef struct
sahilmgandhi 18:6a4db94011d3 577 {
sahilmgandhi 18:6a4db94011d3 578 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 579 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 580 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 581 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 582 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 583 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 584 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 585 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 586 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 587 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 588 } I2C_TypeDef;
sahilmgandhi 18:6a4db94011d3 589
sahilmgandhi 18:6a4db94011d3 590 /**
sahilmgandhi 18:6a4db94011d3 591 * @brief Independent WATCHDOG
sahilmgandhi 18:6a4db94011d3 592 */
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 typedef struct
sahilmgandhi 18:6a4db94011d3 595 {
sahilmgandhi 18:6a4db94011d3 596 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 597 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 598 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 599 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 600 } IWDG_TypeDef;
sahilmgandhi 18:6a4db94011d3 601
sahilmgandhi 18:6a4db94011d3 602 /**
sahilmgandhi 18:6a4db94011d3 603 * @brief Power Control
sahilmgandhi 18:6a4db94011d3 604 */
sahilmgandhi 18:6a4db94011d3 605
sahilmgandhi 18:6a4db94011d3 606 typedef struct
sahilmgandhi 18:6a4db94011d3 607 {
sahilmgandhi 18:6a4db94011d3 608 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 609 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 610 } PWR_TypeDef;
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612 /**
sahilmgandhi 18:6a4db94011d3 613 * @brief Reset and Clock Control
sahilmgandhi 18:6a4db94011d3 614 */
sahilmgandhi 18:6a4db94011d3 615
sahilmgandhi 18:6a4db94011d3 616 typedef struct
sahilmgandhi 18:6a4db94011d3 617 {
sahilmgandhi 18:6a4db94011d3 618 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 619 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 620 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 621 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 622 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 623 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 624 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 625 uint32_t RESERVED0; /*!< Reserved, 0x1C */
sahilmgandhi 18:6a4db94011d3 626 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 627 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 628 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
sahilmgandhi 18:6a4db94011d3 629 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 630 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 631 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 632 uint32_t RESERVED2; /*!< Reserved, 0x3C */
sahilmgandhi 18:6a4db94011d3 633 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 634 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 635 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
sahilmgandhi 18:6a4db94011d3 636 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 637 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
sahilmgandhi 18:6a4db94011d3 638 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
sahilmgandhi 18:6a4db94011d3 639 uint32_t RESERVED4; /*!< Reserved, 0x5C */
sahilmgandhi 18:6a4db94011d3 640 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 641 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
sahilmgandhi 18:6a4db94011d3 642 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
sahilmgandhi 18:6a4db94011d3 643 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
sahilmgandhi 18:6a4db94011d3 644 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
sahilmgandhi 18:6a4db94011d3 645 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
sahilmgandhi 18:6a4db94011d3 646 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 647 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 648
sahilmgandhi 18:6a4db94011d3 649 } RCC_TypeDef;
sahilmgandhi 18:6a4db94011d3 650
sahilmgandhi 18:6a4db94011d3 651 /**
sahilmgandhi 18:6a4db94011d3 652 * @brief Real-Time Clock
sahilmgandhi 18:6a4db94011d3 653 */
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 typedef struct
sahilmgandhi 18:6a4db94011d3 656 {
sahilmgandhi 18:6a4db94011d3 657 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 658 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 659 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 660 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 661 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 662 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 663 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 664 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 665 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 666 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 667 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 668 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 669 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 670 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 671 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 672 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 673 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 674 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 675 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 676 uint32_t RESERVED7; /*!< Reserved, 0x4C */
sahilmgandhi 18:6a4db94011d3 677 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 678 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
sahilmgandhi 18:6a4db94011d3 679 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
sahilmgandhi 18:6a4db94011d3 680 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
sahilmgandhi 18:6a4db94011d3 681 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 682 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
sahilmgandhi 18:6a4db94011d3 683 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
sahilmgandhi 18:6a4db94011d3 684 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
sahilmgandhi 18:6a4db94011d3 685 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
sahilmgandhi 18:6a4db94011d3 686 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
sahilmgandhi 18:6a4db94011d3 687 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
sahilmgandhi 18:6a4db94011d3 688 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
sahilmgandhi 18:6a4db94011d3 689 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 690 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 691 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
sahilmgandhi 18:6a4db94011d3 692 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
sahilmgandhi 18:6a4db94011d3 693 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
sahilmgandhi 18:6a4db94011d3 694 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
sahilmgandhi 18:6a4db94011d3 695 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
sahilmgandhi 18:6a4db94011d3 696 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
sahilmgandhi 18:6a4db94011d3 697 } RTC_TypeDef;
sahilmgandhi 18:6a4db94011d3 698
sahilmgandhi 18:6a4db94011d3 699
sahilmgandhi 18:6a4db94011d3 700 /**
sahilmgandhi 18:6a4db94011d3 701 * @brief SD host Interface
sahilmgandhi 18:6a4db94011d3 702 */
sahilmgandhi 18:6a4db94011d3 703
sahilmgandhi 18:6a4db94011d3 704 typedef struct
sahilmgandhi 18:6a4db94011d3 705 {
sahilmgandhi 18:6a4db94011d3 706 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 707 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 708 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 709 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 710 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 711 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 712 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 713 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 714 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 715 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 716 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 717 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 718 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 719 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 720 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 721 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 722 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
sahilmgandhi 18:6a4db94011d3 723 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 724 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
sahilmgandhi 18:6a4db94011d3 725 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 726 } SDIO_TypeDef;
sahilmgandhi 18:6a4db94011d3 727
sahilmgandhi 18:6a4db94011d3 728 /**
sahilmgandhi 18:6a4db94011d3 729 * @brief Serial Peripheral Interface
sahilmgandhi 18:6a4db94011d3 730 */
sahilmgandhi 18:6a4db94011d3 731
sahilmgandhi 18:6a4db94011d3 732 typedef struct
sahilmgandhi 18:6a4db94011d3 733 {
sahilmgandhi 18:6a4db94011d3 734 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 735 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 736 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 737 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 738 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 739 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 740 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 741 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 742 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 743 } SPI_TypeDef;
sahilmgandhi 18:6a4db94011d3 744
sahilmgandhi 18:6a4db94011d3 745 /**
sahilmgandhi 18:6a4db94011d3 746 * @brief TIM
sahilmgandhi 18:6a4db94011d3 747 */
sahilmgandhi 18:6a4db94011d3 748
sahilmgandhi 18:6a4db94011d3 749 typedef struct
sahilmgandhi 18:6a4db94011d3 750 {
sahilmgandhi 18:6a4db94011d3 751 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 752 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 753 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 754 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 755 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 756 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 757 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 758 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 759 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 760 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 761 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 762 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 763 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 764 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 765 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 766 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 767 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 768 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 769 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 770 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 771 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 772 } TIM_TypeDef;
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 /**
sahilmgandhi 18:6a4db94011d3 775 * @brief Universal Synchronous Asynchronous Receiver Transmitter
sahilmgandhi 18:6a4db94011d3 776 */
sahilmgandhi 18:6a4db94011d3 777
sahilmgandhi 18:6a4db94011d3 778 typedef struct
sahilmgandhi 18:6a4db94011d3 779 {
sahilmgandhi 18:6a4db94011d3 780 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 781 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 782 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 783 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 784 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 785 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 786 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 787 } USART_TypeDef;
sahilmgandhi 18:6a4db94011d3 788
sahilmgandhi 18:6a4db94011d3 789 /**
sahilmgandhi 18:6a4db94011d3 790 * @brief Window WATCHDOG
sahilmgandhi 18:6a4db94011d3 791 */
sahilmgandhi 18:6a4db94011d3 792
sahilmgandhi 18:6a4db94011d3 793 typedef struct
sahilmgandhi 18:6a4db94011d3 794 {
sahilmgandhi 18:6a4db94011d3 795 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 796 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 797 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 798 } WWDG_TypeDef;
sahilmgandhi 18:6a4db94011d3 799
sahilmgandhi 18:6a4db94011d3 800 /**
sahilmgandhi 18:6a4db94011d3 801 * @brief RNG
sahilmgandhi 18:6a4db94011d3 802 */
sahilmgandhi 18:6a4db94011d3 803
sahilmgandhi 18:6a4db94011d3 804 typedef struct
sahilmgandhi 18:6a4db94011d3 805 {
sahilmgandhi 18:6a4db94011d3 806 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 807 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 808 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 809 } RNG_TypeDef;
sahilmgandhi 18:6a4db94011d3 810
sahilmgandhi 18:6a4db94011d3 811
sahilmgandhi 18:6a4db94011d3 812
sahilmgandhi 18:6a4db94011d3 813 /**
sahilmgandhi 18:6a4db94011d3 814 * @brief __USB_OTG_Core_register
sahilmgandhi 18:6a4db94011d3 815 */
sahilmgandhi 18:6a4db94011d3 816 typedef struct
sahilmgandhi 18:6a4db94011d3 817 {
sahilmgandhi 18:6a4db94011d3 818 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
sahilmgandhi 18:6a4db94011d3 819 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
sahilmgandhi 18:6a4db94011d3 820 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
sahilmgandhi 18:6a4db94011d3 821 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
sahilmgandhi 18:6a4db94011d3 822 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
sahilmgandhi 18:6a4db94011d3 823 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
sahilmgandhi 18:6a4db94011d3 824 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
sahilmgandhi 18:6a4db94011d3 825 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
sahilmgandhi 18:6a4db94011d3 826 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
sahilmgandhi 18:6a4db94011d3 827 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
sahilmgandhi 18:6a4db94011d3 828 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
sahilmgandhi 18:6a4db94011d3 829 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
sahilmgandhi 18:6a4db94011d3 830 uint32_t Reserved30[2]; /* Reserved 030h*/
sahilmgandhi 18:6a4db94011d3 831 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
sahilmgandhi 18:6a4db94011d3 832 __IO uint32_t CID; /* User ID Register 03Ch*/
sahilmgandhi 18:6a4db94011d3 833 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
sahilmgandhi 18:6a4db94011d3 834 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
sahilmgandhi 18:6a4db94011d3 835 __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
sahilmgandhi 18:6a4db94011d3 836 }
sahilmgandhi 18:6a4db94011d3 837 USB_OTG_GlobalTypeDef;
sahilmgandhi 18:6a4db94011d3 838
sahilmgandhi 18:6a4db94011d3 839
sahilmgandhi 18:6a4db94011d3 840
sahilmgandhi 18:6a4db94011d3 841 /**
sahilmgandhi 18:6a4db94011d3 842 * @brief __device_Registers
sahilmgandhi 18:6a4db94011d3 843 */
sahilmgandhi 18:6a4db94011d3 844 typedef struct
sahilmgandhi 18:6a4db94011d3 845 {
sahilmgandhi 18:6a4db94011d3 846 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
sahilmgandhi 18:6a4db94011d3 847 __IO uint32_t DCTL; /* dev Control Register 804h*/
sahilmgandhi 18:6a4db94011d3 848 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
sahilmgandhi 18:6a4db94011d3 849 uint32_t Reserved0C; /* Reserved 80Ch*/
sahilmgandhi 18:6a4db94011d3 850 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
sahilmgandhi 18:6a4db94011d3 851 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
sahilmgandhi 18:6a4db94011d3 852 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
sahilmgandhi 18:6a4db94011d3 853 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
sahilmgandhi 18:6a4db94011d3 854 uint32_t Reserved20; /* Reserved 820h*/
sahilmgandhi 18:6a4db94011d3 855 uint32_t Reserved9; /* Reserved 824h*/
sahilmgandhi 18:6a4db94011d3 856 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
sahilmgandhi 18:6a4db94011d3 857 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
sahilmgandhi 18:6a4db94011d3 858 __IO uint32_t DTHRCTL; /* dev thr 830h*/
sahilmgandhi 18:6a4db94011d3 859 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
sahilmgandhi 18:6a4db94011d3 860 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
sahilmgandhi 18:6a4db94011d3 861 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
sahilmgandhi 18:6a4db94011d3 862 uint32_t Reserved40; /* dedicated EP mask 840h*/
sahilmgandhi 18:6a4db94011d3 863 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
sahilmgandhi 18:6a4db94011d3 864 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
sahilmgandhi 18:6a4db94011d3 865 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
sahilmgandhi 18:6a4db94011d3 866 }
sahilmgandhi 18:6a4db94011d3 867 USB_OTG_DeviceTypeDef;
sahilmgandhi 18:6a4db94011d3 868
sahilmgandhi 18:6a4db94011d3 869
sahilmgandhi 18:6a4db94011d3 870 /**
sahilmgandhi 18:6a4db94011d3 871 * @brief __IN_Endpoint-Specific_Register
sahilmgandhi 18:6a4db94011d3 872 */
sahilmgandhi 18:6a4db94011d3 873 typedef struct
sahilmgandhi 18:6a4db94011d3 874 {
sahilmgandhi 18:6a4db94011d3 875 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
sahilmgandhi 18:6a4db94011d3 876 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
sahilmgandhi 18:6a4db94011d3 877 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
sahilmgandhi 18:6a4db94011d3 878 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
sahilmgandhi 18:6a4db94011d3 879 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
sahilmgandhi 18:6a4db94011d3 880 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
sahilmgandhi 18:6a4db94011d3 881 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
sahilmgandhi 18:6a4db94011d3 882 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
sahilmgandhi 18:6a4db94011d3 883 }
sahilmgandhi 18:6a4db94011d3 884 USB_OTG_INEndpointTypeDef;
sahilmgandhi 18:6a4db94011d3 885
sahilmgandhi 18:6a4db94011d3 886
sahilmgandhi 18:6a4db94011d3 887 /**
sahilmgandhi 18:6a4db94011d3 888 * @brief __OUT_Endpoint-Specific_Registers
sahilmgandhi 18:6a4db94011d3 889 */
sahilmgandhi 18:6a4db94011d3 890 typedef struct
sahilmgandhi 18:6a4db94011d3 891 {
sahilmgandhi 18:6a4db94011d3 892 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
sahilmgandhi 18:6a4db94011d3 893 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
sahilmgandhi 18:6a4db94011d3 894 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
sahilmgandhi 18:6a4db94011d3 895 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
sahilmgandhi 18:6a4db94011d3 896 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
sahilmgandhi 18:6a4db94011d3 897 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
sahilmgandhi 18:6a4db94011d3 898 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
sahilmgandhi 18:6a4db94011d3 899 }
sahilmgandhi 18:6a4db94011d3 900 USB_OTG_OUTEndpointTypeDef;
sahilmgandhi 18:6a4db94011d3 901
sahilmgandhi 18:6a4db94011d3 902
sahilmgandhi 18:6a4db94011d3 903 /**
sahilmgandhi 18:6a4db94011d3 904 * @brief __Host_Mode_Register_Structures
sahilmgandhi 18:6a4db94011d3 905 */
sahilmgandhi 18:6a4db94011d3 906 typedef struct
sahilmgandhi 18:6a4db94011d3 907 {
sahilmgandhi 18:6a4db94011d3 908 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
sahilmgandhi 18:6a4db94011d3 909 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
sahilmgandhi 18:6a4db94011d3 910 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
sahilmgandhi 18:6a4db94011d3 911 uint32_t Reserved40C; /* Reserved 40Ch*/
sahilmgandhi 18:6a4db94011d3 912 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
sahilmgandhi 18:6a4db94011d3 913 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
sahilmgandhi 18:6a4db94011d3 914 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
sahilmgandhi 18:6a4db94011d3 915 }
sahilmgandhi 18:6a4db94011d3 916 USB_OTG_HostTypeDef;
sahilmgandhi 18:6a4db94011d3 917
sahilmgandhi 18:6a4db94011d3 918
sahilmgandhi 18:6a4db94011d3 919 /**
sahilmgandhi 18:6a4db94011d3 920 * @brief __Host_Channel_Specific_Registers
sahilmgandhi 18:6a4db94011d3 921 */
sahilmgandhi 18:6a4db94011d3 922 typedef struct
sahilmgandhi 18:6a4db94011d3 923 {
sahilmgandhi 18:6a4db94011d3 924 __IO uint32_t HCCHAR;
sahilmgandhi 18:6a4db94011d3 925 __IO uint32_t HCSPLT;
sahilmgandhi 18:6a4db94011d3 926 __IO uint32_t HCINT;
sahilmgandhi 18:6a4db94011d3 927 __IO uint32_t HCINTMSK;
sahilmgandhi 18:6a4db94011d3 928 __IO uint32_t HCTSIZ;
sahilmgandhi 18:6a4db94011d3 929 __IO uint32_t HCDMA;
sahilmgandhi 18:6a4db94011d3 930 uint32_t Reserved[2];
sahilmgandhi 18:6a4db94011d3 931 }
sahilmgandhi 18:6a4db94011d3 932 USB_OTG_HostChannelTypeDef;
sahilmgandhi 18:6a4db94011d3 933
sahilmgandhi 18:6a4db94011d3 934
sahilmgandhi 18:6a4db94011d3 935 /**
sahilmgandhi 18:6a4db94011d3 936 * @brief Peripheral_memory_map
sahilmgandhi 18:6a4db94011d3 937 */
sahilmgandhi 18:6a4db94011d3 938 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 939 #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 940 #define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 941 #define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 942 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
sahilmgandhi 18:6a4db94011d3 943 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 944 #define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
sahilmgandhi 18:6a4db94011d3 945 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
sahilmgandhi 18:6a4db94011d3 946 #define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
sahilmgandhi 18:6a4db94011d3 947 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
sahilmgandhi 18:6a4db94011d3 948 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
sahilmgandhi 18:6a4db94011d3 949 #define FLASH_END 0x080FFFFFU /*!< FLASH end address */
sahilmgandhi 18:6a4db94011d3 950 #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
sahilmgandhi 18:6a4db94011d3 951
sahilmgandhi 18:6a4db94011d3 952 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 953 #define SRAM_BASE SRAM1_BASE
sahilmgandhi 18:6a4db94011d3 954 #define SRAM_BB_BASE SRAM1_BB_BASE
sahilmgandhi 18:6a4db94011d3 955
sahilmgandhi 18:6a4db94011d3 956
sahilmgandhi 18:6a4db94011d3 957 /*!< Peripheral memory map */
sahilmgandhi 18:6a4db94011d3 958 #define APB1PERIPH_BASE PERIPH_BASE
sahilmgandhi 18:6a4db94011d3 959 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
sahilmgandhi 18:6a4db94011d3 960 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
sahilmgandhi 18:6a4db94011d3 961 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
sahilmgandhi 18:6a4db94011d3 962
sahilmgandhi 18:6a4db94011d3 963 /*!< APB1 peripherals */
sahilmgandhi 18:6a4db94011d3 964 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
sahilmgandhi 18:6a4db94011d3 965 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
sahilmgandhi 18:6a4db94011d3 966 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
sahilmgandhi 18:6a4db94011d3 967 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
sahilmgandhi 18:6a4db94011d3 968 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
sahilmgandhi 18:6a4db94011d3 969 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
sahilmgandhi 18:6a4db94011d3 970 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
sahilmgandhi 18:6a4db94011d3 971 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
sahilmgandhi 18:6a4db94011d3 972 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
sahilmgandhi 18:6a4db94011d3 973 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
sahilmgandhi 18:6a4db94011d3 974 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
sahilmgandhi 18:6a4db94011d3 975 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
sahilmgandhi 18:6a4db94011d3 976 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
sahilmgandhi 18:6a4db94011d3 977 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
sahilmgandhi 18:6a4db94011d3 978 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
sahilmgandhi 18:6a4db94011d3 979 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
sahilmgandhi 18:6a4db94011d3 980 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
sahilmgandhi 18:6a4db94011d3 981 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
sahilmgandhi 18:6a4db94011d3 982 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
sahilmgandhi 18:6a4db94011d3 983 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
sahilmgandhi 18:6a4db94011d3 984 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
sahilmgandhi 18:6a4db94011d3 985 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
sahilmgandhi 18:6a4db94011d3 986 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
sahilmgandhi 18:6a4db94011d3 987 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
sahilmgandhi 18:6a4db94011d3 988 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
sahilmgandhi 18:6a4db94011d3 989 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
sahilmgandhi 18:6a4db94011d3 990 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
sahilmgandhi 18:6a4db94011d3 991
sahilmgandhi 18:6a4db94011d3 992 /*!< APB2 peripherals */
sahilmgandhi 18:6a4db94011d3 993 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
sahilmgandhi 18:6a4db94011d3 994 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
sahilmgandhi 18:6a4db94011d3 995 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
sahilmgandhi 18:6a4db94011d3 996 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
sahilmgandhi 18:6a4db94011d3 997 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
sahilmgandhi 18:6a4db94011d3 998 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
sahilmgandhi 18:6a4db94011d3 999 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
sahilmgandhi 18:6a4db94011d3 1000 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
sahilmgandhi 18:6a4db94011d3 1001 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
sahilmgandhi 18:6a4db94011d3 1002 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
sahilmgandhi 18:6a4db94011d3 1003 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
sahilmgandhi 18:6a4db94011d3 1004 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
sahilmgandhi 18:6a4db94011d3 1005 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
sahilmgandhi 18:6a4db94011d3 1006 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
sahilmgandhi 18:6a4db94011d3 1007 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
sahilmgandhi 18:6a4db94011d3 1008
sahilmgandhi 18:6a4db94011d3 1009 /*!< AHB1 peripherals */
sahilmgandhi 18:6a4db94011d3 1010 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
sahilmgandhi 18:6a4db94011d3 1011 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
sahilmgandhi 18:6a4db94011d3 1012 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
sahilmgandhi 18:6a4db94011d3 1013 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
sahilmgandhi 18:6a4db94011d3 1014 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
sahilmgandhi 18:6a4db94011d3 1015 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
sahilmgandhi 18:6a4db94011d3 1016 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
sahilmgandhi 18:6a4db94011d3 1017 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
sahilmgandhi 18:6a4db94011d3 1018 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
sahilmgandhi 18:6a4db94011d3 1019 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
sahilmgandhi 18:6a4db94011d3 1020 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
sahilmgandhi 18:6a4db94011d3 1021 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
sahilmgandhi 18:6a4db94011d3 1022 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
sahilmgandhi 18:6a4db94011d3 1023 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
sahilmgandhi 18:6a4db94011d3 1024 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
sahilmgandhi 18:6a4db94011d3 1025 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
sahilmgandhi 18:6a4db94011d3 1026 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
sahilmgandhi 18:6a4db94011d3 1027 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
sahilmgandhi 18:6a4db94011d3 1028 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
sahilmgandhi 18:6a4db94011d3 1029 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
sahilmgandhi 18:6a4db94011d3 1030 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
sahilmgandhi 18:6a4db94011d3 1031 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
sahilmgandhi 18:6a4db94011d3 1032 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
sahilmgandhi 18:6a4db94011d3 1033 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
sahilmgandhi 18:6a4db94011d3 1034 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
sahilmgandhi 18:6a4db94011d3 1035 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
sahilmgandhi 18:6a4db94011d3 1036 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
sahilmgandhi 18:6a4db94011d3 1037 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
sahilmgandhi 18:6a4db94011d3 1038 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
sahilmgandhi 18:6a4db94011d3 1039 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
sahilmgandhi 18:6a4db94011d3 1040 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
sahilmgandhi 18:6a4db94011d3 1041 #define ETH_MAC_BASE (ETH_BASE)
sahilmgandhi 18:6a4db94011d3 1042 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
sahilmgandhi 18:6a4db94011d3 1043 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
sahilmgandhi 18:6a4db94011d3 1044 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
sahilmgandhi 18:6a4db94011d3 1045
sahilmgandhi 18:6a4db94011d3 1046 /*!< AHB2 peripherals */
sahilmgandhi 18:6a4db94011d3 1047 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
sahilmgandhi 18:6a4db94011d3 1048 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
sahilmgandhi 18:6a4db94011d3 1049
sahilmgandhi 18:6a4db94011d3 1050 /*!< FSMC Bankx registers base address */
sahilmgandhi 18:6a4db94011d3 1051 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
sahilmgandhi 18:6a4db94011d3 1052 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
sahilmgandhi 18:6a4db94011d3 1053 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
sahilmgandhi 18:6a4db94011d3 1054 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
sahilmgandhi 18:6a4db94011d3 1055
sahilmgandhi 18:6a4db94011d3 1056 /* Debug MCU registers base address */
sahilmgandhi 18:6a4db94011d3 1057 #define DBGMCU_BASE 0xE0042000U
sahilmgandhi 18:6a4db94011d3 1058
sahilmgandhi 18:6a4db94011d3 1059 /*!< USB registers base address */
sahilmgandhi 18:6a4db94011d3 1060 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
sahilmgandhi 18:6a4db94011d3 1061 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
sahilmgandhi 18:6a4db94011d3 1062
sahilmgandhi 18:6a4db94011d3 1063 #define USB_OTG_GLOBAL_BASE 0x000U
sahilmgandhi 18:6a4db94011d3 1064 #define USB_OTG_DEVICE_BASE 0x800U
sahilmgandhi 18:6a4db94011d3 1065 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
sahilmgandhi 18:6a4db94011d3 1066 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
sahilmgandhi 18:6a4db94011d3 1067 #define USB_OTG_EP_REG_SIZE 0x20U
sahilmgandhi 18:6a4db94011d3 1068 #define USB_OTG_HOST_BASE 0x400U
sahilmgandhi 18:6a4db94011d3 1069 #define USB_OTG_HOST_PORT_BASE 0x440U
sahilmgandhi 18:6a4db94011d3 1070 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
sahilmgandhi 18:6a4db94011d3 1071 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
sahilmgandhi 18:6a4db94011d3 1072 #define USB_OTG_PCGCCTL_BASE 0xE00U
sahilmgandhi 18:6a4db94011d3 1073 #define USB_OTG_FIFO_BASE 0x1000U
sahilmgandhi 18:6a4db94011d3 1074 #define USB_OTG_FIFO_SIZE 0x1000U
sahilmgandhi 18:6a4db94011d3 1075
sahilmgandhi 18:6a4db94011d3 1076 /**
sahilmgandhi 18:6a4db94011d3 1077 * @}
sahilmgandhi 18:6a4db94011d3 1078 */
sahilmgandhi 18:6a4db94011d3 1079
sahilmgandhi 18:6a4db94011d3 1080 /** @addtogroup Peripheral_declaration
sahilmgandhi 18:6a4db94011d3 1081 * @{
sahilmgandhi 18:6a4db94011d3 1082 */
sahilmgandhi 18:6a4db94011d3 1083 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
sahilmgandhi 18:6a4db94011d3 1084 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
sahilmgandhi 18:6a4db94011d3 1085 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
sahilmgandhi 18:6a4db94011d3 1086 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
sahilmgandhi 18:6a4db94011d3 1087 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
sahilmgandhi 18:6a4db94011d3 1088 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
sahilmgandhi 18:6a4db94011d3 1089 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
sahilmgandhi 18:6a4db94011d3 1090 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
sahilmgandhi 18:6a4db94011d3 1091 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
sahilmgandhi 18:6a4db94011d3 1092 #define RTC ((RTC_TypeDef *) RTC_BASE)
sahilmgandhi 18:6a4db94011d3 1093 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
sahilmgandhi 18:6a4db94011d3 1094 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
sahilmgandhi 18:6a4db94011d3 1095 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
sahilmgandhi 18:6a4db94011d3 1096 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
sahilmgandhi 18:6a4db94011d3 1097 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
sahilmgandhi 18:6a4db94011d3 1098 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
sahilmgandhi 18:6a4db94011d3 1099 #define USART2 ((USART_TypeDef *) USART2_BASE)
sahilmgandhi 18:6a4db94011d3 1100 #define USART3 ((USART_TypeDef *) USART3_BASE)
sahilmgandhi 18:6a4db94011d3 1101 #define UART4 ((USART_TypeDef *) UART4_BASE)
sahilmgandhi 18:6a4db94011d3 1102 #define UART5 ((USART_TypeDef *) UART5_BASE)
sahilmgandhi 18:6a4db94011d3 1103 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 1104 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
sahilmgandhi 18:6a4db94011d3 1105 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
sahilmgandhi 18:6a4db94011d3 1106 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
sahilmgandhi 18:6a4db94011d3 1107 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
sahilmgandhi 18:6a4db94011d3 1108 #define PWR ((PWR_TypeDef *) PWR_BASE)
sahilmgandhi 18:6a4db94011d3 1109 #define DAC ((DAC_TypeDef *) DAC_BASE)
sahilmgandhi 18:6a4db94011d3 1110 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
sahilmgandhi 18:6a4db94011d3 1111 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
sahilmgandhi 18:6a4db94011d3 1112 #define USART1 ((USART_TypeDef *) USART1_BASE)
sahilmgandhi 18:6a4db94011d3 1113 #define USART6 ((USART_TypeDef *) USART6_BASE)
sahilmgandhi 18:6a4db94011d3 1114 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
sahilmgandhi 18:6a4db94011d3 1115 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
sahilmgandhi 18:6a4db94011d3 1116 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
sahilmgandhi 18:6a4db94011d3 1117 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
sahilmgandhi 18:6a4db94011d3 1118 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
sahilmgandhi 18:6a4db94011d3 1119 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
sahilmgandhi 18:6a4db94011d3 1120 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
sahilmgandhi 18:6a4db94011d3 1121 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
sahilmgandhi 18:6a4db94011d3 1122 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
sahilmgandhi 18:6a4db94011d3 1123 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
sahilmgandhi 18:6a4db94011d3 1124 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
sahilmgandhi 18:6a4db94011d3 1125 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
sahilmgandhi 18:6a4db94011d3 1126 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
sahilmgandhi 18:6a4db94011d3 1127 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
sahilmgandhi 18:6a4db94011d3 1128 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
sahilmgandhi 18:6a4db94011d3 1129 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
sahilmgandhi 18:6a4db94011d3 1130 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
sahilmgandhi 18:6a4db94011d3 1131 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
sahilmgandhi 18:6a4db94011d3 1132 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
sahilmgandhi 18:6a4db94011d3 1133 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
sahilmgandhi 18:6a4db94011d3 1134 #define CRC ((CRC_TypeDef *) CRC_BASE)
sahilmgandhi 18:6a4db94011d3 1135 #define RCC ((RCC_TypeDef *) RCC_BASE)
sahilmgandhi 18:6a4db94011d3 1136 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
sahilmgandhi 18:6a4db94011d3 1137 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
sahilmgandhi 18:6a4db94011d3 1138 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
sahilmgandhi 18:6a4db94011d3 1139 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
sahilmgandhi 18:6a4db94011d3 1140 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
sahilmgandhi 18:6a4db94011d3 1141 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
sahilmgandhi 18:6a4db94011d3 1142 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
sahilmgandhi 18:6a4db94011d3 1143 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
sahilmgandhi 18:6a4db94011d3 1144 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
sahilmgandhi 18:6a4db94011d3 1145 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
sahilmgandhi 18:6a4db94011d3 1146 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
sahilmgandhi 18:6a4db94011d3 1147 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
sahilmgandhi 18:6a4db94011d3 1148 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
sahilmgandhi 18:6a4db94011d3 1149 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
sahilmgandhi 18:6a4db94011d3 1150 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
sahilmgandhi 18:6a4db94011d3 1151 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
sahilmgandhi 18:6a4db94011d3 1152 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
sahilmgandhi 18:6a4db94011d3 1153 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
sahilmgandhi 18:6a4db94011d3 1154 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
sahilmgandhi 18:6a4db94011d3 1155 #define ETH ((ETH_TypeDef *) ETH_BASE)
sahilmgandhi 18:6a4db94011d3 1156 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
sahilmgandhi 18:6a4db94011d3 1157 #define RNG ((RNG_TypeDef *) RNG_BASE)
sahilmgandhi 18:6a4db94011d3 1158 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
sahilmgandhi 18:6a4db94011d3 1159 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
sahilmgandhi 18:6a4db94011d3 1160 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
sahilmgandhi 18:6a4db94011d3 1161 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
sahilmgandhi 18:6a4db94011d3 1162
sahilmgandhi 18:6a4db94011d3 1163 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
sahilmgandhi 18:6a4db94011d3 1164
sahilmgandhi 18:6a4db94011d3 1165 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
sahilmgandhi 18:6a4db94011d3 1166 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
sahilmgandhi 18:6a4db94011d3 1167
sahilmgandhi 18:6a4db94011d3 1168 /**
sahilmgandhi 18:6a4db94011d3 1169 * @}
sahilmgandhi 18:6a4db94011d3 1170 */
sahilmgandhi 18:6a4db94011d3 1171
sahilmgandhi 18:6a4db94011d3 1172 /** @addtogroup Exported_constants
sahilmgandhi 18:6a4db94011d3 1173 * @{
sahilmgandhi 18:6a4db94011d3 1174 */
sahilmgandhi 18:6a4db94011d3 1175
sahilmgandhi 18:6a4db94011d3 1176 /** @addtogroup Peripheral_Registers_Bits_Definition
sahilmgandhi 18:6a4db94011d3 1177 * @{
sahilmgandhi 18:6a4db94011d3 1178 */
sahilmgandhi 18:6a4db94011d3 1179
sahilmgandhi 18:6a4db94011d3 1180 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1181 /* Peripheral Registers_Bits_Definition */
sahilmgandhi 18:6a4db94011d3 1182 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1183
sahilmgandhi 18:6a4db94011d3 1184 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1185 /* */
sahilmgandhi 18:6a4db94011d3 1186 /* Analog to Digital Converter */
sahilmgandhi 18:6a4db94011d3 1187 /* */
sahilmgandhi 18:6a4db94011d3 1188 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1189 /******************** Bit definition for ADC_SR register ********************/
sahilmgandhi 18:6a4db94011d3 1190 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 1191 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
sahilmgandhi 18:6a4db94011d3 1192 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
sahilmgandhi 18:6a4db94011d3 1193 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
sahilmgandhi 18:6a4db94011d3 1194 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
sahilmgandhi 18:6a4db94011d3 1195 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
sahilmgandhi 18:6a4db94011d3 1196
sahilmgandhi 18:6a4db94011d3 1197 /******************* Bit definition for ADC_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 1198 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
sahilmgandhi 18:6a4db94011d3 1199 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1200 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1201 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1202 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1203 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1204 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
sahilmgandhi 18:6a4db94011d3 1205 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
sahilmgandhi 18:6a4db94011d3 1206 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
sahilmgandhi 18:6a4db94011d3 1207 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
sahilmgandhi 18:6a4db94011d3 1208 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
sahilmgandhi 18:6a4db94011d3 1209 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
sahilmgandhi 18:6a4db94011d3 1210 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
sahilmgandhi 18:6a4db94011d3 1211 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
sahilmgandhi 18:6a4db94011d3 1212 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
sahilmgandhi 18:6a4db94011d3 1213 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1214 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1215 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1216 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
sahilmgandhi 18:6a4db94011d3 1217 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
sahilmgandhi 18:6a4db94011d3 1218 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
sahilmgandhi 18:6a4db94011d3 1219 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1220 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1221 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
sahilmgandhi 18:6a4db94011d3 1222
sahilmgandhi 18:6a4db94011d3 1223 /******************* Bit definition for ADC_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 1224 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
sahilmgandhi 18:6a4db94011d3 1225 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
sahilmgandhi 18:6a4db94011d3 1226 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
sahilmgandhi 18:6a4db94011d3 1227 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
sahilmgandhi 18:6a4db94011d3 1228 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
sahilmgandhi 18:6a4db94011d3 1229 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
sahilmgandhi 18:6a4db94011d3 1230 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
sahilmgandhi 18:6a4db94011d3 1231 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1232 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1233 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1234 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1235 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
sahilmgandhi 18:6a4db94011d3 1236 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1237 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1238 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
sahilmgandhi 18:6a4db94011d3 1239 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
sahilmgandhi 18:6a4db94011d3 1240 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1241 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1242 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1243 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1244 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
sahilmgandhi 18:6a4db94011d3 1245 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1246 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1247 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
sahilmgandhi 18:6a4db94011d3 1248
sahilmgandhi 18:6a4db94011d3 1249 /****************** Bit definition for ADC_SMPR1 register *******************/
sahilmgandhi 18:6a4db94011d3 1250 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1251 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1252 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1253 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1254 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1255 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1256 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1257 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1258 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1259 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1260 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1261 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1262 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1263 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1264 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1265 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1266 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1267 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1268 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1269 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1270 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1271 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1272 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1273 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1274 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1275 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1276 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1277 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1278 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1279 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1280 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1281 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1282 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1283 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1284 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1285 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1286
sahilmgandhi 18:6a4db94011d3 1287 /****************** Bit definition for ADC_SMPR2 register *******************/
sahilmgandhi 18:6a4db94011d3 1288 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1289 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1290 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1291 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1292 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1293 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1294 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1295 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1296 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1297 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1298 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1299 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1300 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1301 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1302 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1303 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1304 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1305 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1306 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1307 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1308 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1309 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1310 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1311 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1312 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1313 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1314 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1315 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1316 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1317 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1318 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1319 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1320 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1321 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1322 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1323 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1324 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1325 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1326 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1327 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1328
sahilmgandhi 18:6a4db94011d3 1329 /****************** Bit definition for ADC_JOFR1 register *******************/
sahilmgandhi 18:6a4db94011d3 1330 #define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
sahilmgandhi 18:6a4db94011d3 1331
sahilmgandhi 18:6a4db94011d3 1332 /****************** Bit definition for ADC_JOFR2 register *******************/
sahilmgandhi 18:6a4db94011d3 1333 #define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
sahilmgandhi 18:6a4db94011d3 1334
sahilmgandhi 18:6a4db94011d3 1335 /****************** Bit definition for ADC_JOFR3 register *******************/
sahilmgandhi 18:6a4db94011d3 1336 #define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
sahilmgandhi 18:6a4db94011d3 1337
sahilmgandhi 18:6a4db94011d3 1338 /****************** Bit definition for ADC_JOFR4 register *******************/
sahilmgandhi 18:6a4db94011d3 1339 #define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
sahilmgandhi 18:6a4db94011d3 1340
sahilmgandhi 18:6a4db94011d3 1341 /******************* Bit definition for ADC_HTR register ********************/
sahilmgandhi 18:6a4db94011d3 1342 #define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
sahilmgandhi 18:6a4db94011d3 1343
sahilmgandhi 18:6a4db94011d3 1344 /******************* Bit definition for ADC_LTR register ********************/
sahilmgandhi 18:6a4db94011d3 1345 #define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
sahilmgandhi 18:6a4db94011d3 1346
sahilmgandhi 18:6a4db94011d3 1347 /******************* Bit definition for ADC_SQR1 register *******************/
sahilmgandhi 18:6a4db94011d3 1348 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1349 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1350 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1351 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1352 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1353 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1354 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1355 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1356 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1357 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1358 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1359 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1360 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1361 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1362 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1363 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1364 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1365 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1366 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1367 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1368 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1369 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1370 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1371 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1372 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
sahilmgandhi 18:6a4db94011d3 1373 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1374 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1375 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1376 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1377
sahilmgandhi 18:6a4db94011d3 1378 /******************* Bit definition for ADC_SQR2 register *******************/
sahilmgandhi 18:6a4db94011d3 1379 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1380 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1381 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1382 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1383 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1384 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1385 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1386 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1387 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1388 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1389 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1390 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1391 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1392 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1393 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1394 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1395 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1396 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1397 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1398 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1399 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1400 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1401 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1402 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1403 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1404 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1405 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1406 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1407 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1408 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1409 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1410 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1411 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1412 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1413 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1414 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1415
sahilmgandhi 18:6a4db94011d3 1416 /******************* Bit definition for ADC_SQR3 register *******************/
sahilmgandhi 18:6a4db94011d3 1417 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1418 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1419 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1420 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1421 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1422 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1423 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1424 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1425 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1426 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1427 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1428 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1429 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1430 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1431 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1432 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1433 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1434 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1435 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1436 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1437 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1438 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1439 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1440 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1441 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1442 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1443 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1444 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1445 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1446 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1447 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1448 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1449 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1450 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1451 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1452 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1453
sahilmgandhi 18:6a4db94011d3 1454 /******************* Bit definition for ADC_JSQR register *******************/
sahilmgandhi 18:6a4db94011d3 1455 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
sahilmgandhi 18:6a4db94011d3 1456 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1457 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1458 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1459 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1460 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1461 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
sahilmgandhi 18:6a4db94011d3 1462 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1463 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1464 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1465 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1466 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1467 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
sahilmgandhi 18:6a4db94011d3 1468 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1469 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1470 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1471 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1472 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1473 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
sahilmgandhi 18:6a4db94011d3 1474 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1475 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1476 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1477 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1478 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1479 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
sahilmgandhi 18:6a4db94011d3 1480 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1481 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1482
sahilmgandhi 18:6a4db94011d3 1483 /******************* Bit definition for ADC_JDR1 register *******************/
sahilmgandhi 18:6a4db94011d3 1484 #define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
sahilmgandhi 18:6a4db94011d3 1485
sahilmgandhi 18:6a4db94011d3 1486 /******************* Bit definition for ADC_JDR2 register *******************/
sahilmgandhi 18:6a4db94011d3 1487 #define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
sahilmgandhi 18:6a4db94011d3 1488
sahilmgandhi 18:6a4db94011d3 1489 /******************* Bit definition for ADC_JDR3 register *******************/
sahilmgandhi 18:6a4db94011d3 1490 #define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
sahilmgandhi 18:6a4db94011d3 1491
sahilmgandhi 18:6a4db94011d3 1492 /******************* Bit definition for ADC_JDR4 register *******************/
sahilmgandhi 18:6a4db94011d3 1493 #define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
sahilmgandhi 18:6a4db94011d3 1494
sahilmgandhi 18:6a4db94011d3 1495 /******************** Bit definition for ADC_DR register ********************/
sahilmgandhi 18:6a4db94011d3 1496 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
sahilmgandhi 18:6a4db94011d3 1497 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
sahilmgandhi 18:6a4db94011d3 1498
sahilmgandhi 18:6a4db94011d3 1499 /******************* Bit definition for ADC_CSR register ********************/
sahilmgandhi 18:6a4db94011d3 1500 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 1501 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
sahilmgandhi 18:6a4db94011d3 1502 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
sahilmgandhi 18:6a4db94011d3 1503 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
sahilmgandhi 18:6a4db94011d3 1504 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
sahilmgandhi 18:6a4db94011d3 1505 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
sahilmgandhi 18:6a4db94011d3 1506 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 1507 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
sahilmgandhi 18:6a4db94011d3 1508 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
sahilmgandhi 18:6a4db94011d3 1509 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
sahilmgandhi 18:6a4db94011d3 1510 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
sahilmgandhi 18:6a4db94011d3 1511 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
sahilmgandhi 18:6a4db94011d3 1512 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 1513 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
sahilmgandhi 18:6a4db94011d3 1514 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
sahilmgandhi 18:6a4db94011d3 1515 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
sahilmgandhi 18:6a4db94011d3 1516 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
sahilmgandhi 18:6a4db94011d3 1517 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
sahilmgandhi 18:6a4db94011d3 1518
sahilmgandhi 18:6a4db94011d3 1519 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 1520 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
sahilmgandhi 18:6a4db94011d3 1521 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
sahilmgandhi 18:6a4db94011d3 1522 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
sahilmgandhi 18:6a4db94011d3 1523
sahilmgandhi 18:6a4db94011d3 1524 /******************* Bit definition for ADC_CCR register ********************/
sahilmgandhi 18:6a4db94011d3 1525 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
sahilmgandhi 18:6a4db94011d3 1526 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1527 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1528 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1529 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1530 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 1531 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
sahilmgandhi 18:6a4db94011d3 1532 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1533 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1534 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1535 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1536 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
sahilmgandhi 18:6a4db94011d3 1537 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
sahilmgandhi 18:6a4db94011d3 1538 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1539 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1540 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
sahilmgandhi 18:6a4db94011d3 1541 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1542 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1543 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
sahilmgandhi 18:6a4db94011d3 1544 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
sahilmgandhi 18:6a4db94011d3 1545
sahilmgandhi 18:6a4db94011d3 1546 /******************* Bit definition for ADC_CDR register ********************/
sahilmgandhi 18:6a4db94011d3 1547 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
sahilmgandhi 18:6a4db94011d3 1548 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
sahilmgandhi 18:6a4db94011d3 1549
sahilmgandhi 18:6a4db94011d3 1550 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1551 /* */
sahilmgandhi 18:6a4db94011d3 1552 /* Controller Area Network */
sahilmgandhi 18:6a4db94011d3 1553 /* */
sahilmgandhi 18:6a4db94011d3 1554 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1555 /*!<CAN control and status registers */
sahilmgandhi 18:6a4db94011d3 1556 /******************* Bit definition for CAN_MCR register ********************/
sahilmgandhi 18:6a4db94011d3 1557 #define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
sahilmgandhi 18:6a4db94011d3 1558 #define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
sahilmgandhi 18:6a4db94011d3 1559 #define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
sahilmgandhi 18:6a4db94011d3 1560 #define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
sahilmgandhi 18:6a4db94011d3 1561 #define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
sahilmgandhi 18:6a4db94011d3 1562 #define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
sahilmgandhi 18:6a4db94011d3 1563 #define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
sahilmgandhi 18:6a4db94011d3 1564 #define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
sahilmgandhi 18:6a4db94011d3 1565 #define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
sahilmgandhi 18:6a4db94011d3 1566 #define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
sahilmgandhi 18:6a4db94011d3 1567 /******************* Bit definition for CAN_MSR register ********************/
sahilmgandhi 18:6a4db94011d3 1568 #define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
sahilmgandhi 18:6a4db94011d3 1569 #define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
sahilmgandhi 18:6a4db94011d3 1570 #define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
sahilmgandhi 18:6a4db94011d3 1571 #define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
sahilmgandhi 18:6a4db94011d3 1572 #define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
sahilmgandhi 18:6a4db94011d3 1573 #define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
sahilmgandhi 18:6a4db94011d3 1574 #define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
sahilmgandhi 18:6a4db94011d3 1575 #define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
sahilmgandhi 18:6a4db94011d3 1576 #define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
sahilmgandhi 18:6a4db94011d3 1577
sahilmgandhi 18:6a4db94011d3 1578 /******************* Bit definition for CAN_TSR register ********************/
sahilmgandhi 18:6a4db94011d3 1579 #define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
sahilmgandhi 18:6a4db94011d3 1580 #define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
sahilmgandhi 18:6a4db94011d3 1581 #define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
sahilmgandhi 18:6a4db94011d3 1582 #define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
sahilmgandhi 18:6a4db94011d3 1583 #define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
sahilmgandhi 18:6a4db94011d3 1584 #define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
sahilmgandhi 18:6a4db94011d3 1585 #define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
sahilmgandhi 18:6a4db94011d3 1586 #define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
sahilmgandhi 18:6a4db94011d3 1587 #define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
sahilmgandhi 18:6a4db94011d3 1588 #define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
sahilmgandhi 18:6a4db94011d3 1589 #define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
sahilmgandhi 18:6a4db94011d3 1590 #define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
sahilmgandhi 18:6a4db94011d3 1591 #define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
sahilmgandhi 18:6a4db94011d3 1592 #define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
sahilmgandhi 18:6a4db94011d3 1593 #define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
sahilmgandhi 18:6a4db94011d3 1594 #define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
sahilmgandhi 18:6a4db94011d3 1595
sahilmgandhi 18:6a4db94011d3 1596 #define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
sahilmgandhi 18:6a4db94011d3 1597 #define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
sahilmgandhi 18:6a4db94011d3 1598 #define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
sahilmgandhi 18:6a4db94011d3 1599 #define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
sahilmgandhi 18:6a4db94011d3 1600
sahilmgandhi 18:6a4db94011d3 1601 #define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
sahilmgandhi 18:6a4db94011d3 1602 #define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
sahilmgandhi 18:6a4db94011d3 1603 #define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
sahilmgandhi 18:6a4db94011d3 1604 #define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
sahilmgandhi 18:6a4db94011d3 1605
sahilmgandhi 18:6a4db94011d3 1606 /******************* Bit definition for CAN_RF0R register *******************/
sahilmgandhi 18:6a4db94011d3 1607 #define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
sahilmgandhi 18:6a4db94011d3 1608 #define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
sahilmgandhi 18:6a4db94011d3 1609 #define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
sahilmgandhi 18:6a4db94011d3 1610 #define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
sahilmgandhi 18:6a4db94011d3 1611
sahilmgandhi 18:6a4db94011d3 1612 /******************* Bit definition for CAN_RF1R register *******************/
sahilmgandhi 18:6a4db94011d3 1613 #define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
sahilmgandhi 18:6a4db94011d3 1614 #define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
sahilmgandhi 18:6a4db94011d3 1615 #define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
sahilmgandhi 18:6a4db94011d3 1616 #define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
sahilmgandhi 18:6a4db94011d3 1617
sahilmgandhi 18:6a4db94011d3 1618 /******************** Bit definition for CAN_IER register *******************/
sahilmgandhi 18:6a4db94011d3 1619 #define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1620 #define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1621 #define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1622 #define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1623 #define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1624 #define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1625 #define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1626 #define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1627 #define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1628 #define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1629 #define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1630 #define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1631 #define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1632 #define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1633 #define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
sahilmgandhi 18:6a4db94011d3 1634 #define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
sahilmgandhi 18:6a4db94011d3 1635 #define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
sahilmgandhi 18:6a4db94011d3 1636 #define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
sahilmgandhi 18:6a4db94011d3 1637 #define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
sahilmgandhi 18:6a4db94011d3 1638
sahilmgandhi 18:6a4db94011d3 1639
sahilmgandhi 18:6a4db94011d3 1640 /******************** Bit definition for CAN_ESR register *******************/
sahilmgandhi 18:6a4db94011d3 1641 #define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
sahilmgandhi 18:6a4db94011d3 1642 #define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
sahilmgandhi 18:6a4db94011d3 1643 #define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
sahilmgandhi 18:6a4db94011d3 1644
sahilmgandhi 18:6a4db94011d3 1645 #define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
sahilmgandhi 18:6a4db94011d3 1646 #define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1647 #define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1648 #define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1649
sahilmgandhi 18:6a4db94011d3 1650 #define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
sahilmgandhi 18:6a4db94011d3 1651 #define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
sahilmgandhi 18:6a4db94011d3 1652
sahilmgandhi 18:6a4db94011d3 1653 /******************* Bit definition for CAN_BTR register ********************/
sahilmgandhi 18:6a4db94011d3 1654 #define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
sahilmgandhi 18:6a4db94011d3 1655 #define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
sahilmgandhi 18:6a4db94011d3 1656 #define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1657 #define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1658 #define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1659 #define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 1660 #define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
sahilmgandhi 18:6a4db94011d3 1661 #define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1662 #define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1663 #define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 1664 #define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
sahilmgandhi 18:6a4db94011d3 1665 #define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 1666 #define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 1667 #define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
sahilmgandhi 18:6a4db94011d3 1668 #define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
sahilmgandhi 18:6a4db94011d3 1669
sahilmgandhi 18:6a4db94011d3 1670
sahilmgandhi 18:6a4db94011d3 1671 /*!<Mailbox registers */
sahilmgandhi 18:6a4db94011d3 1672 /****************** Bit definition for CAN_TI0R register ********************/
sahilmgandhi 18:6a4db94011d3 1673 #define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
sahilmgandhi 18:6a4db94011d3 1674 #define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
sahilmgandhi 18:6a4db94011d3 1675 #define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
sahilmgandhi 18:6a4db94011d3 1676 #define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
sahilmgandhi 18:6a4db94011d3 1677 #define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
sahilmgandhi 18:6a4db94011d3 1678
sahilmgandhi 18:6a4db94011d3 1679 /****************** Bit definition for CAN_TDT0R register *******************/
sahilmgandhi 18:6a4db94011d3 1680 #define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
sahilmgandhi 18:6a4db94011d3 1681 #define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
sahilmgandhi 18:6a4db94011d3 1682 #define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
sahilmgandhi 18:6a4db94011d3 1683
sahilmgandhi 18:6a4db94011d3 1684 /****************** Bit definition for CAN_TDL0R register *******************/
sahilmgandhi 18:6a4db94011d3 1685 #define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
sahilmgandhi 18:6a4db94011d3 1686 #define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
sahilmgandhi 18:6a4db94011d3 1687 #define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
sahilmgandhi 18:6a4db94011d3 1688 #define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
sahilmgandhi 18:6a4db94011d3 1689
sahilmgandhi 18:6a4db94011d3 1690 /****************** Bit definition for CAN_TDH0R register *******************/
sahilmgandhi 18:6a4db94011d3 1691 #define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
sahilmgandhi 18:6a4db94011d3 1692 #define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
sahilmgandhi 18:6a4db94011d3 1693 #define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
sahilmgandhi 18:6a4db94011d3 1694 #define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
sahilmgandhi 18:6a4db94011d3 1695
sahilmgandhi 18:6a4db94011d3 1696 /******************* Bit definition for CAN_TI1R register *******************/
sahilmgandhi 18:6a4db94011d3 1697 #define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
sahilmgandhi 18:6a4db94011d3 1698 #define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
sahilmgandhi 18:6a4db94011d3 1699 #define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
sahilmgandhi 18:6a4db94011d3 1700 #define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
sahilmgandhi 18:6a4db94011d3 1701 #define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
sahilmgandhi 18:6a4db94011d3 1702
sahilmgandhi 18:6a4db94011d3 1703 /******************* Bit definition for CAN_TDT1R register ******************/
sahilmgandhi 18:6a4db94011d3 1704 #define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
sahilmgandhi 18:6a4db94011d3 1705 #define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
sahilmgandhi 18:6a4db94011d3 1706 #define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
sahilmgandhi 18:6a4db94011d3 1707
sahilmgandhi 18:6a4db94011d3 1708 /******************* Bit definition for CAN_TDL1R register ******************/
sahilmgandhi 18:6a4db94011d3 1709 #define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
sahilmgandhi 18:6a4db94011d3 1710 #define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
sahilmgandhi 18:6a4db94011d3 1711 #define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
sahilmgandhi 18:6a4db94011d3 1712 #define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
sahilmgandhi 18:6a4db94011d3 1713
sahilmgandhi 18:6a4db94011d3 1714 /******************* Bit definition for CAN_TDH1R register ******************/
sahilmgandhi 18:6a4db94011d3 1715 #define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
sahilmgandhi 18:6a4db94011d3 1716 #define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
sahilmgandhi 18:6a4db94011d3 1717 #define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
sahilmgandhi 18:6a4db94011d3 1718 #define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
sahilmgandhi 18:6a4db94011d3 1719
sahilmgandhi 18:6a4db94011d3 1720 /******************* Bit definition for CAN_TI2R register *******************/
sahilmgandhi 18:6a4db94011d3 1721 #define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
sahilmgandhi 18:6a4db94011d3 1722 #define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
sahilmgandhi 18:6a4db94011d3 1723 #define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
sahilmgandhi 18:6a4db94011d3 1724 #define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
sahilmgandhi 18:6a4db94011d3 1725 #define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
sahilmgandhi 18:6a4db94011d3 1726
sahilmgandhi 18:6a4db94011d3 1727 /******************* Bit definition for CAN_TDT2R register ******************/
sahilmgandhi 18:6a4db94011d3 1728 #define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
sahilmgandhi 18:6a4db94011d3 1729 #define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
sahilmgandhi 18:6a4db94011d3 1730 #define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
sahilmgandhi 18:6a4db94011d3 1731
sahilmgandhi 18:6a4db94011d3 1732 /******************* Bit definition for CAN_TDL2R register ******************/
sahilmgandhi 18:6a4db94011d3 1733 #define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
sahilmgandhi 18:6a4db94011d3 1734 #define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
sahilmgandhi 18:6a4db94011d3 1735 #define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
sahilmgandhi 18:6a4db94011d3 1736 #define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
sahilmgandhi 18:6a4db94011d3 1737
sahilmgandhi 18:6a4db94011d3 1738 /******************* Bit definition for CAN_TDH2R register ******************/
sahilmgandhi 18:6a4db94011d3 1739 #define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
sahilmgandhi 18:6a4db94011d3 1740 #define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
sahilmgandhi 18:6a4db94011d3 1741 #define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
sahilmgandhi 18:6a4db94011d3 1742 #define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
sahilmgandhi 18:6a4db94011d3 1743
sahilmgandhi 18:6a4db94011d3 1744 /******************* Bit definition for CAN_RI0R register *******************/
sahilmgandhi 18:6a4db94011d3 1745 #define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
sahilmgandhi 18:6a4db94011d3 1746 #define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
sahilmgandhi 18:6a4db94011d3 1747 #define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
sahilmgandhi 18:6a4db94011d3 1748 #define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
sahilmgandhi 18:6a4db94011d3 1749
sahilmgandhi 18:6a4db94011d3 1750 /******************* Bit definition for CAN_RDT0R register ******************/
sahilmgandhi 18:6a4db94011d3 1751 #define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
sahilmgandhi 18:6a4db94011d3 1752 #define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
sahilmgandhi 18:6a4db94011d3 1753 #define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
sahilmgandhi 18:6a4db94011d3 1754
sahilmgandhi 18:6a4db94011d3 1755 /******************* Bit definition for CAN_RDL0R register ******************/
sahilmgandhi 18:6a4db94011d3 1756 #define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
sahilmgandhi 18:6a4db94011d3 1757 #define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
sahilmgandhi 18:6a4db94011d3 1758 #define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
sahilmgandhi 18:6a4db94011d3 1759 #define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
sahilmgandhi 18:6a4db94011d3 1760
sahilmgandhi 18:6a4db94011d3 1761 /******************* Bit definition for CAN_RDH0R register ******************/
sahilmgandhi 18:6a4db94011d3 1762 #define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
sahilmgandhi 18:6a4db94011d3 1763 #define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
sahilmgandhi 18:6a4db94011d3 1764 #define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
sahilmgandhi 18:6a4db94011d3 1765 #define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
sahilmgandhi 18:6a4db94011d3 1766
sahilmgandhi 18:6a4db94011d3 1767 /******************* Bit definition for CAN_RI1R register *******************/
sahilmgandhi 18:6a4db94011d3 1768 #define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
sahilmgandhi 18:6a4db94011d3 1769 #define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
sahilmgandhi 18:6a4db94011d3 1770 #define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
sahilmgandhi 18:6a4db94011d3 1771 #define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
sahilmgandhi 18:6a4db94011d3 1772
sahilmgandhi 18:6a4db94011d3 1773 /******************* Bit definition for CAN_RDT1R register ******************/
sahilmgandhi 18:6a4db94011d3 1774 #define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
sahilmgandhi 18:6a4db94011d3 1775 #define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
sahilmgandhi 18:6a4db94011d3 1776 #define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
sahilmgandhi 18:6a4db94011d3 1777
sahilmgandhi 18:6a4db94011d3 1778 /******************* Bit definition for CAN_RDL1R register ******************/
sahilmgandhi 18:6a4db94011d3 1779 #define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
sahilmgandhi 18:6a4db94011d3 1780 #define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
sahilmgandhi 18:6a4db94011d3 1781 #define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
sahilmgandhi 18:6a4db94011d3 1782 #define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
sahilmgandhi 18:6a4db94011d3 1783
sahilmgandhi 18:6a4db94011d3 1784 /******************* Bit definition for CAN_RDH1R register ******************/
sahilmgandhi 18:6a4db94011d3 1785 #define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
sahilmgandhi 18:6a4db94011d3 1786 #define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
sahilmgandhi 18:6a4db94011d3 1787 #define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
sahilmgandhi 18:6a4db94011d3 1788 #define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
sahilmgandhi 18:6a4db94011d3 1789
sahilmgandhi 18:6a4db94011d3 1790 /*!<CAN filter registers */
sahilmgandhi 18:6a4db94011d3 1791 /******************* Bit definition for CAN_FMR register ********************/
sahilmgandhi 18:6a4db94011d3 1792 #define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
sahilmgandhi 18:6a4db94011d3 1793 #define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
sahilmgandhi 18:6a4db94011d3 1794
sahilmgandhi 18:6a4db94011d3 1795 /******************* Bit definition for CAN_FM1R register *******************/
sahilmgandhi 18:6a4db94011d3 1796 #define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
sahilmgandhi 18:6a4db94011d3 1797 #define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
sahilmgandhi 18:6a4db94011d3 1798 #define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
sahilmgandhi 18:6a4db94011d3 1799 #define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
sahilmgandhi 18:6a4db94011d3 1800 #define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
sahilmgandhi 18:6a4db94011d3 1801 #define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
sahilmgandhi 18:6a4db94011d3 1802 #define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
sahilmgandhi 18:6a4db94011d3 1803 #define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
sahilmgandhi 18:6a4db94011d3 1804 #define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
sahilmgandhi 18:6a4db94011d3 1805 #define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
sahilmgandhi 18:6a4db94011d3 1806 #define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
sahilmgandhi 18:6a4db94011d3 1807 #define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
sahilmgandhi 18:6a4db94011d3 1808 #define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
sahilmgandhi 18:6a4db94011d3 1809 #define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
sahilmgandhi 18:6a4db94011d3 1810 #define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
sahilmgandhi 18:6a4db94011d3 1811 #define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
sahilmgandhi 18:6a4db94011d3 1812 #define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
sahilmgandhi 18:6a4db94011d3 1813 #define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
sahilmgandhi 18:6a4db94011d3 1814 #define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
sahilmgandhi 18:6a4db94011d3 1815 #define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
sahilmgandhi 18:6a4db94011d3 1816 #define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
sahilmgandhi 18:6a4db94011d3 1817 #define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
sahilmgandhi 18:6a4db94011d3 1818 #define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
sahilmgandhi 18:6a4db94011d3 1819 #define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
sahilmgandhi 18:6a4db94011d3 1820 #define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
sahilmgandhi 18:6a4db94011d3 1821 #define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
sahilmgandhi 18:6a4db94011d3 1822 #define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
sahilmgandhi 18:6a4db94011d3 1823 #define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
sahilmgandhi 18:6a4db94011d3 1824 #define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
sahilmgandhi 18:6a4db94011d3 1825
sahilmgandhi 18:6a4db94011d3 1826 /******************* Bit definition for CAN_FS1R register *******************/
sahilmgandhi 18:6a4db94011d3 1827 #define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
sahilmgandhi 18:6a4db94011d3 1828 #define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
sahilmgandhi 18:6a4db94011d3 1829 #define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
sahilmgandhi 18:6a4db94011d3 1830 #define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
sahilmgandhi 18:6a4db94011d3 1831 #define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
sahilmgandhi 18:6a4db94011d3 1832 #define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
sahilmgandhi 18:6a4db94011d3 1833 #define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
sahilmgandhi 18:6a4db94011d3 1834 #define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
sahilmgandhi 18:6a4db94011d3 1835 #define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
sahilmgandhi 18:6a4db94011d3 1836 #define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
sahilmgandhi 18:6a4db94011d3 1837 #define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
sahilmgandhi 18:6a4db94011d3 1838 #define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
sahilmgandhi 18:6a4db94011d3 1839 #define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
sahilmgandhi 18:6a4db94011d3 1840 #define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
sahilmgandhi 18:6a4db94011d3 1841 #define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
sahilmgandhi 18:6a4db94011d3 1842 #define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
sahilmgandhi 18:6a4db94011d3 1843 #define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
sahilmgandhi 18:6a4db94011d3 1844 #define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
sahilmgandhi 18:6a4db94011d3 1845 #define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
sahilmgandhi 18:6a4db94011d3 1846 #define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
sahilmgandhi 18:6a4db94011d3 1847 #define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
sahilmgandhi 18:6a4db94011d3 1848 #define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
sahilmgandhi 18:6a4db94011d3 1849 #define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
sahilmgandhi 18:6a4db94011d3 1850 #define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
sahilmgandhi 18:6a4db94011d3 1851 #define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
sahilmgandhi 18:6a4db94011d3 1852 #define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
sahilmgandhi 18:6a4db94011d3 1853 #define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
sahilmgandhi 18:6a4db94011d3 1854 #define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
sahilmgandhi 18:6a4db94011d3 1855 #define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
sahilmgandhi 18:6a4db94011d3 1856
sahilmgandhi 18:6a4db94011d3 1857 /****************** Bit definition for CAN_FFA1R register *******************/
sahilmgandhi 18:6a4db94011d3 1858 #define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
sahilmgandhi 18:6a4db94011d3 1859 #define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
sahilmgandhi 18:6a4db94011d3 1860 #define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
sahilmgandhi 18:6a4db94011d3 1861 #define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
sahilmgandhi 18:6a4db94011d3 1862 #define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
sahilmgandhi 18:6a4db94011d3 1863 #define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
sahilmgandhi 18:6a4db94011d3 1864 #define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
sahilmgandhi 18:6a4db94011d3 1865 #define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
sahilmgandhi 18:6a4db94011d3 1866 #define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
sahilmgandhi 18:6a4db94011d3 1867 #define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
sahilmgandhi 18:6a4db94011d3 1868 #define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
sahilmgandhi 18:6a4db94011d3 1869 #define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
sahilmgandhi 18:6a4db94011d3 1870 #define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
sahilmgandhi 18:6a4db94011d3 1871 #define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
sahilmgandhi 18:6a4db94011d3 1872 #define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
sahilmgandhi 18:6a4db94011d3 1873 #define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
sahilmgandhi 18:6a4db94011d3 1874 #define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
sahilmgandhi 18:6a4db94011d3 1875 #define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
sahilmgandhi 18:6a4db94011d3 1876 #define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
sahilmgandhi 18:6a4db94011d3 1877 #define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
sahilmgandhi 18:6a4db94011d3 1878 #define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
sahilmgandhi 18:6a4db94011d3 1879 #define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
sahilmgandhi 18:6a4db94011d3 1880 #define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
sahilmgandhi 18:6a4db94011d3 1881 #define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
sahilmgandhi 18:6a4db94011d3 1882 #define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
sahilmgandhi 18:6a4db94011d3 1883 #define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
sahilmgandhi 18:6a4db94011d3 1884 #define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
sahilmgandhi 18:6a4db94011d3 1885 #define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
sahilmgandhi 18:6a4db94011d3 1886 #define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
sahilmgandhi 18:6a4db94011d3 1887
sahilmgandhi 18:6a4db94011d3 1888 /******************* Bit definition for CAN_FA1R register *******************/
sahilmgandhi 18:6a4db94011d3 1889 #define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
sahilmgandhi 18:6a4db94011d3 1890 #define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
sahilmgandhi 18:6a4db94011d3 1891 #define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
sahilmgandhi 18:6a4db94011d3 1892 #define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
sahilmgandhi 18:6a4db94011d3 1893 #define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
sahilmgandhi 18:6a4db94011d3 1894 #define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
sahilmgandhi 18:6a4db94011d3 1895 #define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
sahilmgandhi 18:6a4db94011d3 1896 #define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
sahilmgandhi 18:6a4db94011d3 1897 #define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
sahilmgandhi 18:6a4db94011d3 1898 #define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
sahilmgandhi 18:6a4db94011d3 1899 #define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
sahilmgandhi 18:6a4db94011d3 1900 #define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
sahilmgandhi 18:6a4db94011d3 1901 #define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
sahilmgandhi 18:6a4db94011d3 1902 #define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
sahilmgandhi 18:6a4db94011d3 1903 #define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
sahilmgandhi 18:6a4db94011d3 1904 #define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
sahilmgandhi 18:6a4db94011d3 1905 #define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
sahilmgandhi 18:6a4db94011d3 1906 #define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
sahilmgandhi 18:6a4db94011d3 1907 #define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
sahilmgandhi 18:6a4db94011d3 1908 #define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
sahilmgandhi 18:6a4db94011d3 1909 #define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
sahilmgandhi 18:6a4db94011d3 1910 #define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
sahilmgandhi 18:6a4db94011d3 1911 #define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
sahilmgandhi 18:6a4db94011d3 1912 #define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
sahilmgandhi 18:6a4db94011d3 1913 #define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
sahilmgandhi 18:6a4db94011d3 1914 #define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
sahilmgandhi 18:6a4db94011d3 1915 #define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
sahilmgandhi 18:6a4db94011d3 1916 #define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
sahilmgandhi 18:6a4db94011d3 1917 #define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
sahilmgandhi 18:6a4db94011d3 1918
sahilmgandhi 18:6a4db94011d3 1919 /******************* Bit definition for CAN_F0R1 register *******************/
sahilmgandhi 18:6a4db94011d3 1920 #define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 1921 #define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 1922 #define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 1923 #define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 1924 #define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 1925 #define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 1926 #define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 1927 #define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 1928 #define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 1929 #define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 1930 #define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 1931 #define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 1932 #define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 1933 #define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 1934 #define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 1935 #define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 1936 #define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 1937 #define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 1938 #define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 1939 #define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 1940 #define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 1941 #define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 1942 #define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 1943 #define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 1944 #define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 1945 #define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 1946 #define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 1947 #define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 1948 #define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 1949 #define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 1950 #define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 1951 #define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 1952
sahilmgandhi 18:6a4db94011d3 1953 /******************* Bit definition for CAN_F1R1 register *******************/
sahilmgandhi 18:6a4db94011d3 1954 #define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 1955 #define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 1956 #define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 1957 #define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 1958 #define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 1959 #define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 1960 #define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 1961 #define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 1962 #define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 1963 #define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 1964 #define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 1965 #define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 1966 #define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 1967 #define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 1968 #define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 1969 #define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 1970 #define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 1971 #define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 1972 #define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 1973 #define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 1974 #define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 1975 #define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 1976 #define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 1977 #define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 1978 #define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 1979 #define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 1980 #define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 1981 #define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 1982 #define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 1983 #define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 1984 #define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 1985 #define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 1986
sahilmgandhi 18:6a4db94011d3 1987 /******************* Bit definition for CAN_F2R1 register *******************/
sahilmgandhi 18:6a4db94011d3 1988 #define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 1989 #define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 1990 #define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 1991 #define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 1992 #define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 1993 #define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 1994 #define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 1995 #define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 1996 #define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 1997 #define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 1998 #define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 1999 #define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2000 #define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2001 #define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2002 #define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2003 #define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2004 #define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2005 #define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2006 #define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2007 #define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2008 #define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2009 #define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2010 #define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2011 #define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2012 #define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2013 #define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2014 #define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2015 #define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2016 #define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2017 #define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2018 #define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2019 #define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2020
sahilmgandhi 18:6a4db94011d3 2021 /******************* Bit definition for CAN_F3R1 register *******************/
sahilmgandhi 18:6a4db94011d3 2022 #define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2023 #define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2024 #define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2025 #define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2026 #define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2027 #define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2028 #define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2029 #define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2030 #define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2031 #define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2032 #define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2033 #define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2034 #define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2035 #define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2036 #define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2037 #define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2038 #define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2039 #define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2040 #define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2041 #define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2042 #define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2043 #define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2044 #define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2045 #define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2046 #define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2047 #define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2048 #define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2049 #define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2050 #define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2051 #define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2052 #define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2053 #define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2054
sahilmgandhi 18:6a4db94011d3 2055 /******************* Bit definition for CAN_F4R1 register *******************/
sahilmgandhi 18:6a4db94011d3 2056 #define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2057 #define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2058 #define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2059 #define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2060 #define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2061 #define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2062 #define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2063 #define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2064 #define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2065 #define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2066 #define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2067 #define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2068 #define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2069 #define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2070 #define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2071 #define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2072 #define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2073 #define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2074 #define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2075 #define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2076 #define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2077 #define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2078 #define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2079 #define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2080 #define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2081 #define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2082 #define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2083 #define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2084 #define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2085 #define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2086 #define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2087 #define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2088
sahilmgandhi 18:6a4db94011d3 2089 /******************* Bit definition for CAN_F5R1 register *******************/
sahilmgandhi 18:6a4db94011d3 2090 #define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2091 #define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2092 #define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2093 #define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2094 #define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2095 #define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2096 #define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2097 #define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2098 #define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2099 #define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2100 #define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2101 #define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2102 #define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2103 #define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2104 #define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2105 #define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2106 #define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2107 #define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2108 #define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2109 #define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2110 #define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2111 #define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2112 #define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2113 #define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2114 #define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2115 #define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2116 #define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2117 #define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2118 #define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2119 #define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2120 #define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2121 #define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2122
sahilmgandhi 18:6a4db94011d3 2123 /******************* Bit definition for CAN_F6R1 register *******************/
sahilmgandhi 18:6a4db94011d3 2124 #define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2125 #define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2126 #define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2127 #define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2128 #define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2129 #define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2130 #define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2131 #define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2132 #define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2133 #define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2134 #define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2135 #define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2136 #define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2137 #define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2138 #define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2139 #define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2140 #define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2141 #define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2142 #define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2143 #define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2144 #define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2145 #define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2146 #define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2147 #define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2148 #define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2149 #define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2150 #define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2151 #define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2152 #define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2153 #define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2154 #define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2155 #define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2156
sahilmgandhi 18:6a4db94011d3 2157 /******************* Bit definition for CAN_F7R1 register *******************/
sahilmgandhi 18:6a4db94011d3 2158 #define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2159 #define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2160 #define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2161 #define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2162 #define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2163 #define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2164 #define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2165 #define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2166 #define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2167 #define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2168 #define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2169 #define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2170 #define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2171 #define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2172 #define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2173 #define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2174 #define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2175 #define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2176 #define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2177 #define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2178 #define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2179 #define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2180 #define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2181 #define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2182 #define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2183 #define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2184 #define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2185 #define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2186 #define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2187 #define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2188 #define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2189 #define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2190
sahilmgandhi 18:6a4db94011d3 2191 /******************* Bit definition for CAN_F8R1 register *******************/
sahilmgandhi 18:6a4db94011d3 2192 #define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2193 #define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2194 #define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2195 #define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2196 #define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2197 #define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2198 #define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2199 #define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2200 #define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2201 #define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2202 #define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2203 #define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2204 #define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2205 #define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2206 #define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2207 #define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2208 #define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2209 #define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2210 #define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2211 #define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2212 #define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2213 #define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2214 #define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2215 #define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2216 #define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2217 #define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2218 #define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2219 #define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2220 #define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2221 #define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2222 #define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2223 #define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2224
sahilmgandhi 18:6a4db94011d3 2225 /******************* Bit definition for CAN_F9R1 register *******************/
sahilmgandhi 18:6a4db94011d3 2226 #define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2227 #define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2228 #define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2229 #define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2230 #define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2231 #define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2232 #define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2233 #define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2234 #define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2235 #define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2236 #define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2237 #define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2238 #define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2239 #define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2240 #define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2241 #define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2242 #define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2243 #define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2244 #define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2245 #define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2246 #define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2247 #define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2248 #define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2249 #define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2250 #define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2251 #define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2252 #define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2253 #define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2254 #define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2255 #define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2256 #define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2257 #define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2258
sahilmgandhi 18:6a4db94011d3 2259 /******************* Bit definition for CAN_F10R1 register ******************/
sahilmgandhi 18:6a4db94011d3 2260 #define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2261 #define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2262 #define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2263 #define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2264 #define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2265 #define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2266 #define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2267 #define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2268 #define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2269 #define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2270 #define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2271 #define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2272 #define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2273 #define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2274 #define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2275 #define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2276 #define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2277 #define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2278 #define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2279 #define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2280 #define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2281 #define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2282 #define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2283 #define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2284 #define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2285 #define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2286 #define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2287 #define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2288 #define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2289 #define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2290 #define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2291 #define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2292
sahilmgandhi 18:6a4db94011d3 2293 /******************* Bit definition for CAN_F11R1 register ******************/
sahilmgandhi 18:6a4db94011d3 2294 #define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2295 #define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2296 #define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2297 #define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2298 #define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2299 #define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2300 #define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2301 #define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2302 #define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2303 #define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2304 #define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2305 #define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2306 #define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2307 #define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2308 #define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2309 #define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2310 #define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2311 #define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2312 #define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2313 #define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2314 #define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2315 #define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2316 #define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2317 #define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2318 #define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2319 #define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2320 #define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2321 #define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2322 #define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2323 #define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2324 #define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2325 #define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2326
sahilmgandhi 18:6a4db94011d3 2327 /******************* Bit definition for CAN_F12R1 register ******************/
sahilmgandhi 18:6a4db94011d3 2328 #define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2329 #define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2330 #define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2331 #define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2332 #define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2333 #define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2334 #define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2335 #define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2336 #define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2337 #define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2338 #define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2339 #define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2340 #define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2341 #define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2342 #define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2343 #define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2344 #define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2345 #define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2346 #define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2347 #define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2348 #define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2349 #define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2350 #define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2351 #define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2352 #define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2353 #define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2354 #define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2355 #define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2356 #define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2357 #define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2358 #define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2359 #define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2360
sahilmgandhi 18:6a4db94011d3 2361 /******************* Bit definition for CAN_F13R1 register ******************/
sahilmgandhi 18:6a4db94011d3 2362 #define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2363 #define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2364 #define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2365 #define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2366 #define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2367 #define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2368 #define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2369 #define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2370 #define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2371 #define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2372 #define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2373 #define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2374 #define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2375 #define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2376 #define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2377 #define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2378 #define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2379 #define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2380 #define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2381 #define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2382 #define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2383 #define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2384 #define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2385 #define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2386 #define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2387 #define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2388 #define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2389 #define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2390 #define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2391 #define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2392 #define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2393 #define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2394
sahilmgandhi 18:6a4db94011d3 2395 /******************* Bit definition for CAN_F0R2 register *******************/
sahilmgandhi 18:6a4db94011d3 2396 #define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2397 #define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2398 #define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2399 #define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2400 #define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2401 #define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2402 #define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2403 #define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2404 #define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2405 #define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2406 #define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2407 #define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2408 #define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2409 #define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2410 #define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2411 #define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2412 #define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2413 #define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2414 #define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2415 #define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2416 #define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2417 #define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2418 #define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2419 #define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2420 #define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2421 #define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2422 #define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2423 #define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2424 #define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2425 #define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2426 #define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2427 #define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2428
sahilmgandhi 18:6a4db94011d3 2429 /******************* Bit definition for CAN_F1R2 register *******************/
sahilmgandhi 18:6a4db94011d3 2430 #define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2431 #define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2432 #define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2433 #define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2434 #define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2435 #define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2436 #define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2437 #define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2438 #define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2439 #define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2440 #define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2441 #define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2442 #define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2443 #define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2444 #define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2445 #define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2446 #define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2447 #define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2448 #define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2449 #define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2450 #define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2451 #define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2452 #define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2453 #define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2454 #define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2455 #define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2456 #define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2457 #define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2458 #define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2459 #define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2460 #define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2461 #define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2462
sahilmgandhi 18:6a4db94011d3 2463 /******************* Bit definition for CAN_F2R2 register *******************/
sahilmgandhi 18:6a4db94011d3 2464 #define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2465 #define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2466 #define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2467 #define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2468 #define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2469 #define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2470 #define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2471 #define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2472 #define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2473 #define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2474 #define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2475 #define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2476 #define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2477 #define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2478 #define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2479 #define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2480 #define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2481 #define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2482 #define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2483 #define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2484 #define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2485 #define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2486 #define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2487 #define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2488 #define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2489 #define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2490 #define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2491 #define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2492 #define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2493 #define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2494 #define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2495 #define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2496
sahilmgandhi 18:6a4db94011d3 2497 /******************* Bit definition for CAN_F3R2 register *******************/
sahilmgandhi 18:6a4db94011d3 2498 #define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2499 #define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2500 #define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2501 #define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2502 #define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2503 #define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2504 #define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2505 #define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2506 #define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2507 #define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2508 #define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2509 #define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2510 #define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2511 #define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2512 #define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2513 #define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2514 #define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2515 #define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2516 #define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2517 #define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2518 #define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2519 #define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2520 #define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2521 #define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2522 #define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2523 #define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2524 #define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2525 #define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2526 #define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2527 #define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2528 #define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2529 #define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2530
sahilmgandhi 18:6a4db94011d3 2531 /******************* Bit definition for CAN_F4R2 register *******************/
sahilmgandhi 18:6a4db94011d3 2532 #define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2533 #define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2534 #define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2535 #define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2536 #define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2537 #define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2538 #define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2539 #define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2540 #define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2541 #define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2542 #define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2543 #define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2544 #define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2545 #define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2546 #define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2547 #define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2548 #define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2549 #define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2550 #define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2551 #define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2552 #define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2553 #define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2554 #define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2555 #define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2556 #define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2557 #define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2558 #define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2559 #define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2560 #define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2561 #define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2562 #define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2563 #define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2564
sahilmgandhi 18:6a4db94011d3 2565 /******************* Bit definition for CAN_F5R2 register *******************/
sahilmgandhi 18:6a4db94011d3 2566 #define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2567 #define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2568 #define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2569 #define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2570 #define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2571 #define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2572 #define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2573 #define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2574 #define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2575 #define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2576 #define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2577 #define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2578 #define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2579 #define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2580 #define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2581 #define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2582 #define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2583 #define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2584 #define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2585 #define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2586 #define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2587 #define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2588 #define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2589 #define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2590 #define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2591 #define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2592 #define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2593 #define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2594 #define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2595 #define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2596 #define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2597 #define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2598
sahilmgandhi 18:6a4db94011d3 2599 /******************* Bit definition for CAN_F6R2 register *******************/
sahilmgandhi 18:6a4db94011d3 2600 #define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2601 #define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2602 #define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2603 #define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2604 #define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2605 #define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2606 #define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2607 #define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2608 #define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2609 #define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2610 #define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2611 #define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2612 #define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2613 #define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2614 #define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2615 #define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2616 #define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2617 #define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2618 #define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2619 #define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2620 #define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2621 #define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2622 #define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2623 #define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2624 #define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2625 #define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2626 #define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2627 #define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2628 #define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2629 #define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2630 #define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2631 #define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2632
sahilmgandhi 18:6a4db94011d3 2633 /******************* Bit definition for CAN_F7R2 register *******************/
sahilmgandhi 18:6a4db94011d3 2634 #define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2635 #define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2636 #define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2637 #define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2638 #define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2639 #define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2640 #define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2641 #define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2642 #define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2643 #define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2644 #define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2645 #define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2646 #define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2647 #define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2648 #define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2649 #define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2650 #define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2651 #define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2652 #define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2653 #define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2654 #define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2655 #define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2656 #define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2657 #define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2658 #define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2659 #define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2660 #define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2661 #define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2662 #define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2663 #define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2664 #define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2665 #define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2666
sahilmgandhi 18:6a4db94011d3 2667 /******************* Bit definition for CAN_F8R2 register *******************/
sahilmgandhi 18:6a4db94011d3 2668 #define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2669 #define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2670 #define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2671 #define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2672 #define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2673 #define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2674 #define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2675 #define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2676 #define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2677 #define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2678 #define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2679 #define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2680 #define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2681 #define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2682 #define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2683 #define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2684 #define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2685 #define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2686 #define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2687 #define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2688 #define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2689 #define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2690 #define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2691 #define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2692 #define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2693 #define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2694 #define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2695 #define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2696 #define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2697 #define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2698 #define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2699 #define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2700
sahilmgandhi 18:6a4db94011d3 2701 /******************* Bit definition for CAN_F9R2 register *******************/
sahilmgandhi 18:6a4db94011d3 2702 #define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2703 #define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2704 #define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2705 #define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2706 #define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2707 #define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2708 #define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2709 #define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2710 #define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2711 #define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2712 #define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2713 #define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2714 #define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2715 #define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2716 #define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2717 #define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2718 #define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2719 #define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2720 #define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2721 #define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2722 #define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2723 #define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2724 #define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2725 #define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2726 #define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2727 #define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2728 #define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2729 #define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2730 #define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2731 #define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2732 #define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2733 #define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2734
sahilmgandhi 18:6a4db94011d3 2735 /******************* Bit definition for CAN_F10R2 register ******************/
sahilmgandhi 18:6a4db94011d3 2736 #define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2737 #define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2738 #define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2739 #define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2740 #define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2741 #define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2742 #define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2743 #define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2744 #define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2745 #define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2746 #define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2747 #define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2748 #define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2749 #define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2750 #define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2751 #define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2752 #define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2753 #define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2754 #define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2755 #define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2756 #define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2757 #define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2758 #define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2759 #define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2760 #define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2761 #define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2762 #define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2763 #define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2764 #define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2765 #define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2766 #define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2767 #define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2768
sahilmgandhi 18:6a4db94011d3 2769 /******************* Bit definition for CAN_F11R2 register ******************/
sahilmgandhi 18:6a4db94011d3 2770 #define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2771 #define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2772 #define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2773 #define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2774 #define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2775 #define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2776 #define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2777 #define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2778 #define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2779 #define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2780 #define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2781 #define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2782 #define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2783 #define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2784 #define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2785 #define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2786 #define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2787 #define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2788 #define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2789 #define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2790 #define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2791 #define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2792 #define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2793 #define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2794 #define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2795 #define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2796 #define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2797 #define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2798 #define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2799 #define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2800 #define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2801 #define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2802
sahilmgandhi 18:6a4db94011d3 2803 /******************* Bit definition for CAN_F12R2 register ******************/
sahilmgandhi 18:6a4db94011d3 2804 #define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2805 #define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2806 #define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2807 #define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2808 #define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2809 #define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2810 #define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2811 #define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2812 #define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2813 #define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2814 #define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2815 #define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2816 #define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2817 #define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2818 #define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2819 #define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2820 #define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2821 #define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2822 #define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2823 #define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2824 #define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2825 #define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2826 #define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2827 #define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2828 #define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2829 #define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2830 #define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2831 #define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2832 #define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2833 #define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2834 #define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2835 #define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2836
sahilmgandhi 18:6a4db94011d3 2837 /******************* Bit definition for CAN_F13R2 register ******************/
sahilmgandhi 18:6a4db94011d3 2838 #define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2839 #define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2840 #define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2841 #define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2842 #define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2843 #define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2844 #define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2845 #define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2846 #define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2847 #define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2848 #define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2849 #define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2850 #define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2851 #define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2852 #define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2853 #define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2854 #define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2855 #define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2856 #define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2857 #define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2858 #define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2859 #define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2860 #define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2861 #define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2862 #define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2863 #define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2864 #define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2865 #define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2866 #define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2867 #define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2868 #define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2869 #define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2870
sahilmgandhi 18:6a4db94011d3 2871 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2872 /* */
sahilmgandhi 18:6a4db94011d3 2873 /* CRC calculation unit */
sahilmgandhi 18:6a4db94011d3 2874 /* */
sahilmgandhi 18:6a4db94011d3 2875 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2876 /******************* Bit definition for CRC_DR register *********************/
sahilmgandhi 18:6a4db94011d3 2877 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
sahilmgandhi 18:6a4db94011d3 2878
sahilmgandhi 18:6a4db94011d3 2879
sahilmgandhi 18:6a4db94011d3 2880 /******************* Bit definition for CRC_IDR register ********************/
sahilmgandhi 18:6a4db94011d3 2881 #define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
sahilmgandhi 18:6a4db94011d3 2882
sahilmgandhi 18:6a4db94011d3 2883
sahilmgandhi 18:6a4db94011d3 2884 /******************** Bit definition for CRC_CR register ********************/
sahilmgandhi 18:6a4db94011d3 2885 #define CRC_CR_RESET 0x01U /*!< RESET bit */
sahilmgandhi 18:6a4db94011d3 2886
sahilmgandhi 18:6a4db94011d3 2887
sahilmgandhi 18:6a4db94011d3 2888 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2889 /* */
sahilmgandhi 18:6a4db94011d3 2890 /* Digital to Analog Converter */
sahilmgandhi 18:6a4db94011d3 2891 /* */
sahilmgandhi 18:6a4db94011d3 2892 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2893 /******************** Bit definition for DAC_CR register ********************/
sahilmgandhi 18:6a4db94011d3 2894 #define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
sahilmgandhi 18:6a4db94011d3 2895 #define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
sahilmgandhi 18:6a4db94011d3 2896 #define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
sahilmgandhi 18:6a4db94011d3 2897
sahilmgandhi 18:6a4db94011d3 2898 #define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
sahilmgandhi 18:6a4db94011d3 2899 #define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2900 #define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2901 #define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 2902
sahilmgandhi 18:6a4db94011d3 2903 #define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
sahilmgandhi 18:6a4db94011d3 2904 #define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2905 #define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2906
sahilmgandhi 18:6a4db94011d3 2907 #define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
sahilmgandhi 18:6a4db94011d3 2908 #define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2909 #define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2910 #define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 2911 #define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 2912
sahilmgandhi 18:6a4db94011d3 2913 #define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
sahilmgandhi 18:6a4db94011d3 2914 #define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
sahilmgandhi 18:6a4db94011d3 2915 #define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
sahilmgandhi 18:6a4db94011d3 2916 #define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
sahilmgandhi 18:6a4db94011d3 2917 #define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
sahilmgandhi 18:6a4db94011d3 2918
sahilmgandhi 18:6a4db94011d3 2919 #define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
sahilmgandhi 18:6a4db94011d3 2920 #define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2921 #define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2922 #define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 2923
sahilmgandhi 18:6a4db94011d3 2924 #define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
sahilmgandhi 18:6a4db94011d3 2925 #define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2926 #define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2927
sahilmgandhi 18:6a4db94011d3 2928 #define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
sahilmgandhi 18:6a4db94011d3 2929 #define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 2930 #define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 2931 #define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 2932 #define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 2933
sahilmgandhi 18:6a4db94011d3 2934 #define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
sahilmgandhi 18:6a4db94011d3 2935 #define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
sahilmgandhi 18:6a4db94011d3 2936
sahilmgandhi 18:6a4db94011d3 2937 /***************** Bit definition for DAC_SWTRIGR register ******************/
sahilmgandhi 18:6a4db94011d3 2938 #define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
sahilmgandhi 18:6a4db94011d3 2939 #define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
sahilmgandhi 18:6a4db94011d3 2940
sahilmgandhi 18:6a4db94011d3 2941 /***************** Bit definition for DAC_DHR12R1 register ******************/
sahilmgandhi 18:6a4db94011d3 2942 #define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 2943
sahilmgandhi 18:6a4db94011d3 2944 /***************** Bit definition for DAC_DHR12L1 register ******************/
sahilmgandhi 18:6a4db94011d3 2945 #define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
sahilmgandhi 18:6a4db94011d3 2946
sahilmgandhi 18:6a4db94011d3 2947 /****************** Bit definition for DAC_DHR8R1 register ******************/
sahilmgandhi 18:6a4db94011d3 2948 #define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 2949
sahilmgandhi 18:6a4db94011d3 2950 /***************** Bit definition for DAC_DHR12R2 register ******************/
sahilmgandhi 18:6a4db94011d3 2951 #define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 2952
sahilmgandhi 18:6a4db94011d3 2953 /***************** Bit definition for DAC_DHR12L2 register ******************/
sahilmgandhi 18:6a4db94011d3 2954 #define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
sahilmgandhi 18:6a4db94011d3 2955
sahilmgandhi 18:6a4db94011d3 2956 /****************** Bit definition for DAC_DHR8R2 register ******************/
sahilmgandhi 18:6a4db94011d3 2957 #define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 2958
sahilmgandhi 18:6a4db94011d3 2959 /***************** Bit definition for DAC_DHR12RD register ******************/
sahilmgandhi 18:6a4db94011d3 2960 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 2961 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 2962
sahilmgandhi 18:6a4db94011d3 2963 /***************** Bit definition for DAC_DHR12LD register ******************/
sahilmgandhi 18:6a4db94011d3 2964 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
sahilmgandhi 18:6a4db94011d3 2965 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
sahilmgandhi 18:6a4db94011d3 2966
sahilmgandhi 18:6a4db94011d3 2967 /****************** Bit definition for DAC_DHR8RD register ******************/
sahilmgandhi 18:6a4db94011d3 2968 #define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 2969 #define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 2970
sahilmgandhi 18:6a4db94011d3 2971 /******************* Bit definition for DAC_DOR1 register *******************/
sahilmgandhi 18:6a4db94011d3 2972 #define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
sahilmgandhi 18:6a4db94011d3 2973
sahilmgandhi 18:6a4db94011d3 2974 /******************* Bit definition for DAC_DOR2 register *******************/
sahilmgandhi 18:6a4db94011d3 2975 #define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
sahilmgandhi 18:6a4db94011d3 2976
sahilmgandhi 18:6a4db94011d3 2977 /******************** Bit definition for DAC_SR register ********************/
sahilmgandhi 18:6a4db94011d3 2978 #define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
sahilmgandhi 18:6a4db94011d3 2979 #define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
sahilmgandhi 18:6a4db94011d3 2980
sahilmgandhi 18:6a4db94011d3 2981 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2982 /* */
sahilmgandhi 18:6a4db94011d3 2983 /* Debug MCU */
sahilmgandhi 18:6a4db94011d3 2984 /* */
sahilmgandhi 18:6a4db94011d3 2985 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2986
sahilmgandhi 18:6a4db94011d3 2987 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2988 /* */
sahilmgandhi 18:6a4db94011d3 2989 /* DCMI */
sahilmgandhi 18:6a4db94011d3 2990 /* */
sahilmgandhi 18:6a4db94011d3 2991 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2992 /******************** Bits definition for DCMI_CR register ******************/
sahilmgandhi 18:6a4db94011d3 2993 #define DCMI_CR_CAPTURE 0x00000001U
sahilmgandhi 18:6a4db94011d3 2994 #define DCMI_CR_CM 0x00000002U
sahilmgandhi 18:6a4db94011d3 2995 #define DCMI_CR_CROP 0x00000004U
sahilmgandhi 18:6a4db94011d3 2996 #define DCMI_CR_JPEG 0x00000008U
sahilmgandhi 18:6a4db94011d3 2997 #define DCMI_CR_ESS 0x00000010U
sahilmgandhi 18:6a4db94011d3 2998 #define DCMI_CR_PCKPOL 0x00000020U
sahilmgandhi 18:6a4db94011d3 2999 #define DCMI_CR_HSPOL 0x00000040U
sahilmgandhi 18:6a4db94011d3 3000 #define DCMI_CR_VSPOL 0x00000080U
sahilmgandhi 18:6a4db94011d3 3001 #define DCMI_CR_FCRC_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 3002 #define DCMI_CR_FCRC_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 3003 #define DCMI_CR_EDM_0 0x00000400U
sahilmgandhi 18:6a4db94011d3 3004 #define DCMI_CR_EDM_1 0x00000800U
sahilmgandhi 18:6a4db94011d3 3005 #define DCMI_CR_CRE 0x00001000U
sahilmgandhi 18:6a4db94011d3 3006 #define DCMI_CR_ENABLE 0x00004000U
sahilmgandhi 18:6a4db94011d3 3007
sahilmgandhi 18:6a4db94011d3 3008 /******************** Bits definition for DCMI_SR register ******************/
sahilmgandhi 18:6a4db94011d3 3009 #define DCMI_SR_HSYNC 0x00000001U
sahilmgandhi 18:6a4db94011d3 3010 #define DCMI_SR_VSYNC 0x00000002U
sahilmgandhi 18:6a4db94011d3 3011 #define DCMI_SR_FNE 0x00000004U
sahilmgandhi 18:6a4db94011d3 3012
sahilmgandhi 18:6a4db94011d3 3013 /******************** Bits definition for DCMI_RIS register *****************/
sahilmgandhi 18:6a4db94011d3 3014 #define DCMI_RIS_FRAME_RIS 0x00000001U
sahilmgandhi 18:6a4db94011d3 3015 #define DCMI_RIS_OVR_RIS 0x00000002U
sahilmgandhi 18:6a4db94011d3 3016 #define DCMI_RIS_ERR_RIS 0x00000004U
sahilmgandhi 18:6a4db94011d3 3017 #define DCMI_RIS_VSYNC_RIS 0x00000008U
sahilmgandhi 18:6a4db94011d3 3018 #define DCMI_RIS_LINE_RIS 0x00000010U
sahilmgandhi 18:6a4db94011d3 3019 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 3020 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
sahilmgandhi 18:6a4db94011d3 3021 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
sahilmgandhi 18:6a4db94011d3 3022 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
sahilmgandhi 18:6a4db94011d3 3023 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
sahilmgandhi 18:6a4db94011d3 3024 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
sahilmgandhi 18:6a4db94011d3 3025 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
sahilmgandhi 18:6a4db94011d3 3026
sahilmgandhi 18:6a4db94011d3 3027 /******************** Bits definition for DCMI_IER register *****************/
sahilmgandhi 18:6a4db94011d3 3028 #define DCMI_IER_FRAME_IE 0x00000001U
sahilmgandhi 18:6a4db94011d3 3029 #define DCMI_IER_OVR_IE 0x00000002U
sahilmgandhi 18:6a4db94011d3 3030 #define DCMI_IER_ERR_IE 0x00000004U
sahilmgandhi 18:6a4db94011d3 3031 #define DCMI_IER_VSYNC_IE 0x00000008U
sahilmgandhi 18:6a4db94011d3 3032 #define DCMI_IER_LINE_IE 0x00000010U
sahilmgandhi 18:6a4db94011d3 3033 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 3034 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
sahilmgandhi 18:6a4db94011d3 3035
sahilmgandhi 18:6a4db94011d3 3036 /******************** Bits definition for DCMI_MIS register *****************/
sahilmgandhi 18:6a4db94011d3 3037 #define DCMI_MIS_FRAME_MIS 0x00000001U
sahilmgandhi 18:6a4db94011d3 3038 #define DCMI_MIS_OVR_MIS 0x00000002U
sahilmgandhi 18:6a4db94011d3 3039 #define DCMI_MIS_ERR_MIS 0x00000004U
sahilmgandhi 18:6a4db94011d3 3040 #define DCMI_MIS_VSYNC_MIS 0x00000008U
sahilmgandhi 18:6a4db94011d3 3041 #define DCMI_MIS_LINE_MIS 0x00000010U
sahilmgandhi 18:6a4db94011d3 3042
sahilmgandhi 18:6a4db94011d3 3043 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 3044 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
sahilmgandhi 18:6a4db94011d3 3045 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
sahilmgandhi 18:6a4db94011d3 3046 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
sahilmgandhi 18:6a4db94011d3 3047 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
sahilmgandhi 18:6a4db94011d3 3048 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
sahilmgandhi 18:6a4db94011d3 3049
sahilmgandhi 18:6a4db94011d3 3050 /******************** Bits definition for DCMI_ICR register *****************/
sahilmgandhi 18:6a4db94011d3 3051 #define DCMI_ICR_FRAME_ISC 0x00000001U
sahilmgandhi 18:6a4db94011d3 3052 #define DCMI_ICR_OVR_ISC 0x00000002U
sahilmgandhi 18:6a4db94011d3 3053 #define DCMI_ICR_ERR_ISC 0x00000004U
sahilmgandhi 18:6a4db94011d3 3054 #define DCMI_ICR_VSYNC_ISC 0x00000008U
sahilmgandhi 18:6a4db94011d3 3055 #define DCMI_ICR_LINE_ISC 0x00000010U
sahilmgandhi 18:6a4db94011d3 3056
sahilmgandhi 18:6a4db94011d3 3057 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 3058 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
sahilmgandhi 18:6a4db94011d3 3059
sahilmgandhi 18:6a4db94011d3 3060 /******************** Bits definition for DCMI_ESCR register ******************/
sahilmgandhi 18:6a4db94011d3 3061 #define DCMI_ESCR_FSC 0x000000FFU
sahilmgandhi 18:6a4db94011d3 3062 #define DCMI_ESCR_LSC 0x0000FF00U
sahilmgandhi 18:6a4db94011d3 3063 #define DCMI_ESCR_LEC 0x00FF0000U
sahilmgandhi 18:6a4db94011d3 3064 #define DCMI_ESCR_FEC 0xFF000000U
sahilmgandhi 18:6a4db94011d3 3065
sahilmgandhi 18:6a4db94011d3 3066 /******************** Bits definition for DCMI_ESUR register ******************/
sahilmgandhi 18:6a4db94011d3 3067 #define DCMI_ESUR_FSU 0x000000FFU
sahilmgandhi 18:6a4db94011d3 3068 #define DCMI_ESUR_LSU 0x0000FF00U
sahilmgandhi 18:6a4db94011d3 3069 #define DCMI_ESUR_LEU 0x00FF0000U
sahilmgandhi 18:6a4db94011d3 3070 #define DCMI_ESUR_FEU 0xFF000000U
sahilmgandhi 18:6a4db94011d3 3071
sahilmgandhi 18:6a4db94011d3 3072 /******************** Bits definition for DCMI_CWSTRT register ******************/
sahilmgandhi 18:6a4db94011d3 3073 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
sahilmgandhi 18:6a4db94011d3 3074 #define DCMI_CWSTRT_VST 0x1FFF0000U
sahilmgandhi 18:6a4db94011d3 3075
sahilmgandhi 18:6a4db94011d3 3076 /******************** Bits definition for DCMI_CWSIZE register ******************/
sahilmgandhi 18:6a4db94011d3 3077 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
sahilmgandhi 18:6a4db94011d3 3078 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
sahilmgandhi 18:6a4db94011d3 3079
sahilmgandhi 18:6a4db94011d3 3080 /******************** Bits definition for DCMI_DR register ******************/
sahilmgandhi 18:6a4db94011d3 3081 #define DCMI_DR_BYTE0 0x000000FFU
sahilmgandhi 18:6a4db94011d3 3082 #define DCMI_DR_BYTE1 0x0000FF00U
sahilmgandhi 18:6a4db94011d3 3083 #define DCMI_DR_BYTE2 0x00FF0000U
sahilmgandhi 18:6a4db94011d3 3084 #define DCMI_DR_BYTE3 0xFF000000U
sahilmgandhi 18:6a4db94011d3 3085
sahilmgandhi 18:6a4db94011d3 3086 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3087 /* */
sahilmgandhi 18:6a4db94011d3 3088 /* DMA Controller */
sahilmgandhi 18:6a4db94011d3 3089 /* */
sahilmgandhi 18:6a4db94011d3 3090 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3091 /******************** Bits definition for DMA_SxCR register *****************/
sahilmgandhi 18:6a4db94011d3 3092 #define DMA_SxCR_CHSEL 0x0E000000U
sahilmgandhi 18:6a4db94011d3 3093 #define DMA_SxCR_CHSEL_0 0x02000000U
sahilmgandhi 18:6a4db94011d3 3094 #define DMA_SxCR_CHSEL_1 0x04000000U
sahilmgandhi 18:6a4db94011d3 3095 #define DMA_SxCR_CHSEL_2 0x08000000U
sahilmgandhi 18:6a4db94011d3 3096 #define DMA_SxCR_MBURST 0x01800000U
sahilmgandhi 18:6a4db94011d3 3097 #define DMA_SxCR_MBURST_0 0x00800000U
sahilmgandhi 18:6a4db94011d3 3098 #define DMA_SxCR_MBURST_1 0x01000000U
sahilmgandhi 18:6a4db94011d3 3099 #define DMA_SxCR_PBURST 0x00600000U
sahilmgandhi 18:6a4db94011d3 3100 #define DMA_SxCR_PBURST_0 0x00200000U
sahilmgandhi 18:6a4db94011d3 3101 #define DMA_SxCR_PBURST_1 0x00400000U
sahilmgandhi 18:6a4db94011d3 3102 #define DMA_SxCR_CT 0x00080000U
sahilmgandhi 18:6a4db94011d3 3103 #define DMA_SxCR_DBM 0x00040000U
sahilmgandhi 18:6a4db94011d3 3104 #define DMA_SxCR_PL 0x00030000U
sahilmgandhi 18:6a4db94011d3 3105 #define DMA_SxCR_PL_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 3106 #define DMA_SxCR_PL_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 3107 #define DMA_SxCR_PINCOS 0x00008000U
sahilmgandhi 18:6a4db94011d3 3108 #define DMA_SxCR_MSIZE 0x00006000U
sahilmgandhi 18:6a4db94011d3 3109 #define DMA_SxCR_MSIZE_0 0x00002000U
sahilmgandhi 18:6a4db94011d3 3110 #define DMA_SxCR_MSIZE_1 0x00004000U
sahilmgandhi 18:6a4db94011d3 3111 #define DMA_SxCR_PSIZE 0x00001800U
sahilmgandhi 18:6a4db94011d3 3112 #define DMA_SxCR_PSIZE_0 0x00000800U
sahilmgandhi 18:6a4db94011d3 3113 #define DMA_SxCR_PSIZE_1 0x00001000U
sahilmgandhi 18:6a4db94011d3 3114 #define DMA_SxCR_MINC 0x00000400U
sahilmgandhi 18:6a4db94011d3 3115 #define DMA_SxCR_PINC 0x00000200U
sahilmgandhi 18:6a4db94011d3 3116 #define DMA_SxCR_CIRC 0x00000100U
sahilmgandhi 18:6a4db94011d3 3117 #define DMA_SxCR_DIR 0x000000C0U
sahilmgandhi 18:6a4db94011d3 3118 #define DMA_SxCR_DIR_0 0x00000040U
sahilmgandhi 18:6a4db94011d3 3119 #define DMA_SxCR_DIR_1 0x00000080U
sahilmgandhi 18:6a4db94011d3 3120 #define DMA_SxCR_PFCTRL 0x00000020U
sahilmgandhi 18:6a4db94011d3 3121 #define DMA_SxCR_TCIE 0x00000010U
sahilmgandhi 18:6a4db94011d3 3122 #define DMA_SxCR_HTIE 0x00000008U
sahilmgandhi 18:6a4db94011d3 3123 #define DMA_SxCR_TEIE 0x00000004U
sahilmgandhi 18:6a4db94011d3 3124 #define DMA_SxCR_DMEIE 0x00000002U
sahilmgandhi 18:6a4db94011d3 3125 #define DMA_SxCR_EN 0x00000001U
sahilmgandhi 18:6a4db94011d3 3126
sahilmgandhi 18:6a4db94011d3 3127 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 3128 #define DMA_SxCR_ACK 0x00100000U
sahilmgandhi 18:6a4db94011d3 3129
sahilmgandhi 18:6a4db94011d3 3130 /******************** Bits definition for DMA_SxCNDTR register **************/
sahilmgandhi 18:6a4db94011d3 3131 #define DMA_SxNDT 0x0000FFFFU
sahilmgandhi 18:6a4db94011d3 3132 #define DMA_SxNDT_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 3133 #define DMA_SxNDT_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 3134 #define DMA_SxNDT_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 3135 #define DMA_SxNDT_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 3136 #define DMA_SxNDT_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 3137 #define DMA_SxNDT_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 3138 #define DMA_SxNDT_6 0x00000040U
sahilmgandhi 18:6a4db94011d3 3139 #define DMA_SxNDT_7 0x00000080U
sahilmgandhi 18:6a4db94011d3 3140 #define DMA_SxNDT_8 0x00000100U
sahilmgandhi 18:6a4db94011d3 3141 #define DMA_SxNDT_9 0x00000200U
sahilmgandhi 18:6a4db94011d3 3142 #define DMA_SxNDT_10 0x00000400U
sahilmgandhi 18:6a4db94011d3 3143 #define DMA_SxNDT_11 0x00000800U
sahilmgandhi 18:6a4db94011d3 3144 #define DMA_SxNDT_12 0x00001000U
sahilmgandhi 18:6a4db94011d3 3145 #define DMA_SxNDT_13 0x00002000U
sahilmgandhi 18:6a4db94011d3 3146 #define DMA_SxNDT_14 0x00004000U
sahilmgandhi 18:6a4db94011d3 3147 #define DMA_SxNDT_15 0x00008000U
sahilmgandhi 18:6a4db94011d3 3148
sahilmgandhi 18:6a4db94011d3 3149 /******************** Bits definition for DMA_SxFCR register ****************/
sahilmgandhi 18:6a4db94011d3 3150 #define DMA_SxFCR_FEIE 0x00000080U
sahilmgandhi 18:6a4db94011d3 3151 #define DMA_SxFCR_FS 0x00000038U
sahilmgandhi 18:6a4db94011d3 3152 #define DMA_SxFCR_FS_0 0x00000008U
sahilmgandhi 18:6a4db94011d3 3153 #define DMA_SxFCR_FS_1 0x00000010U
sahilmgandhi 18:6a4db94011d3 3154 #define DMA_SxFCR_FS_2 0x00000020U
sahilmgandhi 18:6a4db94011d3 3155 #define DMA_SxFCR_DMDIS 0x00000004U
sahilmgandhi 18:6a4db94011d3 3156 #define DMA_SxFCR_FTH 0x00000003U
sahilmgandhi 18:6a4db94011d3 3157 #define DMA_SxFCR_FTH_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 3158 #define DMA_SxFCR_FTH_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 3159
sahilmgandhi 18:6a4db94011d3 3160 /******************** Bits definition for DMA_LISR register *****************/
sahilmgandhi 18:6a4db94011d3 3161 #define DMA_LISR_TCIF3 0x08000000U
sahilmgandhi 18:6a4db94011d3 3162 #define DMA_LISR_HTIF3 0x04000000U
sahilmgandhi 18:6a4db94011d3 3163 #define DMA_LISR_TEIF3 0x02000000U
sahilmgandhi 18:6a4db94011d3 3164 #define DMA_LISR_DMEIF3 0x01000000U
sahilmgandhi 18:6a4db94011d3 3165 #define DMA_LISR_FEIF3 0x00400000U
sahilmgandhi 18:6a4db94011d3 3166 #define DMA_LISR_TCIF2 0x00200000U
sahilmgandhi 18:6a4db94011d3 3167 #define DMA_LISR_HTIF2 0x00100000U
sahilmgandhi 18:6a4db94011d3 3168 #define DMA_LISR_TEIF2 0x00080000U
sahilmgandhi 18:6a4db94011d3 3169 #define DMA_LISR_DMEIF2 0x00040000U
sahilmgandhi 18:6a4db94011d3 3170 #define DMA_LISR_FEIF2 0x00010000U
sahilmgandhi 18:6a4db94011d3 3171 #define DMA_LISR_TCIF1 0x00000800U
sahilmgandhi 18:6a4db94011d3 3172 #define DMA_LISR_HTIF1 0x00000400U
sahilmgandhi 18:6a4db94011d3 3173 #define DMA_LISR_TEIF1 0x00000200U
sahilmgandhi 18:6a4db94011d3 3174 #define DMA_LISR_DMEIF1 0x00000100U
sahilmgandhi 18:6a4db94011d3 3175 #define DMA_LISR_FEIF1 0x00000040U
sahilmgandhi 18:6a4db94011d3 3176 #define DMA_LISR_TCIF0 0x00000020U
sahilmgandhi 18:6a4db94011d3 3177 #define DMA_LISR_HTIF0 0x00000010U
sahilmgandhi 18:6a4db94011d3 3178 #define DMA_LISR_TEIF0 0x00000008U
sahilmgandhi 18:6a4db94011d3 3179 #define DMA_LISR_DMEIF0 0x00000004U
sahilmgandhi 18:6a4db94011d3 3180 #define DMA_LISR_FEIF0 0x00000001U
sahilmgandhi 18:6a4db94011d3 3181
sahilmgandhi 18:6a4db94011d3 3182 /******************** Bits definition for DMA_HISR register *****************/
sahilmgandhi 18:6a4db94011d3 3183 #define DMA_HISR_TCIF7 0x08000000U
sahilmgandhi 18:6a4db94011d3 3184 #define DMA_HISR_HTIF7 0x04000000U
sahilmgandhi 18:6a4db94011d3 3185 #define DMA_HISR_TEIF7 0x02000000U
sahilmgandhi 18:6a4db94011d3 3186 #define DMA_HISR_DMEIF7 0x01000000U
sahilmgandhi 18:6a4db94011d3 3187 #define DMA_HISR_FEIF7 0x00400000U
sahilmgandhi 18:6a4db94011d3 3188 #define DMA_HISR_TCIF6 0x00200000U
sahilmgandhi 18:6a4db94011d3 3189 #define DMA_HISR_HTIF6 0x00100000U
sahilmgandhi 18:6a4db94011d3 3190 #define DMA_HISR_TEIF6 0x00080000U
sahilmgandhi 18:6a4db94011d3 3191 #define DMA_HISR_DMEIF6 0x00040000U
sahilmgandhi 18:6a4db94011d3 3192 #define DMA_HISR_FEIF6 0x00010000U
sahilmgandhi 18:6a4db94011d3 3193 #define DMA_HISR_TCIF5 0x00000800U
sahilmgandhi 18:6a4db94011d3 3194 #define DMA_HISR_HTIF5 0x00000400U
sahilmgandhi 18:6a4db94011d3 3195 #define DMA_HISR_TEIF5 0x00000200U
sahilmgandhi 18:6a4db94011d3 3196 #define DMA_HISR_DMEIF5 0x00000100U
sahilmgandhi 18:6a4db94011d3 3197 #define DMA_HISR_FEIF5 0x00000040U
sahilmgandhi 18:6a4db94011d3 3198 #define DMA_HISR_TCIF4 0x00000020U
sahilmgandhi 18:6a4db94011d3 3199 #define DMA_HISR_HTIF4 0x00000010U
sahilmgandhi 18:6a4db94011d3 3200 #define DMA_HISR_TEIF4 0x00000008U
sahilmgandhi 18:6a4db94011d3 3201 #define DMA_HISR_DMEIF4 0x00000004U
sahilmgandhi 18:6a4db94011d3 3202 #define DMA_HISR_FEIF4 0x00000001U
sahilmgandhi 18:6a4db94011d3 3203
sahilmgandhi 18:6a4db94011d3 3204 /******************** Bits definition for DMA_LIFCR register ****************/
sahilmgandhi 18:6a4db94011d3 3205 #define DMA_LIFCR_CTCIF3 0x08000000U
sahilmgandhi 18:6a4db94011d3 3206 #define DMA_LIFCR_CHTIF3 0x04000000U
sahilmgandhi 18:6a4db94011d3 3207 #define DMA_LIFCR_CTEIF3 0x02000000U
sahilmgandhi 18:6a4db94011d3 3208 #define DMA_LIFCR_CDMEIF3 0x01000000U
sahilmgandhi 18:6a4db94011d3 3209 #define DMA_LIFCR_CFEIF3 0x00400000U
sahilmgandhi 18:6a4db94011d3 3210 #define DMA_LIFCR_CTCIF2 0x00200000U
sahilmgandhi 18:6a4db94011d3 3211 #define DMA_LIFCR_CHTIF2 0x00100000U
sahilmgandhi 18:6a4db94011d3 3212 #define DMA_LIFCR_CTEIF2 0x00080000U
sahilmgandhi 18:6a4db94011d3 3213 #define DMA_LIFCR_CDMEIF2 0x00040000U
sahilmgandhi 18:6a4db94011d3 3214 #define DMA_LIFCR_CFEIF2 0x00010000U
sahilmgandhi 18:6a4db94011d3 3215 #define DMA_LIFCR_CTCIF1 0x00000800U
sahilmgandhi 18:6a4db94011d3 3216 #define DMA_LIFCR_CHTIF1 0x00000400U
sahilmgandhi 18:6a4db94011d3 3217 #define DMA_LIFCR_CTEIF1 0x00000200U
sahilmgandhi 18:6a4db94011d3 3218 #define DMA_LIFCR_CDMEIF1 0x00000100U
sahilmgandhi 18:6a4db94011d3 3219 #define DMA_LIFCR_CFEIF1 0x00000040U
sahilmgandhi 18:6a4db94011d3 3220 #define DMA_LIFCR_CTCIF0 0x00000020U
sahilmgandhi 18:6a4db94011d3 3221 #define DMA_LIFCR_CHTIF0 0x00000010U
sahilmgandhi 18:6a4db94011d3 3222 #define DMA_LIFCR_CTEIF0 0x00000008U
sahilmgandhi 18:6a4db94011d3 3223 #define DMA_LIFCR_CDMEIF0 0x00000004U
sahilmgandhi 18:6a4db94011d3 3224 #define DMA_LIFCR_CFEIF0 0x00000001U
sahilmgandhi 18:6a4db94011d3 3225
sahilmgandhi 18:6a4db94011d3 3226 /******************** Bits definition for DMA_HIFCR register ****************/
sahilmgandhi 18:6a4db94011d3 3227 #define DMA_HIFCR_CTCIF7 0x08000000U
sahilmgandhi 18:6a4db94011d3 3228 #define DMA_HIFCR_CHTIF7 0x04000000U
sahilmgandhi 18:6a4db94011d3 3229 #define DMA_HIFCR_CTEIF7 0x02000000U
sahilmgandhi 18:6a4db94011d3 3230 #define DMA_HIFCR_CDMEIF7 0x01000000U
sahilmgandhi 18:6a4db94011d3 3231 #define DMA_HIFCR_CFEIF7 0x00400000U
sahilmgandhi 18:6a4db94011d3 3232 #define DMA_HIFCR_CTCIF6 0x00200000U
sahilmgandhi 18:6a4db94011d3 3233 #define DMA_HIFCR_CHTIF6 0x00100000U
sahilmgandhi 18:6a4db94011d3 3234 #define DMA_HIFCR_CTEIF6 0x00080000U
sahilmgandhi 18:6a4db94011d3 3235 #define DMA_HIFCR_CDMEIF6 0x00040000U
sahilmgandhi 18:6a4db94011d3 3236 #define DMA_HIFCR_CFEIF6 0x00010000U
sahilmgandhi 18:6a4db94011d3 3237 #define DMA_HIFCR_CTCIF5 0x00000800U
sahilmgandhi 18:6a4db94011d3 3238 #define DMA_HIFCR_CHTIF5 0x00000400U
sahilmgandhi 18:6a4db94011d3 3239 #define DMA_HIFCR_CTEIF5 0x00000200U
sahilmgandhi 18:6a4db94011d3 3240 #define DMA_HIFCR_CDMEIF5 0x00000100U
sahilmgandhi 18:6a4db94011d3 3241 #define DMA_HIFCR_CFEIF5 0x00000040U
sahilmgandhi 18:6a4db94011d3 3242 #define DMA_HIFCR_CTCIF4 0x00000020U
sahilmgandhi 18:6a4db94011d3 3243 #define DMA_HIFCR_CHTIF4 0x00000010U
sahilmgandhi 18:6a4db94011d3 3244 #define DMA_HIFCR_CTEIF4 0x00000008U
sahilmgandhi 18:6a4db94011d3 3245 #define DMA_HIFCR_CDMEIF4 0x00000004U
sahilmgandhi 18:6a4db94011d3 3246 #define DMA_HIFCR_CFEIF4 0x00000001U
sahilmgandhi 18:6a4db94011d3 3247
sahilmgandhi 18:6a4db94011d3 3248
sahilmgandhi 18:6a4db94011d3 3249 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3250 /* */
sahilmgandhi 18:6a4db94011d3 3251 /* External Interrupt/Event Controller */
sahilmgandhi 18:6a4db94011d3 3252 /* */
sahilmgandhi 18:6a4db94011d3 3253 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3254 /******************* Bit definition for EXTI_IMR register *******************/
sahilmgandhi 18:6a4db94011d3 3255 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
sahilmgandhi 18:6a4db94011d3 3256 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
sahilmgandhi 18:6a4db94011d3 3257 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
sahilmgandhi 18:6a4db94011d3 3258 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
sahilmgandhi 18:6a4db94011d3 3259 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
sahilmgandhi 18:6a4db94011d3 3260 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
sahilmgandhi 18:6a4db94011d3 3261 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
sahilmgandhi 18:6a4db94011d3 3262 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
sahilmgandhi 18:6a4db94011d3 3263 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
sahilmgandhi 18:6a4db94011d3 3264 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
sahilmgandhi 18:6a4db94011d3 3265 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
sahilmgandhi 18:6a4db94011d3 3266 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
sahilmgandhi 18:6a4db94011d3 3267 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
sahilmgandhi 18:6a4db94011d3 3268 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
sahilmgandhi 18:6a4db94011d3 3269 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
sahilmgandhi 18:6a4db94011d3 3270 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
sahilmgandhi 18:6a4db94011d3 3271 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
sahilmgandhi 18:6a4db94011d3 3272 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
sahilmgandhi 18:6a4db94011d3 3273 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
sahilmgandhi 18:6a4db94011d3 3274 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
sahilmgandhi 18:6a4db94011d3 3275 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
sahilmgandhi 18:6a4db94011d3 3276 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
sahilmgandhi 18:6a4db94011d3 3277 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
sahilmgandhi 18:6a4db94011d3 3278
sahilmgandhi 18:6a4db94011d3 3279 /******************* Bit definition for EXTI_EMR register *******************/
sahilmgandhi 18:6a4db94011d3 3280 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
sahilmgandhi 18:6a4db94011d3 3281 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
sahilmgandhi 18:6a4db94011d3 3282 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
sahilmgandhi 18:6a4db94011d3 3283 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
sahilmgandhi 18:6a4db94011d3 3284 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
sahilmgandhi 18:6a4db94011d3 3285 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
sahilmgandhi 18:6a4db94011d3 3286 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
sahilmgandhi 18:6a4db94011d3 3287 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
sahilmgandhi 18:6a4db94011d3 3288 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
sahilmgandhi 18:6a4db94011d3 3289 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
sahilmgandhi 18:6a4db94011d3 3290 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
sahilmgandhi 18:6a4db94011d3 3291 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
sahilmgandhi 18:6a4db94011d3 3292 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
sahilmgandhi 18:6a4db94011d3 3293 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
sahilmgandhi 18:6a4db94011d3 3294 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
sahilmgandhi 18:6a4db94011d3 3295 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
sahilmgandhi 18:6a4db94011d3 3296 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
sahilmgandhi 18:6a4db94011d3 3297 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
sahilmgandhi 18:6a4db94011d3 3298 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
sahilmgandhi 18:6a4db94011d3 3299 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
sahilmgandhi 18:6a4db94011d3 3300 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
sahilmgandhi 18:6a4db94011d3 3301 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
sahilmgandhi 18:6a4db94011d3 3302 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
sahilmgandhi 18:6a4db94011d3 3303
sahilmgandhi 18:6a4db94011d3 3304 /****************** Bit definition for EXTI_RTSR register *******************/
sahilmgandhi 18:6a4db94011d3 3305 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
sahilmgandhi 18:6a4db94011d3 3306 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
sahilmgandhi 18:6a4db94011d3 3307 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
sahilmgandhi 18:6a4db94011d3 3308 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
sahilmgandhi 18:6a4db94011d3 3309 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
sahilmgandhi 18:6a4db94011d3 3310 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
sahilmgandhi 18:6a4db94011d3 3311 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
sahilmgandhi 18:6a4db94011d3 3312 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
sahilmgandhi 18:6a4db94011d3 3313 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
sahilmgandhi 18:6a4db94011d3 3314 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
sahilmgandhi 18:6a4db94011d3 3315 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
sahilmgandhi 18:6a4db94011d3 3316 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
sahilmgandhi 18:6a4db94011d3 3317 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
sahilmgandhi 18:6a4db94011d3 3318 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
sahilmgandhi 18:6a4db94011d3 3319 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
sahilmgandhi 18:6a4db94011d3 3320 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
sahilmgandhi 18:6a4db94011d3 3321 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
sahilmgandhi 18:6a4db94011d3 3322 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
sahilmgandhi 18:6a4db94011d3 3323 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
sahilmgandhi 18:6a4db94011d3 3324 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
sahilmgandhi 18:6a4db94011d3 3325 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
sahilmgandhi 18:6a4db94011d3 3326 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
sahilmgandhi 18:6a4db94011d3 3327 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
sahilmgandhi 18:6a4db94011d3 3328
sahilmgandhi 18:6a4db94011d3 3329 /****************** Bit definition for EXTI_FTSR register *******************/
sahilmgandhi 18:6a4db94011d3 3330 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
sahilmgandhi 18:6a4db94011d3 3331 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
sahilmgandhi 18:6a4db94011d3 3332 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
sahilmgandhi 18:6a4db94011d3 3333 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
sahilmgandhi 18:6a4db94011d3 3334 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
sahilmgandhi 18:6a4db94011d3 3335 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
sahilmgandhi 18:6a4db94011d3 3336 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
sahilmgandhi 18:6a4db94011d3 3337 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
sahilmgandhi 18:6a4db94011d3 3338 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
sahilmgandhi 18:6a4db94011d3 3339 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
sahilmgandhi 18:6a4db94011d3 3340 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
sahilmgandhi 18:6a4db94011d3 3341 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
sahilmgandhi 18:6a4db94011d3 3342 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
sahilmgandhi 18:6a4db94011d3 3343 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
sahilmgandhi 18:6a4db94011d3 3344 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
sahilmgandhi 18:6a4db94011d3 3345 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
sahilmgandhi 18:6a4db94011d3 3346 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
sahilmgandhi 18:6a4db94011d3 3347 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
sahilmgandhi 18:6a4db94011d3 3348 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
sahilmgandhi 18:6a4db94011d3 3349 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
sahilmgandhi 18:6a4db94011d3 3350 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
sahilmgandhi 18:6a4db94011d3 3351 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
sahilmgandhi 18:6a4db94011d3 3352 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
sahilmgandhi 18:6a4db94011d3 3353
sahilmgandhi 18:6a4db94011d3 3354 /****************** Bit definition for EXTI_SWIER register ******************/
sahilmgandhi 18:6a4db94011d3 3355 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
sahilmgandhi 18:6a4db94011d3 3356 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
sahilmgandhi 18:6a4db94011d3 3357 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
sahilmgandhi 18:6a4db94011d3 3358 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
sahilmgandhi 18:6a4db94011d3 3359 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
sahilmgandhi 18:6a4db94011d3 3360 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
sahilmgandhi 18:6a4db94011d3 3361 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
sahilmgandhi 18:6a4db94011d3 3362 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
sahilmgandhi 18:6a4db94011d3 3363 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
sahilmgandhi 18:6a4db94011d3 3364 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
sahilmgandhi 18:6a4db94011d3 3365 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
sahilmgandhi 18:6a4db94011d3 3366 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
sahilmgandhi 18:6a4db94011d3 3367 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
sahilmgandhi 18:6a4db94011d3 3368 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
sahilmgandhi 18:6a4db94011d3 3369 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
sahilmgandhi 18:6a4db94011d3 3370 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
sahilmgandhi 18:6a4db94011d3 3371 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
sahilmgandhi 18:6a4db94011d3 3372 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
sahilmgandhi 18:6a4db94011d3 3373 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
sahilmgandhi 18:6a4db94011d3 3374 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
sahilmgandhi 18:6a4db94011d3 3375 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
sahilmgandhi 18:6a4db94011d3 3376 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
sahilmgandhi 18:6a4db94011d3 3377 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
sahilmgandhi 18:6a4db94011d3 3378
sahilmgandhi 18:6a4db94011d3 3379 /******************* Bit definition for EXTI_PR register ********************/
sahilmgandhi 18:6a4db94011d3 3380 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
sahilmgandhi 18:6a4db94011d3 3381 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
sahilmgandhi 18:6a4db94011d3 3382 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
sahilmgandhi 18:6a4db94011d3 3383 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
sahilmgandhi 18:6a4db94011d3 3384 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
sahilmgandhi 18:6a4db94011d3 3385 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
sahilmgandhi 18:6a4db94011d3 3386 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
sahilmgandhi 18:6a4db94011d3 3387 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
sahilmgandhi 18:6a4db94011d3 3388 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
sahilmgandhi 18:6a4db94011d3 3389 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
sahilmgandhi 18:6a4db94011d3 3390 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
sahilmgandhi 18:6a4db94011d3 3391 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
sahilmgandhi 18:6a4db94011d3 3392 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
sahilmgandhi 18:6a4db94011d3 3393 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
sahilmgandhi 18:6a4db94011d3 3394 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
sahilmgandhi 18:6a4db94011d3 3395 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
sahilmgandhi 18:6a4db94011d3 3396 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
sahilmgandhi 18:6a4db94011d3 3397 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
sahilmgandhi 18:6a4db94011d3 3398 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
sahilmgandhi 18:6a4db94011d3 3399 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
sahilmgandhi 18:6a4db94011d3 3400 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
sahilmgandhi 18:6a4db94011d3 3401 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
sahilmgandhi 18:6a4db94011d3 3402 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
sahilmgandhi 18:6a4db94011d3 3403
sahilmgandhi 18:6a4db94011d3 3404 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3405 /* */
sahilmgandhi 18:6a4db94011d3 3406 /* FLASH */
sahilmgandhi 18:6a4db94011d3 3407 /* */
sahilmgandhi 18:6a4db94011d3 3408 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3409 /******************* Bits definition for FLASH_ACR register *****************/
sahilmgandhi 18:6a4db94011d3 3410 #define FLASH_ACR_LATENCY 0x0000000FU
sahilmgandhi 18:6a4db94011d3 3411 #define FLASH_ACR_LATENCY_0WS 0x00000000U
sahilmgandhi 18:6a4db94011d3 3412 #define FLASH_ACR_LATENCY_1WS 0x00000001U
sahilmgandhi 18:6a4db94011d3 3413 #define FLASH_ACR_LATENCY_2WS 0x00000002U
sahilmgandhi 18:6a4db94011d3 3414 #define FLASH_ACR_LATENCY_3WS 0x00000003U
sahilmgandhi 18:6a4db94011d3 3415 #define FLASH_ACR_LATENCY_4WS 0x00000004U
sahilmgandhi 18:6a4db94011d3 3416 #define FLASH_ACR_LATENCY_5WS 0x00000005U
sahilmgandhi 18:6a4db94011d3 3417 #define FLASH_ACR_LATENCY_6WS 0x00000006U
sahilmgandhi 18:6a4db94011d3 3418 #define FLASH_ACR_LATENCY_7WS 0x00000007U
sahilmgandhi 18:6a4db94011d3 3419
sahilmgandhi 18:6a4db94011d3 3420 #define FLASH_ACR_PRFTEN 0x00000100U
sahilmgandhi 18:6a4db94011d3 3421 #define FLASH_ACR_ICEN 0x00000200U
sahilmgandhi 18:6a4db94011d3 3422 #define FLASH_ACR_DCEN 0x00000400U
sahilmgandhi 18:6a4db94011d3 3423 #define FLASH_ACR_ICRST 0x00000800U
sahilmgandhi 18:6a4db94011d3 3424 #define FLASH_ACR_DCRST 0x00001000U
sahilmgandhi 18:6a4db94011d3 3425 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
sahilmgandhi 18:6a4db94011d3 3426 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
sahilmgandhi 18:6a4db94011d3 3427
sahilmgandhi 18:6a4db94011d3 3428 /******************* Bits definition for FLASH_SR register ******************/
sahilmgandhi 18:6a4db94011d3 3429 #define FLASH_SR_EOP 0x00000001U
sahilmgandhi 18:6a4db94011d3 3430 #define FLASH_SR_SOP 0x00000002U
sahilmgandhi 18:6a4db94011d3 3431 #define FLASH_SR_WRPERR 0x00000010U
sahilmgandhi 18:6a4db94011d3 3432 #define FLASH_SR_PGAERR 0x00000020U
sahilmgandhi 18:6a4db94011d3 3433 #define FLASH_SR_PGPERR 0x00000040U
sahilmgandhi 18:6a4db94011d3 3434 #define FLASH_SR_PGSERR 0x00000080U
sahilmgandhi 18:6a4db94011d3 3435 #define FLASH_SR_BSY 0x00010000U
sahilmgandhi 18:6a4db94011d3 3436
sahilmgandhi 18:6a4db94011d3 3437 /******************* Bits definition for FLASH_CR register ******************/
sahilmgandhi 18:6a4db94011d3 3438 #define FLASH_CR_PG 0x00000001U
sahilmgandhi 18:6a4db94011d3 3439 #define FLASH_CR_SER 0x00000002U
sahilmgandhi 18:6a4db94011d3 3440 #define FLASH_CR_MER 0x00000004U
sahilmgandhi 18:6a4db94011d3 3441 #define FLASH_CR_SNB 0x000000F8U
sahilmgandhi 18:6a4db94011d3 3442 #define FLASH_CR_SNB_0 0x00000008U
sahilmgandhi 18:6a4db94011d3 3443 #define FLASH_CR_SNB_1 0x00000010U
sahilmgandhi 18:6a4db94011d3 3444 #define FLASH_CR_SNB_2 0x00000020U
sahilmgandhi 18:6a4db94011d3 3445 #define FLASH_CR_SNB_3 0x00000040U
sahilmgandhi 18:6a4db94011d3 3446 #define FLASH_CR_SNB_4 0x00000080U
sahilmgandhi 18:6a4db94011d3 3447 #define FLASH_CR_PSIZE 0x00000300U
sahilmgandhi 18:6a4db94011d3 3448 #define FLASH_CR_PSIZE_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 3449 #define FLASH_CR_PSIZE_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 3450 #define FLASH_CR_STRT 0x00010000U
sahilmgandhi 18:6a4db94011d3 3451 #define FLASH_CR_EOPIE 0x01000000U
sahilmgandhi 18:6a4db94011d3 3452 #define FLASH_CR_LOCK 0x80000000U
sahilmgandhi 18:6a4db94011d3 3453
sahilmgandhi 18:6a4db94011d3 3454 /******************* Bits definition for FLASH_OPTCR register ***************/
sahilmgandhi 18:6a4db94011d3 3455 #define FLASH_OPTCR_OPTLOCK 0x00000001U
sahilmgandhi 18:6a4db94011d3 3456 #define FLASH_OPTCR_OPTSTRT 0x00000002U
sahilmgandhi 18:6a4db94011d3 3457 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
sahilmgandhi 18:6a4db94011d3 3458 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
sahilmgandhi 18:6a4db94011d3 3459 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
sahilmgandhi 18:6a4db94011d3 3460
sahilmgandhi 18:6a4db94011d3 3461 #define FLASH_OPTCR_WDG_SW 0x00000020U
sahilmgandhi 18:6a4db94011d3 3462 #define FLASH_OPTCR_nRST_STOP 0x00000040U
sahilmgandhi 18:6a4db94011d3 3463 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
sahilmgandhi 18:6a4db94011d3 3464 #define FLASH_OPTCR_RDP 0x0000FF00U
sahilmgandhi 18:6a4db94011d3 3465 #define FLASH_OPTCR_RDP_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 3466 #define FLASH_OPTCR_RDP_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 3467 #define FLASH_OPTCR_RDP_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 3468 #define FLASH_OPTCR_RDP_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 3469 #define FLASH_OPTCR_RDP_4 0x00001000U
sahilmgandhi 18:6a4db94011d3 3470 #define FLASH_OPTCR_RDP_5 0x00002000U
sahilmgandhi 18:6a4db94011d3 3471 #define FLASH_OPTCR_RDP_6 0x00004000U
sahilmgandhi 18:6a4db94011d3 3472 #define FLASH_OPTCR_RDP_7 0x00008000U
sahilmgandhi 18:6a4db94011d3 3473 #define FLASH_OPTCR_nWRP 0x0FFF0000U
sahilmgandhi 18:6a4db94011d3 3474 #define FLASH_OPTCR_nWRP_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 3475 #define FLASH_OPTCR_nWRP_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 3476 #define FLASH_OPTCR_nWRP_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 3477 #define FLASH_OPTCR_nWRP_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 3478 #define FLASH_OPTCR_nWRP_4 0x00100000U
sahilmgandhi 18:6a4db94011d3 3479 #define FLASH_OPTCR_nWRP_5 0x00200000U
sahilmgandhi 18:6a4db94011d3 3480 #define FLASH_OPTCR_nWRP_6 0x00400000U
sahilmgandhi 18:6a4db94011d3 3481 #define FLASH_OPTCR_nWRP_7 0x00800000U
sahilmgandhi 18:6a4db94011d3 3482 #define FLASH_OPTCR_nWRP_8 0x01000000U
sahilmgandhi 18:6a4db94011d3 3483 #define FLASH_OPTCR_nWRP_9 0x02000000U
sahilmgandhi 18:6a4db94011d3 3484 #define FLASH_OPTCR_nWRP_10 0x04000000U
sahilmgandhi 18:6a4db94011d3 3485 #define FLASH_OPTCR_nWRP_11 0x08000000U
sahilmgandhi 18:6a4db94011d3 3486
sahilmgandhi 18:6a4db94011d3 3487 /****************** Bits definition for FLASH_OPTCR1 register ***************/
sahilmgandhi 18:6a4db94011d3 3488 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
sahilmgandhi 18:6a4db94011d3 3489 #define FLASH_OPTCR1_nWRP_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 3490 #define FLASH_OPTCR1_nWRP_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 3491 #define FLASH_OPTCR1_nWRP_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 3492 #define FLASH_OPTCR1_nWRP_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 3493 #define FLASH_OPTCR1_nWRP_4 0x00100000U
sahilmgandhi 18:6a4db94011d3 3494 #define FLASH_OPTCR1_nWRP_5 0x00200000U
sahilmgandhi 18:6a4db94011d3 3495 #define FLASH_OPTCR1_nWRP_6 0x00400000U
sahilmgandhi 18:6a4db94011d3 3496 #define FLASH_OPTCR1_nWRP_7 0x00800000U
sahilmgandhi 18:6a4db94011d3 3497 #define FLASH_OPTCR1_nWRP_8 0x01000000U
sahilmgandhi 18:6a4db94011d3 3498 #define FLASH_OPTCR1_nWRP_9 0x02000000U
sahilmgandhi 18:6a4db94011d3 3499 #define FLASH_OPTCR1_nWRP_10 0x04000000U
sahilmgandhi 18:6a4db94011d3 3500 #define FLASH_OPTCR1_nWRP_11 0x08000000U
sahilmgandhi 18:6a4db94011d3 3501
sahilmgandhi 18:6a4db94011d3 3502 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3503 /* */
sahilmgandhi 18:6a4db94011d3 3504 /* Flexible Static Memory Controller */
sahilmgandhi 18:6a4db94011d3 3505 /* */
sahilmgandhi 18:6a4db94011d3 3506 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 3507 /****************** Bit definition for FSMC_BCR1 register *******************/
sahilmgandhi 18:6a4db94011d3 3508 #define FSMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 3509 #define FSMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
sahilmgandhi 18:6a4db94011d3 3510
sahilmgandhi 18:6a4db94011d3 3511 #define FSMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
sahilmgandhi 18:6a4db94011d3 3512 #define FSMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3513 #define FSMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3514
sahilmgandhi 18:6a4db94011d3 3515 #define FSMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
sahilmgandhi 18:6a4db94011d3 3516 #define FSMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3517 #define FSMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3518
sahilmgandhi 18:6a4db94011d3 3519 #define FSMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
sahilmgandhi 18:6a4db94011d3 3520 #define FSMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
sahilmgandhi 18:6a4db94011d3 3521 #define FSMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
sahilmgandhi 18:6a4db94011d3 3522 #define FSMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
sahilmgandhi 18:6a4db94011d3 3523 #define FSMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
sahilmgandhi 18:6a4db94011d3 3524 #define FSMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
sahilmgandhi 18:6a4db94011d3 3525 #define FSMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
sahilmgandhi 18:6a4db94011d3 3526 #define FSMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
sahilmgandhi 18:6a4db94011d3 3527 #define FSMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
sahilmgandhi 18:6a4db94011d3 3528 #define FSMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
sahilmgandhi 18:6a4db94011d3 3529 #define FSMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3530 #define FSMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3531 #define FSMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3532 #define FSMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
sahilmgandhi 18:6a4db94011d3 3533
sahilmgandhi 18:6a4db94011d3 3534 /****************** Bit definition for FSMC_BCR2 register *******************/
sahilmgandhi 18:6a4db94011d3 3535 #define FSMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 3536 #define FSMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
sahilmgandhi 18:6a4db94011d3 3537
sahilmgandhi 18:6a4db94011d3 3538 #define FSMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
sahilmgandhi 18:6a4db94011d3 3539 #define FSMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3540 #define FSMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3541
sahilmgandhi 18:6a4db94011d3 3542 #define FSMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
sahilmgandhi 18:6a4db94011d3 3543 #define FSMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3544 #define FSMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3545
sahilmgandhi 18:6a4db94011d3 3546 #define FSMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
sahilmgandhi 18:6a4db94011d3 3547 #define FSMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
sahilmgandhi 18:6a4db94011d3 3548 #define FSMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
sahilmgandhi 18:6a4db94011d3 3549 #define FSMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
sahilmgandhi 18:6a4db94011d3 3550 #define FSMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
sahilmgandhi 18:6a4db94011d3 3551 #define FSMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
sahilmgandhi 18:6a4db94011d3 3552 #define FSMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
sahilmgandhi 18:6a4db94011d3 3553 #define FSMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
sahilmgandhi 18:6a4db94011d3 3554 #define FSMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
sahilmgandhi 18:6a4db94011d3 3555 #define FSMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
sahilmgandhi 18:6a4db94011d3 3556 #define FSMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3557 #define FSMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3558 #define FSMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3559 #define FSMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
sahilmgandhi 18:6a4db94011d3 3560
sahilmgandhi 18:6a4db94011d3 3561 /****************** Bit definition for FSMC_BCR3 register *******************/
sahilmgandhi 18:6a4db94011d3 3562 #define FSMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 3563 #define FSMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
sahilmgandhi 18:6a4db94011d3 3564
sahilmgandhi 18:6a4db94011d3 3565 #define FSMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
sahilmgandhi 18:6a4db94011d3 3566 #define FSMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3567 #define FSMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3568
sahilmgandhi 18:6a4db94011d3 3569 #define FSMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
sahilmgandhi 18:6a4db94011d3 3570 #define FSMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3571 #define FSMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3572
sahilmgandhi 18:6a4db94011d3 3573 #define FSMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
sahilmgandhi 18:6a4db94011d3 3574 #define FSMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
sahilmgandhi 18:6a4db94011d3 3575 #define FSMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
sahilmgandhi 18:6a4db94011d3 3576 #define FSMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
sahilmgandhi 18:6a4db94011d3 3577 #define FSMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
sahilmgandhi 18:6a4db94011d3 3578 #define FSMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
sahilmgandhi 18:6a4db94011d3 3579 #define FSMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
sahilmgandhi 18:6a4db94011d3 3580 #define FSMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
sahilmgandhi 18:6a4db94011d3 3581 #define FSMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
sahilmgandhi 18:6a4db94011d3 3582 #define FSMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
sahilmgandhi 18:6a4db94011d3 3583 #define FSMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3584 #define FSMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3585 #define FSMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3586 #define FSMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
sahilmgandhi 18:6a4db94011d3 3587
sahilmgandhi 18:6a4db94011d3 3588 /****************** Bit definition for FSMC_BCR4 register *******************/
sahilmgandhi 18:6a4db94011d3 3589 #define FSMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 3590 #define FSMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
sahilmgandhi 18:6a4db94011d3 3591
sahilmgandhi 18:6a4db94011d3 3592 #define FSMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
sahilmgandhi 18:6a4db94011d3 3593 #define FSMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3594 #define FSMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3595
sahilmgandhi 18:6a4db94011d3 3596 #define FSMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
sahilmgandhi 18:6a4db94011d3 3597 #define FSMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3598 #define FSMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3599
sahilmgandhi 18:6a4db94011d3 3600 #define FSMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
sahilmgandhi 18:6a4db94011d3 3601 #define FSMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
sahilmgandhi 18:6a4db94011d3 3602 #define FSMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
sahilmgandhi 18:6a4db94011d3 3603 #define FSMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
sahilmgandhi 18:6a4db94011d3 3604 #define FSMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
sahilmgandhi 18:6a4db94011d3 3605 #define FSMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
sahilmgandhi 18:6a4db94011d3 3606 #define FSMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
sahilmgandhi 18:6a4db94011d3 3607 #define FSMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
sahilmgandhi 18:6a4db94011d3 3608 #define FSMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
sahilmgandhi 18:6a4db94011d3 3609 #define FSMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
sahilmgandhi 18:6a4db94011d3 3610 #define FSMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3611 #define FSMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3612 #define FSMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3613 #define FSMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
sahilmgandhi 18:6a4db94011d3 3614
sahilmgandhi 18:6a4db94011d3 3615 /****************** Bit definition for FSMC_BTR1 register ******************/
sahilmgandhi 18:6a4db94011d3 3616 #define FSMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 3617 #define FSMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3618 #define FSMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3619 #define FSMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3620 #define FSMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3621
sahilmgandhi 18:6a4db94011d3 3622 #define FSMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 3623 #define FSMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3624 #define FSMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3625 #define FSMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3626 #define FSMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3627
sahilmgandhi 18:6a4db94011d3 3628 #define FSMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 3629 #define FSMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3630 #define FSMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3631 #define FSMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3632 #define FSMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3633 #define FSMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3634 #define FSMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 3635 #define FSMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 3636 #define FSMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 3637
sahilmgandhi 18:6a4db94011d3 3638 #define FSMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
sahilmgandhi 18:6a4db94011d3 3639 #define FSMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3640 #define FSMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3641 #define FSMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3642 #define FSMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3643
sahilmgandhi 18:6a4db94011d3 3644 #define FSMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
sahilmgandhi 18:6a4db94011d3 3645 #define FSMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3646 #define FSMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3647 #define FSMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3648 #define FSMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3649
sahilmgandhi 18:6a4db94011d3 3650 #define FSMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
sahilmgandhi 18:6a4db94011d3 3651 #define FSMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3652 #define FSMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3653 #define FSMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3654 #define FSMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3655
sahilmgandhi 18:6a4db94011d3 3656 #define FSMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 3657 #define FSMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3658 #define FSMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3659
sahilmgandhi 18:6a4db94011d3 3660 /****************** Bit definition for FSMC_BTR2 register *******************/
sahilmgandhi 18:6a4db94011d3 3661 #define FSMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 3662 #define FSMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3663 #define FSMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3664 #define FSMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3665 #define FSMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3666
sahilmgandhi 18:6a4db94011d3 3667 #define FSMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 3668 #define FSMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3669 #define FSMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3670 #define FSMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3671 #define FSMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3672
sahilmgandhi 18:6a4db94011d3 3673 #define FSMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 3674 #define FSMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3675 #define FSMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3676 #define FSMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3677 #define FSMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3678 #define FSMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3679 #define FSMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 3680 #define FSMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 3681 #define FSMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 3682
sahilmgandhi 18:6a4db94011d3 3683 #define FSMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
sahilmgandhi 18:6a4db94011d3 3684 #define FSMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3685 #define FSMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3686 #define FSMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3687 #define FSMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3688
sahilmgandhi 18:6a4db94011d3 3689 #define FSMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
sahilmgandhi 18:6a4db94011d3 3690 #define FSMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3691 #define FSMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3692 #define FSMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3693 #define FSMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3694
sahilmgandhi 18:6a4db94011d3 3695 #define FSMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
sahilmgandhi 18:6a4db94011d3 3696 #define FSMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3697 #define FSMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3698 #define FSMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3699 #define FSMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3700
sahilmgandhi 18:6a4db94011d3 3701 #define FSMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 3702 #define FSMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3703 #define FSMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3704
sahilmgandhi 18:6a4db94011d3 3705 /******************* Bit definition for FSMC_BTR3 register *******************/
sahilmgandhi 18:6a4db94011d3 3706 #define FSMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 3707 #define FSMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3708 #define FSMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3709 #define FSMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3710 #define FSMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3711
sahilmgandhi 18:6a4db94011d3 3712 #define FSMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 3713 #define FSMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3714 #define FSMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3715 #define FSMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3716 #define FSMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3717
sahilmgandhi 18:6a4db94011d3 3718 #define FSMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 3719 #define FSMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3720 #define FSMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3721 #define FSMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3722 #define FSMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3723 #define FSMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3724 #define FSMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 3725 #define FSMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 3726 #define FSMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 3727
sahilmgandhi 18:6a4db94011d3 3728 #define FSMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
sahilmgandhi 18:6a4db94011d3 3729 #define FSMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3730 #define FSMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3731 #define FSMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3732 #define FSMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3733
sahilmgandhi 18:6a4db94011d3 3734 #define FSMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
sahilmgandhi 18:6a4db94011d3 3735 #define FSMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3736 #define FSMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3737 #define FSMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3738 #define FSMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3739
sahilmgandhi 18:6a4db94011d3 3740 #define FSMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
sahilmgandhi 18:6a4db94011d3 3741 #define FSMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3742 #define FSMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3743 #define FSMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3744 #define FSMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3745
sahilmgandhi 18:6a4db94011d3 3746 #define FSMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 3747 #define FSMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3748 #define FSMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3749
sahilmgandhi 18:6a4db94011d3 3750 /****************** Bit definition for FSMC_BTR4 register *******************/
sahilmgandhi 18:6a4db94011d3 3751 #define FSMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 3752 #define FSMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3753 #define FSMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3754 #define FSMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3755 #define FSMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3756
sahilmgandhi 18:6a4db94011d3 3757 #define FSMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 3758 #define FSMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3759 #define FSMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3760 #define FSMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3761 #define FSMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3762
sahilmgandhi 18:6a4db94011d3 3763 #define FSMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 3764 #define FSMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3765 #define FSMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3766 #define FSMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3767 #define FSMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3768 #define FSMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3769 #define FSMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 3770 #define FSMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 3771 #define FSMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 3772
sahilmgandhi 18:6a4db94011d3 3773 #define FSMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
sahilmgandhi 18:6a4db94011d3 3774 #define FSMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3775 #define FSMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3776 #define FSMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3777 #define FSMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3778
sahilmgandhi 18:6a4db94011d3 3779 #define FSMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
sahilmgandhi 18:6a4db94011d3 3780 #define FSMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3781 #define FSMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3782 #define FSMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3783 #define FSMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3784
sahilmgandhi 18:6a4db94011d3 3785 #define FSMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
sahilmgandhi 18:6a4db94011d3 3786 #define FSMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3787 #define FSMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3788 #define FSMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3789 #define FSMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3790
sahilmgandhi 18:6a4db94011d3 3791 #define FSMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 3792 #define FSMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3793 #define FSMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3794
sahilmgandhi 18:6a4db94011d3 3795 /****************** Bit definition for FSMC_BWTR1 register ******************/
sahilmgandhi 18:6a4db94011d3 3796 #define FSMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 3797 #define FSMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3798 #define FSMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3799 #define FSMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3800 #define FSMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3801
sahilmgandhi 18:6a4db94011d3 3802 #define FSMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 3803 #define FSMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3804 #define FSMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3805 #define FSMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3806 #define FSMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3807
sahilmgandhi 18:6a4db94011d3 3808 #define FSMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 3809 #define FSMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3810 #define FSMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3811 #define FSMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3812 #define FSMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3813 #define FSMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3814 #define FSMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 3815 #define FSMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 3816 #define FSMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 3817
sahilmgandhi 18:6a4db94011d3 3818 #define FSMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
sahilmgandhi 18:6a4db94011d3 3819 #define FSMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3820 #define FSMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3821 #define FSMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3822 #define FSMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3823
sahilmgandhi 18:6a4db94011d3 3824 #define FSMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 3825 #define FSMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3826 #define FSMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3827
sahilmgandhi 18:6a4db94011d3 3828 /****************** Bit definition for FSMC_BWTR2 register ******************/
sahilmgandhi 18:6a4db94011d3 3829 #define FSMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 3830 #define FSMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3831 #define FSMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3832 #define FSMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3833 #define FSMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3834
sahilmgandhi 18:6a4db94011d3 3835 #define FSMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 3836 #define FSMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3837 #define FSMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3838 #define FSMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3839 #define FSMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3840
sahilmgandhi 18:6a4db94011d3 3841 #define FSMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 3842 #define FSMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3843 #define FSMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3844 #define FSMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3845 #define FSMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3846 #define FSMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3847 #define FSMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 3848 #define FSMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 3849 #define FSMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 3850
sahilmgandhi 18:6a4db94011d3 3851 #define FSMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
sahilmgandhi 18:6a4db94011d3 3852 #define FSMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3853 #define FSMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3854 #define FSMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3855 #define FSMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3856
sahilmgandhi 18:6a4db94011d3 3857 #define FSMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 3858 #define FSMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3859 #define FSMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3860
sahilmgandhi 18:6a4db94011d3 3861 /****************** Bit definition for FSMC_BWTR3 register ******************/
sahilmgandhi 18:6a4db94011d3 3862 #define FSMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 3863 #define FSMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3864 #define FSMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3865 #define FSMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3866 #define FSMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3867
sahilmgandhi 18:6a4db94011d3 3868 #define FSMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 3869 #define FSMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3870 #define FSMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3871 #define FSMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3872 #define FSMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3873
sahilmgandhi 18:6a4db94011d3 3874 #define FSMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 3875 #define FSMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3876 #define FSMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3877 #define FSMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3878 #define FSMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3879 #define FSMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3880 #define FSMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 3881 #define FSMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 3882 #define FSMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 3883
sahilmgandhi 18:6a4db94011d3 3884 #define FSMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
sahilmgandhi 18:6a4db94011d3 3885 #define FSMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3886 #define FSMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3887 #define FSMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3888 #define FSMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3889
sahilmgandhi 18:6a4db94011d3 3890 #define FSMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 3891 #define FSMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3892 #define FSMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3893
sahilmgandhi 18:6a4db94011d3 3894 /****************** Bit definition for FSMC_BWTR4 register ******************/
sahilmgandhi 18:6a4db94011d3 3895 #define FSMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 3896 #define FSMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3897 #define FSMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3898 #define FSMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3899 #define FSMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3900
sahilmgandhi 18:6a4db94011d3 3901 #define FSMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 3902 #define FSMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3903 #define FSMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3904 #define FSMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3905 #define FSMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3906
sahilmgandhi 18:6a4db94011d3 3907 #define FSMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 3908 #define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3909 #define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3910 #define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3911 #define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3912 #define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 3913 #define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 3914 #define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 3915 #define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 3916
sahilmgandhi 18:6a4db94011d3 3917 #define FSMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
sahilmgandhi 18:6a4db94011d3 3918 #define FSMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3919 #define FSMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3920 #define FSMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3921 #define FSMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3922
sahilmgandhi 18:6a4db94011d3 3923 #define FSMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 3924 #define FSMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3925 #define FSMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3926
sahilmgandhi 18:6a4db94011d3 3927 /****************** Bit definition for FSMC_PCR2 register *******************/
sahilmgandhi 18:6a4db94011d3 3928 #define FSMC_PCR2_PWAITEN 0x00000002U /*!<Wait feature enable bit */
sahilmgandhi 18:6a4db94011d3 3929 #define FSMC_PCR2_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 3930 #define FSMC_PCR2_PTYP 0x00000008U /*!<Memory type */
sahilmgandhi 18:6a4db94011d3 3931
sahilmgandhi 18:6a4db94011d3 3932 #define FSMC_PCR2_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
sahilmgandhi 18:6a4db94011d3 3933 #define FSMC_PCR2_PWID_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3934 #define FSMC_PCR2_PWID_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3935
sahilmgandhi 18:6a4db94011d3 3936 #define FSMC_PCR2_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
sahilmgandhi 18:6a4db94011d3 3937
sahilmgandhi 18:6a4db94011d3 3938 #define FSMC_PCR2_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
sahilmgandhi 18:6a4db94011d3 3939 #define FSMC_PCR2_TCLR_0 0x00000200U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3940 #define FSMC_PCR2_TCLR_1 0x00000400U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3941 #define FSMC_PCR2_TCLR_2 0x00000800U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3942 #define FSMC_PCR2_TCLR_3 0x00001000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3943
sahilmgandhi 18:6a4db94011d3 3944 #define FSMC_PCR2_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
sahilmgandhi 18:6a4db94011d3 3945 #define FSMC_PCR2_TAR_0 0x00002000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3946 #define FSMC_PCR2_TAR_1 0x00004000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3947 #define FSMC_PCR2_TAR_2 0x00008000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3948 #define FSMC_PCR2_TAR_3 0x00010000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3949
sahilmgandhi 18:6a4db94011d3 3950 #define FSMC_PCR2_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
sahilmgandhi 18:6a4db94011d3 3951 #define FSMC_PCR2_ECCPS_0 0x00020000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3952 #define FSMC_PCR2_ECCPS_1 0x00040000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3953 #define FSMC_PCR2_ECCPS_2 0x00080000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3954
sahilmgandhi 18:6a4db94011d3 3955 /****************** Bit definition for FSMC_PCR3 register *******************/
sahilmgandhi 18:6a4db94011d3 3956 #define FSMC_PCR3_PWAITEN 0x00000002U /*!<Wait feature enable bit */
sahilmgandhi 18:6a4db94011d3 3957 #define FSMC_PCR3_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 3958 #define FSMC_PCR3_PTYP 0x00000008U /*!<Memory type */
sahilmgandhi 18:6a4db94011d3 3959
sahilmgandhi 18:6a4db94011d3 3960 #define FSMC_PCR3_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
sahilmgandhi 18:6a4db94011d3 3961 #define FSMC_PCR3_PWID_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3962 #define FSMC_PCR3_PWID_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3963
sahilmgandhi 18:6a4db94011d3 3964 #define FSMC_PCR3_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
sahilmgandhi 18:6a4db94011d3 3965
sahilmgandhi 18:6a4db94011d3 3966 #define FSMC_PCR3_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
sahilmgandhi 18:6a4db94011d3 3967 #define FSMC_PCR3_TCLR_0 0x00000200U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3968 #define FSMC_PCR3_TCLR_1 0x00000400U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3969 #define FSMC_PCR3_TCLR_2 0x00000800U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3970 #define FSMC_PCR3_TCLR_3 0x00001000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3971
sahilmgandhi 18:6a4db94011d3 3972 #define FSMC_PCR3_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
sahilmgandhi 18:6a4db94011d3 3973 #define FSMC_PCR3_TAR_0 0x00002000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3974 #define FSMC_PCR3_TAR_1 0x00004000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3975 #define FSMC_PCR3_TAR_2 0x00008000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3976 #define FSMC_PCR3_TAR_3 0x00010000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3977
sahilmgandhi 18:6a4db94011d3 3978 #define FSMC_PCR3_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
sahilmgandhi 18:6a4db94011d3 3979 #define FSMC_PCR3_ECCPS_0 0x00020000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3980 #define FSMC_PCR3_ECCPS_1 0x00040000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3981 #define FSMC_PCR3_ECCPS_2 0x00080000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3982
sahilmgandhi 18:6a4db94011d3 3983 /****************** Bit definition for FSMC_PCR4 register *******************/
sahilmgandhi 18:6a4db94011d3 3984 #define FSMC_PCR4_PWAITEN 0x00000002U /*!<Wait feature enable bit */
sahilmgandhi 18:6a4db94011d3 3985 #define FSMC_PCR4_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 3986 #define FSMC_PCR4_PTYP 0x00000008U /*!<Memory type */
sahilmgandhi 18:6a4db94011d3 3987
sahilmgandhi 18:6a4db94011d3 3988 #define FSMC_PCR4_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
sahilmgandhi 18:6a4db94011d3 3989 #define FSMC_PCR4_PWID_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3990 #define FSMC_PCR4_PWID_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3991
sahilmgandhi 18:6a4db94011d3 3992 #define FSMC_PCR4_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
sahilmgandhi 18:6a4db94011d3 3993
sahilmgandhi 18:6a4db94011d3 3994 #define FSMC_PCR4_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
sahilmgandhi 18:6a4db94011d3 3995 #define FSMC_PCR4_TCLR_0 0x00000200U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 3996 #define FSMC_PCR4_TCLR_1 0x00000400U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 3997 #define FSMC_PCR4_TCLR_2 0x00000800U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 3998 #define FSMC_PCR4_TCLR_3 0x00001000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 3999
sahilmgandhi 18:6a4db94011d3 4000 #define FSMC_PCR4_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
sahilmgandhi 18:6a4db94011d3 4001 #define FSMC_PCR4_TAR_0 0x00002000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4002 #define FSMC_PCR4_TAR_1 0x00004000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4003 #define FSMC_PCR4_TAR_2 0x00008000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4004 #define FSMC_PCR4_TAR_3 0x00010000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4005
sahilmgandhi 18:6a4db94011d3 4006 #define FSMC_PCR4_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
sahilmgandhi 18:6a4db94011d3 4007 #define FSMC_PCR4_ECCPS_0 0x00020000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4008 #define FSMC_PCR4_ECCPS_1 0x00040000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4009 #define FSMC_PCR4_ECCPS_2 0x00080000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4010
sahilmgandhi 18:6a4db94011d3 4011 /******************* Bit definition for FSMC_SR2 register *******************/
sahilmgandhi 18:6a4db94011d3 4012 #define FSMC_SR2_IRS 0x01U /*!<Interrupt Rising Edge status */
sahilmgandhi 18:6a4db94011d3 4013 #define FSMC_SR2_ILS 0x02U /*!<Interrupt Level status */
sahilmgandhi 18:6a4db94011d3 4014 #define FSMC_SR2_IFS 0x04U /*!<Interrupt Falling Edge status */
sahilmgandhi 18:6a4db94011d3 4015 #define FSMC_SR2_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
sahilmgandhi 18:6a4db94011d3 4016 #define FSMC_SR2_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
sahilmgandhi 18:6a4db94011d3 4017 #define FSMC_SR2_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
sahilmgandhi 18:6a4db94011d3 4018 #define FSMC_SR2_FEMPT 0x40U /*!<FIFO empty */
sahilmgandhi 18:6a4db94011d3 4019
sahilmgandhi 18:6a4db94011d3 4020 /******************* Bit definition for FSMC_SR3 register *******************/
sahilmgandhi 18:6a4db94011d3 4021 #define FSMC_SR3_IRS 0x01U /*!<Interrupt Rising Edge status */
sahilmgandhi 18:6a4db94011d3 4022 #define FSMC_SR3_ILS 0x02U /*!<Interrupt Level status */
sahilmgandhi 18:6a4db94011d3 4023 #define FSMC_SR3_IFS 0x04U /*!<Interrupt Falling Edge status */
sahilmgandhi 18:6a4db94011d3 4024 #define FSMC_SR3_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
sahilmgandhi 18:6a4db94011d3 4025 #define FSMC_SR3_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
sahilmgandhi 18:6a4db94011d3 4026 #define FSMC_SR3_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
sahilmgandhi 18:6a4db94011d3 4027 #define FSMC_SR3_FEMPT 0x40U /*!<FIFO empty */
sahilmgandhi 18:6a4db94011d3 4028
sahilmgandhi 18:6a4db94011d3 4029 /******************* Bit definition for FSMC_SR4 register *******************/
sahilmgandhi 18:6a4db94011d3 4030 #define FSMC_SR4_IRS 0x01U /*!<Interrupt Rising Edge status */
sahilmgandhi 18:6a4db94011d3 4031 #define FSMC_SR4_ILS 0x02U /*!<Interrupt Level status */
sahilmgandhi 18:6a4db94011d3 4032 #define FSMC_SR4_IFS 0x04U /*!<Interrupt Falling Edge status */
sahilmgandhi 18:6a4db94011d3 4033 #define FSMC_SR4_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
sahilmgandhi 18:6a4db94011d3 4034 #define FSMC_SR4_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
sahilmgandhi 18:6a4db94011d3 4035 #define FSMC_SR4_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
sahilmgandhi 18:6a4db94011d3 4036 #define FSMC_SR4_FEMPT 0x40U /*!<FIFO empty */
sahilmgandhi 18:6a4db94011d3 4037
sahilmgandhi 18:6a4db94011d3 4038 /****************** Bit definition for FSMC_PMEM2 register ******************/
sahilmgandhi 18:6a4db94011d3 4039 #define FSMC_PMEM2_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
sahilmgandhi 18:6a4db94011d3 4040 #define FSMC_PMEM2_MEMSET2_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4041 #define FSMC_PMEM2_MEMSET2_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4042 #define FSMC_PMEM2_MEMSET2_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4043 #define FSMC_PMEM2_MEMSET2_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4044 #define FSMC_PMEM2_MEMSET2_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4045 #define FSMC_PMEM2_MEMSET2_5 0x00000020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4046 #define FSMC_PMEM2_MEMSET2_6 0x00000040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4047 #define FSMC_PMEM2_MEMSET2_7 0x00000080U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4048
sahilmgandhi 18:6a4db94011d3 4049 #define FSMC_PMEM2_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
sahilmgandhi 18:6a4db94011d3 4050 #define FSMC_PMEM2_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4051 #define FSMC_PMEM2_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4052 #define FSMC_PMEM2_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4053 #define FSMC_PMEM2_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4054 #define FSMC_PMEM2_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4055 #define FSMC_PMEM2_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4056 #define FSMC_PMEM2_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4057 #define FSMC_PMEM2_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4058
sahilmgandhi 18:6a4db94011d3 4059 #define FSMC_PMEM2_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
sahilmgandhi 18:6a4db94011d3 4060 #define FSMC_PMEM2_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4061 #define FSMC_PMEM2_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4062 #define FSMC_PMEM2_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4063 #define FSMC_PMEM2_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4064 #define FSMC_PMEM2_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4065 #define FSMC_PMEM2_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4066 #define FSMC_PMEM2_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4067 #define FSMC_PMEM2_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4068
sahilmgandhi 18:6a4db94011d3 4069 #define FSMC_PMEM2_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 4070 #define FSMC_PMEM2_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4071 #define FSMC_PMEM2_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4072 #define FSMC_PMEM2_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4073 #define FSMC_PMEM2_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4074 #define FSMC_PMEM2_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4075 #define FSMC_PMEM2_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4076 #define FSMC_PMEM2_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4077 #define FSMC_PMEM2_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4078
sahilmgandhi 18:6a4db94011d3 4079 /****************** Bit definition for FSMC_PMEM3 register ******************/
sahilmgandhi 18:6a4db94011d3 4080 #define FSMC_PMEM3_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
sahilmgandhi 18:6a4db94011d3 4081 #define FSMC_PMEM3_MEMSET3_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4082 #define FSMC_PMEM3_MEMSET3_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4083 #define FSMC_PMEM3_MEMSET3_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4084 #define FSMC_PMEM3_MEMSET3_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4085 #define FSMC_PMEM3_MEMSET3_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4086 #define FSMC_PMEM3_MEMSET3_5 0x00000020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4087 #define FSMC_PMEM3_MEMSET3_6 0x00000040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4088 #define FSMC_PMEM3_MEMSET3_7 0x00000080U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4089
sahilmgandhi 18:6a4db94011d3 4090 #define FSMC_PMEM3_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
sahilmgandhi 18:6a4db94011d3 4091 #define FSMC_PMEM3_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4092 #define FSMC_PMEM3_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4093 #define FSMC_PMEM3_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4094 #define FSMC_PMEM3_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4095 #define FSMC_PMEM3_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4096 #define FSMC_PMEM3_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4097 #define FSMC_PMEM3_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4098 #define FSMC_PMEM3_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4099
sahilmgandhi 18:6a4db94011d3 4100 #define FSMC_PMEM3_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
sahilmgandhi 18:6a4db94011d3 4101 #define FSMC_PMEM3_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4102 #define FSMC_PMEM3_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4103 #define FSMC_PMEM3_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4104 #define FSMC_PMEM3_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4105 #define FSMC_PMEM3_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4106 #define FSMC_PMEM3_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4107 #define FSMC_PMEM3_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4108 #define FSMC_PMEM3_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4109
sahilmgandhi 18:6a4db94011d3 4110 #define FSMC_PMEM3_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 4111 #define FSMC_PMEM3_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4112 #define FSMC_PMEM3_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4113 #define FSMC_PMEM3_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4114 #define FSMC_PMEM3_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4115 #define FSMC_PMEM3_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4116 #define FSMC_PMEM3_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4117 #define FSMC_PMEM3_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4118 #define FSMC_PMEM3_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4119
sahilmgandhi 18:6a4db94011d3 4120 /****************** Bit definition for FSMC_PMEM4 register ******************/
sahilmgandhi 18:6a4db94011d3 4121 #define FSMC_PMEM4_MEMSET4 0x000000FFU /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
sahilmgandhi 18:6a4db94011d3 4122 #define FSMC_PMEM4_MEMSET4_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4123 #define FSMC_PMEM4_MEMSET4_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4124 #define FSMC_PMEM4_MEMSET4_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4125 #define FSMC_PMEM4_MEMSET4_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4126 #define FSMC_PMEM4_MEMSET4_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4127 #define FSMC_PMEM4_MEMSET4_5 0x00000020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4128 #define FSMC_PMEM4_MEMSET4_6 0x00000040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4129 #define FSMC_PMEM4_MEMSET4_7 0x00000080U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4130
sahilmgandhi 18:6a4db94011d3 4131 #define FSMC_PMEM4_MEMWAIT4 0x0000FF00U /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
sahilmgandhi 18:6a4db94011d3 4132 #define FSMC_PMEM4_MEMWAIT4_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4133 #define FSMC_PMEM4_MEMWAIT4_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4134 #define FSMC_PMEM4_MEMWAIT4_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4135 #define FSMC_PMEM4_MEMWAIT4_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4136 #define FSMC_PMEM4_MEMWAIT4_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4137 #define FSMC_PMEM4_MEMWAIT4_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4138 #define FSMC_PMEM4_MEMWAIT4_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4139 #define FSMC_PMEM4_MEMWAIT4_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4140
sahilmgandhi 18:6a4db94011d3 4141 #define FSMC_PMEM4_MEMHOLD4 0x00FF0000U /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
sahilmgandhi 18:6a4db94011d3 4142 #define FSMC_PMEM4_MEMHOLD4_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4143 #define FSMC_PMEM4_MEMHOLD4_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4144 #define FSMC_PMEM4_MEMHOLD4_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4145 #define FSMC_PMEM4_MEMHOLD4_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4146 #define FSMC_PMEM4_MEMHOLD4_4 0x00100000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4147 #define FSMC_PMEM4_MEMHOLD4_5 0x00200000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4148 #define FSMC_PMEM4_MEMHOLD4_6 0x00400000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4149 #define FSMC_PMEM4_MEMHOLD4_7 0x00800000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4150
sahilmgandhi 18:6a4db94011d3 4151 #define FSMC_PMEM4_MEMHIZ4 0xFF000000U /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 4152 #define FSMC_PMEM4_MEMHIZ4_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4153 #define FSMC_PMEM4_MEMHIZ4_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4154 #define FSMC_PMEM4_MEMHIZ4_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4155 #define FSMC_PMEM4_MEMHIZ4_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4156 #define FSMC_PMEM4_MEMHIZ4_4 0x10000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4157 #define FSMC_PMEM4_MEMHIZ4_5 0x20000000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4158 #define FSMC_PMEM4_MEMHIZ4_6 0x40000000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4159 #define FSMC_PMEM4_MEMHIZ4_7 0x80000000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4160
sahilmgandhi 18:6a4db94011d3 4161 /****************** Bit definition for FSMC_PATT2 register ******************/
sahilmgandhi 18:6a4db94011d3 4162 #define FSMC_PATT2_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
sahilmgandhi 18:6a4db94011d3 4163 #define FSMC_PATT2_ATTSET2_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4164 #define FSMC_PATT2_ATTSET2_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4165 #define FSMC_PATT2_ATTSET2_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4166 #define FSMC_PATT2_ATTSET2_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4167 #define FSMC_PATT2_ATTSET2_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4168 #define FSMC_PATT2_ATTSET2_5 0x00000020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4169 #define FSMC_PATT2_ATTSET2_6 0x00000040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4170 #define FSMC_PATT2_ATTSET2_7 0x00000080U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4171
sahilmgandhi 18:6a4db94011d3 4172 #define FSMC_PATT2_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
sahilmgandhi 18:6a4db94011d3 4173 #define FSMC_PATT2_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4174 #define FSMC_PATT2_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4175 #define FSMC_PATT2_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4176 #define FSMC_PATT2_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4177 #define FSMC_PATT2_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4178 #define FSMC_PATT2_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4179 #define FSMC_PATT2_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4180 #define FSMC_PATT2_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4181
sahilmgandhi 18:6a4db94011d3 4182 #define FSMC_PATT2_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
sahilmgandhi 18:6a4db94011d3 4183 #define FSMC_PATT2_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4184 #define FSMC_PATT2_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4185 #define FSMC_PATT2_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4186 #define FSMC_PATT2_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4187 #define FSMC_PATT2_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4188 #define FSMC_PATT2_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4189 #define FSMC_PATT2_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4190 #define FSMC_PATT2_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4191
sahilmgandhi 18:6a4db94011d3 4192 #define FSMC_PATT2_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 4193 #define FSMC_PATT2_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4194 #define FSMC_PATT2_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4195 #define FSMC_PATT2_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4196 #define FSMC_PATT2_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4197 #define FSMC_PATT2_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4198 #define FSMC_PATT2_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4199 #define FSMC_PATT2_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4200 #define FSMC_PATT2_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4201
sahilmgandhi 18:6a4db94011d3 4202 /****************** Bit definition for FSMC_PATT3 register ******************/
sahilmgandhi 18:6a4db94011d3 4203 #define FSMC_PATT3_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
sahilmgandhi 18:6a4db94011d3 4204 #define FSMC_PATT3_ATTSET3_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4205 #define FSMC_PATT3_ATTSET3_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4206 #define FSMC_PATT3_ATTSET3_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4207 #define FSMC_PATT3_ATTSET3_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4208 #define FSMC_PATT3_ATTSET3_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4209 #define FSMC_PATT3_ATTSET3_5 0x00000020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4210 #define FSMC_PATT3_ATTSET3_6 0x00000040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4211 #define FSMC_PATT3_ATTSET3_7 0x00000080U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4212
sahilmgandhi 18:6a4db94011d3 4213 #define FSMC_PATT3_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
sahilmgandhi 18:6a4db94011d3 4214 #define FSMC_PATT3_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4215 #define FSMC_PATT3_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4216 #define FSMC_PATT3_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4217 #define FSMC_PATT3_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4218 #define FSMC_PATT3_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4219 #define FSMC_PATT3_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4220 #define FSMC_PATT3_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4221 #define FSMC_PATT3_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4222
sahilmgandhi 18:6a4db94011d3 4223 #define FSMC_PATT3_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
sahilmgandhi 18:6a4db94011d3 4224 #define FSMC_PATT3_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4225 #define FSMC_PATT3_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4226 #define FSMC_PATT3_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4227 #define FSMC_PATT3_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4228 #define FSMC_PATT3_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4229 #define FSMC_PATT3_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4230 #define FSMC_PATT3_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4231 #define FSMC_PATT3_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4232
sahilmgandhi 18:6a4db94011d3 4233 #define FSMC_PATT3_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 4234 #define FSMC_PATT3_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4235 #define FSMC_PATT3_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4236 #define FSMC_PATT3_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4237 #define FSMC_PATT3_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4238 #define FSMC_PATT3_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4239 #define FSMC_PATT3_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4240 #define FSMC_PATT3_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4241 #define FSMC_PATT3_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4242
sahilmgandhi 18:6a4db94011d3 4243 /****************** Bit definition for FSMC_PATT4 register ******************/
sahilmgandhi 18:6a4db94011d3 4244 #define FSMC_PATT4_ATTSET4 0x000000FFU /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
sahilmgandhi 18:6a4db94011d3 4245 #define FSMC_PATT4_ATTSET4_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4246 #define FSMC_PATT4_ATTSET4_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4247 #define FSMC_PATT4_ATTSET4_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4248 #define FSMC_PATT4_ATTSET4_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4249 #define FSMC_PATT4_ATTSET4_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4250 #define FSMC_PATT4_ATTSET4_5 0x00000020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4251 #define FSMC_PATT4_ATTSET4_6 0x00000040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4252 #define FSMC_PATT4_ATTSET4_7 0x00000080U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4253
sahilmgandhi 18:6a4db94011d3 4254 #define FSMC_PATT4_ATTWAIT4 0x0000FF00U /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
sahilmgandhi 18:6a4db94011d3 4255 #define FSMC_PATT4_ATTWAIT4_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4256 #define FSMC_PATT4_ATTWAIT4_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4257 #define FSMC_PATT4_ATTWAIT4_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4258 #define FSMC_PATT4_ATTWAIT4_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4259 #define FSMC_PATT4_ATTWAIT4_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4260 #define FSMC_PATT4_ATTWAIT4_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4261 #define FSMC_PATT4_ATTWAIT4_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4262 #define FSMC_PATT4_ATTWAIT4_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4263
sahilmgandhi 18:6a4db94011d3 4264 #define FSMC_PATT4_ATTHOLD4 0x00FF0000U /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
sahilmgandhi 18:6a4db94011d3 4265 #define FSMC_PATT4_ATTHOLD4_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4266 #define FSMC_PATT4_ATTHOLD4_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4267 #define FSMC_PATT4_ATTHOLD4_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4268 #define FSMC_PATT4_ATTHOLD4_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4269 #define FSMC_PATT4_ATTHOLD4_4 0x00100000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4270 #define FSMC_PATT4_ATTHOLD4_5 0x00200000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4271 #define FSMC_PATT4_ATTHOLD4_6 0x00400000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4272 #define FSMC_PATT4_ATTHOLD4_7 0x00800000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4273
sahilmgandhi 18:6a4db94011d3 4274 #define FSMC_PATT4_ATTHIZ4 0xFF000000U /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 4275 #define FSMC_PATT4_ATTHIZ4_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4276 #define FSMC_PATT4_ATTHIZ4_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4277 #define FSMC_PATT4_ATTHIZ4_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4278 #define FSMC_PATT4_ATTHIZ4_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4279 #define FSMC_PATT4_ATTHIZ4_4 0x10000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4280 #define FSMC_PATT4_ATTHIZ4_5 0x20000000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4281 #define FSMC_PATT4_ATTHIZ4_6 0x40000000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4282 #define FSMC_PATT4_ATTHIZ4_7 0x80000000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4283
sahilmgandhi 18:6a4db94011d3 4284 /****************** Bit definition for FSMC_PIO4 register *******************/
sahilmgandhi 18:6a4db94011d3 4285 #define FSMC_PIO4_IOSET4 0x000000FFU /*!<IOSET4[7:0] bits (I/O 4 setup time) */
sahilmgandhi 18:6a4db94011d3 4286 #define FSMC_PIO4_IOSET4_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4287 #define FSMC_PIO4_IOSET4_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4288 #define FSMC_PIO4_IOSET4_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4289 #define FSMC_PIO4_IOSET4_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4290 #define FSMC_PIO4_IOSET4_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4291 #define FSMC_PIO4_IOSET4_5 0x00000020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4292 #define FSMC_PIO4_IOSET4_6 0x00000040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4293 #define FSMC_PIO4_IOSET4_7 0x00000080U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4294
sahilmgandhi 18:6a4db94011d3 4295 #define FSMC_PIO4_IOWAIT4 0x0000FF00U /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
sahilmgandhi 18:6a4db94011d3 4296 #define FSMC_PIO4_IOWAIT4_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4297 #define FSMC_PIO4_IOWAIT4_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4298 #define FSMC_PIO4_IOWAIT4_2 0x00000400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4299 #define FSMC_PIO4_IOWAIT4_3 0x00000800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4300 #define FSMC_PIO4_IOWAIT4_4 0x00001000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4301 #define FSMC_PIO4_IOWAIT4_5 0x00002000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4302 #define FSMC_PIO4_IOWAIT4_6 0x00004000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4303 #define FSMC_PIO4_IOWAIT4_7 0x00008000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4304
sahilmgandhi 18:6a4db94011d3 4305 #define FSMC_PIO4_IOHOLD4 0x00FF0000U /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
sahilmgandhi 18:6a4db94011d3 4306 #define FSMC_PIO4_IOHOLD4_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4307 #define FSMC_PIO4_IOHOLD4_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4308 #define FSMC_PIO4_IOHOLD4_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4309 #define FSMC_PIO4_IOHOLD4_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4310 #define FSMC_PIO4_IOHOLD4_4 0x00100000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4311 #define FSMC_PIO4_IOHOLD4_5 0x00200000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4312 #define FSMC_PIO4_IOHOLD4_6 0x00400000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4313 #define FSMC_PIO4_IOHOLD4_7 0x00800000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4314
sahilmgandhi 18:6a4db94011d3 4315 #define FSMC_PIO4_IOHIZ4 0xFF000000U /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 4316 #define FSMC_PIO4_IOHIZ4_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4317 #define FSMC_PIO4_IOHIZ4_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4318 #define FSMC_PIO4_IOHIZ4_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4319 #define FSMC_PIO4_IOHIZ4_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4320 #define FSMC_PIO4_IOHIZ4_4 0x10000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4321 #define FSMC_PIO4_IOHIZ4_5 0x20000000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4322 #define FSMC_PIO4_IOHIZ4_6 0x40000000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4323 #define FSMC_PIO4_IOHIZ4_7 0x80000000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4324
sahilmgandhi 18:6a4db94011d3 4325 /****************** Bit definition for FSMC_ECCR2 register ******************/
sahilmgandhi 18:6a4db94011d3 4326 #define FSMC_ECCR2_ECC2 0xFFFFFFFFU /*!<ECC result */
sahilmgandhi 18:6a4db94011d3 4327
sahilmgandhi 18:6a4db94011d3 4328 /****************** Bit definition for FSMC_ECCR3 register ******************/
sahilmgandhi 18:6a4db94011d3 4329 #define FSMC_ECCR3_ECC3 0xFFFFFFFFU /*!<ECC result */
sahilmgandhi 18:6a4db94011d3 4330
sahilmgandhi 18:6a4db94011d3 4331 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4332 /* */
sahilmgandhi 18:6a4db94011d3 4333 /* General Purpose I/O */
sahilmgandhi 18:6a4db94011d3 4334 /* */
sahilmgandhi 18:6a4db94011d3 4335 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4336 /****************** Bits definition for GPIO_MODER register *****************/
sahilmgandhi 18:6a4db94011d3 4337 #define GPIO_MODER_MODER0 0x00000003U
sahilmgandhi 18:6a4db94011d3 4338 #define GPIO_MODER_MODER0_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 4339 #define GPIO_MODER_MODER0_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 4340
sahilmgandhi 18:6a4db94011d3 4341 #define GPIO_MODER_MODER1 0x0000000CU
sahilmgandhi 18:6a4db94011d3 4342 #define GPIO_MODER_MODER1_0 0x00000004U
sahilmgandhi 18:6a4db94011d3 4343 #define GPIO_MODER_MODER1_1 0x00000008U
sahilmgandhi 18:6a4db94011d3 4344
sahilmgandhi 18:6a4db94011d3 4345 #define GPIO_MODER_MODER2 0x00000030U
sahilmgandhi 18:6a4db94011d3 4346 #define GPIO_MODER_MODER2_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 4347 #define GPIO_MODER_MODER2_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 4348
sahilmgandhi 18:6a4db94011d3 4349 #define GPIO_MODER_MODER3 0x000000C0U
sahilmgandhi 18:6a4db94011d3 4350 #define GPIO_MODER_MODER3_0 0x00000040U
sahilmgandhi 18:6a4db94011d3 4351 #define GPIO_MODER_MODER3_1 0x00000080U
sahilmgandhi 18:6a4db94011d3 4352
sahilmgandhi 18:6a4db94011d3 4353 #define GPIO_MODER_MODER4 0x00000300U
sahilmgandhi 18:6a4db94011d3 4354 #define GPIO_MODER_MODER4_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 4355 #define GPIO_MODER_MODER4_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 4356
sahilmgandhi 18:6a4db94011d3 4357 #define GPIO_MODER_MODER5 0x00000C00U
sahilmgandhi 18:6a4db94011d3 4358 #define GPIO_MODER_MODER5_0 0x00000400U
sahilmgandhi 18:6a4db94011d3 4359 #define GPIO_MODER_MODER5_1 0x00000800U
sahilmgandhi 18:6a4db94011d3 4360
sahilmgandhi 18:6a4db94011d3 4361 #define GPIO_MODER_MODER6 0x00003000U
sahilmgandhi 18:6a4db94011d3 4362 #define GPIO_MODER_MODER6_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 4363 #define GPIO_MODER_MODER6_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 4364
sahilmgandhi 18:6a4db94011d3 4365 #define GPIO_MODER_MODER7 0x0000C000U
sahilmgandhi 18:6a4db94011d3 4366 #define GPIO_MODER_MODER7_0 0x00004000U
sahilmgandhi 18:6a4db94011d3 4367 #define GPIO_MODER_MODER7_1 0x00008000U
sahilmgandhi 18:6a4db94011d3 4368
sahilmgandhi 18:6a4db94011d3 4369 #define GPIO_MODER_MODER8 0x00030000U
sahilmgandhi 18:6a4db94011d3 4370 #define GPIO_MODER_MODER8_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 4371 #define GPIO_MODER_MODER8_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 4372
sahilmgandhi 18:6a4db94011d3 4373 #define GPIO_MODER_MODER9 0x000C0000U
sahilmgandhi 18:6a4db94011d3 4374 #define GPIO_MODER_MODER9_0 0x00040000U
sahilmgandhi 18:6a4db94011d3 4375 #define GPIO_MODER_MODER9_1 0x00080000U
sahilmgandhi 18:6a4db94011d3 4376
sahilmgandhi 18:6a4db94011d3 4377 #define GPIO_MODER_MODER10 0x00300000U
sahilmgandhi 18:6a4db94011d3 4378 #define GPIO_MODER_MODER10_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 4379 #define GPIO_MODER_MODER10_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 4380
sahilmgandhi 18:6a4db94011d3 4381 #define GPIO_MODER_MODER11 0x00C00000U
sahilmgandhi 18:6a4db94011d3 4382 #define GPIO_MODER_MODER11_0 0x00400000U
sahilmgandhi 18:6a4db94011d3 4383 #define GPIO_MODER_MODER11_1 0x00800000U
sahilmgandhi 18:6a4db94011d3 4384
sahilmgandhi 18:6a4db94011d3 4385 #define GPIO_MODER_MODER12 0x03000000U
sahilmgandhi 18:6a4db94011d3 4386 #define GPIO_MODER_MODER12_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 4387 #define GPIO_MODER_MODER12_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 4388
sahilmgandhi 18:6a4db94011d3 4389 #define GPIO_MODER_MODER13 0x0C000000U
sahilmgandhi 18:6a4db94011d3 4390 #define GPIO_MODER_MODER13_0 0x04000000U
sahilmgandhi 18:6a4db94011d3 4391 #define GPIO_MODER_MODER13_1 0x08000000U
sahilmgandhi 18:6a4db94011d3 4392
sahilmgandhi 18:6a4db94011d3 4393 #define GPIO_MODER_MODER14 0x30000000U
sahilmgandhi 18:6a4db94011d3 4394 #define GPIO_MODER_MODER14_0 0x10000000U
sahilmgandhi 18:6a4db94011d3 4395 #define GPIO_MODER_MODER14_1 0x20000000U
sahilmgandhi 18:6a4db94011d3 4396
sahilmgandhi 18:6a4db94011d3 4397 #define GPIO_MODER_MODER15 0xC0000000U
sahilmgandhi 18:6a4db94011d3 4398 #define GPIO_MODER_MODER15_0 0x40000000U
sahilmgandhi 18:6a4db94011d3 4399 #define GPIO_MODER_MODER15_1 0x80000000U
sahilmgandhi 18:6a4db94011d3 4400
sahilmgandhi 18:6a4db94011d3 4401 /****************** Bits definition for GPIO_OTYPER register ****************/
sahilmgandhi 18:6a4db94011d3 4402 #define GPIO_OTYPER_OT_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 4403 #define GPIO_OTYPER_OT_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 4404 #define GPIO_OTYPER_OT_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 4405 #define GPIO_OTYPER_OT_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 4406 #define GPIO_OTYPER_OT_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 4407 #define GPIO_OTYPER_OT_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 4408 #define GPIO_OTYPER_OT_6 0x00000040U
sahilmgandhi 18:6a4db94011d3 4409 #define GPIO_OTYPER_OT_7 0x00000080U
sahilmgandhi 18:6a4db94011d3 4410 #define GPIO_OTYPER_OT_8 0x00000100U
sahilmgandhi 18:6a4db94011d3 4411 #define GPIO_OTYPER_OT_9 0x00000200U
sahilmgandhi 18:6a4db94011d3 4412 #define GPIO_OTYPER_OT_10 0x00000400U
sahilmgandhi 18:6a4db94011d3 4413 #define GPIO_OTYPER_OT_11 0x00000800U
sahilmgandhi 18:6a4db94011d3 4414 #define GPIO_OTYPER_OT_12 0x00001000U
sahilmgandhi 18:6a4db94011d3 4415 #define GPIO_OTYPER_OT_13 0x00002000U
sahilmgandhi 18:6a4db94011d3 4416 #define GPIO_OTYPER_OT_14 0x00004000U
sahilmgandhi 18:6a4db94011d3 4417 #define GPIO_OTYPER_OT_15 0x00008000U
sahilmgandhi 18:6a4db94011d3 4418
sahilmgandhi 18:6a4db94011d3 4419 /****************** Bits definition for GPIO_OSPEEDR register ***************/
sahilmgandhi 18:6a4db94011d3 4420 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
sahilmgandhi 18:6a4db94011d3 4421 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 4422 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 4423
sahilmgandhi 18:6a4db94011d3 4424 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
sahilmgandhi 18:6a4db94011d3 4425 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
sahilmgandhi 18:6a4db94011d3 4426 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
sahilmgandhi 18:6a4db94011d3 4427
sahilmgandhi 18:6a4db94011d3 4428 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
sahilmgandhi 18:6a4db94011d3 4429 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 4430 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 4431
sahilmgandhi 18:6a4db94011d3 4432 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
sahilmgandhi 18:6a4db94011d3 4433 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
sahilmgandhi 18:6a4db94011d3 4434 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
sahilmgandhi 18:6a4db94011d3 4435
sahilmgandhi 18:6a4db94011d3 4436 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
sahilmgandhi 18:6a4db94011d3 4437 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 4438 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 4439
sahilmgandhi 18:6a4db94011d3 4440 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
sahilmgandhi 18:6a4db94011d3 4441 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
sahilmgandhi 18:6a4db94011d3 4442 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
sahilmgandhi 18:6a4db94011d3 4443
sahilmgandhi 18:6a4db94011d3 4444 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
sahilmgandhi 18:6a4db94011d3 4445 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 4446 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 4447
sahilmgandhi 18:6a4db94011d3 4448 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
sahilmgandhi 18:6a4db94011d3 4449 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
sahilmgandhi 18:6a4db94011d3 4450 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
sahilmgandhi 18:6a4db94011d3 4451
sahilmgandhi 18:6a4db94011d3 4452 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
sahilmgandhi 18:6a4db94011d3 4453 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 4454 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 4455
sahilmgandhi 18:6a4db94011d3 4456 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
sahilmgandhi 18:6a4db94011d3 4457 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
sahilmgandhi 18:6a4db94011d3 4458 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
sahilmgandhi 18:6a4db94011d3 4459
sahilmgandhi 18:6a4db94011d3 4460 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
sahilmgandhi 18:6a4db94011d3 4461 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 4462 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 4463
sahilmgandhi 18:6a4db94011d3 4464 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
sahilmgandhi 18:6a4db94011d3 4465 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
sahilmgandhi 18:6a4db94011d3 4466 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
sahilmgandhi 18:6a4db94011d3 4467
sahilmgandhi 18:6a4db94011d3 4468 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
sahilmgandhi 18:6a4db94011d3 4469 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 4470 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 4471
sahilmgandhi 18:6a4db94011d3 4472 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
sahilmgandhi 18:6a4db94011d3 4473 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
sahilmgandhi 18:6a4db94011d3 4474 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
sahilmgandhi 18:6a4db94011d3 4475
sahilmgandhi 18:6a4db94011d3 4476 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
sahilmgandhi 18:6a4db94011d3 4477 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
sahilmgandhi 18:6a4db94011d3 4478 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
sahilmgandhi 18:6a4db94011d3 4479
sahilmgandhi 18:6a4db94011d3 4480 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
sahilmgandhi 18:6a4db94011d3 4481 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
sahilmgandhi 18:6a4db94011d3 4482 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
sahilmgandhi 18:6a4db94011d3 4483
sahilmgandhi 18:6a4db94011d3 4484 /****************** Bits definition for GPIO_PUPDR register *****************/
sahilmgandhi 18:6a4db94011d3 4485 #define GPIO_PUPDR_PUPDR0 0x00000003U
sahilmgandhi 18:6a4db94011d3 4486 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 4487 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 4488
sahilmgandhi 18:6a4db94011d3 4489 #define GPIO_PUPDR_PUPDR1 0x0000000CU
sahilmgandhi 18:6a4db94011d3 4490 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
sahilmgandhi 18:6a4db94011d3 4491 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
sahilmgandhi 18:6a4db94011d3 4492
sahilmgandhi 18:6a4db94011d3 4493 #define GPIO_PUPDR_PUPDR2 0x00000030U
sahilmgandhi 18:6a4db94011d3 4494 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 4495 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 4496
sahilmgandhi 18:6a4db94011d3 4497 #define GPIO_PUPDR_PUPDR3 0x000000C0U
sahilmgandhi 18:6a4db94011d3 4498 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
sahilmgandhi 18:6a4db94011d3 4499 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
sahilmgandhi 18:6a4db94011d3 4500
sahilmgandhi 18:6a4db94011d3 4501 #define GPIO_PUPDR_PUPDR4 0x00000300U
sahilmgandhi 18:6a4db94011d3 4502 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 4503 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 4504
sahilmgandhi 18:6a4db94011d3 4505 #define GPIO_PUPDR_PUPDR5 0x00000C00U
sahilmgandhi 18:6a4db94011d3 4506 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
sahilmgandhi 18:6a4db94011d3 4507 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
sahilmgandhi 18:6a4db94011d3 4508
sahilmgandhi 18:6a4db94011d3 4509 #define GPIO_PUPDR_PUPDR6 0x00003000U
sahilmgandhi 18:6a4db94011d3 4510 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 4511 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 4512
sahilmgandhi 18:6a4db94011d3 4513 #define GPIO_PUPDR_PUPDR7 0x0000C000U
sahilmgandhi 18:6a4db94011d3 4514 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
sahilmgandhi 18:6a4db94011d3 4515 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
sahilmgandhi 18:6a4db94011d3 4516
sahilmgandhi 18:6a4db94011d3 4517 #define GPIO_PUPDR_PUPDR8 0x00030000U
sahilmgandhi 18:6a4db94011d3 4518 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 4519 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 4520
sahilmgandhi 18:6a4db94011d3 4521 #define GPIO_PUPDR_PUPDR9 0x000C0000U
sahilmgandhi 18:6a4db94011d3 4522 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
sahilmgandhi 18:6a4db94011d3 4523 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
sahilmgandhi 18:6a4db94011d3 4524
sahilmgandhi 18:6a4db94011d3 4525 #define GPIO_PUPDR_PUPDR10 0x00300000U
sahilmgandhi 18:6a4db94011d3 4526 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 4527 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 4528
sahilmgandhi 18:6a4db94011d3 4529 #define GPIO_PUPDR_PUPDR11 0x00C00000U
sahilmgandhi 18:6a4db94011d3 4530 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
sahilmgandhi 18:6a4db94011d3 4531 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
sahilmgandhi 18:6a4db94011d3 4532
sahilmgandhi 18:6a4db94011d3 4533 #define GPIO_PUPDR_PUPDR12 0x03000000U
sahilmgandhi 18:6a4db94011d3 4534 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 4535 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 4536
sahilmgandhi 18:6a4db94011d3 4537 #define GPIO_PUPDR_PUPDR13 0x0C000000U
sahilmgandhi 18:6a4db94011d3 4538 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
sahilmgandhi 18:6a4db94011d3 4539 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
sahilmgandhi 18:6a4db94011d3 4540
sahilmgandhi 18:6a4db94011d3 4541 #define GPIO_PUPDR_PUPDR14 0x30000000U
sahilmgandhi 18:6a4db94011d3 4542 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
sahilmgandhi 18:6a4db94011d3 4543 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
sahilmgandhi 18:6a4db94011d3 4544
sahilmgandhi 18:6a4db94011d3 4545 #define GPIO_PUPDR_PUPDR15 0xC0000000U
sahilmgandhi 18:6a4db94011d3 4546 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
sahilmgandhi 18:6a4db94011d3 4547 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
sahilmgandhi 18:6a4db94011d3 4548
sahilmgandhi 18:6a4db94011d3 4549 /****************** Bits definition for GPIO_IDR register *******************/
sahilmgandhi 18:6a4db94011d3 4550 #define GPIO_IDR_IDR_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 4551 #define GPIO_IDR_IDR_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 4552 #define GPIO_IDR_IDR_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 4553 #define GPIO_IDR_IDR_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 4554 #define GPIO_IDR_IDR_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 4555 #define GPIO_IDR_IDR_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 4556 #define GPIO_IDR_IDR_6 0x00000040U
sahilmgandhi 18:6a4db94011d3 4557 #define GPIO_IDR_IDR_7 0x00000080U
sahilmgandhi 18:6a4db94011d3 4558 #define GPIO_IDR_IDR_8 0x00000100U
sahilmgandhi 18:6a4db94011d3 4559 #define GPIO_IDR_IDR_9 0x00000200U
sahilmgandhi 18:6a4db94011d3 4560 #define GPIO_IDR_IDR_10 0x00000400U
sahilmgandhi 18:6a4db94011d3 4561 #define GPIO_IDR_IDR_11 0x00000800U
sahilmgandhi 18:6a4db94011d3 4562 #define GPIO_IDR_IDR_12 0x00001000U
sahilmgandhi 18:6a4db94011d3 4563 #define GPIO_IDR_IDR_13 0x00002000U
sahilmgandhi 18:6a4db94011d3 4564 #define GPIO_IDR_IDR_14 0x00004000U
sahilmgandhi 18:6a4db94011d3 4565 #define GPIO_IDR_IDR_15 0x00008000U
sahilmgandhi 18:6a4db94011d3 4566 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 4567 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
sahilmgandhi 18:6a4db94011d3 4568 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
sahilmgandhi 18:6a4db94011d3 4569 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
sahilmgandhi 18:6a4db94011d3 4570 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
sahilmgandhi 18:6a4db94011d3 4571 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
sahilmgandhi 18:6a4db94011d3 4572 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
sahilmgandhi 18:6a4db94011d3 4573 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
sahilmgandhi 18:6a4db94011d3 4574 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
sahilmgandhi 18:6a4db94011d3 4575 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
sahilmgandhi 18:6a4db94011d3 4576 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
sahilmgandhi 18:6a4db94011d3 4577 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
sahilmgandhi 18:6a4db94011d3 4578 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
sahilmgandhi 18:6a4db94011d3 4579 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
sahilmgandhi 18:6a4db94011d3 4580 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
sahilmgandhi 18:6a4db94011d3 4581 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
sahilmgandhi 18:6a4db94011d3 4582 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
sahilmgandhi 18:6a4db94011d3 4583
sahilmgandhi 18:6a4db94011d3 4584 /****************** Bits definition for GPIO_ODR register *******************/
sahilmgandhi 18:6a4db94011d3 4585 #define GPIO_ODR_ODR_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 4586 #define GPIO_ODR_ODR_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 4587 #define GPIO_ODR_ODR_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 4588 #define GPIO_ODR_ODR_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 4589 #define GPIO_ODR_ODR_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 4590 #define GPIO_ODR_ODR_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 4591 #define GPIO_ODR_ODR_6 0x00000040U
sahilmgandhi 18:6a4db94011d3 4592 #define GPIO_ODR_ODR_7 0x00000080U
sahilmgandhi 18:6a4db94011d3 4593 #define GPIO_ODR_ODR_8 0x00000100U
sahilmgandhi 18:6a4db94011d3 4594 #define GPIO_ODR_ODR_9 0x00000200U
sahilmgandhi 18:6a4db94011d3 4595 #define GPIO_ODR_ODR_10 0x00000400U
sahilmgandhi 18:6a4db94011d3 4596 #define GPIO_ODR_ODR_11 0x00000800U
sahilmgandhi 18:6a4db94011d3 4597 #define GPIO_ODR_ODR_12 0x00001000U
sahilmgandhi 18:6a4db94011d3 4598 #define GPIO_ODR_ODR_13 0x00002000U
sahilmgandhi 18:6a4db94011d3 4599 #define GPIO_ODR_ODR_14 0x00004000U
sahilmgandhi 18:6a4db94011d3 4600 #define GPIO_ODR_ODR_15 0x00008000U
sahilmgandhi 18:6a4db94011d3 4601 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 4602 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
sahilmgandhi 18:6a4db94011d3 4603 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
sahilmgandhi 18:6a4db94011d3 4604 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
sahilmgandhi 18:6a4db94011d3 4605 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
sahilmgandhi 18:6a4db94011d3 4606 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
sahilmgandhi 18:6a4db94011d3 4607 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
sahilmgandhi 18:6a4db94011d3 4608 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
sahilmgandhi 18:6a4db94011d3 4609 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
sahilmgandhi 18:6a4db94011d3 4610 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
sahilmgandhi 18:6a4db94011d3 4611 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
sahilmgandhi 18:6a4db94011d3 4612 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
sahilmgandhi 18:6a4db94011d3 4613 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
sahilmgandhi 18:6a4db94011d3 4614 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
sahilmgandhi 18:6a4db94011d3 4615 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
sahilmgandhi 18:6a4db94011d3 4616 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
sahilmgandhi 18:6a4db94011d3 4617 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
sahilmgandhi 18:6a4db94011d3 4618
sahilmgandhi 18:6a4db94011d3 4619 /****************** Bits definition for GPIO_BSRR register ******************/
sahilmgandhi 18:6a4db94011d3 4620 #define GPIO_BSRR_BS_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 4621 #define GPIO_BSRR_BS_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 4622 #define GPIO_BSRR_BS_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 4623 #define GPIO_BSRR_BS_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 4624 #define GPIO_BSRR_BS_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 4625 #define GPIO_BSRR_BS_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 4626 #define GPIO_BSRR_BS_6 0x00000040U
sahilmgandhi 18:6a4db94011d3 4627 #define GPIO_BSRR_BS_7 0x00000080U
sahilmgandhi 18:6a4db94011d3 4628 #define GPIO_BSRR_BS_8 0x00000100U
sahilmgandhi 18:6a4db94011d3 4629 #define GPIO_BSRR_BS_9 0x00000200U
sahilmgandhi 18:6a4db94011d3 4630 #define GPIO_BSRR_BS_10 0x00000400U
sahilmgandhi 18:6a4db94011d3 4631 #define GPIO_BSRR_BS_11 0x00000800U
sahilmgandhi 18:6a4db94011d3 4632 #define GPIO_BSRR_BS_12 0x00001000U
sahilmgandhi 18:6a4db94011d3 4633 #define GPIO_BSRR_BS_13 0x00002000U
sahilmgandhi 18:6a4db94011d3 4634 #define GPIO_BSRR_BS_14 0x00004000U
sahilmgandhi 18:6a4db94011d3 4635 #define GPIO_BSRR_BS_15 0x00008000U
sahilmgandhi 18:6a4db94011d3 4636 #define GPIO_BSRR_BR_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 4637 #define GPIO_BSRR_BR_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 4638 #define GPIO_BSRR_BR_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 4639 #define GPIO_BSRR_BR_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 4640 #define GPIO_BSRR_BR_4 0x00100000U
sahilmgandhi 18:6a4db94011d3 4641 #define GPIO_BSRR_BR_5 0x00200000U
sahilmgandhi 18:6a4db94011d3 4642 #define GPIO_BSRR_BR_6 0x00400000U
sahilmgandhi 18:6a4db94011d3 4643 #define GPIO_BSRR_BR_7 0x00800000U
sahilmgandhi 18:6a4db94011d3 4644 #define GPIO_BSRR_BR_8 0x01000000U
sahilmgandhi 18:6a4db94011d3 4645 #define GPIO_BSRR_BR_9 0x02000000U
sahilmgandhi 18:6a4db94011d3 4646 #define GPIO_BSRR_BR_10 0x04000000U
sahilmgandhi 18:6a4db94011d3 4647 #define GPIO_BSRR_BR_11 0x08000000U
sahilmgandhi 18:6a4db94011d3 4648 #define GPIO_BSRR_BR_12 0x10000000U
sahilmgandhi 18:6a4db94011d3 4649 #define GPIO_BSRR_BR_13 0x20000000U
sahilmgandhi 18:6a4db94011d3 4650 #define GPIO_BSRR_BR_14 0x40000000U
sahilmgandhi 18:6a4db94011d3 4651 #define GPIO_BSRR_BR_15 0x80000000U
sahilmgandhi 18:6a4db94011d3 4652
sahilmgandhi 18:6a4db94011d3 4653 /****************** Bit definition for GPIO_LCKR register *********************/
sahilmgandhi 18:6a4db94011d3 4654 #define GPIO_LCKR_LCK0 0x00000001U
sahilmgandhi 18:6a4db94011d3 4655 #define GPIO_LCKR_LCK1 0x00000002U
sahilmgandhi 18:6a4db94011d3 4656 #define GPIO_LCKR_LCK2 0x00000004U
sahilmgandhi 18:6a4db94011d3 4657 #define GPIO_LCKR_LCK3 0x00000008U
sahilmgandhi 18:6a4db94011d3 4658 #define GPIO_LCKR_LCK4 0x00000010U
sahilmgandhi 18:6a4db94011d3 4659 #define GPIO_LCKR_LCK5 0x00000020U
sahilmgandhi 18:6a4db94011d3 4660 #define GPIO_LCKR_LCK6 0x00000040U
sahilmgandhi 18:6a4db94011d3 4661 #define GPIO_LCKR_LCK7 0x00000080U
sahilmgandhi 18:6a4db94011d3 4662 #define GPIO_LCKR_LCK8 0x00000100U
sahilmgandhi 18:6a4db94011d3 4663 #define GPIO_LCKR_LCK9 0x00000200U
sahilmgandhi 18:6a4db94011d3 4664 #define GPIO_LCKR_LCK10 0x00000400U
sahilmgandhi 18:6a4db94011d3 4665 #define GPIO_LCKR_LCK11 0x00000800U
sahilmgandhi 18:6a4db94011d3 4666 #define GPIO_LCKR_LCK12 0x00001000U
sahilmgandhi 18:6a4db94011d3 4667 #define GPIO_LCKR_LCK13 0x00002000U
sahilmgandhi 18:6a4db94011d3 4668 #define GPIO_LCKR_LCK14 0x00004000U
sahilmgandhi 18:6a4db94011d3 4669 #define GPIO_LCKR_LCK15 0x00008000U
sahilmgandhi 18:6a4db94011d3 4670 #define GPIO_LCKR_LCKK 0x00010000U
sahilmgandhi 18:6a4db94011d3 4671
sahilmgandhi 18:6a4db94011d3 4672 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4673 /* */
sahilmgandhi 18:6a4db94011d3 4674 /* Inter-integrated Circuit Interface */
sahilmgandhi 18:6a4db94011d3 4675 /* */
sahilmgandhi 18:6a4db94011d3 4676 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4677 /******************* Bit definition for I2C_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 4678 #define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
sahilmgandhi 18:6a4db94011d3 4679 #define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
sahilmgandhi 18:6a4db94011d3 4680 #define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
sahilmgandhi 18:6a4db94011d3 4681 #define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
sahilmgandhi 18:6a4db94011d3 4682 #define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
sahilmgandhi 18:6a4db94011d3 4683 #define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
sahilmgandhi 18:6a4db94011d3 4684 #define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
sahilmgandhi 18:6a4db94011d3 4685 #define I2C_CR1_START 0x00000100U /*!<Start Generation */
sahilmgandhi 18:6a4db94011d3 4686 #define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
sahilmgandhi 18:6a4db94011d3 4687 #define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
sahilmgandhi 18:6a4db94011d3 4688 #define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
sahilmgandhi 18:6a4db94011d3 4689 #define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
sahilmgandhi 18:6a4db94011d3 4690 #define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
sahilmgandhi 18:6a4db94011d3 4691 #define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
sahilmgandhi 18:6a4db94011d3 4692
sahilmgandhi 18:6a4db94011d3 4693 /******************* Bit definition for I2C_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 4694 #define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
sahilmgandhi 18:6a4db94011d3 4695 #define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4696 #define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4697 #define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4698 #define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4699 #define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4700 #define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4701
sahilmgandhi 18:6a4db94011d3 4702 #define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4703 #define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4704 #define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4705 #define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
sahilmgandhi 18:6a4db94011d3 4706 #define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
sahilmgandhi 18:6a4db94011d3 4707
sahilmgandhi 18:6a4db94011d3 4708 /******************* Bit definition for I2C_OAR1 register *******************/
sahilmgandhi 18:6a4db94011d3 4709 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
sahilmgandhi 18:6a4db94011d3 4710 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
sahilmgandhi 18:6a4db94011d3 4711
sahilmgandhi 18:6a4db94011d3 4712 #define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4713 #define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4714 #define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4715 #define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4716 #define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4717 #define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4718 #define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4719 #define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4720 #define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
sahilmgandhi 18:6a4db94011d3 4721 #define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
sahilmgandhi 18:6a4db94011d3 4722
sahilmgandhi 18:6a4db94011d3 4723 #define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
sahilmgandhi 18:6a4db94011d3 4724
sahilmgandhi 18:6a4db94011d3 4725 /******************* Bit definition for I2C_OAR2 register *******************/
sahilmgandhi 18:6a4db94011d3 4726 #define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
sahilmgandhi 18:6a4db94011d3 4727 #define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
sahilmgandhi 18:6a4db94011d3 4728
sahilmgandhi 18:6a4db94011d3 4729 /******************** Bit definition for I2C_DR register ********************/
sahilmgandhi 18:6a4db94011d3 4730 #define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
sahilmgandhi 18:6a4db94011d3 4731
sahilmgandhi 18:6a4db94011d3 4732 /******************* Bit definition for I2C_SR1 register ********************/
sahilmgandhi 18:6a4db94011d3 4733 #define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
sahilmgandhi 18:6a4db94011d3 4734 #define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
sahilmgandhi 18:6a4db94011d3 4735 #define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
sahilmgandhi 18:6a4db94011d3 4736 #define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
sahilmgandhi 18:6a4db94011d3 4737 #define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
sahilmgandhi 18:6a4db94011d3 4738 #define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
sahilmgandhi 18:6a4db94011d3 4739 #define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
sahilmgandhi 18:6a4db94011d3 4740 #define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
sahilmgandhi 18:6a4db94011d3 4741 #define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
sahilmgandhi 18:6a4db94011d3 4742 #define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
sahilmgandhi 18:6a4db94011d3 4743 #define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
sahilmgandhi 18:6a4db94011d3 4744 #define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
sahilmgandhi 18:6a4db94011d3 4745 #define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
sahilmgandhi 18:6a4db94011d3 4746 #define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
sahilmgandhi 18:6a4db94011d3 4747
sahilmgandhi 18:6a4db94011d3 4748 /******************* Bit definition for I2C_SR2 register ********************/
sahilmgandhi 18:6a4db94011d3 4749 #define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
sahilmgandhi 18:6a4db94011d3 4750 #define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
sahilmgandhi 18:6a4db94011d3 4751 #define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
sahilmgandhi 18:6a4db94011d3 4752 #define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
sahilmgandhi 18:6a4db94011d3 4753 #define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
sahilmgandhi 18:6a4db94011d3 4754 #define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
sahilmgandhi 18:6a4db94011d3 4755 #define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
sahilmgandhi 18:6a4db94011d3 4756 #define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
sahilmgandhi 18:6a4db94011d3 4757
sahilmgandhi 18:6a4db94011d3 4758 /******************* Bit definition for I2C_CCR register ********************/
sahilmgandhi 18:6a4db94011d3 4759 #define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
sahilmgandhi 18:6a4db94011d3 4760 #define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
sahilmgandhi 18:6a4db94011d3 4761 #define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
sahilmgandhi 18:6a4db94011d3 4762
sahilmgandhi 18:6a4db94011d3 4763 /****************** Bit definition for I2C_TRISE register *******************/
sahilmgandhi 18:6a4db94011d3 4764 #define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
sahilmgandhi 18:6a4db94011d3 4765
sahilmgandhi 18:6a4db94011d3 4766 /****************** Bit definition for I2C_FLTR register *******************/
sahilmgandhi 18:6a4db94011d3 4767 #define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
sahilmgandhi 18:6a4db94011d3 4768 #define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
sahilmgandhi 18:6a4db94011d3 4769
sahilmgandhi 18:6a4db94011d3 4770 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4771 /* */
sahilmgandhi 18:6a4db94011d3 4772 /* Independent WATCHDOG */
sahilmgandhi 18:6a4db94011d3 4773 /* */
sahilmgandhi 18:6a4db94011d3 4774 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4775 /******************* Bit definition for IWDG_KR register ********************/
sahilmgandhi 18:6a4db94011d3 4776 #define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
sahilmgandhi 18:6a4db94011d3 4777
sahilmgandhi 18:6a4db94011d3 4778 /******************* Bit definition for IWDG_PR register ********************/
sahilmgandhi 18:6a4db94011d3 4779 #define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
sahilmgandhi 18:6a4db94011d3 4780 #define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4781 #define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4782 #define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4783
sahilmgandhi 18:6a4db94011d3 4784 /******************* Bit definition for IWDG_RLR register *******************/
sahilmgandhi 18:6a4db94011d3 4785 #define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
sahilmgandhi 18:6a4db94011d3 4786
sahilmgandhi 18:6a4db94011d3 4787 /******************* Bit definition for IWDG_SR register ********************/
sahilmgandhi 18:6a4db94011d3 4788 #define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
sahilmgandhi 18:6a4db94011d3 4789 #define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
sahilmgandhi 18:6a4db94011d3 4790
sahilmgandhi 18:6a4db94011d3 4791
sahilmgandhi 18:6a4db94011d3 4792 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4793 /* */
sahilmgandhi 18:6a4db94011d3 4794 /* Power Control */
sahilmgandhi 18:6a4db94011d3 4795 /* */
sahilmgandhi 18:6a4db94011d3 4796 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4797 /******************** Bit definition for PWR_CR register ********************/
sahilmgandhi 18:6a4db94011d3 4798 #define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
sahilmgandhi 18:6a4db94011d3 4799 #define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
sahilmgandhi 18:6a4db94011d3 4800 #define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
sahilmgandhi 18:6a4db94011d3 4801 #define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
sahilmgandhi 18:6a4db94011d3 4802 #define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
sahilmgandhi 18:6a4db94011d3 4803
sahilmgandhi 18:6a4db94011d3 4804 #define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
sahilmgandhi 18:6a4db94011d3 4805 #define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 4806 #define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 4807 #define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
sahilmgandhi 18:6a4db94011d3 4808
sahilmgandhi 18:6a4db94011d3 4809 /*!< PVD level configuration */
sahilmgandhi 18:6a4db94011d3 4810 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
sahilmgandhi 18:6a4db94011d3 4811 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
sahilmgandhi 18:6a4db94011d3 4812 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
sahilmgandhi 18:6a4db94011d3 4813 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
sahilmgandhi 18:6a4db94011d3 4814 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
sahilmgandhi 18:6a4db94011d3 4815 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
sahilmgandhi 18:6a4db94011d3 4816 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
sahilmgandhi 18:6a4db94011d3 4817 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
sahilmgandhi 18:6a4db94011d3 4818
sahilmgandhi 18:6a4db94011d3 4819 #define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
sahilmgandhi 18:6a4db94011d3 4820 #define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
sahilmgandhi 18:6a4db94011d3 4821 #define PWR_CR_VOS 0x00004000U /*!< VOS bit (Regulator voltage scaling output selection) */
sahilmgandhi 18:6a4db94011d3 4822
sahilmgandhi 18:6a4db94011d3 4823 /* Legacy define */
sahilmgandhi 18:6a4db94011d3 4824 #define PWR_CR_PMODE PWR_CR_VOS
sahilmgandhi 18:6a4db94011d3 4825
sahilmgandhi 18:6a4db94011d3 4826 /******************* Bit definition for PWR_CSR register ********************/
sahilmgandhi 18:6a4db94011d3 4827 #define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
sahilmgandhi 18:6a4db94011d3 4828 #define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
sahilmgandhi 18:6a4db94011d3 4829 #define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
sahilmgandhi 18:6a4db94011d3 4830 #define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
sahilmgandhi 18:6a4db94011d3 4831 #define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
sahilmgandhi 18:6a4db94011d3 4832 #define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
sahilmgandhi 18:6a4db94011d3 4833 #define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
sahilmgandhi 18:6a4db94011d3 4834
sahilmgandhi 18:6a4db94011d3 4835 /* Legacy define */
sahilmgandhi 18:6a4db94011d3 4836 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
sahilmgandhi 18:6a4db94011d3 4837
sahilmgandhi 18:6a4db94011d3 4838 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4839 /* */
sahilmgandhi 18:6a4db94011d3 4840 /* Reset and Clock Control */
sahilmgandhi 18:6a4db94011d3 4841 /* */
sahilmgandhi 18:6a4db94011d3 4842 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 4843 /******************** Bit definition for RCC_CR register ********************/
sahilmgandhi 18:6a4db94011d3 4844 #define RCC_CR_HSION 0x00000001U
sahilmgandhi 18:6a4db94011d3 4845 #define RCC_CR_HSIRDY 0x00000002U
sahilmgandhi 18:6a4db94011d3 4846
sahilmgandhi 18:6a4db94011d3 4847 #define RCC_CR_HSITRIM 0x000000F8U
sahilmgandhi 18:6a4db94011d3 4848 #define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4849 #define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4850 #define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4851 #define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4852 #define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4853
sahilmgandhi 18:6a4db94011d3 4854 #define RCC_CR_HSICAL 0x0000FF00U
sahilmgandhi 18:6a4db94011d3 4855 #define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 4856 #define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 4857 #define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 4858 #define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 4859 #define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 4860 #define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 4861 #define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 4862 #define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 4863
sahilmgandhi 18:6a4db94011d3 4864 #define RCC_CR_HSEON 0x00010000U
sahilmgandhi 18:6a4db94011d3 4865 #define RCC_CR_HSERDY 0x00020000U
sahilmgandhi 18:6a4db94011d3 4866 #define RCC_CR_HSEBYP 0x00040000U
sahilmgandhi 18:6a4db94011d3 4867 #define RCC_CR_CSSON 0x00080000U
sahilmgandhi 18:6a4db94011d3 4868 #define RCC_CR_PLLON 0x01000000U
sahilmgandhi 18:6a4db94011d3 4869 #define RCC_CR_PLLRDY 0x02000000U
sahilmgandhi 18:6a4db94011d3 4870 #define RCC_CR_PLLI2SON 0x04000000U
sahilmgandhi 18:6a4db94011d3 4871 #define RCC_CR_PLLI2SRDY 0x08000000U
sahilmgandhi 18:6a4db94011d3 4872
sahilmgandhi 18:6a4db94011d3 4873 /******************** Bit definition for RCC_PLLCFGR register ***************/
sahilmgandhi 18:6a4db94011d3 4874 #define RCC_PLLCFGR_PLLM 0x0000003FU
sahilmgandhi 18:6a4db94011d3 4875 #define RCC_PLLCFGR_PLLM_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 4876 #define RCC_PLLCFGR_PLLM_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 4877 #define RCC_PLLCFGR_PLLM_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 4878 #define RCC_PLLCFGR_PLLM_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 4879 #define RCC_PLLCFGR_PLLM_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 4880 #define RCC_PLLCFGR_PLLM_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 4881
sahilmgandhi 18:6a4db94011d3 4882 #define RCC_PLLCFGR_PLLN 0x00007FC0U
sahilmgandhi 18:6a4db94011d3 4883 #define RCC_PLLCFGR_PLLN_0 0x00000040U
sahilmgandhi 18:6a4db94011d3 4884 #define RCC_PLLCFGR_PLLN_1 0x00000080U
sahilmgandhi 18:6a4db94011d3 4885 #define RCC_PLLCFGR_PLLN_2 0x00000100U
sahilmgandhi 18:6a4db94011d3 4886 #define RCC_PLLCFGR_PLLN_3 0x00000200U
sahilmgandhi 18:6a4db94011d3 4887 #define RCC_PLLCFGR_PLLN_4 0x00000400U
sahilmgandhi 18:6a4db94011d3 4888 #define RCC_PLLCFGR_PLLN_5 0x00000800U
sahilmgandhi 18:6a4db94011d3 4889 #define RCC_PLLCFGR_PLLN_6 0x00001000U
sahilmgandhi 18:6a4db94011d3 4890 #define RCC_PLLCFGR_PLLN_7 0x00002000U
sahilmgandhi 18:6a4db94011d3 4891 #define RCC_PLLCFGR_PLLN_8 0x00004000U
sahilmgandhi 18:6a4db94011d3 4892
sahilmgandhi 18:6a4db94011d3 4893 #define RCC_PLLCFGR_PLLP 0x00030000U
sahilmgandhi 18:6a4db94011d3 4894 #define RCC_PLLCFGR_PLLP_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 4895 #define RCC_PLLCFGR_PLLP_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 4896
sahilmgandhi 18:6a4db94011d3 4897 #define RCC_PLLCFGR_PLLSRC 0x00400000U
sahilmgandhi 18:6a4db94011d3 4898 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
sahilmgandhi 18:6a4db94011d3 4899 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
sahilmgandhi 18:6a4db94011d3 4900
sahilmgandhi 18:6a4db94011d3 4901 #define RCC_PLLCFGR_PLLQ 0x0F000000U
sahilmgandhi 18:6a4db94011d3 4902 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 4903 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 4904 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
sahilmgandhi 18:6a4db94011d3 4905 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
sahilmgandhi 18:6a4db94011d3 4906
sahilmgandhi 18:6a4db94011d3 4907 /******************** Bit definition for RCC_CFGR register ******************/
sahilmgandhi 18:6a4db94011d3 4908 /*!< SW configuration */
sahilmgandhi 18:6a4db94011d3 4909 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
sahilmgandhi 18:6a4db94011d3 4910 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 4911 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 4912
sahilmgandhi 18:6a4db94011d3 4913 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
sahilmgandhi 18:6a4db94011d3 4914 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
sahilmgandhi 18:6a4db94011d3 4915 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
sahilmgandhi 18:6a4db94011d3 4916
sahilmgandhi 18:6a4db94011d3 4917 /*!< SWS configuration */
sahilmgandhi 18:6a4db94011d3 4918 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
sahilmgandhi 18:6a4db94011d3 4919 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 4920 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 4921
sahilmgandhi 18:6a4db94011d3 4922 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
sahilmgandhi 18:6a4db94011d3 4923 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
sahilmgandhi 18:6a4db94011d3 4924 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
sahilmgandhi 18:6a4db94011d3 4925
sahilmgandhi 18:6a4db94011d3 4926 /*!< HPRE configuration */
sahilmgandhi 18:6a4db94011d3 4927 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
sahilmgandhi 18:6a4db94011d3 4928 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 4929 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 4930 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
sahilmgandhi 18:6a4db94011d3 4931 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
sahilmgandhi 18:6a4db94011d3 4932
sahilmgandhi 18:6a4db94011d3 4933 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
sahilmgandhi 18:6a4db94011d3 4934 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 4935 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 4936 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 4937 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 4938 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
sahilmgandhi 18:6a4db94011d3 4939 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
sahilmgandhi 18:6a4db94011d3 4940 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
sahilmgandhi 18:6a4db94011d3 4941 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
sahilmgandhi 18:6a4db94011d3 4942
sahilmgandhi 18:6a4db94011d3 4943 /*!< PPRE1 configuration */
sahilmgandhi 18:6a4db94011d3 4944 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
sahilmgandhi 18:6a4db94011d3 4945 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 4946 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 4947 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
sahilmgandhi 18:6a4db94011d3 4948
sahilmgandhi 18:6a4db94011d3 4949 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
sahilmgandhi 18:6a4db94011d3 4950 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 4951 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 4952 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 4953 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 4954
sahilmgandhi 18:6a4db94011d3 4955 /*!< PPRE2 configuration */
sahilmgandhi 18:6a4db94011d3 4956 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
sahilmgandhi 18:6a4db94011d3 4957 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 4958 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 4959 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
sahilmgandhi 18:6a4db94011d3 4960
sahilmgandhi 18:6a4db94011d3 4961 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
sahilmgandhi 18:6a4db94011d3 4962 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 4963 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 4964 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 4965 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 4966
sahilmgandhi 18:6a4db94011d3 4967 /*!< RTCPRE configuration */
sahilmgandhi 18:6a4db94011d3 4968 #define RCC_CFGR_RTCPRE 0x001F0000U
sahilmgandhi 18:6a4db94011d3 4969 #define RCC_CFGR_RTCPRE_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 4970 #define RCC_CFGR_RTCPRE_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 4971 #define RCC_CFGR_RTCPRE_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 4972 #define RCC_CFGR_RTCPRE_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 4973 #define RCC_CFGR_RTCPRE_4 0x00100000U
sahilmgandhi 18:6a4db94011d3 4974
sahilmgandhi 18:6a4db94011d3 4975 /*!< MCO1 configuration */
sahilmgandhi 18:6a4db94011d3 4976 #define RCC_CFGR_MCO1 0x00600000U
sahilmgandhi 18:6a4db94011d3 4977 #define RCC_CFGR_MCO1_0 0x00200000U
sahilmgandhi 18:6a4db94011d3 4978 #define RCC_CFGR_MCO1_1 0x00400000U
sahilmgandhi 18:6a4db94011d3 4979
sahilmgandhi 18:6a4db94011d3 4980 #define RCC_CFGR_I2SSRC 0x00800000U
sahilmgandhi 18:6a4db94011d3 4981
sahilmgandhi 18:6a4db94011d3 4982 #define RCC_CFGR_MCO1PRE 0x07000000U
sahilmgandhi 18:6a4db94011d3 4983 #define RCC_CFGR_MCO1PRE_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 4984 #define RCC_CFGR_MCO1PRE_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 4985 #define RCC_CFGR_MCO1PRE_2 0x04000000U
sahilmgandhi 18:6a4db94011d3 4986
sahilmgandhi 18:6a4db94011d3 4987 #define RCC_CFGR_MCO2PRE 0x38000000U
sahilmgandhi 18:6a4db94011d3 4988 #define RCC_CFGR_MCO2PRE_0 0x08000000U
sahilmgandhi 18:6a4db94011d3 4989 #define RCC_CFGR_MCO2PRE_1 0x10000000U
sahilmgandhi 18:6a4db94011d3 4990 #define RCC_CFGR_MCO2PRE_2 0x20000000U
sahilmgandhi 18:6a4db94011d3 4991
sahilmgandhi 18:6a4db94011d3 4992 #define RCC_CFGR_MCO2 0xC0000000U
sahilmgandhi 18:6a4db94011d3 4993 #define RCC_CFGR_MCO2_0 0x40000000U
sahilmgandhi 18:6a4db94011d3 4994 #define RCC_CFGR_MCO2_1 0x80000000U
sahilmgandhi 18:6a4db94011d3 4995
sahilmgandhi 18:6a4db94011d3 4996 /******************** Bit definition for RCC_CIR register *******************/
sahilmgandhi 18:6a4db94011d3 4997 #define RCC_CIR_LSIRDYF 0x00000001U
sahilmgandhi 18:6a4db94011d3 4998 #define RCC_CIR_LSERDYF 0x00000002U
sahilmgandhi 18:6a4db94011d3 4999 #define RCC_CIR_HSIRDYF 0x00000004U
sahilmgandhi 18:6a4db94011d3 5000 #define RCC_CIR_HSERDYF 0x00000008U
sahilmgandhi 18:6a4db94011d3 5001 #define RCC_CIR_PLLRDYF 0x00000010U
sahilmgandhi 18:6a4db94011d3 5002 #define RCC_CIR_PLLI2SRDYF 0x00000020U
sahilmgandhi 18:6a4db94011d3 5003
sahilmgandhi 18:6a4db94011d3 5004 #define RCC_CIR_CSSF 0x00000080U
sahilmgandhi 18:6a4db94011d3 5005 #define RCC_CIR_LSIRDYIE 0x00000100U
sahilmgandhi 18:6a4db94011d3 5006 #define RCC_CIR_LSERDYIE 0x00000200U
sahilmgandhi 18:6a4db94011d3 5007 #define RCC_CIR_HSIRDYIE 0x00000400U
sahilmgandhi 18:6a4db94011d3 5008 #define RCC_CIR_HSERDYIE 0x00000800U
sahilmgandhi 18:6a4db94011d3 5009 #define RCC_CIR_PLLRDYIE 0x00001000U
sahilmgandhi 18:6a4db94011d3 5010 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
sahilmgandhi 18:6a4db94011d3 5011
sahilmgandhi 18:6a4db94011d3 5012 #define RCC_CIR_LSIRDYC 0x00010000U
sahilmgandhi 18:6a4db94011d3 5013 #define RCC_CIR_LSERDYC 0x00020000U
sahilmgandhi 18:6a4db94011d3 5014 #define RCC_CIR_HSIRDYC 0x00040000U
sahilmgandhi 18:6a4db94011d3 5015 #define RCC_CIR_HSERDYC 0x00080000U
sahilmgandhi 18:6a4db94011d3 5016 #define RCC_CIR_PLLRDYC 0x00100000U
sahilmgandhi 18:6a4db94011d3 5017 #define RCC_CIR_PLLI2SRDYC 0x00200000U
sahilmgandhi 18:6a4db94011d3 5018
sahilmgandhi 18:6a4db94011d3 5019 #define RCC_CIR_CSSC 0x00800000U
sahilmgandhi 18:6a4db94011d3 5020
sahilmgandhi 18:6a4db94011d3 5021 /******************** Bit definition for RCC_AHB1RSTR register **************/
sahilmgandhi 18:6a4db94011d3 5022 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
sahilmgandhi 18:6a4db94011d3 5023 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
sahilmgandhi 18:6a4db94011d3 5024 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
sahilmgandhi 18:6a4db94011d3 5025 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
sahilmgandhi 18:6a4db94011d3 5026 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
sahilmgandhi 18:6a4db94011d3 5027 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
sahilmgandhi 18:6a4db94011d3 5028 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
sahilmgandhi 18:6a4db94011d3 5029 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
sahilmgandhi 18:6a4db94011d3 5030 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
sahilmgandhi 18:6a4db94011d3 5031 #define RCC_AHB1RSTR_CRCRST 0x00001000U
sahilmgandhi 18:6a4db94011d3 5032 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
sahilmgandhi 18:6a4db94011d3 5033 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
sahilmgandhi 18:6a4db94011d3 5034 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
sahilmgandhi 18:6a4db94011d3 5035 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
sahilmgandhi 18:6a4db94011d3 5036
sahilmgandhi 18:6a4db94011d3 5037 /******************** Bit definition for RCC_AHB2RSTR register **************/
sahilmgandhi 18:6a4db94011d3 5038 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
sahilmgandhi 18:6a4db94011d3 5039 #define RCC_AHB2RSTR_RNGRST 0x00000040U
sahilmgandhi 18:6a4db94011d3 5040 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
sahilmgandhi 18:6a4db94011d3 5041
sahilmgandhi 18:6a4db94011d3 5042 /******************** Bit definition for RCC_AHB3RSTR register **************/
sahilmgandhi 18:6a4db94011d3 5043
sahilmgandhi 18:6a4db94011d3 5044 #define RCC_AHB3RSTR_FSMCRST 0x00000001U
sahilmgandhi 18:6a4db94011d3 5045
sahilmgandhi 18:6a4db94011d3 5046 /******************** Bit definition for RCC_APB1RSTR register **************/
sahilmgandhi 18:6a4db94011d3 5047 #define RCC_APB1RSTR_TIM2RST 0x00000001U
sahilmgandhi 18:6a4db94011d3 5048 #define RCC_APB1RSTR_TIM3RST 0x00000002U
sahilmgandhi 18:6a4db94011d3 5049 #define RCC_APB1RSTR_TIM4RST 0x00000004U
sahilmgandhi 18:6a4db94011d3 5050 #define RCC_APB1RSTR_TIM5RST 0x00000008U
sahilmgandhi 18:6a4db94011d3 5051 #define RCC_APB1RSTR_TIM6RST 0x00000010U
sahilmgandhi 18:6a4db94011d3 5052 #define RCC_APB1RSTR_TIM7RST 0x00000020U
sahilmgandhi 18:6a4db94011d3 5053 #define RCC_APB1RSTR_TIM12RST 0x00000040U
sahilmgandhi 18:6a4db94011d3 5054 #define RCC_APB1RSTR_TIM13RST 0x00000080U
sahilmgandhi 18:6a4db94011d3 5055 #define RCC_APB1RSTR_TIM14RST 0x00000100U
sahilmgandhi 18:6a4db94011d3 5056 #define RCC_APB1RSTR_WWDGRST 0x00000800U
sahilmgandhi 18:6a4db94011d3 5057 #define RCC_APB1RSTR_SPI2RST 0x00004000U
sahilmgandhi 18:6a4db94011d3 5058 #define RCC_APB1RSTR_SPI3RST 0x00008000U
sahilmgandhi 18:6a4db94011d3 5059 #define RCC_APB1RSTR_USART2RST 0x00020000U
sahilmgandhi 18:6a4db94011d3 5060 #define RCC_APB1RSTR_USART3RST 0x00040000U
sahilmgandhi 18:6a4db94011d3 5061 #define RCC_APB1RSTR_UART4RST 0x00080000U
sahilmgandhi 18:6a4db94011d3 5062 #define RCC_APB1RSTR_UART5RST 0x00100000U
sahilmgandhi 18:6a4db94011d3 5063 #define RCC_APB1RSTR_I2C1RST 0x00200000U
sahilmgandhi 18:6a4db94011d3 5064 #define RCC_APB1RSTR_I2C2RST 0x00400000U
sahilmgandhi 18:6a4db94011d3 5065 #define RCC_APB1RSTR_I2C3RST 0x00800000U
sahilmgandhi 18:6a4db94011d3 5066 #define RCC_APB1RSTR_CAN1RST 0x02000000U
sahilmgandhi 18:6a4db94011d3 5067 #define RCC_APB1RSTR_CAN2RST 0x04000000U
sahilmgandhi 18:6a4db94011d3 5068 #define RCC_APB1RSTR_PWRRST 0x10000000U
sahilmgandhi 18:6a4db94011d3 5069 #define RCC_APB1RSTR_DACRST 0x20000000U
sahilmgandhi 18:6a4db94011d3 5070
sahilmgandhi 18:6a4db94011d3 5071 /******************** Bit definition for RCC_APB2RSTR register **************/
sahilmgandhi 18:6a4db94011d3 5072 #define RCC_APB2RSTR_TIM1RST 0x00000001U
sahilmgandhi 18:6a4db94011d3 5073 #define RCC_APB2RSTR_TIM8RST 0x00000002U
sahilmgandhi 18:6a4db94011d3 5074 #define RCC_APB2RSTR_USART1RST 0x00000010U
sahilmgandhi 18:6a4db94011d3 5075 #define RCC_APB2RSTR_USART6RST 0x00000020U
sahilmgandhi 18:6a4db94011d3 5076 #define RCC_APB2RSTR_ADCRST 0x00000100U
sahilmgandhi 18:6a4db94011d3 5077 #define RCC_APB2RSTR_SDIORST 0x00000800U
sahilmgandhi 18:6a4db94011d3 5078 #define RCC_APB2RSTR_SPI1RST 0x00001000U
sahilmgandhi 18:6a4db94011d3 5079 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
sahilmgandhi 18:6a4db94011d3 5080 #define RCC_APB2RSTR_TIM9RST 0x00010000U
sahilmgandhi 18:6a4db94011d3 5081 #define RCC_APB2RSTR_TIM10RST 0x00020000U
sahilmgandhi 18:6a4db94011d3 5082 #define RCC_APB2RSTR_TIM11RST 0x00040000U
sahilmgandhi 18:6a4db94011d3 5083
sahilmgandhi 18:6a4db94011d3 5084 /* Old SPI1RST bit definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 5085 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
sahilmgandhi 18:6a4db94011d3 5086
sahilmgandhi 18:6a4db94011d3 5087 /******************** Bit definition for RCC_AHB1ENR register ***************/
sahilmgandhi 18:6a4db94011d3 5088 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
sahilmgandhi 18:6a4db94011d3 5089 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
sahilmgandhi 18:6a4db94011d3 5090 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
sahilmgandhi 18:6a4db94011d3 5091 #define RCC_AHB1ENR_GPIODEN 0x00000008U
sahilmgandhi 18:6a4db94011d3 5092 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
sahilmgandhi 18:6a4db94011d3 5093 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
sahilmgandhi 18:6a4db94011d3 5094 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
sahilmgandhi 18:6a4db94011d3 5095 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
sahilmgandhi 18:6a4db94011d3 5096 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
sahilmgandhi 18:6a4db94011d3 5097 #define RCC_AHB1ENR_CRCEN 0x00001000U
sahilmgandhi 18:6a4db94011d3 5098 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
sahilmgandhi 18:6a4db94011d3 5099 #define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
sahilmgandhi 18:6a4db94011d3 5100 #define RCC_AHB1ENR_DMA1EN 0x00200000U
sahilmgandhi 18:6a4db94011d3 5101 #define RCC_AHB1ENR_DMA2EN 0x00400000U
sahilmgandhi 18:6a4db94011d3 5102
sahilmgandhi 18:6a4db94011d3 5103 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
sahilmgandhi 18:6a4db94011d3 5104 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
sahilmgandhi 18:6a4db94011d3 5105 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
sahilmgandhi 18:6a4db94011d3 5106 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
sahilmgandhi 18:6a4db94011d3 5107 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
sahilmgandhi 18:6a4db94011d3 5108 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
sahilmgandhi 18:6a4db94011d3 5109
sahilmgandhi 18:6a4db94011d3 5110 /******************** Bit definition for RCC_AHB2ENR register ***************/
sahilmgandhi 18:6a4db94011d3 5111 #define RCC_AHB2ENR_DCMIEN 0x00000001U
sahilmgandhi 18:6a4db94011d3 5112 #define RCC_AHB2ENR_RNGEN 0x00000040U
sahilmgandhi 18:6a4db94011d3 5113 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
sahilmgandhi 18:6a4db94011d3 5114
sahilmgandhi 18:6a4db94011d3 5115 /******************** Bit definition for RCC_AHB3ENR register ***************/
sahilmgandhi 18:6a4db94011d3 5116
sahilmgandhi 18:6a4db94011d3 5117 #define RCC_AHB3ENR_FSMCEN 0x00000001U
sahilmgandhi 18:6a4db94011d3 5118
sahilmgandhi 18:6a4db94011d3 5119 /******************** Bit definition for RCC_APB1ENR register ***************/
sahilmgandhi 18:6a4db94011d3 5120 #define RCC_APB1ENR_TIM2EN 0x00000001U
sahilmgandhi 18:6a4db94011d3 5121 #define RCC_APB1ENR_TIM3EN 0x00000002U
sahilmgandhi 18:6a4db94011d3 5122 #define RCC_APB1ENR_TIM4EN 0x00000004U
sahilmgandhi 18:6a4db94011d3 5123 #define RCC_APB1ENR_TIM5EN 0x00000008U
sahilmgandhi 18:6a4db94011d3 5124 #define RCC_APB1ENR_TIM6EN 0x00000010U
sahilmgandhi 18:6a4db94011d3 5125 #define RCC_APB1ENR_TIM7EN 0x00000020U
sahilmgandhi 18:6a4db94011d3 5126 #define RCC_APB1ENR_TIM12EN 0x00000040U
sahilmgandhi 18:6a4db94011d3 5127 #define RCC_APB1ENR_TIM13EN 0x00000080U
sahilmgandhi 18:6a4db94011d3 5128 #define RCC_APB1ENR_TIM14EN 0x00000100U
sahilmgandhi 18:6a4db94011d3 5129 #define RCC_APB1ENR_WWDGEN 0x00000800U
sahilmgandhi 18:6a4db94011d3 5130 #define RCC_APB1ENR_SPI2EN 0x00004000U
sahilmgandhi 18:6a4db94011d3 5131 #define RCC_APB1ENR_SPI3EN 0x00008000U
sahilmgandhi 18:6a4db94011d3 5132 #define RCC_APB1ENR_USART2EN 0x00020000U
sahilmgandhi 18:6a4db94011d3 5133 #define RCC_APB1ENR_USART3EN 0x00040000U
sahilmgandhi 18:6a4db94011d3 5134 #define RCC_APB1ENR_UART4EN 0x00080000U
sahilmgandhi 18:6a4db94011d3 5135 #define RCC_APB1ENR_UART5EN 0x00100000U
sahilmgandhi 18:6a4db94011d3 5136 #define RCC_APB1ENR_I2C1EN 0x00200000U
sahilmgandhi 18:6a4db94011d3 5137 #define RCC_APB1ENR_I2C2EN 0x00400000U
sahilmgandhi 18:6a4db94011d3 5138 #define RCC_APB1ENR_I2C3EN 0x00800000U
sahilmgandhi 18:6a4db94011d3 5139 #define RCC_APB1ENR_CAN1EN 0x02000000U
sahilmgandhi 18:6a4db94011d3 5140 #define RCC_APB1ENR_CAN2EN 0x04000000U
sahilmgandhi 18:6a4db94011d3 5141 #define RCC_APB1ENR_PWREN 0x10000000U
sahilmgandhi 18:6a4db94011d3 5142 #define RCC_APB1ENR_DACEN 0x20000000U
sahilmgandhi 18:6a4db94011d3 5143
sahilmgandhi 18:6a4db94011d3 5144 /******************** Bit definition for RCC_APB2ENR register ***************/
sahilmgandhi 18:6a4db94011d3 5145 #define RCC_APB2ENR_TIM1EN 0x00000001U
sahilmgandhi 18:6a4db94011d3 5146 #define RCC_APB2ENR_TIM8EN 0x00000002U
sahilmgandhi 18:6a4db94011d3 5147 #define RCC_APB2ENR_USART1EN 0x00000010U
sahilmgandhi 18:6a4db94011d3 5148 #define RCC_APB2ENR_USART6EN 0x00000020U
sahilmgandhi 18:6a4db94011d3 5149 #define RCC_APB2ENR_ADC1EN 0x00000100U
sahilmgandhi 18:6a4db94011d3 5150 #define RCC_APB2ENR_ADC2EN 0x00000200U
sahilmgandhi 18:6a4db94011d3 5151 #define RCC_APB2ENR_ADC3EN 0x00000400U
sahilmgandhi 18:6a4db94011d3 5152 #define RCC_APB2ENR_SDIOEN 0x00000800U
sahilmgandhi 18:6a4db94011d3 5153 #define RCC_APB2ENR_SPI1EN 0x00001000U
sahilmgandhi 18:6a4db94011d3 5154 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
sahilmgandhi 18:6a4db94011d3 5155 #define RCC_APB2ENR_TIM9EN 0x00010000U
sahilmgandhi 18:6a4db94011d3 5156 #define RCC_APB2ENR_TIM10EN 0x00020000U
sahilmgandhi 18:6a4db94011d3 5157 #define RCC_APB2ENR_TIM11EN 0x00040000U
sahilmgandhi 18:6a4db94011d3 5158 #define RCC_APB2ENR_SPI5EN 0x00100000U
sahilmgandhi 18:6a4db94011d3 5159 #define RCC_APB2ENR_SPI6EN 0x00200000U
sahilmgandhi 18:6a4db94011d3 5160
sahilmgandhi 18:6a4db94011d3 5161 /******************** Bit definition for RCC_AHB1LPENR register *************/
sahilmgandhi 18:6a4db94011d3 5162 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
sahilmgandhi 18:6a4db94011d3 5163 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
sahilmgandhi 18:6a4db94011d3 5164 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
sahilmgandhi 18:6a4db94011d3 5165 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
sahilmgandhi 18:6a4db94011d3 5166 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
sahilmgandhi 18:6a4db94011d3 5167 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
sahilmgandhi 18:6a4db94011d3 5168 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
sahilmgandhi 18:6a4db94011d3 5169 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
sahilmgandhi 18:6a4db94011d3 5170 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
sahilmgandhi 18:6a4db94011d3 5171 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
sahilmgandhi 18:6a4db94011d3 5172 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
sahilmgandhi 18:6a4db94011d3 5173 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
sahilmgandhi 18:6a4db94011d3 5174 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
sahilmgandhi 18:6a4db94011d3 5175 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
sahilmgandhi 18:6a4db94011d3 5176 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
sahilmgandhi 18:6a4db94011d3 5177 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
sahilmgandhi 18:6a4db94011d3 5178 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
sahilmgandhi 18:6a4db94011d3 5179 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
sahilmgandhi 18:6a4db94011d3 5180 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
sahilmgandhi 18:6a4db94011d3 5181 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
sahilmgandhi 18:6a4db94011d3 5182 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
sahilmgandhi 18:6a4db94011d3 5183 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
sahilmgandhi 18:6a4db94011d3 5184
sahilmgandhi 18:6a4db94011d3 5185 /******************** Bit definition for RCC_AHB2LPENR register *************/
sahilmgandhi 18:6a4db94011d3 5186 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
sahilmgandhi 18:6a4db94011d3 5187 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
sahilmgandhi 18:6a4db94011d3 5188 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
sahilmgandhi 18:6a4db94011d3 5189
sahilmgandhi 18:6a4db94011d3 5190 /******************** Bit definition for RCC_AHB3LPENR register *************/
sahilmgandhi 18:6a4db94011d3 5191
sahilmgandhi 18:6a4db94011d3 5192 #define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
sahilmgandhi 18:6a4db94011d3 5193
sahilmgandhi 18:6a4db94011d3 5194 /******************** Bit definition for RCC_APB1LPENR register *************/
sahilmgandhi 18:6a4db94011d3 5195 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
sahilmgandhi 18:6a4db94011d3 5196 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
sahilmgandhi 18:6a4db94011d3 5197 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
sahilmgandhi 18:6a4db94011d3 5198 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
sahilmgandhi 18:6a4db94011d3 5199 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
sahilmgandhi 18:6a4db94011d3 5200 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
sahilmgandhi 18:6a4db94011d3 5201 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
sahilmgandhi 18:6a4db94011d3 5202 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
sahilmgandhi 18:6a4db94011d3 5203 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
sahilmgandhi 18:6a4db94011d3 5204 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
sahilmgandhi 18:6a4db94011d3 5205 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
sahilmgandhi 18:6a4db94011d3 5206 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
sahilmgandhi 18:6a4db94011d3 5207 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
sahilmgandhi 18:6a4db94011d3 5208 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
sahilmgandhi 18:6a4db94011d3 5209 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
sahilmgandhi 18:6a4db94011d3 5210 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
sahilmgandhi 18:6a4db94011d3 5211 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
sahilmgandhi 18:6a4db94011d3 5212 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
sahilmgandhi 18:6a4db94011d3 5213 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
sahilmgandhi 18:6a4db94011d3 5214 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
sahilmgandhi 18:6a4db94011d3 5215 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
sahilmgandhi 18:6a4db94011d3 5216 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
sahilmgandhi 18:6a4db94011d3 5217 #define RCC_APB1LPENR_DACLPEN 0x20000000U
sahilmgandhi 18:6a4db94011d3 5218
sahilmgandhi 18:6a4db94011d3 5219 /******************** Bit definition for RCC_APB2LPENR register *************/
sahilmgandhi 18:6a4db94011d3 5220 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
sahilmgandhi 18:6a4db94011d3 5221 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
sahilmgandhi 18:6a4db94011d3 5222 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
sahilmgandhi 18:6a4db94011d3 5223 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
sahilmgandhi 18:6a4db94011d3 5224 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
sahilmgandhi 18:6a4db94011d3 5225 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
sahilmgandhi 18:6a4db94011d3 5226 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
sahilmgandhi 18:6a4db94011d3 5227 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
sahilmgandhi 18:6a4db94011d3 5228 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
sahilmgandhi 18:6a4db94011d3 5229 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
sahilmgandhi 18:6a4db94011d3 5230 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
sahilmgandhi 18:6a4db94011d3 5231 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
sahilmgandhi 18:6a4db94011d3 5232 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
sahilmgandhi 18:6a4db94011d3 5233
sahilmgandhi 18:6a4db94011d3 5234 /******************** Bit definition for RCC_BDCR register ******************/
sahilmgandhi 18:6a4db94011d3 5235 #define RCC_BDCR_LSEON 0x00000001U
sahilmgandhi 18:6a4db94011d3 5236 #define RCC_BDCR_LSERDY 0x00000002U
sahilmgandhi 18:6a4db94011d3 5237 #define RCC_BDCR_LSEBYP 0x00000004U
sahilmgandhi 18:6a4db94011d3 5238
sahilmgandhi 18:6a4db94011d3 5239 #define RCC_BDCR_RTCSEL 0x00000300U
sahilmgandhi 18:6a4db94011d3 5240 #define RCC_BDCR_RTCSEL_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 5241 #define RCC_BDCR_RTCSEL_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 5242
sahilmgandhi 18:6a4db94011d3 5243 #define RCC_BDCR_RTCEN 0x00008000U
sahilmgandhi 18:6a4db94011d3 5244 #define RCC_BDCR_BDRST 0x00010000U
sahilmgandhi 18:6a4db94011d3 5245
sahilmgandhi 18:6a4db94011d3 5246 /******************** Bit definition for RCC_CSR register *******************/
sahilmgandhi 18:6a4db94011d3 5247 #define RCC_CSR_LSION 0x00000001U
sahilmgandhi 18:6a4db94011d3 5248 #define RCC_CSR_LSIRDY 0x00000002U
sahilmgandhi 18:6a4db94011d3 5249 #define RCC_CSR_RMVF 0x01000000U
sahilmgandhi 18:6a4db94011d3 5250 #define RCC_CSR_BORRSTF 0x02000000U
sahilmgandhi 18:6a4db94011d3 5251 #define RCC_CSR_PADRSTF 0x04000000U
sahilmgandhi 18:6a4db94011d3 5252 #define RCC_CSR_PORRSTF 0x08000000U
sahilmgandhi 18:6a4db94011d3 5253 #define RCC_CSR_SFTRSTF 0x10000000U
sahilmgandhi 18:6a4db94011d3 5254 #define RCC_CSR_WDGRSTF 0x20000000U
sahilmgandhi 18:6a4db94011d3 5255 #define RCC_CSR_WWDGRSTF 0x40000000U
sahilmgandhi 18:6a4db94011d3 5256 #define RCC_CSR_LPWRRSTF 0x80000000U
sahilmgandhi 18:6a4db94011d3 5257
sahilmgandhi 18:6a4db94011d3 5258 /******************** Bit definition for RCC_SSCGR register *****************/
sahilmgandhi 18:6a4db94011d3 5259 #define RCC_SSCGR_MODPER 0x00001FFFU
sahilmgandhi 18:6a4db94011d3 5260 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
sahilmgandhi 18:6a4db94011d3 5261 #define RCC_SSCGR_SPREADSEL 0x40000000U
sahilmgandhi 18:6a4db94011d3 5262 #define RCC_SSCGR_SSCGEN 0x80000000U
sahilmgandhi 18:6a4db94011d3 5263
sahilmgandhi 18:6a4db94011d3 5264 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
sahilmgandhi 18:6a4db94011d3 5265 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
sahilmgandhi 18:6a4db94011d3 5266 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
sahilmgandhi 18:6a4db94011d3 5267 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
sahilmgandhi 18:6a4db94011d3 5268 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
sahilmgandhi 18:6a4db94011d3 5269 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
sahilmgandhi 18:6a4db94011d3 5270 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
sahilmgandhi 18:6a4db94011d3 5271 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
sahilmgandhi 18:6a4db94011d3 5272 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
sahilmgandhi 18:6a4db94011d3 5273 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
sahilmgandhi 18:6a4db94011d3 5274 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
sahilmgandhi 18:6a4db94011d3 5275
sahilmgandhi 18:6a4db94011d3 5276 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
sahilmgandhi 18:6a4db94011d3 5277 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
sahilmgandhi 18:6a4db94011d3 5278 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
sahilmgandhi 18:6a4db94011d3 5279 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
sahilmgandhi 18:6a4db94011d3 5280
sahilmgandhi 18:6a4db94011d3 5281 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5282 /* */
sahilmgandhi 18:6a4db94011d3 5283 /* RNG */
sahilmgandhi 18:6a4db94011d3 5284 /* */
sahilmgandhi 18:6a4db94011d3 5285 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5286 /******************** Bits definition for RNG_CR register *******************/
sahilmgandhi 18:6a4db94011d3 5287 #define RNG_CR_RNGEN 0x00000004U
sahilmgandhi 18:6a4db94011d3 5288 #define RNG_CR_IE 0x00000008U
sahilmgandhi 18:6a4db94011d3 5289
sahilmgandhi 18:6a4db94011d3 5290 /******************** Bits definition for RNG_SR register *******************/
sahilmgandhi 18:6a4db94011d3 5291 #define RNG_SR_DRDY 0x00000001U
sahilmgandhi 18:6a4db94011d3 5292 #define RNG_SR_CECS 0x00000002U
sahilmgandhi 18:6a4db94011d3 5293 #define RNG_SR_SECS 0x00000004U
sahilmgandhi 18:6a4db94011d3 5294 #define RNG_SR_CEIS 0x00000020U
sahilmgandhi 18:6a4db94011d3 5295 #define RNG_SR_SEIS 0x00000040U
sahilmgandhi 18:6a4db94011d3 5296
sahilmgandhi 18:6a4db94011d3 5297 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5298 /* */
sahilmgandhi 18:6a4db94011d3 5299 /* Real-Time Clock (RTC) */
sahilmgandhi 18:6a4db94011d3 5300 /* */
sahilmgandhi 18:6a4db94011d3 5301 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5302 /******************** Bits definition for RTC_TR register *******************/
sahilmgandhi 18:6a4db94011d3 5303 #define RTC_TR_PM 0x00400000U
sahilmgandhi 18:6a4db94011d3 5304 #define RTC_TR_HT 0x00300000U
sahilmgandhi 18:6a4db94011d3 5305 #define RTC_TR_HT_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 5306 #define RTC_TR_HT_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 5307 #define RTC_TR_HU 0x000F0000U
sahilmgandhi 18:6a4db94011d3 5308 #define RTC_TR_HU_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 5309 #define RTC_TR_HU_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 5310 #define RTC_TR_HU_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 5311 #define RTC_TR_HU_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 5312 #define RTC_TR_MNT 0x00007000U
sahilmgandhi 18:6a4db94011d3 5313 #define RTC_TR_MNT_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 5314 #define RTC_TR_MNT_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 5315 #define RTC_TR_MNT_2 0x00004000U
sahilmgandhi 18:6a4db94011d3 5316 #define RTC_TR_MNU 0x00000F00U
sahilmgandhi 18:6a4db94011d3 5317 #define RTC_TR_MNU_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 5318 #define RTC_TR_MNU_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 5319 #define RTC_TR_MNU_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 5320 #define RTC_TR_MNU_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 5321 #define RTC_TR_ST 0x00000070U
sahilmgandhi 18:6a4db94011d3 5322 #define RTC_TR_ST_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 5323 #define RTC_TR_ST_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 5324 #define RTC_TR_ST_2 0x00000040U
sahilmgandhi 18:6a4db94011d3 5325 #define RTC_TR_SU 0x0000000FU
sahilmgandhi 18:6a4db94011d3 5326 #define RTC_TR_SU_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 5327 #define RTC_TR_SU_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 5328 #define RTC_TR_SU_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 5329 #define RTC_TR_SU_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 5330
sahilmgandhi 18:6a4db94011d3 5331 /******************** Bits definition for RTC_DR register *******************/
sahilmgandhi 18:6a4db94011d3 5332 #define RTC_DR_YT 0x00F00000U
sahilmgandhi 18:6a4db94011d3 5333 #define RTC_DR_YT_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 5334 #define RTC_DR_YT_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 5335 #define RTC_DR_YT_2 0x00400000U
sahilmgandhi 18:6a4db94011d3 5336 #define RTC_DR_YT_3 0x00800000U
sahilmgandhi 18:6a4db94011d3 5337 #define RTC_DR_YU 0x000F0000U
sahilmgandhi 18:6a4db94011d3 5338 #define RTC_DR_YU_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 5339 #define RTC_DR_YU_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 5340 #define RTC_DR_YU_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 5341 #define RTC_DR_YU_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 5342 #define RTC_DR_WDU 0x0000E000U
sahilmgandhi 18:6a4db94011d3 5343 #define RTC_DR_WDU_0 0x00002000U
sahilmgandhi 18:6a4db94011d3 5344 #define RTC_DR_WDU_1 0x00004000U
sahilmgandhi 18:6a4db94011d3 5345 #define RTC_DR_WDU_2 0x00008000U
sahilmgandhi 18:6a4db94011d3 5346 #define RTC_DR_MT 0x00001000U
sahilmgandhi 18:6a4db94011d3 5347 #define RTC_DR_MU 0x00000F00U
sahilmgandhi 18:6a4db94011d3 5348 #define RTC_DR_MU_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 5349 #define RTC_DR_MU_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 5350 #define RTC_DR_MU_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 5351 #define RTC_DR_MU_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 5352 #define RTC_DR_DT 0x00000030U
sahilmgandhi 18:6a4db94011d3 5353 #define RTC_DR_DT_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 5354 #define RTC_DR_DT_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 5355 #define RTC_DR_DU 0x0000000FU
sahilmgandhi 18:6a4db94011d3 5356 #define RTC_DR_DU_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 5357 #define RTC_DR_DU_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 5358 #define RTC_DR_DU_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 5359 #define RTC_DR_DU_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 5360
sahilmgandhi 18:6a4db94011d3 5361 /******************** Bits definition for RTC_CR register *******************/
sahilmgandhi 18:6a4db94011d3 5362 #define RTC_CR_COE 0x00800000U
sahilmgandhi 18:6a4db94011d3 5363 #define RTC_CR_OSEL 0x00600000U
sahilmgandhi 18:6a4db94011d3 5364 #define RTC_CR_OSEL_0 0x00200000U
sahilmgandhi 18:6a4db94011d3 5365 #define RTC_CR_OSEL_1 0x00400000U
sahilmgandhi 18:6a4db94011d3 5366 #define RTC_CR_POL 0x00100000U
sahilmgandhi 18:6a4db94011d3 5367 #define RTC_CR_COSEL 0x00080000U
sahilmgandhi 18:6a4db94011d3 5368 #define RTC_CR_BCK 0x00040000U
sahilmgandhi 18:6a4db94011d3 5369 #define RTC_CR_SUB1H 0x00020000U
sahilmgandhi 18:6a4db94011d3 5370 #define RTC_CR_ADD1H 0x00010000U
sahilmgandhi 18:6a4db94011d3 5371 #define RTC_CR_TSIE 0x00008000U
sahilmgandhi 18:6a4db94011d3 5372 #define RTC_CR_WUTIE 0x00004000U
sahilmgandhi 18:6a4db94011d3 5373 #define RTC_CR_ALRBIE 0x00002000U
sahilmgandhi 18:6a4db94011d3 5374 #define RTC_CR_ALRAIE 0x00001000U
sahilmgandhi 18:6a4db94011d3 5375 #define RTC_CR_TSE 0x00000800U
sahilmgandhi 18:6a4db94011d3 5376 #define RTC_CR_WUTE 0x00000400U
sahilmgandhi 18:6a4db94011d3 5377 #define RTC_CR_ALRBE 0x00000200U
sahilmgandhi 18:6a4db94011d3 5378 #define RTC_CR_ALRAE 0x00000100U
sahilmgandhi 18:6a4db94011d3 5379 #define RTC_CR_DCE 0x00000080U
sahilmgandhi 18:6a4db94011d3 5380 #define RTC_CR_FMT 0x00000040U
sahilmgandhi 18:6a4db94011d3 5381 #define RTC_CR_BYPSHAD 0x00000020U
sahilmgandhi 18:6a4db94011d3 5382 #define RTC_CR_REFCKON 0x00000010U
sahilmgandhi 18:6a4db94011d3 5383 #define RTC_CR_TSEDGE 0x00000008U
sahilmgandhi 18:6a4db94011d3 5384 #define RTC_CR_WUCKSEL 0x00000007U
sahilmgandhi 18:6a4db94011d3 5385 #define RTC_CR_WUCKSEL_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 5386 #define RTC_CR_WUCKSEL_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 5387 #define RTC_CR_WUCKSEL_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 5388
sahilmgandhi 18:6a4db94011d3 5389 /******************** Bits definition for RTC_ISR register ******************/
sahilmgandhi 18:6a4db94011d3 5390 #define RTC_ISR_RECALPF 0x00010000U
sahilmgandhi 18:6a4db94011d3 5391 #define RTC_ISR_TAMP1F 0x00002000U
sahilmgandhi 18:6a4db94011d3 5392 #define RTC_ISR_TAMP2F 0x00004000U
sahilmgandhi 18:6a4db94011d3 5393 #define RTC_ISR_TSOVF 0x00001000U
sahilmgandhi 18:6a4db94011d3 5394 #define RTC_ISR_TSF 0x00000800U
sahilmgandhi 18:6a4db94011d3 5395 #define RTC_ISR_WUTF 0x00000400U
sahilmgandhi 18:6a4db94011d3 5396 #define RTC_ISR_ALRBF 0x00000200U
sahilmgandhi 18:6a4db94011d3 5397 #define RTC_ISR_ALRAF 0x00000100U
sahilmgandhi 18:6a4db94011d3 5398 #define RTC_ISR_INIT 0x00000080U
sahilmgandhi 18:6a4db94011d3 5399 #define RTC_ISR_INITF 0x00000040U
sahilmgandhi 18:6a4db94011d3 5400 #define RTC_ISR_RSF 0x00000020U
sahilmgandhi 18:6a4db94011d3 5401 #define RTC_ISR_INITS 0x00000010U
sahilmgandhi 18:6a4db94011d3 5402 #define RTC_ISR_SHPF 0x00000008U
sahilmgandhi 18:6a4db94011d3 5403 #define RTC_ISR_WUTWF 0x00000004U
sahilmgandhi 18:6a4db94011d3 5404 #define RTC_ISR_ALRBWF 0x00000002U
sahilmgandhi 18:6a4db94011d3 5405 #define RTC_ISR_ALRAWF 0x00000001U
sahilmgandhi 18:6a4db94011d3 5406
sahilmgandhi 18:6a4db94011d3 5407 /******************** Bits definition for RTC_PRER register *****************/
sahilmgandhi 18:6a4db94011d3 5408 #define RTC_PRER_PREDIV_A 0x007F0000U
sahilmgandhi 18:6a4db94011d3 5409 #define RTC_PRER_PREDIV_S 0x00007FFFU
sahilmgandhi 18:6a4db94011d3 5410
sahilmgandhi 18:6a4db94011d3 5411 /******************** Bits definition for RTC_WUTR register *****************/
sahilmgandhi 18:6a4db94011d3 5412 #define RTC_WUTR_WUT 0x0000FFFFU
sahilmgandhi 18:6a4db94011d3 5413
sahilmgandhi 18:6a4db94011d3 5414 /******************** Bits definition for RTC_CALIBR register ***************/
sahilmgandhi 18:6a4db94011d3 5415 #define RTC_CALIBR_DCS 0x00000080U
sahilmgandhi 18:6a4db94011d3 5416 #define RTC_CALIBR_DC 0x0000001FU
sahilmgandhi 18:6a4db94011d3 5417
sahilmgandhi 18:6a4db94011d3 5418 /******************** Bits definition for RTC_ALRMAR register ***************/
sahilmgandhi 18:6a4db94011d3 5419 #define RTC_ALRMAR_MSK4 0x80000000U
sahilmgandhi 18:6a4db94011d3 5420 #define RTC_ALRMAR_WDSEL 0x40000000U
sahilmgandhi 18:6a4db94011d3 5421 #define RTC_ALRMAR_DT 0x30000000U
sahilmgandhi 18:6a4db94011d3 5422 #define RTC_ALRMAR_DT_0 0x10000000U
sahilmgandhi 18:6a4db94011d3 5423 #define RTC_ALRMAR_DT_1 0x20000000U
sahilmgandhi 18:6a4db94011d3 5424 #define RTC_ALRMAR_DU 0x0F000000U
sahilmgandhi 18:6a4db94011d3 5425 #define RTC_ALRMAR_DU_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 5426 #define RTC_ALRMAR_DU_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 5427 #define RTC_ALRMAR_DU_2 0x04000000U
sahilmgandhi 18:6a4db94011d3 5428 #define RTC_ALRMAR_DU_3 0x08000000U
sahilmgandhi 18:6a4db94011d3 5429 #define RTC_ALRMAR_MSK3 0x00800000U
sahilmgandhi 18:6a4db94011d3 5430 #define RTC_ALRMAR_PM 0x00400000U
sahilmgandhi 18:6a4db94011d3 5431 #define RTC_ALRMAR_HT 0x00300000U
sahilmgandhi 18:6a4db94011d3 5432 #define RTC_ALRMAR_HT_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 5433 #define RTC_ALRMAR_HT_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 5434 #define RTC_ALRMAR_HU 0x000F0000U
sahilmgandhi 18:6a4db94011d3 5435 #define RTC_ALRMAR_HU_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 5436 #define RTC_ALRMAR_HU_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 5437 #define RTC_ALRMAR_HU_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 5438 #define RTC_ALRMAR_HU_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 5439 #define RTC_ALRMAR_MSK2 0x00008000U
sahilmgandhi 18:6a4db94011d3 5440 #define RTC_ALRMAR_MNT 0x00007000U
sahilmgandhi 18:6a4db94011d3 5441 #define RTC_ALRMAR_MNT_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 5442 #define RTC_ALRMAR_MNT_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 5443 #define RTC_ALRMAR_MNT_2 0x00004000U
sahilmgandhi 18:6a4db94011d3 5444 #define RTC_ALRMAR_MNU 0x00000F00U
sahilmgandhi 18:6a4db94011d3 5445 #define RTC_ALRMAR_MNU_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 5446 #define RTC_ALRMAR_MNU_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 5447 #define RTC_ALRMAR_MNU_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 5448 #define RTC_ALRMAR_MNU_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 5449 #define RTC_ALRMAR_MSK1 0x00000080U
sahilmgandhi 18:6a4db94011d3 5450 #define RTC_ALRMAR_ST 0x00000070U
sahilmgandhi 18:6a4db94011d3 5451 #define RTC_ALRMAR_ST_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 5452 #define RTC_ALRMAR_ST_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 5453 #define RTC_ALRMAR_ST_2 0x00000040U
sahilmgandhi 18:6a4db94011d3 5454 #define RTC_ALRMAR_SU 0x0000000FU
sahilmgandhi 18:6a4db94011d3 5455 #define RTC_ALRMAR_SU_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 5456 #define RTC_ALRMAR_SU_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 5457 #define RTC_ALRMAR_SU_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 5458 #define RTC_ALRMAR_SU_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 5459
sahilmgandhi 18:6a4db94011d3 5460 /******************** Bits definition for RTC_ALRMBR register ***************/
sahilmgandhi 18:6a4db94011d3 5461 #define RTC_ALRMBR_MSK4 0x80000000U
sahilmgandhi 18:6a4db94011d3 5462 #define RTC_ALRMBR_WDSEL 0x40000000U
sahilmgandhi 18:6a4db94011d3 5463 #define RTC_ALRMBR_DT 0x30000000U
sahilmgandhi 18:6a4db94011d3 5464 #define RTC_ALRMBR_DT_0 0x10000000U
sahilmgandhi 18:6a4db94011d3 5465 #define RTC_ALRMBR_DT_1 0x20000000U
sahilmgandhi 18:6a4db94011d3 5466 #define RTC_ALRMBR_DU 0x0F000000U
sahilmgandhi 18:6a4db94011d3 5467 #define RTC_ALRMBR_DU_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 5468 #define RTC_ALRMBR_DU_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 5469 #define RTC_ALRMBR_DU_2 0x04000000U
sahilmgandhi 18:6a4db94011d3 5470 #define RTC_ALRMBR_DU_3 0x08000000U
sahilmgandhi 18:6a4db94011d3 5471 #define RTC_ALRMBR_MSK3 0x00800000U
sahilmgandhi 18:6a4db94011d3 5472 #define RTC_ALRMBR_PM 0x00400000U
sahilmgandhi 18:6a4db94011d3 5473 #define RTC_ALRMBR_HT 0x00300000U
sahilmgandhi 18:6a4db94011d3 5474 #define RTC_ALRMBR_HT_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 5475 #define RTC_ALRMBR_HT_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 5476 #define RTC_ALRMBR_HU 0x000F0000U
sahilmgandhi 18:6a4db94011d3 5477 #define RTC_ALRMBR_HU_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 5478 #define RTC_ALRMBR_HU_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 5479 #define RTC_ALRMBR_HU_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 5480 #define RTC_ALRMBR_HU_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 5481 #define RTC_ALRMBR_MSK2 0x00008000U
sahilmgandhi 18:6a4db94011d3 5482 #define RTC_ALRMBR_MNT 0x00007000U
sahilmgandhi 18:6a4db94011d3 5483 #define RTC_ALRMBR_MNT_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 5484 #define RTC_ALRMBR_MNT_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 5485 #define RTC_ALRMBR_MNT_2 0x00004000U
sahilmgandhi 18:6a4db94011d3 5486 #define RTC_ALRMBR_MNU 0x00000F00U
sahilmgandhi 18:6a4db94011d3 5487 #define RTC_ALRMBR_MNU_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 5488 #define RTC_ALRMBR_MNU_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 5489 #define RTC_ALRMBR_MNU_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 5490 #define RTC_ALRMBR_MNU_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 5491 #define RTC_ALRMBR_MSK1 0x00000080U
sahilmgandhi 18:6a4db94011d3 5492 #define RTC_ALRMBR_ST 0x00000070U
sahilmgandhi 18:6a4db94011d3 5493 #define RTC_ALRMBR_ST_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 5494 #define RTC_ALRMBR_ST_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 5495 #define RTC_ALRMBR_ST_2 0x00000040U
sahilmgandhi 18:6a4db94011d3 5496 #define RTC_ALRMBR_SU 0x0000000FU
sahilmgandhi 18:6a4db94011d3 5497 #define RTC_ALRMBR_SU_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 5498 #define RTC_ALRMBR_SU_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 5499 #define RTC_ALRMBR_SU_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 5500 #define RTC_ALRMBR_SU_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 5501
sahilmgandhi 18:6a4db94011d3 5502 /******************** Bits definition for RTC_WPR register ******************/
sahilmgandhi 18:6a4db94011d3 5503 #define RTC_WPR_KEY 0x000000FFU
sahilmgandhi 18:6a4db94011d3 5504
sahilmgandhi 18:6a4db94011d3 5505 /******************** Bits definition for RTC_SSR register ******************/
sahilmgandhi 18:6a4db94011d3 5506 #define RTC_SSR_SS 0x0000FFFFU
sahilmgandhi 18:6a4db94011d3 5507
sahilmgandhi 18:6a4db94011d3 5508 /******************** Bits definition for RTC_SHIFTR register ***************/
sahilmgandhi 18:6a4db94011d3 5509 #define RTC_SHIFTR_SUBFS 0x00007FFFU
sahilmgandhi 18:6a4db94011d3 5510 #define RTC_SHIFTR_ADD1S 0x80000000U
sahilmgandhi 18:6a4db94011d3 5511
sahilmgandhi 18:6a4db94011d3 5512 /******************** Bits definition for RTC_TSTR register *****************/
sahilmgandhi 18:6a4db94011d3 5513 #define RTC_TSTR_PM 0x00400000U
sahilmgandhi 18:6a4db94011d3 5514 #define RTC_TSTR_HT 0x00300000U
sahilmgandhi 18:6a4db94011d3 5515 #define RTC_TSTR_HT_0 0x00100000U
sahilmgandhi 18:6a4db94011d3 5516 #define RTC_TSTR_HT_1 0x00200000U
sahilmgandhi 18:6a4db94011d3 5517 #define RTC_TSTR_HU 0x000F0000U
sahilmgandhi 18:6a4db94011d3 5518 #define RTC_TSTR_HU_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 5519 #define RTC_TSTR_HU_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 5520 #define RTC_TSTR_HU_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 5521 #define RTC_TSTR_HU_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 5522 #define RTC_TSTR_MNT 0x00007000U
sahilmgandhi 18:6a4db94011d3 5523 #define RTC_TSTR_MNT_0 0x00001000U
sahilmgandhi 18:6a4db94011d3 5524 #define RTC_TSTR_MNT_1 0x00002000U
sahilmgandhi 18:6a4db94011d3 5525 #define RTC_TSTR_MNT_2 0x00004000U
sahilmgandhi 18:6a4db94011d3 5526 #define RTC_TSTR_MNU 0x00000F00U
sahilmgandhi 18:6a4db94011d3 5527 #define RTC_TSTR_MNU_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 5528 #define RTC_TSTR_MNU_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 5529 #define RTC_TSTR_MNU_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 5530 #define RTC_TSTR_MNU_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 5531 #define RTC_TSTR_ST 0x00000070U
sahilmgandhi 18:6a4db94011d3 5532 #define RTC_TSTR_ST_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 5533 #define RTC_TSTR_ST_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 5534 #define RTC_TSTR_ST_2 0x00000040U
sahilmgandhi 18:6a4db94011d3 5535 #define RTC_TSTR_SU 0x0000000FU
sahilmgandhi 18:6a4db94011d3 5536 #define RTC_TSTR_SU_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 5537 #define RTC_TSTR_SU_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 5538 #define RTC_TSTR_SU_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 5539 #define RTC_TSTR_SU_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 5540
sahilmgandhi 18:6a4db94011d3 5541 /******************** Bits definition for RTC_TSDR register *****************/
sahilmgandhi 18:6a4db94011d3 5542 #define RTC_TSDR_WDU 0x0000E000U
sahilmgandhi 18:6a4db94011d3 5543 #define RTC_TSDR_WDU_0 0x00002000U
sahilmgandhi 18:6a4db94011d3 5544 #define RTC_TSDR_WDU_1 0x00004000U
sahilmgandhi 18:6a4db94011d3 5545 #define RTC_TSDR_WDU_2 0x00008000U
sahilmgandhi 18:6a4db94011d3 5546 #define RTC_TSDR_MT 0x00001000U
sahilmgandhi 18:6a4db94011d3 5547 #define RTC_TSDR_MU 0x00000F00U
sahilmgandhi 18:6a4db94011d3 5548 #define RTC_TSDR_MU_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 5549 #define RTC_TSDR_MU_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 5550 #define RTC_TSDR_MU_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 5551 #define RTC_TSDR_MU_3 0x00000800U
sahilmgandhi 18:6a4db94011d3 5552 #define RTC_TSDR_DT 0x00000030U
sahilmgandhi 18:6a4db94011d3 5553 #define RTC_TSDR_DT_0 0x00000010U
sahilmgandhi 18:6a4db94011d3 5554 #define RTC_TSDR_DT_1 0x00000020U
sahilmgandhi 18:6a4db94011d3 5555 #define RTC_TSDR_DU 0x0000000FU
sahilmgandhi 18:6a4db94011d3 5556 #define RTC_TSDR_DU_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 5557 #define RTC_TSDR_DU_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 5558 #define RTC_TSDR_DU_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 5559 #define RTC_TSDR_DU_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 5560
sahilmgandhi 18:6a4db94011d3 5561 /******************** Bits definition for RTC_TSSSR register ****************/
sahilmgandhi 18:6a4db94011d3 5562 #define RTC_TSSSR_SS 0x0000FFFFU
sahilmgandhi 18:6a4db94011d3 5563
sahilmgandhi 18:6a4db94011d3 5564 /******************** Bits definition for RTC_CAL register *****************/
sahilmgandhi 18:6a4db94011d3 5565 #define RTC_CALR_CALP 0x00008000U
sahilmgandhi 18:6a4db94011d3 5566 #define RTC_CALR_CALW8 0x00004000U
sahilmgandhi 18:6a4db94011d3 5567 #define RTC_CALR_CALW16 0x00002000U
sahilmgandhi 18:6a4db94011d3 5568 #define RTC_CALR_CALM 0x000001FFU
sahilmgandhi 18:6a4db94011d3 5569 #define RTC_CALR_CALM_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 5570 #define RTC_CALR_CALM_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 5571 #define RTC_CALR_CALM_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 5572 #define RTC_CALR_CALM_3 0x00000008U
sahilmgandhi 18:6a4db94011d3 5573 #define RTC_CALR_CALM_4 0x00000010U
sahilmgandhi 18:6a4db94011d3 5574 #define RTC_CALR_CALM_5 0x00000020U
sahilmgandhi 18:6a4db94011d3 5575 #define RTC_CALR_CALM_6 0x00000040U
sahilmgandhi 18:6a4db94011d3 5576 #define RTC_CALR_CALM_7 0x00000080U
sahilmgandhi 18:6a4db94011d3 5577 #define RTC_CALR_CALM_8 0x00000100U
sahilmgandhi 18:6a4db94011d3 5578
sahilmgandhi 18:6a4db94011d3 5579 /******************** Bits definition for RTC_TAFCR register ****************/
sahilmgandhi 18:6a4db94011d3 5580 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
sahilmgandhi 18:6a4db94011d3 5581 #define RTC_TAFCR_TSINSEL 0x00020000U
sahilmgandhi 18:6a4db94011d3 5582 #define RTC_TAFCR_TAMPINSEL 0x00010000U
sahilmgandhi 18:6a4db94011d3 5583 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
sahilmgandhi 18:6a4db94011d3 5584 #define RTC_TAFCR_TAMPPRCH 0x00006000U
sahilmgandhi 18:6a4db94011d3 5585 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
sahilmgandhi 18:6a4db94011d3 5586 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
sahilmgandhi 18:6a4db94011d3 5587 #define RTC_TAFCR_TAMPFLT 0x00001800U
sahilmgandhi 18:6a4db94011d3 5588 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
sahilmgandhi 18:6a4db94011d3 5589 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
sahilmgandhi 18:6a4db94011d3 5590 #define RTC_TAFCR_TAMPFREQ 0x00000700U
sahilmgandhi 18:6a4db94011d3 5591 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 5592 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 5593 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
sahilmgandhi 18:6a4db94011d3 5594 #define RTC_TAFCR_TAMPTS 0x00000080U
sahilmgandhi 18:6a4db94011d3 5595 #define RTC_TAFCR_TAMP2TRG 0x00000010U
sahilmgandhi 18:6a4db94011d3 5596 #define RTC_TAFCR_TAMP2E 0x00000008U
sahilmgandhi 18:6a4db94011d3 5597 #define RTC_TAFCR_TAMPIE 0x00000004U
sahilmgandhi 18:6a4db94011d3 5598 #define RTC_TAFCR_TAMP1TRG 0x00000002U
sahilmgandhi 18:6a4db94011d3 5599 #define RTC_TAFCR_TAMP1E 0x00000001U
sahilmgandhi 18:6a4db94011d3 5600
sahilmgandhi 18:6a4db94011d3 5601 /******************** Bits definition for RTC_ALRMASSR register *************/
sahilmgandhi 18:6a4db94011d3 5602 #define RTC_ALRMASSR_MASKSS 0x0F000000U
sahilmgandhi 18:6a4db94011d3 5603 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 5604 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 5605 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
sahilmgandhi 18:6a4db94011d3 5606 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
sahilmgandhi 18:6a4db94011d3 5607 #define RTC_ALRMASSR_SS 0x00007FFFU
sahilmgandhi 18:6a4db94011d3 5608
sahilmgandhi 18:6a4db94011d3 5609 /******************** Bits definition for RTC_ALRMBSSR register *************/
sahilmgandhi 18:6a4db94011d3 5610 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
sahilmgandhi 18:6a4db94011d3 5611 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
sahilmgandhi 18:6a4db94011d3 5612 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
sahilmgandhi 18:6a4db94011d3 5613 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
sahilmgandhi 18:6a4db94011d3 5614 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
sahilmgandhi 18:6a4db94011d3 5615 #define RTC_ALRMBSSR_SS 0x00007FFFU
sahilmgandhi 18:6a4db94011d3 5616
sahilmgandhi 18:6a4db94011d3 5617 /******************** Bits definition for RTC_BKP0R register ****************/
sahilmgandhi 18:6a4db94011d3 5618 #define RTC_BKP0R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5619
sahilmgandhi 18:6a4db94011d3 5620 /******************** Bits definition for RTC_BKP1R register ****************/
sahilmgandhi 18:6a4db94011d3 5621 #define RTC_BKP1R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5622
sahilmgandhi 18:6a4db94011d3 5623 /******************** Bits definition for RTC_BKP2R register ****************/
sahilmgandhi 18:6a4db94011d3 5624 #define RTC_BKP2R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5625
sahilmgandhi 18:6a4db94011d3 5626 /******************** Bits definition for RTC_BKP3R register ****************/
sahilmgandhi 18:6a4db94011d3 5627 #define RTC_BKP3R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5628
sahilmgandhi 18:6a4db94011d3 5629 /******************** Bits definition for RTC_BKP4R register ****************/
sahilmgandhi 18:6a4db94011d3 5630 #define RTC_BKP4R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5631
sahilmgandhi 18:6a4db94011d3 5632 /******************** Bits definition for RTC_BKP5R register ****************/
sahilmgandhi 18:6a4db94011d3 5633 #define RTC_BKP5R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5634
sahilmgandhi 18:6a4db94011d3 5635 /******************** Bits definition for RTC_BKP6R register ****************/
sahilmgandhi 18:6a4db94011d3 5636 #define RTC_BKP6R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5637
sahilmgandhi 18:6a4db94011d3 5638 /******************** Bits definition for RTC_BKP7R register ****************/
sahilmgandhi 18:6a4db94011d3 5639 #define RTC_BKP7R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5640
sahilmgandhi 18:6a4db94011d3 5641 /******************** Bits definition for RTC_BKP8R register ****************/
sahilmgandhi 18:6a4db94011d3 5642 #define RTC_BKP8R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5643
sahilmgandhi 18:6a4db94011d3 5644 /******************** Bits definition for RTC_BKP9R register ****************/
sahilmgandhi 18:6a4db94011d3 5645 #define RTC_BKP9R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5646
sahilmgandhi 18:6a4db94011d3 5647 /******************** Bits definition for RTC_BKP10R register ***************/
sahilmgandhi 18:6a4db94011d3 5648 #define RTC_BKP10R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5649
sahilmgandhi 18:6a4db94011d3 5650 /******************** Bits definition for RTC_BKP11R register ***************/
sahilmgandhi 18:6a4db94011d3 5651 #define RTC_BKP11R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5652
sahilmgandhi 18:6a4db94011d3 5653 /******************** Bits definition for RTC_BKP12R register ***************/
sahilmgandhi 18:6a4db94011d3 5654 #define RTC_BKP12R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5655
sahilmgandhi 18:6a4db94011d3 5656 /******************** Bits definition for RTC_BKP13R register ***************/
sahilmgandhi 18:6a4db94011d3 5657 #define RTC_BKP13R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5658
sahilmgandhi 18:6a4db94011d3 5659 /******************** Bits definition for RTC_BKP14R register ***************/
sahilmgandhi 18:6a4db94011d3 5660 #define RTC_BKP14R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5661
sahilmgandhi 18:6a4db94011d3 5662 /******************** Bits definition for RTC_BKP15R register ***************/
sahilmgandhi 18:6a4db94011d3 5663 #define RTC_BKP15R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5664
sahilmgandhi 18:6a4db94011d3 5665 /******************** Bits definition for RTC_BKP16R register ***************/
sahilmgandhi 18:6a4db94011d3 5666 #define RTC_BKP16R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5667
sahilmgandhi 18:6a4db94011d3 5668 /******************** Bits definition for RTC_BKP17R register ***************/
sahilmgandhi 18:6a4db94011d3 5669 #define RTC_BKP17R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5670
sahilmgandhi 18:6a4db94011d3 5671 /******************** Bits definition for RTC_BKP18R register ***************/
sahilmgandhi 18:6a4db94011d3 5672 #define RTC_BKP18R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5673
sahilmgandhi 18:6a4db94011d3 5674 /******************** Bits definition for RTC_BKP19R register ***************/
sahilmgandhi 18:6a4db94011d3 5675 #define RTC_BKP19R 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 5676
sahilmgandhi 18:6a4db94011d3 5677
sahilmgandhi 18:6a4db94011d3 5678
sahilmgandhi 18:6a4db94011d3 5679 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5680 /* */
sahilmgandhi 18:6a4db94011d3 5681 /* SD host Interface */
sahilmgandhi 18:6a4db94011d3 5682 /* */
sahilmgandhi 18:6a4db94011d3 5683 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5684 /****************** Bit definition for SDIO_POWER register ******************/
sahilmgandhi 18:6a4db94011d3 5685 #define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
sahilmgandhi 18:6a4db94011d3 5686 #define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 5687 #define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 5688
sahilmgandhi 18:6a4db94011d3 5689 /****************** Bit definition for SDIO_CLKCR register ******************/
sahilmgandhi 18:6a4db94011d3 5690 #define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
sahilmgandhi 18:6a4db94011d3 5691 #define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
sahilmgandhi 18:6a4db94011d3 5692 #define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
sahilmgandhi 18:6a4db94011d3 5693 #define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
sahilmgandhi 18:6a4db94011d3 5694
sahilmgandhi 18:6a4db94011d3 5695 #define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
sahilmgandhi 18:6a4db94011d3 5696 #define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 5697 #define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 5698
sahilmgandhi 18:6a4db94011d3 5699 #define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
sahilmgandhi 18:6a4db94011d3 5700 #define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
sahilmgandhi 18:6a4db94011d3 5701
sahilmgandhi 18:6a4db94011d3 5702 /******************* Bit definition for SDIO_ARG register *******************/
sahilmgandhi 18:6a4db94011d3 5703 #define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
sahilmgandhi 18:6a4db94011d3 5704
sahilmgandhi 18:6a4db94011d3 5705 /******************* Bit definition for SDIO_CMD register *******************/
sahilmgandhi 18:6a4db94011d3 5706 #define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
sahilmgandhi 18:6a4db94011d3 5707
sahilmgandhi 18:6a4db94011d3 5708 #define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
sahilmgandhi 18:6a4db94011d3 5709 #define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 5710 #define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 5711
sahilmgandhi 18:6a4db94011d3 5712 #define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
sahilmgandhi 18:6a4db94011d3 5713 #define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
sahilmgandhi 18:6a4db94011d3 5714 #define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
sahilmgandhi 18:6a4db94011d3 5715 #define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
sahilmgandhi 18:6a4db94011d3 5716 #define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
sahilmgandhi 18:6a4db94011d3 5717 #define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5718 #define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
sahilmgandhi 18:6a4db94011d3 5719
sahilmgandhi 18:6a4db94011d3 5720 /***************** Bit definition for SDIO_RESPCMD register *****************/
sahilmgandhi 18:6a4db94011d3 5721 #define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
sahilmgandhi 18:6a4db94011d3 5722
sahilmgandhi 18:6a4db94011d3 5723 /****************** Bit definition for SDIO_RESP0 register ******************/
sahilmgandhi 18:6a4db94011d3 5724 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 5725
sahilmgandhi 18:6a4db94011d3 5726 /****************** Bit definition for SDIO_RESP1 register ******************/
sahilmgandhi 18:6a4db94011d3 5727 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 5728
sahilmgandhi 18:6a4db94011d3 5729 /****************** Bit definition for SDIO_RESP2 register ******************/
sahilmgandhi 18:6a4db94011d3 5730 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 5731
sahilmgandhi 18:6a4db94011d3 5732 /****************** Bit definition for SDIO_RESP3 register ******************/
sahilmgandhi 18:6a4db94011d3 5733 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 5734
sahilmgandhi 18:6a4db94011d3 5735 /****************** Bit definition for SDIO_RESP4 register ******************/
sahilmgandhi 18:6a4db94011d3 5736 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 5737
sahilmgandhi 18:6a4db94011d3 5738 /****************** Bit definition for SDIO_DTIMER register *****************/
sahilmgandhi 18:6a4db94011d3 5739 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
sahilmgandhi 18:6a4db94011d3 5740
sahilmgandhi 18:6a4db94011d3 5741 /****************** Bit definition for SDIO_DLEN register *******************/
sahilmgandhi 18:6a4db94011d3 5742 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
sahilmgandhi 18:6a4db94011d3 5743
sahilmgandhi 18:6a4db94011d3 5744 /****************** Bit definition for SDIO_DCTRL register ******************/
sahilmgandhi 18:6a4db94011d3 5745 #define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
sahilmgandhi 18:6a4db94011d3 5746 #define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
sahilmgandhi 18:6a4db94011d3 5747 #define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
sahilmgandhi 18:6a4db94011d3 5748 #define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
sahilmgandhi 18:6a4db94011d3 5749
sahilmgandhi 18:6a4db94011d3 5750 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
sahilmgandhi 18:6a4db94011d3 5751 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 5752 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 5753 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 5754 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 5755
sahilmgandhi 18:6a4db94011d3 5756 #define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
sahilmgandhi 18:6a4db94011d3 5757 #define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
sahilmgandhi 18:6a4db94011d3 5758 #define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
sahilmgandhi 18:6a4db94011d3 5759 #define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
sahilmgandhi 18:6a4db94011d3 5760
sahilmgandhi 18:6a4db94011d3 5761 /****************** Bit definition for SDIO_DCOUNT register *****************/
sahilmgandhi 18:6a4db94011d3 5762 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
sahilmgandhi 18:6a4db94011d3 5763
sahilmgandhi 18:6a4db94011d3 5764 /****************** Bit definition for SDIO_STA register ********************/
sahilmgandhi 18:6a4db94011d3 5765 #define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
sahilmgandhi 18:6a4db94011d3 5766 #define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
sahilmgandhi 18:6a4db94011d3 5767 #define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
sahilmgandhi 18:6a4db94011d3 5768 #define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
sahilmgandhi 18:6a4db94011d3 5769 #define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
sahilmgandhi 18:6a4db94011d3 5770 #define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
sahilmgandhi 18:6a4db94011d3 5771 #define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
sahilmgandhi 18:6a4db94011d3 5772 #define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
sahilmgandhi 18:6a4db94011d3 5773 #define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
sahilmgandhi 18:6a4db94011d3 5774 #define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
sahilmgandhi 18:6a4db94011d3 5775 #define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
sahilmgandhi 18:6a4db94011d3 5776 #define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
sahilmgandhi 18:6a4db94011d3 5777 #define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
sahilmgandhi 18:6a4db94011d3 5778 #define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
sahilmgandhi 18:6a4db94011d3 5779 #define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
sahilmgandhi 18:6a4db94011d3 5780 #define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
sahilmgandhi 18:6a4db94011d3 5781 #define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
sahilmgandhi 18:6a4db94011d3 5782 #define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
sahilmgandhi 18:6a4db94011d3 5783 #define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
sahilmgandhi 18:6a4db94011d3 5784 #define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
sahilmgandhi 18:6a4db94011d3 5785 #define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
sahilmgandhi 18:6a4db94011d3 5786 #define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
sahilmgandhi 18:6a4db94011d3 5787 #define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
sahilmgandhi 18:6a4db94011d3 5788 #define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
sahilmgandhi 18:6a4db94011d3 5789
sahilmgandhi 18:6a4db94011d3 5790 /******************* Bit definition for SDIO_ICR register *******************/
sahilmgandhi 18:6a4db94011d3 5791 #define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
sahilmgandhi 18:6a4db94011d3 5792 #define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
sahilmgandhi 18:6a4db94011d3 5793 #define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
sahilmgandhi 18:6a4db94011d3 5794 #define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
sahilmgandhi 18:6a4db94011d3 5795 #define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
sahilmgandhi 18:6a4db94011d3 5796 #define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
sahilmgandhi 18:6a4db94011d3 5797 #define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
sahilmgandhi 18:6a4db94011d3 5798 #define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
sahilmgandhi 18:6a4db94011d3 5799 #define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
sahilmgandhi 18:6a4db94011d3 5800 #define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
sahilmgandhi 18:6a4db94011d3 5801 #define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
sahilmgandhi 18:6a4db94011d3 5802 #define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
sahilmgandhi 18:6a4db94011d3 5803 #define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
sahilmgandhi 18:6a4db94011d3 5804
sahilmgandhi 18:6a4db94011d3 5805 /****************** Bit definition for SDIO_MASK register *******************/
sahilmgandhi 18:6a4db94011d3 5806 #define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5807 #define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5808 #define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5809 #define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5810 #define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5811 #define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5812 #define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5813 #define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5814 #define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5815 #define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5816 #define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5817 #define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5818 #define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5819 #define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
sahilmgandhi 18:6a4db94011d3 5820 #define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5821 #define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5822 #define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5823 #define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5824 #define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5825 #define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5826 #define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5827 #define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5828 #define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5829 #define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5830
sahilmgandhi 18:6a4db94011d3 5831 /***************** Bit definition for SDIO_FIFOCNT register *****************/
sahilmgandhi 18:6a4db94011d3 5832 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
sahilmgandhi 18:6a4db94011d3 5833
sahilmgandhi 18:6a4db94011d3 5834 /****************** Bit definition for SDIO_FIFO register *******************/
sahilmgandhi 18:6a4db94011d3 5835 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
sahilmgandhi 18:6a4db94011d3 5836
sahilmgandhi 18:6a4db94011d3 5837 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5838 /* */
sahilmgandhi 18:6a4db94011d3 5839 /* Serial Peripheral Interface */
sahilmgandhi 18:6a4db94011d3 5840 /* */
sahilmgandhi 18:6a4db94011d3 5841 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5842 /******************* Bit definition for SPI_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 5843 #define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
sahilmgandhi 18:6a4db94011d3 5844 #define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
sahilmgandhi 18:6a4db94011d3 5845 #define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
sahilmgandhi 18:6a4db94011d3 5846
sahilmgandhi 18:6a4db94011d3 5847 #define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
sahilmgandhi 18:6a4db94011d3 5848 #define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 5849 #define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 5850 #define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 5851
sahilmgandhi 18:6a4db94011d3 5852 #define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
sahilmgandhi 18:6a4db94011d3 5853 #define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
sahilmgandhi 18:6a4db94011d3 5854 #define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
sahilmgandhi 18:6a4db94011d3 5855 #define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
sahilmgandhi 18:6a4db94011d3 5856 #define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
sahilmgandhi 18:6a4db94011d3 5857 #define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
sahilmgandhi 18:6a4db94011d3 5858 #define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
sahilmgandhi 18:6a4db94011d3 5859 #define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
sahilmgandhi 18:6a4db94011d3 5860 #define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
sahilmgandhi 18:6a4db94011d3 5861 #define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
sahilmgandhi 18:6a4db94011d3 5862
sahilmgandhi 18:6a4db94011d3 5863 /******************* Bit definition for SPI_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 5864 #define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
sahilmgandhi 18:6a4db94011d3 5865 #define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
sahilmgandhi 18:6a4db94011d3 5866 #define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
sahilmgandhi 18:6a4db94011d3 5867 #define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
sahilmgandhi 18:6a4db94011d3 5868 #define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5869 #define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5870 #define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5871
sahilmgandhi 18:6a4db94011d3 5872 /******************** Bit definition for SPI_SR register ********************/
sahilmgandhi 18:6a4db94011d3 5873 #define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
sahilmgandhi 18:6a4db94011d3 5874 #define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
sahilmgandhi 18:6a4db94011d3 5875 #define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
sahilmgandhi 18:6a4db94011d3 5876 #define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
sahilmgandhi 18:6a4db94011d3 5877 #define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
sahilmgandhi 18:6a4db94011d3 5878 #define SPI_SR_MODF 0x00000020U /*!<Mode fault */
sahilmgandhi 18:6a4db94011d3 5879 #define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
sahilmgandhi 18:6a4db94011d3 5880 #define SPI_SR_BSY 0x00000080U /*!<Busy flag */
sahilmgandhi 18:6a4db94011d3 5881 #define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
sahilmgandhi 18:6a4db94011d3 5882
sahilmgandhi 18:6a4db94011d3 5883 /******************** Bit definition for SPI_DR register ********************/
sahilmgandhi 18:6a4db94011d3 5884 #define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
sahilmgandhi 18:6a4db94011d3 5885
sahilmgandhi 18:6a4db94011d3 5886 /******************* Bit definition for SPI_CRCPR register ******************/
sahilmgandhi 18:6a4db94011d3 5887 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
sahilmgandhi 18:6a4db94011d3 5888
sahilmgandhi 18:6a4db94011d3 5889 /****************** Bit definition for SPI_RXCRCR register ******************/
sahilmgandhi 18:6a4db94011d3 5890 #define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
sahilmgandhi 18:6a4db94011d3 5891
sahilmgandhi 18:6a4db94011d3 5892 /****************** Bit definition for SPI_TXCRCR register ******************/
sahilmgandhi 18:6a4db94011d3 5893 #define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
sahilmgandhi 18:6a4db94011d3 5894
sahilmgandhi 18:6a4db94011d3 5895 /****************** Bit definition for SPI_I2SCFGR register *****************/
sahilmgandhi 18:6a4db94011d3 5896 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
sahilmgandhi 18:6a4db94011d3 5897
sahilmgandhi 18:6a4db94011d3 5898 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
sahilmgandhi 18:6a4db94011d3 5899 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 5900 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 5901
sahilmgandhi 18:6a4db94011d3 5902 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
sahilmgandhi 18:6a4db94011d3 5903
sahilmgandhi 18:6a4db94011d3 5904 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
sahilmgandhi 18:6a4db94011d3 5905 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 5906 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 5907
sahilmgandhi 18:6a4db94011d3 5908 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
sahilmgandhi 18:6a4db94011d3 5909
sahilmgandhi 18:6a4db94011d3 5910 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
sahilmgandhi 18:6a4db94011d3 5911 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 5912 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 5913
sahilmgandhi 18:6a4db94011d3 5914 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
sahilmgandhi 18:6a4db94011d3 5915 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
sahilmgandhi 18:6a4db94011d3 5916
sahilmgandhi 18:6a4db94011d3 5917 /****************** Bit definition for SPI_I2SPR register *******************/
sahilmgandhi 18:6a4db94011d3 5918 #define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
sahilmgandhi 18:6a4db94011d3 5919 #define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
sahilmgandhi 18:6a4db94011d3 5920 #define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
sahilmgandhi 18:6a4db94011d3 5921
sahilmgandhi 18:6a4db94011d3 5922 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5923 /* */
sahilmgandhi 18:6a4db94011d3 5924 /* SYSCFG */
sahilmgandhi 18:6a4db94011d3 5925 /* */
sahilmgandhi 18:6a4db94011d3 5926 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5927 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
sahilmgandhi 18:6a4db94011d3 5928 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
sahilmgandhi 18:6a4db94011d3 5929 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
sahilmgandhi 18:6a4db94011d3 5930 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
sahilmgandhi 18:6a4db94011d3 5931 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
sahilmgandhi 18:6a4db94011d3 5932
sahilmgandhi 18:6a4db94011d3 5933 /****************** Bit definition for SYSCFG_PMC register ******************/
sahilmgandhi 18:6a4db94011d3 5934 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
sahilmgandhi 18:6a4db94011d3 5935 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 5936 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
sahilmgandhi 18:6a4db94011d3 5937
sahilmgandhi 18:6a4db94011d3 5938 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
sahilmgandhi 18:6a4db94011d3 5939 #define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
sahilmgandhi 18:6a4db94011d3 5940 #define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
sahilmgandhi 18:6a4db94011d3 5941 #define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
sahilmgandhi 18:6a4db94011d3 5942 #define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
sahilmgandhi 18:6a4db94011d3 5943 /**
sahilmgandhi 18:6a4db94011d3 5944 * @brief EXTI0 configuration
sahilmgandhi 18:6a4db94011d3 5945 */
sahilmgandhi 18:6a4db94011d3 5946 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
sahilmgandhi 18:6a4db94011d3 5947 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
sahilmgandhi 18:6a4db94011d3 5948 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
sahilmgandhi 18:6a4db94011d3 5949 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
sahilmgandhi 18:6a4db94011d3 5950 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
sahilmgandhi 18:6a4db94011d3 5951 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
sahilmgandhi 18:6a4db94011d3 5952 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
sahilmgandhi 18:6a4db94011d3 5953 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
sahilmgandhi 18:6a4db94011d3 5954 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
sahilmgandhi 18:6a4db94011d3 5955
sahilmgandhi 18:6a4db94011d3 5956 /**
sahilmgandhi 18:6a4db94011d3 5957 * @brief EXTI1 configuration
sahilmgandhi 18:6a4db94011d3 5958 */
sahilmgandhi 18:6a4db94011d3 5959 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
sahilmgandhi 18:6a4db94011d3 5960 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
sahilmgandhi 18:6a4db94011d3 5961 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
sahilmgandhi 18:6a4db94011d3 5962 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
sahilmgandhi 18:6a4db94011d3 5963 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
sahilmgandhi 18:6a4db94011d3 5964 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
sahilmgandhi 18:6a4db94011d3 5965 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
sahilmgandhi 18:6a4db94011d3 5966 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
sahilmgandhi 18:6a4db94011d3 5967 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
sahilmgandhi 18:6a4db94011d3 5968
sahilmgandhi 18:6a4db94011d3 5969 /**
sahilmgandhi 18:6a4db94011d3 5970 * @brief EXTI2 configuration
sahilmgandhi 18:6a4db94011d3 5971 */
sahilmgandhi 18:6a4db94011d3 5972 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
sahilmgandhi 18:6a4db94011d3 5973 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
sahilmgandhi 18:6a4db94011d3 5974 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
sahilmgandhi 18:6a4db94011d3 5975 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
sahilmgandhi 18:6a4db94011d3 5976 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
sahilmgandhi 18:6a4db94011d3 5977 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
sahilmgandhi 18:6a4db94011d3 5978 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
sahilmgandhi 18:6a4db94011d3 5979 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
sahilmgandhi 18:6a4db94011d3 5980 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
sahilmgandhi 18:6a4db94011d3 5981
sahilmgandhi 18:6a4db94011d3 5982 /**
sahilmgandhi 18:6a4db94011d3 5983 * @brief EXTI3 configuration
sahilmgandhi 18:6a4db94011d3 5984 */
sahilmgandhi 18:6a4db94011d3 5985 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
sahilmgandhi 18:6a4db94011d3 5986 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
sahilmgandhi 18:6a4db94011d3 5987 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
sahilmgandhi 18:6a4db94011d3 5988 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
sahilmgandhi 18:6a4db94011d3 5989 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
sahilmgandhi 18:6a4db94011d3 5990 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
sahilmgandhi 18:6a4db94011d3 5991 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
sahilmgandhi 18:6a4db94011d3 5992 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
sahilmgandhi 18:6a4db94011d3 5993 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
sahilmgandhi 18:6a4db94011d3 5994
sahilmgandhi 18:6a4db94011d3 5995 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
sahilmgandhi 18:6a4db94011d3 5996 #define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
sahilmgandhi 18:6a4db94011d3 5997 #define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
sahilmgandhi 18:6a4db94011d3 5998 #define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
sahilmgandhi 18:6a4db94011d3 5999 #define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
sahilmgandhi 18:6a4db94011d3 6000 /**
sahilmgandhi 18:6a4db94011d3 6001 * @brief EXTI4 configuration
sahilmgandhi 18:6a4db94011d3 6002 */
sahilmgandhi 18:6a4db94011d3 6003 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
sahilmgandhi 18:6a4db94011d3 6004 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
sahilmgandhi 18:6a4db94011d3 6005 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
sahilmgandhi 18:6a4db94011d3 6006 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
sahilmgandhi 18:6a4db94011d3 6007 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
sahilmgandhi 18:6a4db94011d3 6008 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
sahilmgandhi 18:6a4db94011d3 6009 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
sahilmgandhi 18:6a4db94011d3 6010 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
sahilmgandhi 18:6a4db94011d3 6011 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
sahilmgandhi 18:6a4db94011d3 6012
sahilmgandhi 18:6a4db94011d3 6013 /**
sahilmgandhi 18:6a4db94011d3 6014 * @brief EXTI5 configuration
sahilmgandhi 18:6a4db94011d3 6015 */
sahilmgandhi 18:6a4db94011d3 6016 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
sahilmgandhi 18:6a4db94011d3 6017 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
sahilmgandhi 18:6a4db94011d3 6018 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
sahilmgandhi 18:6a4db94011d3 6019 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
sahilmgandhi 18:6a4db94011d3 6020 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
sahilmgandhi 18:6a4db94011d3 6021 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
sahilmgandhi 18:6a4db94011d3 6022 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
sahilmgandhi 18:6a4db94011d3 6023 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
sahilmgandhi 18:6a4db94011d3 6024 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
sahilmgandhi 18:6a4db94011d3 6025
sahilmgandhi 18:6a4db94011d3 6026 /**
sahilmgandhi 18:6a4db94011d3 6027 * @brief EXTI6 configuration
sahilmgandhi 18:6a4db94011d3 6028 */
sahilmgandhi 18:6a4db94011d3 6029 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
sahilmgandhi 18:6a4db94011d3 6030 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
sahilmgandhi 18:6a4db94011d3 6031 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
sahilmgandhi 18:6a4db94011d3 6032 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
sahilmgandhi 18:6a4db94011d3 6033 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
sahilmgandhi 18:6a4db94011d3 6034 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
sahilmgandhi 18:6a4db94011d3 6035 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
sahilmgandhi 18:6a4db94011d3 6036 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
sahilmgandhi 18:6a4db94011d3 6037 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
sahilmgandhi 18:6a4db94011d3 6038
sahilmgandhi 18:6a4db94011d3 6039 /**
sahilmgandhi 18:6a4db94011d3 6040 * @brief EXTI7 configuration
sahilmgandhi 18:6a4db94011d3 6041 */
sahilmgandhi 18:6a4db94011d3 6042 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
sahilmgandhi 18:6a4db94011d3 6043 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
sahilmgandhi 18:6a4db94011d3 6044 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
sahilmgandhi 18:6a4db94011d3 6045 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
sahilmgandhi 18:6a4db94011d3 6046 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
sahilmgandhi 18:6a4db94011d3 6047 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
sahilmgandhi 18:6a4db94011d3 6048 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
sahilmgandhi 18:6a4db94011d3 6049 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
sahilmgandhi 18:6a4db94011d3 6050 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
sahilmgandhi 18:6a4db94011d3 6051
sahilmgandhi 18:6a4db94011d3 6052
sahilmgandhi 18:6a4db94011d3 6053 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
sahilmgandhi 18:6a4db94011d3 6054 #define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
sahilmgandhi 18:6a4db94011d3 6055 #define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
sahilmgandhi 18:6a4db94011d3 6056 #define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
sahilmgandhi 18:6a4db94011d3 6057 #define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
sahilmgandhi 18:6a4db94011d3 6058
sahilmgandhi 18:6a4db94011d3 6059 /**
sahilmgandhi 18:6a4db94011d3 6060 * @brief EXTI8 configuration
sahilmgandhi 18:6a4db94011d3 6061 */
sahilmgandhi 18:6a4db94011d3 6062 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
sahilmgandhi 18:6a4db94011d3 6063 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
sahilmgandhi 18:6a4db94011d3 6064 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
sahilmgandhi 18:6a4db94011d3 6065 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
sahilmgandhi 18:6a4db94011d3 6066 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
sahilmgandhi 18:6a4db94011d3 6067 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
sahilmgandhi 18:6a4db94011d3 6068 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
sahilmgandhi 18:6a4db94011d3 6069 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
sahilmgandhi 18:6a4db94011d3 6070 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
sahilmgandhi 18:6a4db94011d3 6071
sahilmgandhi 18:6a4db94011d3 6072 /**
sahilmgandhi 18:6a4db94011d3 6073 * @brief EXTI9 configuration
sahilmgandhi 18:6a4db94011d3 6074 */
sahilmgandhi 18:6a4db94011d3 6075 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
sahilmgandhi 18:6a4db94011d3 6076 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
sahilmgandhi 18:6a4db94011d3 6077 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
sahilmgandhi 18:6a4db94011d3 6078 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
sahilmgandhi 18:6a4db94011d3 6079 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
sahilmgandhi 18:6a4db94011d3 6080 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
sahilmgandhi 18:6a4db94011d3 6081 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
sahilmgandhi 18:6a4db94011d3 6082 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
sahilmgandhi 18:6a4db94011d3 6083 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
sahilmgandhi 18:6a4db94011d3 6084
sahilmgandhi 18:6a4db94011d3 6085 /**
sahilmgandhi 18:6a4db94011d3 6086 * @brief EXTI10 configuration
sahilmgandhi 18:6a4db94011d3 6087 */
sahilmgandhi 18:6a4db94011d3 6088 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
sahilmgandhi 18:6a4db94011d3 6089 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
sahilmgandhi 18:6a4db94011d3 6090 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
sahilmgandhi 18:6a4db94011d3 6091 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
sahilmgandhi 18:6a4db94011d3 6092 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
sahilmgandhi 18:6a4db94011d3 6093 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
sahilmgandhi 18:6a4db94011d3 6094 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
sahilmgandhi 18:6a4db94011d3 6095 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
sahilmgandhi 18:6a4db94011d3 6096 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
sahilmgandhi 18:6a4db94011d3 6097
sahilmgandhi 18:6a4db94011d3 6098 /**
sahilmgandhi 18:6a4db94011d3 6099 * @brief EXTI11 configuration
sahilmgandhi 18:6a4db94011d3 6100 */
sahilmgandhi 18:6a4db94011d3 6101 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
sahilmgandhi 18:6a4db94011d3 6102 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
sahilmgandhi 18:6a4db94011d3 6103 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
sahilmgandhi 18:6a4db94011d3 6104 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
sahilmgandhi 18:6a4db94011d3 6105 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
sahilmgandhi 18:6a4db94011d3 6106 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
sahilmgandhi 18:6a4db94011d3 6107 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
sahilmgandhi 18:6a4db94011d3 6108 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
sahilmgandhi 18:6a4db94011d3 6109 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
sahilmgandhi 18:6a4db94011d3 6110
sahilmgandhi 18:6a4db94011d3 6111 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
sahilmgandhi 18:6a4db94011d3 6112 #define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
sahilmgandhi 18:6a4db94011d3 6113 #define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
sahilmgandhi 18:6a4db94011d3 6114 #define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
sahilmgandhi 18:6a4db94011d3 6115 #define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
sahilmgandhi 18:6a4db94011d3 6116 /**
sahilmgandhi 18:6a4db94011d3 6117 * @brief EXTI12 configuration
sahilmgandhi 18:6a4db94011d3 6118 */
sahilmgandhi 18:6a4db94011d3 6119 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
sahilmgandhi 18:6a4db94011d3 6120 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
sahilmgandhi 18:6a4db94011d3 6121 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
sahilmgandhi 18:6a4db94011d3 6122 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
sahilmgandhi 18:6a4db94011d3 6123 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
sahilmgandhi 18:6a4db94011d3 6124 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
sahilmgandhi 18:6a4db94011d3 6125 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
sahilmgandhi 18:6a4db94011d3 6126 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
sahilmgandhi 18:6a4db94011d3 6127
sahilmgandhi 18:6a4db94011d3 6128 /**
sahilmgandhi 18:6a4db94011d3 6129 * @brief EXTI13 configuration
sahilmgandhi 18:6a4db94011d3 6130 */
sahilmgandhi 18:6a4db94011d3 6131 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
sahilmgandhi 18:6a4db94011d3 6132 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
sahilmgandhi 18:6a4db94011d3 6133 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
sahilmgandhi 18:6a4db94011d3 6134 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
sahilmgandhi 18:6a4db94011d3 6135 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
sahilmgandhi 18:6a4db94011d3 6136 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
sahilmgandhi 18:6a4db94011d3 6137 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
sahilmgandhi 18:6a4db94011d3 6138 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
sahilmgandhi 18:6a4db94011d3 6139
sahilmgandhi 18:6a4db94011d3 6140 /**
sahilmgandhi 18:6a4db94011d3 6141 * @brief EXTI14 configuration
sahilmgandhi 18:6a4db94011d3 6142 */
sahilmgandhi 18:6a4db94011d3 6143 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
sahilmgandhi 18:6a4db94011d3 6144 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
sahilmgandhi 18:6a4db94011d3 6145 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
sahilmgandhi 18:6a4db94011d3 6146 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
sahilmgandhi 18:6a4db94011d3 6147 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
sahilmgandhi 18:6a4db94011d3 6148 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
sahilmgandhi 18:6a4db94011d3 6149 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
sahilmgandhi 18:6a4db94011d3 6150 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
sahilmgandhi 18:6a4db94011d3 6151
sahilmgandhi 18:6a4db94011d3 6152 /**
sahilmgandhi 18:6a4db94011d3 6153 * @brief EXTI15 configuration
sahilmgandhi 18:6a4db94011d3 6154 */
sahilmgandhi 18:6a4db94011d3 6155 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
sahilmgandhi 18:6a4db94011d3 6156 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
sahilmgandhi 18:6a4db94011d3 6157 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
sahilmgandhi 18:6a4db94011d3 6158 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
sahilmgandhi 18:6a4db94011d3 6159 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
sahilmgandhi 18:6a4db94011d3 6160 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
sahilmgandhi 18:6a4db94011d3 6161 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
sahilmgandhi 18:6a4db94011d3 6162 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
sahilmgandhi 18:6a4db94011d3 6163
sahilmgandhi 18:6a4db94011d3 6164 /****************** Bit definition for SYSCFG_CMPCR register ****************/
sahilmgandhi 18:6a4db94011d3 6165 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
sahilmgandhi 18:6a4db94011d3 6166 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
sahilmgandhi 18:6a4db94011d3 6167
sahilmgandhi 18:6a4db94011d3 6168 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6169 /* */
sahilmgandhi 18:6a4db94011d3 6170 /* TIM */
sahilmgandhi 18:6a4db94011d3 6171 /* */
sahilmgandhi 18:6a4db94011d3 6172 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6173 /******************* Bit definition for TIM_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 6174 #define TIM_CR1_CEN 0x0001U /*!<Counter enable */
sahilmgandhi 18:6a4db94011d3 6175 #define TIM_CR1_UDIS 0x0002U /*!<Update disable */
sahilmgandhi 18:6a4db94011d3 6176 #define TIM_CR1_URS 0x0004U /*!<Update request source */
sahilmgandhi 18:6a4db94011d3 6177 #define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
sahilmgandhi 18:6a4db94011d3 6178 #define TIM_CR1_DIR 0x0010U /*!<Direction */
sahilmgandhi 18:6a4db94011d3 6179
sahilmgandhi 18:6a4db94011d3 6180 #define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
sahilmgandhi 18:6a4db94011d3 6181 #define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6182 #define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6183
sahilmgandhi 18:6a4db94011d3 6184 #define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
sahilmgandhi 18:6a4db94011d3 6185
sahilmgandhi 18:6a4db94011d3 6186 #define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
sahilmgandhi 18:6a4db94011d3 6187 #define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6188 #define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6189
sahilmgandhi 18:6a4db94011d3 6190 /******************* Bit definition for TIM_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 6191 #define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
sahilmgandhi 18:6a4db94011d3 6192 #define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
sahilmgandhi 18:6a4db94011d3 6193 #define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
sahilmgandhi 18:6a4db94011d3 6194
sahilmgandhi 18:6a4db94011d3 6195 #define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
sahilmgandhi 18:6a4db94011d3 6196 #define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6197 #define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6198 #define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6199
sahilmgandhi 18:6a4db94011d3 6200 #define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
sahilmgandhi 18:6a4db94011d3 6201 #define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
sahilmgandhi 18:6a4db94011d3 6202 #define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
sahilmgandhi 18:6a4db94011d3 6203 #define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
sahilmgandhi 18:6a4db94011d3 6204 #define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
sahilmgandhi 18:6a4db94011d3 6205 #define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
sahilmgandhi 18:6a4db94011d3 6206 #define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
sahilmgandhi 18:6a4db94011d3 6207 #define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
sahilmgandhi 18:6a4db94011d3 6208
sahilmgandhi 18:6a4db94011d3 6209 /******************* Bit definition for TIM_SMCR register *******************/
sahilmgandhi 18:6a4db94011d3 6210 #define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
sahilmgandhi 18:6a4db94011d3 6211 #define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6212 #define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6213 #define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6214
sahilmgandhi 18:6a4db94011d3 6215 #define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
sahilmgandhi 18:6a4db94011d3 6216 #define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6217 #define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6218 #define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6219
sahilmgandhi 18:6a4db94011d3 6220 #define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
sahilmgandhi 18:6a4db94011d3 6221
sahilmgandhi 18:6a4db94011d3 6222 #define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
sahilmgandhi 18:6a4db94011d3 6223 #define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6224 #define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6225 #define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6226 #define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 6227
sahilmgandhi 18:6a4db94011d3 6228 #define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
sahilmgandhi 18:6a4db94011d3 6229 #define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6230 #define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6231
sahilmgandhi 18:6a4db94011d3 6232 #define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
sahilmgandhi 18:6a4db94011d3 6233 #define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
sahilmgandhi 18:6a4db94011d3 6234
sahilmgandhi 18:6a4db94011d3 6235 /******************* Bit definition for TIM_DIER register *******************/
sahilmgandhi 18:6a4db94011d3 6236 #define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
sahilmgandhi 18:6a4db94011d3 6237 #define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
sahilmgandhi 18:6a4db94011d3 6238 #define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
sahilmgandhi 18:6a4db94011d3 6239 #define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
sahilmgandhi 18:6a4db94011d3 6240 #define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
sahilmgandhi 18:6a4db94011d3 6241 #define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
sahilmgandhi 18:6a4db94011d3 6242 #define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
sahilmgandhi 18:6a4db94011d3 6243 #define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
sahilmgandhi 18:6a4db94011d3 6244 #define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
sahilmgandhi 18:6a4db94011d3 6245 #define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
sahilmgandhi 18:6a4db94011d3 6246 #define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
sahilmgandhi 18:6a4db94011d3 6247 #define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
sahilmgandhi 18:6a4db94011d3 6248 #define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
sahilmgandhi 18:6a4db94011d3 6249 #define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
sahilmgandhi 18:6a4db94011d3 6250 #define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
sahilmgandhi 18:6a4db94011d3 6251
sahilmgandhi 18:6a4db94011d3 6252 /******************** Bit definition for TIM_SR register ********************/
sahilmgandhi 18:6a4db94011d3 6253 #define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6254 #define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6255 #define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6256 #define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6257 #define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6258 #define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6259 #define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6260 #define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6261 #define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 6262 #define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 6263 #define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 6264 #define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 6265
sahilmgandhi 18:6a4db94011d3 6266 /******************* Bit definition for TIM_EGR register ********************/
sahilmgandhi 18:6a4db94011d3 6267 #define TIM_EGR_UG 0x01U /*!<Update Generation */
sahilmgandhi 18:6a4db94011d3 6268 #define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
sahilmgandhi 18:6a4db94011d3 6269 #define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
sahilmgandhi 18:6a4db94011d3 6270 #define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
sahilmgandhi 18:6a4db94011d3 6271 #define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
sahilmgandhi 18:6a4db94011d3 6272 #define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
sahilmgandhi 18:6a4db94011d3 6273 #define TIM_EGR_TG 0x40U /*!<Trigger Generation */
sahilmgandhi 18:6a4db94011d3 6274 #define TIM_EGR_BG 0x80U /*!<Break Generation */
sahilmgandhi 18:6a4db94011d3 6275
sahilmgandhi 18:6a4db94011d3 6276 /****************** Bit definition for TIM_CCMR1 register *******************/
sahilmgandhi 18:6a4db94011d3 6277 #define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
sahilmgandhi 18:6a4db94011d3 6278 #define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6279 #define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6280
sahilmgandhi 18:6a4db94011d3 6281 #define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
sahilmgandhi 18:6a4db94011d3 6282 #define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
sahilmgandhi 18:6a4db94011d3 6283
sahilmgandhi 18:6a4db94011d3 6284 #define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
sahilmgandhi 18:6a4db94011d3 6285 #define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6286 #define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6287 #define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6288
sahilmgandhi 18:6a4db94011d3 6289 #define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
sahilmgandhi 18:6a4db94011d3 6290
sahilmgandhi 18:6a4db94011d3 6291 #define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
sahilmgandhi 18:6a4db94011d3 6292 #define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6293 #define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6294
sahilmgandhi 18:6a4db94011d3 6295 #define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
sahilmgandhi 18:6a4db94011d3 6296 #define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
sahilmgandhi 18:6a4db94011d3 6297
sahilmgandhi 18:6a4db94011d3 6298 #define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
sahilmgandhi 18:6a4db94011d3 6299 #define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6300 #define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6301 #define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6302
sahilmgandhi 18:6a4db94011d3 6303 #define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
sahilmgandhi 18:6a4db94011d3 6304
sahilmgandhi 18:6a4db94011d3 6305 /*----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 6306
sahilmgandhi 18:6a4db94011d3 6307 #define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
sahilmgandhi 18:6a4db94011d3 6308 #define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6309 #define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6310
sahilmgandhi 18:6a4db94011d3 6311 #define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
sahilmgandhi 18:6a4db94011d3 6312 #define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6313 #define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6314 #define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6315 #define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 6316
sahilmgandhi 18:6a4db94011d3 6317 #define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
sahilmgandhi 18:6a4db94011d3 6318 #define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6319 #define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6320
sahilmgandhi 18:6a4db94011d3 6321 #define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
sahilmgandhi 18:6a4db94011d3 6322 #define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6323 #define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6324 #define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6325 #define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 6326
sahilmgandhi 18:6a4db94011d3 6327 /****************** Bit definition for TIM_CCMR2 register *******************/
sahilmgandhi 18:6a4db94011d3 6328 #define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
sahilmgandhi 18:6a4db94011d3 6329 #define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6330 #define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6331
sahilmgandhi 18:6a4db94011d3 6332 #define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
sahilmgandhi 18:6a4db94011d3 6333 #define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
sahilmgandhi 18:6a4db94011d3 6334
sahilmgandhi 18:6a4db94011d3 6335 #define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
sahilmgandhi 18:6a4db94011d3 6336 #define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6337 #define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6338 #define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6339
sahilmgandhi 18:6a4db94011d3 6340 #define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
sahilmgandhi 18:6a4db94011d3 6341
sahilmgandhi 18:6a4db94011d3 6342 #define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
sahilmgandhi 18:6a4db94011d3 6343 #define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6344 #define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6345
sahilmgandhi 18:6a4db94011d3 6346 #define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
sahilmgandhi 18:6a4db94011d3 6347 #define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
sahilmgandhi 18:6a4db94011d3 6348
sahilmgandhi 18:6a4db94011d3 6349 #define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
sahilmgandhi 18:6a4db94011d3 6350 #define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6351 #define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6352 #define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6353
sahilmgandhi 18:6a4db94011d3 6354 #define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
sahilmgandhi 18:6a4db94011d3 6355
sahilmgandhi 18:6a4db94011d3 6356 /*----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 6357
sahilmgandhi 18:6a4db94011d3 6358 #define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
sahilmgandhi 18:6a4db94011d3 6359 #define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6360 #define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6361
sahilmgandhi 18:6a4db94011d3 6362 #define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
sahilmgandhi 18:6a4db94011d3 6363 #define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6364 #define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6365 #define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6366 #define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 6367
sahilmgandhi 18:6a4db94011d3 6368 #define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
sahilmgandhi 18:6a4db94011d3 6369 #define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6370 #define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6371
sahilmgandhi 18:6a4db94011d3 6372 #define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
sahilmgandhi 18:6a4db94011d3 6373 #define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6374 #define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6375 #define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6376 #define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 6377
sahilmgandhi 18:6a4db94011d3 6378 /******************* Bit definition for TIM_CCER register *******************/
sahilmgandhi 18:6a4db94011d3 6379 #define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
sahilmgandhi 18:6a4db94011d3 6380 #define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
sahilmgandhi 18:6a4db94011d3 6381 #define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
sahilmgandhi 18:6a4db94011d3 6382 #define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 6383 #define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
sahilmgandhi 18:6a4db94011d3 6384 #define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
sahilmgandhi 18:6a4db94011d3 6385 #define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
sahilmgandhi 18:6a4db94011d3 6386 #define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 6387 #define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
sahilmgandhi 18:6a4db94011d3 6388 #define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
sahilmgandhi 18:6a4db94011d3 6389 #define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
sahilmgandhi 18:6a4db94011d3 6390 #define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 6391 #define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
sahilmgandhi 18:6a4db94011d3 6392 #define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
sahilmgandhi 18:6a4db94011d3 6393 #define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 6394
sahilmgandhi 18:6a4db94011d3 6395 /******************* Bit definition for TIM_CNT register ********************/
sahilmgandhi 18:6a4db94011d3 6396 #define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
sahilmgandhi 18:6a4db94011d3 6397
sahilmgandhi 18:6a4db94011d3 6398 /******************* Bit definition for TIM_PSC register ********************/
sahilmgandhi 18:6a4db94011d3 6399 #define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
sahilmgandhi 18:6a4db94011d3 6400
sahilmgandhi 18:6a4db94011d3 6401 /******************* Bit definition for TIM_ARR register ********************/
sahilmgandhi 18:6a4db94011d3 6402 #define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
sahilmgandhi 18:6a4db94011d3 6403
sahilmgandhi 18:6a4db94011d3 6404 /******************* Bit definition for TIM_RCR register ********************/
sahilmgandhi 18:6a4db94011d3 6405 #define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
sahilmgandhi 18:6a4db94011d3 6406
sahilmgandhi 18:6a4db94011d3 6407 /******************* Bit definition for TIM_CCR1 register *******************/
sahilmgandhi 18:6a4db94011d3 6408 #define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
sahilmgandhi 18:6a4db94011d3 6409
sahilmgandhi 18:6a4db94011d3 6410 /******************* Bit definition for TIM_CCR2 register *******************/
sahilmgandhi 18:6a4db94011d3 6411 #define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
sahilmgandhi 18:6a4db94011d3 6412
sahilmgandhi 18:6a4db94011d3 6413 /******************* Bit definition for TIM_CCR3 register *******************/
sahilmgandhi 18:6a4db94011d3 6414 #define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
sahilmgandhi 18:6a4db94011d3 6415
sahilmgandhi 18:6a4db94011d3 6416 /******************* Bit definition for TIM_CCR4 register *******************/
sahilmgandhi 18:6a4db94011d3 6417 #define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
sahilmgandhi 18:6a4db94011d3 6418
sahilmgandhi 18:6a4db94011d3 6419 /******************* Bit definition for TIM_BDTR register *******************/
sahilmgandhi 18:6a4db94011d3 6420 #define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
sahilmgandhi 18:6a4db94011d3 6421 #define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6422 #define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6423 #define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6424 #define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 6425 #define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 6426 #define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 6427 #define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 6428 #define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 6429
sahilmgandhi 18:6a4db94011d3 6430 #define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
sahilmgandhi 18:6a4db94011d3 6431 #define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6432 #define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6433
sahilmgandhi 18:6a4db94011d3 6434 #define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
sahilmgandhi 18:6a4db94011d3 6435 #define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
sahilmgandhi 18:6a4db94011d3 6436 #define TIM_BDTR_BKE 0x1000U /*!<Break enable */
sahilmgandhi 18:6a4db94011d3 6437 #define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
sahilmgandhi 18:6a4db94011d3 6438 #define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
sahilmgandhi 18:6a4db94011d3 6439 #define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
sahilmgandhi 18:6a4db94011d3 6440
sahilmgandhi 18:6a4db94011d3 6441 /******************* Bit definition for TIM_DCR register ********************/
sahilmgandhi 18:6a4db94011d3 6442 #define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
sahilmgandhi 18:6a4db94011d3 6443 #define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6444 #define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6445 #define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6446 #define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 6447 #define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 6448
sahilmgandhi 18:6a4db94011d3 6449 #define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
sahilmgandhi 18:6a4db94011d3 6450 #define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6451 #define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6452 #define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6453 #define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 6454 #define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 6455
sahilmgandhi 18:6a4db94011d3 6456 /******************* Bit definition for TIM_DMAR register *******************/
sahilmgandhi 18:6a4db94011d3 6457 #define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
sahilmgandhi 18:6a4db94011d3 6458
sahilmgandhi 18:6a4db94011d3 6459 /******************* Bit definition for TIM_OR register *********************/
sahilmgandhi 18:6a4db94011d3 6460 #define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
sahilmgandhi 18:6a4db94011d3 6461 #define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6462 #define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6463 #define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
sahilmgandhi 18:6a4db94011d3 6464 #define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6465 #define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6466
sahilmgandhi 18:6a4db94011d3 6467
sahilmgandhi 18:6a4db94011d3 6468 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6469 /* */
sahilmgandhi 18:6a4db94011d3 6470 /* Universal Synchronous Asynchronous Receiver Transmitter */
sahilmgandhi 18:6a4db94011d3 6471 /* */
sahilmgandhi 18:6a4db94011d3 6472 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6473 /******************* Bit definition for USART_SR register *******************/
sahilmgandhi 18:6a4db94011d3 6474 #define USART_SR_PE 0x0001U /*!<Parity Error */
sahilmgandhi 18:6a4db94011d3 6475 #define USART_SR_FE 0x0002U /*!<Framing Error */
sahilmgandhi 18:6a4db94011d3 6476 #define USART_SR_NE 0x0004U /*!<Noise Error Flag */
sahilmgandhi 18:6a4db94011d3 6477 #define USART_SR_ORE 0x0008U /*!<OverRun Error */
sahilmgandhi 18:6a4db94011d3 6478 #define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
sahilmgandhi 18:6a4db94011d3 6479 #define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
sahilmgandhi 18:6a4db94011d3 6480 #define USART_SR_TC 0x0040U /*!<Transmission Complete */
sahilmgandhi 18:6a4db94011d3 6481 #define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
sahilmgandhi 18:6a4db94011d3 6482 #define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
sahilmgandhi 18:6a4db94011d3 6483 #define USART_SR_CTS 0x0200U /*!<CTS Flag */
sahilmgandhi 18:6a4db94011d3 6484
sahilmgandhi 18:6a4db94011d3 6485 /******************* Bit definition for USART_DR register *******************/
sahilmgandhi 18:6a4db94011d3 6486 #define USART_DR_DR 0x01FFU /*!<Data value */
sahilmgandhi 18:6a4db94011d3 6487
sahilmgandhi 18:6a4db94011d3 6488 /****************** Bit definition for USART_BRR register *******************/
sahilmgandhi 18:6a4db94011d3 6489 #define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
sahilmgandhi 18:6a4db94011d3 6490 #define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
sahilmgandhi 18:6a4db94011d3 6491
sahilmgandhi 18:6a4db94011d3 6492 /****************** Bit definition for USART_CR1 register *******************/
sahilmgandhi 18:6a4db94011d3 6493 #define USART_CR1_SBK 0x0001U /*!<Send Break */
sahilmgandhi 18:6a4db94011d3 6494 #define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
sahilmgandhi 18:6a4db94011d3 6495 #define USART_CR1_RE 0x0004U /*!<Receiver Enable */
sahilmgandhi 18:6a4db94011d3 6496 #define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
sahilmgandhi 18:6a4db94011d3 6497 #define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6498 #define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6499 #define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6500 #define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6501 #define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6502 #define USART_CR1_PS 0x0200U /*!<Parity Selection */
sahilmgandhi 18:6a4db94011d3 6503 #define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
sahilmgandhi 18:6a4db94011d3 6504 #define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
sahilmgandhi 18:6a4db94011d3 6505 #define USART_CR1_M 0x1000U /*!<Word length */
sahilmgandhi 18:6a4db94011d3 6506 #define USART_CR1_UE 0x2000U /*!<USART Enable */
sahilmgandhi 18:6a4db94011d3 6507 #define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
sahilmgandhi 18:6a4db94011d3 6508
sahilmgandhi 18:6a4db94011d3 6509 /****************** Bit definition for USART_CR2 register *******************/
sahilmgandhi 18:6a4db94011d3 6510 #define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
sahilmgandhi 18:6a4db94011d3 6511 #define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
sahilmgandhi 18:6a4db94011d3 6512 #define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6513 #define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
sahilmgandhi 18:6a4db94011d3 6514 #define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
sahilmgandhi 18:6a4db94011d3 6515 #define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
sahilmgandhi 18:6a4db94011d3 6516 #define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
sahilmgandhi 18:6a4db94011d3 6517
sahilmgandhi 18:6a4db94011d3 6518 #define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
sahilmgandhi 18:6a4db94011d3 6519 #define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6520 #define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6521
sahilmgandhi 18:6a4db94011d3 6522 #define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
sahilmgandhi 18:6a4db94011d3 6523
sahilmgandhi 18:6a4db94011d3 6524 /****************** Bit definition for USART_CR3 register *******************/
sahilmgandhi 18:6a4db94011d3 6525 #define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6526 #define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
sahilmgandhi 18:6a4db94011d3 6527 #define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
sahilmgandhi 18:6a4db94011d3 6528 #define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
sahilmgandhi 18:6a4db94011d3 6529 #define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
sahilmgandhi 18:6a4db94011d3 6530 #define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
sahilmgandhi 18:6a4db94011d3 6531 #define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
sahilmgandhi 18:6a4db94011d3 6532 #define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
sahilmgandhi 18:6a4db94011d3 6533 #define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
sahilmgandhi 18:6a4db94011d3 6534 #define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
sahilmgandhi 18:6a4db94011d3 6535 #define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6536 #define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
sahilmgandhi 18:6a4db94011d3 6537
sahilmgandhi 18:6a4db94011d3 6538 /****************** Bit definition for USART_GTPR register ******************/
sahilmgandhi 18:6a4db94011d3 6539 #define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
sahilmgandhi 18:6a4db94011d3 6540 #define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6541 #define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6542 #define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6543 #define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 6544 #define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 6545 #define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 6546 #define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 6547 #define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 6548
sahilmgandhi 18:6a4db94011d3 6549 #define USART_GTPR_GT 0xFF00U /*!<Guard time value */
sahilmgandhi 18:6a4db94011d3 6550
sahilmgandhi 18:6a4db94011d3 6551 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6552 /* */
sahilmgandhi 18:6a4db94011d3 6553 /* Window WATCHDOG */
sahilmgandhi 18:6a4db94011d3 6554 /* */
sahilmgandhi 18:6a4db94011d3 6555 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6556 /******************* Bit definition for WWDG_CR register ********************/
sahilmgandhi 18:6a4db94011d3 6557 #define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
sahilmgandhi 18:6a4db94011d3 6558 #define WWDG_CR_T_0 0x01U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6559 #define WWDG_CR_T_1 0x02U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6560 #define WWDG_CR_T_2 0x04U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6561 #define WWDG_CR_T_3 0x08U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 6562 #define WWDG_CR_T_4 0x10U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 6563 #define WWDG_CR_T_5 0x20U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 6564 #define WWDG_CR_T_6 0x40U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 6565 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 6566 #define WWDG_CR_T0 WWDG_CR_T_0
sahilmgandhi 18:6a4db94011d3 6567 #define WWDG_CR_T1 WWDG_CR_T_1
sahilmgandhi 18:6a4db94011d3 6568 #define WWDG_CR_T2 WWDG_CR_T_2
sahilmgandhi 18:6a4db94011d3 6569 #define WWDG_CR_T3 WWDG_CR_T_3
sahilmgandhi 18:6a4db94011d3 6570 #define WWDG_CR_T4 WWDG_CR_T_4
sahilmgandhi 18:6a4db94011d3 6571 #define WWDG_CR_T5 WWDG_CR_T_5
sahilmgandhi 18:6a4db94011d3 6572 #define WWDG_CR_T6 WWDG_CR_T_6
sahilmgandhi 18:6a4db94011d3 6573
sahilmgandhi 18:6a4db94011d3 6574 #define WWDG_CR_WDGA 0x80U /*!<Activation bit */
sahilmgandhi 18:6a4db94011d3 6575
sahilmgandhi 18:6a4db94011d3 6576 /******************* Bit definition for WWDG_CFR register *******************/
sahilmgandhi 18:6a4db94011d3 6577 #define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
sahilmgandhi 18:6a4db94011d3 6578 #define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6579 #define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6580 #define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 6581 #define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 6582 #define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 6583 #define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 6584 #define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 6585 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 6586 #define WWDG_CFR_W0 WWDG_CFR_W_0
sahilmgandhi 18:6a4db94011d3 6587 #define WWDG_CFR_W1 WWDG_CFR_W_1
sahilmgandhi 18:6a4db94011d3 6588 #define WWDG_CFR_W2 WWDG_CFR_W_2
sahilmgandhi 18:6a4db94011d3 6589 #define WWDG_CFR_W3 WWDG_CFR_W_3
sahilmgandhi 18:6a4db94011d3 6590 #define WWDG_CFR_W4 WWDG_CFR_W_4
sahilmgandhi 18:6a4db94011d3 6591 #define WWDG_CFR_W5 WWDG_CFR_W_5
sahilmgandhi 18:6a4db94011d3 6592 #define WWDG_CFR_W6 WWDG_CFR_W_6
sahilmgandhi 18:6a4db94011d3 6593
sahilmgandhi 18:6a4db94011d3 6594 #define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
sahilmgandhi 18:6a4db94011d3 6595 #define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6596 #define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6597 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 6598 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
sahilmgandhi 18:6a4db94011d3 6599 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
sahilmgandhi 18:6a4db94011d3 6600
sahilmgandhi 18:6a4db94011d3 6601 #define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
sahilmgandhi 18:6a4db94011d3 6602
sahilmgandhi 18:6a4db94011d3 6603 /******************* Bit definition for WWDG_SR register ********************/
sahilmgandhi 18:6a4db94011d3 6604 #define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6605
sahilmgandhi 18:6a4db94011d3 6606
sahilmgandhi 18:6a4db94011d3 6607 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6608 /* */
sahilmgandhi 18:6a4db94011d3 6609 /* DBG */
sahilmgandhi 18:6a4db94011d3 6610 /* */
sahilmgandhi 18:6a4db94011d3 6611 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6612 /******************** Bit definition for DBGMCU_IDCODE register *************/
sahilmgandhi 18:6a4db94011d3 6613 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
sahilmgandhi 18:6a4db94011d3 6614 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
sahilmgandhi 18:6a4db94011d3 6615
sahilmgandhi 18:6a4db94011d3 6616 /******************** Bit definition for DBGMCU_CR register *****************/
sahilmgandhi 18:6a4db94011d3 6617 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
sahilmgandhi 18:6a4db94011d3 6618 #define DBGMCU_CR_DBG_STOP 0x00000002U
sahilmgandhi 18:6a4db94011d3 6619 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
sahilmgandhi 18:6a4db94011d3 6620 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
sahilmgandhi 18:6a4db94011d3 6621
sahilmgandhi 18:6a4db94011d3 6622 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
sahilmgandhi 18:6a4db94011d3 6623 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 6624 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 6625
sahilmgandhi 18:6a4db94011d3 6626 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
sahilmgandhi 18:6a4db94011d3 6627 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
sahilmgandhi 18:6a4db94011d3 6628 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
sahilmgandhi 18:6a4db94011d3 6629 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
sahilmgandhi 18:6a4db94011d3 6630 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
sahilmgandhi 18:6a4db94011d3 6631 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
sahilmgandhi 18:6a4db94011d3 6632 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
sahilmgandhi 18:6a4db94011d3 6633 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
sahilmgandhi 18:6a4db94011d3 6634 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
sahilmgandhi 18:6a4db94011d3 6635 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
sahilmgandhi 18:6a4db94011d3 6636 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
sahilmgandhi 18:6a4db94011d3 6637 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
sahilmgandhi 18:6a4db94011d3 6638 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
sahilmgandhi 18:6a4db94011d3 6639 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
sahilmgandhi 18:6a4db94011d3 6640 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
sahilmgandhi 18:6a4db94011d3 6641 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
sahilmgandhi 18:6a4db94011d3 6642 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
sahilmgandhi 18:6a4db94011d3 6643 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
sahilmgandhi 18:6a4db94011d3 6644 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 6645 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
sahilmgandhi 18:6a4db94011d3 6646
sahilmgandhi 18:6a4db94011d3 6647 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
sahilmgandhi 18:6a4db94011d3 6648 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
sahilmgandhi 18:6a4db94011d3 6649 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
sahilmgandhi 18:6a4db94011d3 6650 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
sahilmgandhi 18:6a4db94011d3 6651 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
sahilmgandhi 18:6a4db94011d3 6652 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
sahilmgandhi 18:6a4db94011d3 6653
sahilmgandhi 18:6a4db94011d3 6654 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6655 /* */
sahilmgandhi 18:6a4db94011d3 6656 /* Ethernet MAC Registers bits definitions */
sahilmgandhi 18:6a4db94011d3 6657 /* */
sahilmgandhi 18:6a4db94011d3 6658 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6659 /* Bit definition for Ethernet MAC Control Register register */
sahilmgandhi 18:6a4db94011d3 6660 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
sahilmgandhi 18:6a4db94011d3 6661 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
sahilmgandhi 18:6a4db94011d3 6662 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
sahilmgandhi 18:6a4db94011d3 6663 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
sahilmgandhi 18:6a4db94011d3 6664 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
sahilmgandhi 18:6a4db94011d3 6665 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
sahilmgandhi 18:6a4db94011d3 6666 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
sahilmgandhi 18:6a4db94011d3 6667 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
sahilmgandhi 18:6a4db94011d3 6668 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
sahilmgandhi 18:6a4db94011d3 6669 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
sahilmgandhi 18:6a4db94011d3 6670 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
sahilmgandhi 18:6a4db94011d3 6671 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
sahilmgandhi 18:6a4db94011d3 6672 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
sahilmgandhi 18:6a4db94011d3 6673 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
sahilmgandhi 18:6a4db94011d3 6674 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
sahilmgandhi 18:6a4db94011d3 6675 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
sahilmgandhi 18:6a4db94011d3 6676 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
sahilmgandhi 18:6a4db94011d3 6677 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
sahilmgandhi 18:6a4db94011d3 6678 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
sahilmgandhi 18:6a4db94011d3 6679 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
sahilmgandhi 18:6a4db94011d3 6680 a transmission attempt during retries after a collision: 0 =< r <2^k */
sahilmgandhi 18:6a4db94011d3 6681 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
sahilmgandhi 18:6a4db94011d3 6682 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
sahilmgandhi 18:6a4db94011d3 6683 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
sahilmgandhi 18:6a4db94011d3 6684 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
sahilmgandhi 18:6a4db94011d3 6685 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
sahilmgandhi 18:6a4db94011d3 6686 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
sahilmgandhi 18:6a4db94011d3 6687 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
sahilmgandhi 18:6a4db94011d3 6688
sahilmgandhi 18:6a4db94011d3 6689 /* Bit definition for Ethernet MAC Frame Filter Register */
sahilmgandhi 18:6a4db94011d3 6690 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
sahilmgandhi 18:6a4db94011d3 6691 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
sahilmgandhi 18:6a4db94011d3 6692 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
sahilmgandhi 18:6a4db94011d3 6693 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
sahilmgandhi 18:6a4db94011d3 6694 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
sahilmgandhi 18:6a4db94011d3 6695 #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
sahilmgandhi 18:6a4db94011d3 6696 #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
sahilmgandhi 18:6a4db94011d3 6697 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
sahilmgandhi 18:6a4db94011d3 6698 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
sahilmgandhi 18:6a4db94011d3 6699 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
sahilmgandhi 18:6a4db94011d3 6700 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
sahilmgandhi 18:6a4db94011d3 6701 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
sahilmgandhi 18:6a4db94011d3 6702 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
sahilmgandhi 18:6a4db94011d3 6703 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
sahilmgandhi 18:6a4db94011d3 6704
sahilmgandhi 18:6a4db94011d3 6705 /* Bit definition for Ethernet MAC Hash Table High Register */
sahilmgandhi 18:6a4db94011d3 6706 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
sahilmgandhi 18:6a4db94011d3 6707
sahilmgandhi 18:6a4db94011d3 6708 /* Bit definition for Ethernet MAC Hash Table Low Register */
sahilmgandhi 18:6a4db94011d3 6709 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
sahilmgandhi 18:6a4db94011d3 6710
sahilmgandhi 18:6a4db94011d3 6711 /* Bit definition for Ethernet MAC MII Address Register */
sahilmgandhi 18:6a4db94011d3 6712 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
sahilmgandhi 18:6a4db94011d3 6713 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
sahilmgandhi 18:6a4db94011d3 6714 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
sahilmgandhi 18:6a4db94011d3 6715 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
sahilmgandhi 18:6a4db94011d3 6716 #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
sahilmgandhi 18:6a4db94011d3 6717 #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
sahilmgandhi 18:6a4db94011d3 6718 #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
sahilmgandhi 18:6a4db94011d3 6719 #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
sahilmgandhi 18:6a4db94011d3 6720 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
sahilmgandhi 18:6a4db94011d3 6721 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
sahilmgandhi 18:6a4db94011d3 6722
sahilmgandhi 18:6a4db94011d3 6723 /* Bit definition for Ethernet MAC MII Data Register */
sahilmgandhi 18:6a4db94011d3 6724 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
sahilmgandhi 18:6a4db94011d3 6725
sahilmgandhi 18:6a4db94011d3 6726 /* Bit definition for Ethernet MAC Flow Control Register */
sahilmgandhi 18:6a4db94011d3 6727 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
sahilmgandhi 18:6a4db94011d3 6728 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
sahilmgandhi 18:6a4db94011d3 6729 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
sahilmgandhi 18:6a4db94011d3 6730 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
sahilmgandhi 18:6a4db94011d3 6731 #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
sahilmgandhi 18:6a4db94011d3 6732 #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
sahilmgandhi 18:6a4db94011d3 6733 #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
sahilmgandhi 18:6a4db94011d3 6734 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
sahilmgandhi 18:6a4db94011d3 6735 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
sahilmgandhi 18:6a4db94011d3 6736 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
sahilmgandhi 18:6a4db94011d3 6737 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
sahilmgandhi 18:6a4db94011d3 6738
sahilmgandhi 18:6a4db94011d3 6739 /* Bit definition for Ethernet MAC VLAN Tag Register */
sahilmgandhi 18:6a4db94011d3 6740 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
sahilmgandhi 18:6a4db94011d3 6741 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
sahilmgandhi 18:6a4db94011d3 6742
sahilmgandhi 18:6a4db94011d3 6743 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
sahilmgandhi 18:6a4db94011d3 6744 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
sahilmgandhi 18:6a4db94011d3 6745 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
sahilmgandhi 18:6a4db94011d3 6746 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
sahilmgandhi 18:6a4db94011d3 6747 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
sahilmgandhi 18:6a4db94011d3 6748 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
sahilmgandhi 18:6a4db94011d3 6749 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
sahilmgandhi 18:6a4db94011d3 6750 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
sahilmgandhi 18:6a4db94011d3 6751 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
sahilmgandhi 18:6a4db94011d3 6752 RSVD - Filter1 Command - RSVD - Filter0 Command
sahilmgandhi 18:6a4db94011d3 6753 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
sahilmgandhi 18:6a4db94011d3 6754 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
sahilmgandhi 18:6a4db94011d3 6755 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
sahilmgandhi 18:6a4db94011d3 6756
sahilmgandhi 18:6a4db94011d3 6757 /* Bit definition for Ethernet MAC PMT Control and Status Register */
sahilmgandhi 18:6a4db94011d3 6758 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
sahilmgandhi 18:6a4db94011d3 6759 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
sahilmgandhi 18:6a4db94011d3 6760 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
sahilmgandhi 18:6a4db94011d3 6761 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
sahilmgandhi 18:6a4db94011d3 6762 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
sahilmgandhi 18:6a4db94011d3 6763 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
sahilmgandhi 18:6a4db94011d3 6764 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
sahilmgandhi 18:6a4db94011d3 6765
sahilmgandhi 18:6a4db94011d3 6766 /* Bit definition for Ethernet MAC Status Register */
sahilmgandhi 18:6a4db94011d3 6767 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
sahilmgandhi 18:6a4db94011d3 6768 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
sahilmgandhi 18:6a4db94011d3 6769 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
sahilmgandhi 18:6a4db94011d3 6770 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
sahilmgandhi 18:6a4db94011d3 6771 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
sahilmgandhi 18:6a4db94011d3 6772
sahilmgandhi 18:6a4db94011d3 6773 /* Bit definition for Ethernet MAC Interrupt Mask Register */
sahilmgandhi 18:6a4db94011d3 6774 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
sahilmgandhi 18:6a4db94011d3 6775 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
sahilmgandhi 18:6a4db94011d3 6776
sahilmgandhi 18:6a4db94011d3 6777 /* Bit definition for Ethernet MAC Address0 High Register */
sahilmgandhi 18:6a4db94011d3 6778 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
sahilmgandhi 18:6a4db94011d3 6779
sahilmgandhi 18:6a4db94011d3 6780 /* Bit definition for Ethernet MAC Address0 Low Register */
sahilmgandhi 18:6a4db94011d3 6781 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
sahilmgandhi 18:6a4db94011d3 6782
sahilmgandhi 18:6a4db94011d3 6783 /* Bit definition for Ethernet MAC Address1 High Register */
sahilmgandhi 18:6a4db94011d3 6784 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
sahilmgandhi 18:6a4db94011d3 6785 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
sahilmgandhi 18:6a4db94011d3 6786 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
sahilmgandhi 18:6a4db94011d3 6787 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
sahilmgandhi 18:6a4db94011d3 6788 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
sahilmgandhi 18:6a4db94011d3 6789 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
sahilmgandhi 18:6a4db94011d3 6790 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
sahilmgandhi 18:6a4db94011d3 6791 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
sahilmgandhi 18:6a4db94011d3 6792 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
sahilmgandhi 18:6a4db94011d3 6793 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
sahilmgandhi 18:6a4db94011d3 6794
sahilmgandhi 18:6a4db94011d3 6795 /* Bit definition for Ethernet MAC Address1 Low Register */
sahilmgandhi 18:6a4db94011d3 6796 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
sahilmgandhi 18:6a4db94011d3 6797
sahilmgandhi 18:6a4db94011d3 6798 /* Bit definition for Ethernet MAC Address2 High Register */
sahilmgandhi 18:6a4db94011d3 6799 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
sahilmgandhi 18:6a4db94011d3 6800 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
sahilmgandhi 18:6a4db94011d3 6801 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
sahilmgandhi 18:6a4db94011d3 6802 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
sahilmgandhi 18:6a4db94011d3 6803 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
sahilmgandhi 18:6a4db94011d3 6804 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
sahilmgandhi 18:6a4db94011d3 6805 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
sahilmgandhi 18:6a4db94011d3 6806 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
sahilmgandhi 18:6a4db94011d3 6807 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
sahilmgandhi 18:6a4db94011d3 6808 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
sahilmgandhi 18:6a4db94011d3 6809
sahilmgandhi 18:6a4db94011d3 6810 /* Bit definition for Ethernet MAC Address2 Low Register */
sahilmgandhi 18:6a4db94011d3 6811 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
sahilmgandhi 18:6a4db94011d3 6812
sahilmgandhi 18:6a4db94011d3 6813 /* Bit definition for Ethernet MAC Address3 High Register */
sahilmgandhi 18:6a4db94011d3 6814 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
sahilmgandhi 18:6a4db94011d3 6815 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
sahilmgandhi 18:6a4db94011d3 6816 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
sahilmgandhi 18:6a4db94011d3 6817 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
sahilmgandhi 18:6a4db94011d3 6818 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
sahilmgandhi 18:6a4db94011d3 6819 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
sahilmgandhi 18:6a4db94011d3 6820 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
sahilmgandhi 18:6a4db94011d3 6821 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
sahilmgandhi 18:6a4db94011d3 6822 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
sahilmgandhi 18:6a4db94011d3 6823 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
sahilmgandhi 18:6a4db94011d3 6824
sahilmgandhi 18:6a4db94011d3 6825 /* Bit definition for Ethernet MAC Address3 Low Register */
sahilmgandhi 18:6a4db94011d3 6826 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
sahilmgandhi 18:6a4db94011d3 6827
sahilmgandhi 18:6a4db94011d3 6828 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6829 /* Ethernet MMC Registers bits definition */
sahilmgandhi 18:6a4db94011d3 6830 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6831
sahilmgandhi 18:6a4db94011d3 6832 /* Bit definition for Ethernet MMC Contol Register */
sahilmgandhi 18:6a4db94011d3 6833 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
sahilmgandhi 18:6a4db94011d3 6834 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
sahilmgandhi 18:6a4db94011d3 6835 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
sahilmgandhi 18:6a4db94011d3 6836 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
sahilmgandhi 18:6a4db94011d3 6837 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
sahilmgandhi 18:6a4db94011d3 6838 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
sahilmgandhi 18:6a4db94011d3 6839
sahilmgandhi 18:6a4db94011d3 6840 /* Bit definition for Ethernet MMC Receive Interrupt Register */
sahilmgandhi 18:6a4db94011d3 6841 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 6842 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 6843 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 6844
sahilmgandhi 18:6a4db94011d3 6845 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
sahilmgandhi 18:6a4db94011d3 6846 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 6847 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 6848 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 6849
sahilmgandhi 18:6a4db94011d3 6850 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
sahilmgandhi 18:6a4db94011d3 6851 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 6852 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 6853 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 6854
sahilmgandhi 18:6a4db94011d3 6855 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
sahilmgandhi 18:6a4db94011d3 6856 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 6857 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 6858 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 6859
sahilmgandhi 18:6a4db94011d3 6860 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
sahilmgandhi 18:6a4db94011d3 6861 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
sahilmgandhi 18:6a4db94011d3 6862
sahilmgandhi 18:6a4db94011d3 6863 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
sahilmgandhi 18:6a4db94011d3 6864 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
sahilmgandhi 18:6a4db94011d3 6865
sahilmgandhi 18:6a4db94011d3 6866 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
sahilmgandhi 18:6a4db94011d3 6867 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
sahilmgandhi 18:6a4db94011d3 6868
sahilmgandhi 18:6a4db94011d3 6869 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
sahilmgandhi 18:6a4db94011d3 6870 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
sahilmgandhi 18:6a4db94011d3 6871
sahilmgandhi 18:6a4db94011d3 6872 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
sahilmgandhi 18:6a4db94011d3 6873 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
sahilmgandhi 18:6a4db94011d3 6874
sahilmgandhi 18:6a4db94011d3 6875 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
sahilmgandhi 18:6a4db94011d3 6876 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
sahilmgandhi 18:6a4db94011d3 6877
sahilmgandhi 18:6a4db94011d3 6878 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6879 /* Ethernet PTP Registers bits definition */
sahilmgandhi 18:6a4db94011d3 6880 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6881
sahilmgandhi 18:6a4db94011d3 6882 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
sahilmgandhi 18:6a4db94011d3 6883 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
sahilmgandhi 18:6a4db94011d3 6884 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
sahilmgandhi 18:6a4db94011d3 6885 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
sahilmgandhi 18:6a4db94011d3 6886 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
sahilmgandhi 18:6a4db94011d3 6887 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
sahilmgandhi 18:6a4db94011d3 6888 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
sahilmgandhi 18:6a4db94011d3 6889 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
sahilmgandhi 18:6a4db94011d3 6890 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
sahilmgandhi 18:6a4db94011d3 6891 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
sahilmgandhi 18:6a4db94011d3 6892
sahilmgandhi 18:6a4db94011d3 6893 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
sahilmgandhi 18:6a4db94011d3 6894 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
sahilmgandhi 18:6a4db94011d3 6895 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
sahilmgandhi 18:6a4db94011d3 6896 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
sahilmgandhi 18:6a4db94011d3 6897 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
sahilmgandhi 18:6a4db94011d3 6898 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
sahilmgandhi 18:6a4db94011d3 6899
sahilmgandhi 18:6a4db94011d3 6900 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
sahilmgandhi 18:6a4db94011d3 6901 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
sahilmgandhi 18:6a4db94011d3 6902
sahilmgandhi 18:6a4db94011d3 6903 /* Bit definition for Ethernet PTP Time Stamp High Register */
sahilmgandhi 18:6a4db94011d3 6904 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
sahilmgandhi 18:6a4db94011d3 6905
sahilmgandhi 18:6a4db94011d3 6906 /* Bit definition for Ethernet PTP Time Stamp Low Register */
sahilmgandhi 18:6a4db94011d3 6907 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
sahilmgandhi 18:6a4db94011d3 6908 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
sahilmgandhi 18:6a4db94011d3 6909
sahilmgandhi 18:6a4db94011d3 6910 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
sahilmgandhi 18:6a4db94011d3 6911 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
sahilmgandhi 18:6a4db94011d3 6912
sahilmgandhi 18:6a4db94011d3 6913 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
sahilmgandhi 18:6a4db94011d3 6914 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
sahilmgandhi 18:6a4db94011d3 6915 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
sahilmgandhi 18:6a4db94011d3 6916
sahilmgandhi 18:6a4db94011d3 6917 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
sahilmgandhi 18:6a4db94011d3 6918 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
sahilmgandhi 18:6a4db94011d3 6919
sahilmgandhi 18:6a4db94011d3 6920 /* Bit definition for Ethernet PTP Target Time High Register */
sahilmgandhi 18:6a4db94011d3 6921 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
sahilmgandhi 18:6a4db94011d3 6922
sahilmgandhi 18:6a4db94011d3 6923 /* Bit definition for Ethernet PTP Target Time Low Register */
sahilmgandhi 18:6a4db94011d3 6924 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
sahilmgandhi 18:6a4db94011d3 6925
sahilmgandhi 18:6a4db94011d3 6926 /* Bit definition for Ethernet PTP Time Stamp Status Register */
sahilmgandhi 18:6a4db94011d3 6927 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
sahilmgandhi 18:6a4db94011d3 6928 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
sahilmgandhi 18:6a4db94011d3 6929
sahilmgandhi 18:6a4db94011d3 6930 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6931 /* Ethernet DMA Registers bits definition */
sahilmgandhi 18:6a4db94011d3 6932 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6933
sahilmgandhi 18:6a4db94011d3 6934 /* Bit definition for Ethernet DMA Bus Mode Register */
sahilmgandhi 18:6a4db94011d3 6935 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
sahilmgandhi 18:6a4db94011d3 6936 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
sahilmgandhi 18:6a4db94011d3 6937 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
sahilmgandhi 18:6a4db94011d3 6938 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
sahilmgandhi 18:6a4db94011d3 6939 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
sahilmgandhi 18:6a4db94011d3 6940 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
sahilmgandhi 18:6a4db94011d3 6941 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
sahilmgandhi 18:6a4db94011d3 6942 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
sahilmgandhi 18:6a4db94011d3 6943 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
sahilmgandhi 18:6a4db94011d3 6944 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
sahilmgandhi 18:6a4db94011d3 6945 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
sahilmgandhi 18:6a4db94011d3 6946 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
sahilmgandhi 18:6a4db94011d3 6947 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
sahilmgandhi 18:6a4db94011d3 6948 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
sahilmgandhi 18:6a4db94011d3 6949 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
sahilmgandhi 18:6a4db94011d3 6950 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
sahilmgandhi 18:6a4db94011d3 6951 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
sahilmgandhi 18:6a4db94011d3 6952 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
sahilmgandhi 18:6a4db94011d3 6953 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
sahilmgandhi 18:6a4db94011d3 6954 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
sahilmgandhi 18:6a4db94011d3 6955 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
sahilmgandhi 18:6a4db94011d3 6956 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
sahilmgandhi 18:6a4db94011d3 6957 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
sahilmgandhi 18:6a4db94011d3 6958 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
sahilmgandhi 18:6a4db94011d3 6959 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
sahilmgandhi 18:6a4db94011d3 6960 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
sahilmgandhi 18:6a4db94011d3 6961 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
sahilmgandhi 18:6a4db94011d3 6962 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
sahilmgandhi 18:6a4db94011d3 6963 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
sahilmgandhi 18:6a4db94011d3 6964 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
sahilmgandhi 18:6a4db94011d3 6965 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
sahilmgandhi 18:6a4db94011d3 6966 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
sahilmgandhi 18:6a4db94011d3 6967 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
sahilmgandhi 18:6a4db94011d3 6968 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
sahilmgandhi 18:6a4db94011d3 6969 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
sahilmgandhi 18:6a4db94011d3 6970 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
sahilmgandhi 18:6a4db94011d3 6971 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
sahilmgandhi 18:6a4db94011d3 6972 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
sahilmgandhi 18:6a4db94011d3 6973 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
sahilmgandhi 18:6a4db94011d3 6974
sahilmgandhi 18:6a4db94011d3 6975 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
sahilmgandhi 18:6a4db94011d3 6976 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
sahilmgandhi 18:6a4db94011d3 6977
sahilmgandhi 18:6a4db94011d3 6978 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
sahilmgandhi 18:6a4db94011d3 6979 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
sahilmgandhi 18:6a4db94011d3 6980
sahilmgandhi 18:6a4db94011d3 6981 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
sahilmgandhi 18:6a4db94011d3 6982 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
sahilmgandhi 18:6a4db94011d3 6983
sahilmgandhi 18:6a4db94011d3 6984 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
sahilmgandhi 18:6a4db94011d3 6985 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
sahilmgandhi 18:6a4db94011d3 6986
sahilmgandhi 18:6a4db94011d3 6987 /* Bit definition for Ethernet DMA Status Register */
sahilmgandhi 18:6a4db94011d3 6988 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
sahilmgandhi 18:6a4db94011d3 6989 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
sahilmgandhi 18:6a4db94011d3 6990 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
sahilmgandhi 18:6a4db94011d3 6991 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
sahilmgandhi 18:6a4db94011d3 6992 /* combination with EBS[2:0] for GetFlagStatus function */
sahilmgandhi 18:6a4db94011d3 6993 #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
sahilmgandhi 18:6a4db94011d3 6994 #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
sahilmgandhi 18:6a4db94011d3 6995 #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
sahilmgandhi 18:6a4db94011d3 6996 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
sahilmgandhi 18:6a4db94011d3 6997 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
sahilmgandhi 18:6a4db94011d3 6998 #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
sahilmgandhi 18:6a4db94011d3 6999 #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
sahilmgandhi 18:6a4db94011d3 7000 #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
sahilmgandhi 18:6a4db94011d3 7001 #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
sahilmgandhi 18:6a4db94011d3 7002 #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
sahilmgandhi 18:6a4db94011d3 7003 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
sahilmgandhi 18:6a4db94011d3 7004 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
sahilmgandhi 18:6a4db94011d3 7005 #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
sahilmgandhi 18:6a4db94011d3 7006 #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
sahilmgandhi 18:6a4db94011d3 7007 #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
sahilmgandhi 18:6a4db94011d3 7008 #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
sahilmgandhi 18:6a4db94011d3 7009 #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
sahilmgandhi 18:6a4db94011d3 7010 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
sahilmgandhi 18:6a4db94011d3 7011 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
sahilmgandhi 18:6a4db94011d3 7012 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
sahilmgandhi 18:6a4db94011d3 7013 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
sahilmgandhi 18:6a4db94011d3 7014 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
sahilmgandhi 18:6a4db94011d3 7015 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
sahilmgandhi 18:6a4db94011d3 7016 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
sahilmgandhi 18:6a4db94011d3 7017 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
sahilmgandhi 18:6a4db94011d3 7018 #define ETH_DMASR_RS 0x00000040U /* Receive status */
sahilmgandhi 18:6a4db94011d3 7019 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
sahilmgandhi 18:6a4db94011d3 7020 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
sahilmgandhi 18:6a4db94011d3 7021 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
sahilmgandhi 18:6a4db94011d3 7022 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
sahilmgandhi 18:6a4db94011d3 7023 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
sahilmgandhi 18:6a4db94011d3 7024 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
sahilmgandhi 18:6a4db94011d3 7025
sahilmgandhi 18:6a4db94011d3 7026 /* Bit definition for Ethernet DMA Operation Mode Register */
sahilmgandhi 18:6a4db94011d3 7027 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
sahilmgandhi 18:6a4db94011d3 7028 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
sahilmgandhi 18:6a4db94011d3 7029 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
sahilmgandhi 18:6a4db94011d3 7030 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
sahilmgandhi 18:6a4db94011d3 7031 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
sahilmgandhi 18:6a4db94011d3 7032 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
sahilmgandhi 18:6a4db94011d3 7033 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
sahilmgandhi 18:6a4db94011d3 7034 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
sahilmgandhi 18:6a4db94011d3 7035 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
sahilmgandhi 18:6a4db94011d3 7036 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
sahilmgandhi 18:6a4db94011d3 7037 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
sahilmgandhi 18:6a4db94011d3 7038 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
sahilmgandhi 18:6a4db94011d3 7039 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
sahilmgandhi 18:6a4db94011d3 7040 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
sahilmgandhi 18:6a4db94011d3 7041 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
sahilmgandhi 18:6a4db94011d3 7042 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
sahilmgandhi 18:6a4db94011d3 7043 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
sahilmgandhi 18:6a4db94011d3 7044 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
sahilmgandhi 18:6a4db94011d3 7045 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
sahilmgandhi 18:6a4db94011d3 7046 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
sahilmgandhi 18:6a4db94011d3 7047 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
sahilmgandhi 18:6a4db94011d3 7048 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
sahilmgandhi 18:6a4db94011d3 7049 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
sahilmgandhi 18:6a4db94011d3 7050 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
sahilmgandhi 18:6a4db94011d3 7051
sahilmgandhi 18:6a4db94011d3 7052 /* Bit definition for Ethernet DMA Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 7053 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
sahilmgandhi 18:6a4db94011d3 7054 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
sahilmgandhi 18:6a4db94011d3 7055 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
sahilmgandhi 18:6a4db94011d3 7056 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
sahilmgandhi 18:6a4db94011d3 7057 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
sahilmgandhi 18:6a4db94011d3 7058 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
sahilmgandhi 18:6a4db94011d3 7059 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
sahilmgandhi 18:6a4db94011d3 7060 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
sahilmgandhi 18:6a4db94011d3 7061 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
sahilmgandhi 18:6a4db94011d3 7062 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
sahilmgandhi 18:6a4db94011d3 7063 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
sahilmgandhi 18:6a4db94011d3 7064 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
sahilmgandhi 18:6a4db94011d3 7065 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
sahilmgandhi 18:6a4db94011d3 7066 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
sahilmgandhi 18:6a4db94011d3 7067 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
sahilmgandhi 18:6a4db94011d3 7068
sahilmgandhi 18:6a4db94011d3 7069 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
sahilmgandhi 18:6a4db94011d3 7070 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
sahilmgandhi 18:6a4db94011d3 7071 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
sahilmgandhi 18:6a4db94011d3 7072 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
sahilmgandhi 18:6a4db94011d3 7073 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
sahilmgandhi 18:6a4db94011d3 7074
sahilmgandhi 18:6a4db94011d3 7075 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
sahilmgandhi 18:6a4db94011d3 7076 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
sahilmgandhi 18:6a4db94011d3 7077
sahilmgandhi 18:6a4db94011d3 7078 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
sahilmgandhi 18:6a4db94011d3 7079 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
sahilmgandhi 18:6a4db94011d3 7080
sahilmgandhi 18:6a4db94011d3 7081 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
sahilmgandhi 18:6a4db94011d3 7082 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
sahilmgandhi 18:6a4db94011d3 7083
sahilmgandhi 18:6a4db94011d3 7084 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
sahilmgandhi 18:6a4db94011d3 7085 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
sahilmgandhi 18:6a4db94011d3 7086
sahilmgandhi 18:6a4db94011d3 7087 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 7088 /* */
sahilmgandhi 18:6a4db94011d3 7089 /* USB_OTG */
sahilmgandhi 18:6a4db94011d3 7090 /* */
sahilmgandhi 18:6a4db94011d3 7091 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 7092 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
sahilmgandhi 18:6a4db94011d3 7093 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
sahilmgandhi 18:6a4db94011d3 7094 #define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
sahilmgandhi 18:6a4db94011d3 7095 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
sahilmgandhi 18:6a4db94011d3 7096 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
sahilmgandhi 18:6a4db94011d3 7097 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
sahilmgandhi 18:6a4db94011d3 7098 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
sahilmgandhi 18:6a4db94011d3 7099 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
sahilmgandhi 18:6a4db94011d3 7100 #define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
sahilmgandhi 18:6a4db94011d3 7101 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
sahilmgandhi 18:6a4db94011d3 7102 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
sahilmgandhi 18:6a4db94011d3 7103
sahilmgandhi 18:6a4db94011d3 7104 /******************** Bit definition forUSB_OTG_HCFG register ********************/
sahilmgandhi 18:6a4db94011d3 7105
sahilmgandhi 18:6a4db94011d3 7106 #define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
sahilmgandhi 18:6a4db94011d3 7107 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7108 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7109 #define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
sahilmgandhi 18:6a4db94011d3 7110
sahilmgandhi 18:6a4db94011d3 7111 /******************** Bit definition forUSB_OTG_DCFG register ********************/
sahilmgandhi 18:6a4db94011d3 7112
sahilmgandhi 18:6a4db94011d3 7113 #define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
sahilmgandhi 18:6a4db94011d3 7114 #define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7115 #define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7116 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
sahilmgandhi 18:6a4db94011d3 7117
sahilmgandhi 18:6a4db94011d3 7118 #define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
sahilmgandhi 18:6a4db94011d3 7119 #define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7120 #define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7121 #define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7122 #define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7123 #define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 7124 #define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 7125 #define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 7126
sahilmgandhi 18:6a4db94011d3 7127 #define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
sahilmgandhi 18:6a4db94011d3 7128 #define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7129 #define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7130
sahilmgandhi 18:6a4db94011d3 7131 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
sahilmgandhi 18:6a4db94011d3 7132 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7133 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7134
sahilmgandhi 18:6a4db94011d3 7135 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
sahilmgandhi 18:6a4db94011d3 7136 #define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
sahilmgandhi 18:6a4db94011d3 7137 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
sahilmgandhi 18:6a4db94011d3 7138 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
sahilmgandhi 18:6a4db94011d3 7139
sahilmgandhi 18:6a4db94011d3 7140 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
sahilmgandhi 18:6a4db94011d3 7141 #define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
sahilmgandhi 18:6a4db94011d3 7142 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
sahilmgandhi 18:6a4db94011d3 7143 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
sahilmgandhi 18:6a4db94011d3 7144 #define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
sahilmgandhi 18:6a4db94011d3 7145 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
sahilmgandhi 18:6a4db94011d3 7146 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
sahilmgandhi 18:6a4db94011d3 7147
sahilmgandhi 18:6a4db94011d3 7148 /******************** Bit definition forUSB_OTG_DCTL register ********************/
sahilmgandhi 18:6a4db94011d3 7149 #define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
sahilmgandhi 18:6a4db94011d3 7150 #define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
sahilmgandhi 18:6a4db94011d3 7151 #define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
sahilmgandhi 18:6a4db94011d3 7152 #define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
sahilmgandhi 18:6a4db94011d3 7153
sahilmgandhi 18:6a4db94011d3 7154 #define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
sahilmgandhi 18:6a4db94011d3 7155 #define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7156 #define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7157 #define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7158 #define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
sahilmgandhi 18:6a4db94011d3 7159 #define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
sahilmgandhi 18:6a4db94011d3 7160 #define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
sahilmgandhi 18:6a4db94011d3 7161 #define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
sahilmgandhi 18:6a4db94011d3 7162 #define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
sahilmgandhi 18:6a4db94011d3 7163
sahilmgandhi 18:6a4db94011d3 7164 /******************** Bit definition forUSB_OTG_HFIR register ********************/
sahilmgandhi 18:6a4db94011d3 7165 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
sahilmgandhi 18:6a4db94011d3 7166
sahilmgandhi 18:6a4db94011d3 7167 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
sahilmgandhi 18:6a4db94011d3 7168 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
sahilmgandhi 18:6a4db94011d3 7169 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
sahilmgandhi 18:6a4db94011d3 7170
sahilmgandhi 18:6a4db94011d3 7171 /******************** Bit definition forUSB_OTG_DSTS register ********************/
sahilmgandhi 18:6a4db94011d3 7172 #define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
sahilmgandhi 18:6a4db94011d3 7173
sahilmgandhi 18:6a4db94011d3 7174 #define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
sahilmgandhi 18:6a4db94011d3 7175 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7176 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7177 #define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
sahilmgandhi 18:6a4db94011d3 7178 #define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
sahilmgandhi 18:6a4db94011d3 7179
sahilmgandhi 18:6a4db94011d3 7180 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
sahilmgandhi 18:6a4db94011d3 7181 #define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
sahilmgandhi 18:6a4db94011d3 7182
sahilmgandhi 18:6a4db94011d3 7183 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
sahilmgandhi 18:6a4db94011d3 7184 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7185 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7186 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7187 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7188 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
sahilmgandhi 18:6a4db94011d3 7189 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
sahilmgandhi 18:6a4db94011d3 7190 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
sahilmgandhi 18:6a4db94011d3 7191
sahilmgandhi 18:6a4db94011d3 7192 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
sahilmgandhi 18:6a4db94011d3 7193
sahilmgandhi 18:6a4db94011d3 7194 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
sahilmgandhi 18:6a4db94011d3 7195 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7196 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7197 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7198 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
sahilmgandhi 18:6a4db94011d3 7199 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
sahilmgandhi 18:6a4db94011d3 7200 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
sahilmgandhi 18:6a4db94011d3 7201
sahilmgandhi 18:6a4db94011d3 7202 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
sahilmgandhi 18:6a4db94011d3 7203 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7204 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7205 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7206 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7207 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
sahilmgandhi 18:6a4db94011d3 7208 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
sahilmgandhi 18:6a4db94011d3 7209 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
sahilmgandhi 18:6a4db94011d3 7210 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
sahilmgandhi 18:6a4db94011d3 7211 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
sahilmgandhi 18:6a4db94011d3 7212 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
sahilmgandhi 18:6a4db94011d3 7213 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
sahilmgandhi 18:6a4db94011d3 7214 #define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
sahilmgandhi 18:6a4db94011d3 7215 #define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
sahilmgandhi 18:6a4db94011d3 7216 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
sahilmgandhi 18:6a4db94011d3 7217 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
sahilmgandhi 18:6a4db94011d3 7218 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
sahilmgandhi 18:6a4db94011d3 7219 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
sahilmgandhi 18:6a4db94011d3 7220
sahilmgandhi 18:6a4db94011d3 7221 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
sahilmgandhi 18:6a4db94011d3 7222 #define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
sahilmgandhi 18:6a4db94011d3 7223 #define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
sahilmgandhi 18:6a4db94011d3 7224 #define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
sahilmgandhi 18:6a4db94011d3 7225 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
sahilmgandhi 18:6a4db94011d3 7226 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
sahilmgandhi 18:6a4db94011d3 7227
sahilmgandhi 18:6a4db94011d3 7228 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
sahilmgandhi 18:6a4db94011d3 7229 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7230 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7231 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7232 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7233 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 7234 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
sahilmgandhi 18:6a4db94011d3 7235 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
sahilmgandhi 18:6a4db94011d3 7236
sahilmgandhi 18:6a4db94011d3 7237 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
sahilmgandhi 18:6a4db94011d3 7238 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
sahilmgandhi 18:6a4db94011d3 7239 #define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
sahilmgandhi 18:6a4db94011d3 7240 #define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
sahilmgandhi 18:6a4db94011d3 7241 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 7242 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
sahilmgandhi 18:6a4db94011d3 7243 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
sahilmgandhi 18:6a4db94011d3 7244 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
sahilmgandhi 18:6a4db94011d3 7245 #define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
sahilmgandhi 18:6a4db94011d3 7246
sahilmgandhi 18:6a4db94011d3 7247 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
sahilmgandhi 18:6a4db94011d3 7248 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
sahilmgandhi 18:6a4db94011d3 7249
sahilmgandhi 18:6a4db94011d3 7250 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
sahilmgandhi 18:6a4db94011d3 7251 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7252 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7253 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7254 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7255 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 7256 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 7257 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 7258 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 7259
sahilmgandhi 18:6a4db94011d3 7260 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
sahilmgandhi 18:6a4db94011d3 7261 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7262 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7263 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7264 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7265 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 7266 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 7267 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 7268 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 7269
sahilmgandhi 18:6a4db94011d3 7270 /******************** Bit definition forUSB_OTG_HAINT register ********************/
sahilmgandhi 18:6a4db94011d3 7271 #define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
sahilmgandhi 18:6a4db94011d3 7272
sahilmgandhi 18:6a4db94011d3 7273 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
sahilmgandhi 18:6a4db94011d3 7274 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
sahilmgandhi 18:6a4db94011d3 7275 #define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
sahilmgandhi 18:6a4db94011d3 7276 #define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
sahilmgandhi 18:6a4db94011d3 7277 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
sahilmgandhi 18:6a4db94011d3 7278 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
sahilmgandhi 18:6a4db94011d3 7279 #define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
sahilmgandhi 18:6a4db94011d3 7280 #define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
sahilmgandhi 18:6a4db94011d3 7281
sahilmgandhi 18:6a4db94011d3 7282 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
sahilmgandhi 18:6a4db94011d3 7283 #define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
sahilmgandhi 18:6a4db94011d3 7284 #define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
sahilmgandhi 18:6a4db94011d3 7285 #define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
sahilmgandhi 18:6a4db94011d3 7286 #define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
sahilmgandhi 18:6a4db94011d3 7287 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
sahilmgandhi 18:6a4db94011d3 7288 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
sahilmgandhi 18:6a4db94011d3 7289 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
sahilmgandhi 18:6a4db94011d3 7290 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
sahilmgandhi 18:6a4db94011d3 7291 #define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
sahilmgandhi 18:6a4db94011d3 7292 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
sahilmgandhi 18:6a4db94011d3 7293 #define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
sahilmgandhi 18:6a4db94011d3 7294 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
sahilmgandhi 18:6a4db94011d3 7295 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
sahilmgandhi 18:6a4db94011d3 7296 #define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
sahilmgandhi 18:6a4db94011d3 7297 #define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
sahilmgandhi 18:6a4db94011d3 7298 #define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
sahilmgandhi 18:6a4db94011d3 7299 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
sahilmgandhi 18:6a4db94011d3 7300 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
sahilmgandhi 18:6a4db94011d3 7301 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
sahilmgandhi 18:6a4db94011d3 7302 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
sahilmgandhi 18:6a4db94011d3 7303 #define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
sahilmgandhi 18:6a4db94011d3 7304 #define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
sahilmgandhi 18:6a4db94011d3 7305 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
sahilmgandhi 18:6a4db94011d3 7306 #define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
sahilmgandhi 18:6a4db94011d3 7307 #define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
sahilmgandhi 18:6a4db94011d3 7308 #define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
sahilmgandhi 18:6a4db94011d3 7309
sahilmgandhi 18:6a4db94011d3 7310 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 7311 #define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
sahilmgandhi 18:6a4db94011d3 7312 #define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
sahilmgandhi 18:6a4db94011d3 7313 #define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
sahilmgandhi 18:6a4db94011d3 7314 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
sahilmgandhi 18:6a4db94011d3 7315 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 7316 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
sahilmgandhi 18:6a4db94011d3 7317 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
sahilmgandhi 18:6a4db94011d3 7318 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
sahilmgandhi 18:6a4db94011d3 7319 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
sahilmgandhi 18:6a4db94011d3 7320 #define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
sahilmgandhi 18:6a4db94011d3 7321 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
sahilmgandhi 18:6a4db94011d3 7322 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
sahilmgandhi 18:6a4db94011d3 7323 #define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
sahilmgandhi 18:6a4db94011d3 7324 #define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
sahilmgandhi 18:6a4db94011d3 7325 #define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
sahilmgandhi 18:6a4db94011d3 7326 #define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
sahilmgandhi 18:6a4db94011d3 7327 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
sahilmgandhi 18:6a4db94011d3 7328 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
sahilmgandhi 18:6a4db94011d3 7329 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
sahilmgandhi 18:6a4db94011d3 7330 #define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
sahilmgandhi 18:6a4db94011d3 7331 #define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
sahilmgandhi 18:6a4db94011d3 7332 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 7333 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
sahilmgandhi 18:6a4db94011d3 7334 #define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
sahilmgandhi 18:6a4db94011d3 7335 #define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
sahilmgandhi 18:6a4db94011d3 7336 #define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
sahilmgandhi 18:6a4db94011d3 7337
sahilmgandhi 18:6a4db94011d3 7338 /******************** Bit definition forUSB_OTG_DAINT register ********************/
sahilmgandhi 18:6a4db94011d3 7339 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
sahilmgandhi 18:6a4db94011d3 7340 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
sahilmgandhi 18:6a4db94011d3 7341
sahilmgandhi 18:6a4db94011d3 7342 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 7343 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
sahilmgandhi 18:6a4db94011d3 7344
sahilmgandhi 18:6a4db94011d3 7345 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
sahilmgandhi 18:6a4db94011d3 7346 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 7347 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 7348 #define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 7349 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 7350
sahilmgandhi 18:6a4db94011d3 7351 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 7352 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 7353 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 7354
sahilmgandhi 18:6a4db94011d3 7355 /******************** Bit definition for OTG register ********************/
sahilmgandhi 18:6a4db94011d3 7356
sahilmgandhi 18:6a4db94011d3 7357 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
sahilmgandhi 18:6a4db94011d3 7358 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7359 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7360 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7361 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7362 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
sahilmgandhi 18:6a4db94011d3 7363
sahilmgandhi 18:6a4db94011d3 7364 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
sahilmgandhi 18:6a4db94011d3 7365 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7366 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7367
sahilmgandhi 18:6a4db94011d3 7368 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
sahilmgandhi 18:6a4db94011d3 7369 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7370 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7371 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7372 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7373
sahilmgandhi 18:6a4db94011d3 7374 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
sahilmgandhi 18:6a4db94011d3 7375 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7376 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7377 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7378 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7379
sahilmgandhi 18:6a4db94011d3 7380 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
sahilmgandhi 18:6a4db94011d3 7381 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7382 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7383 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7384 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7385
sahilmgandhi 18:6a4db94011d3 7386 /******************** Bit definition for OTG register ********************/
sahilmgandhi 18:6a4db94011d3 7387
sahilmgandhi 18:6a4db94011d3 7388 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
sahilmgandhi 18:6a4db94011d3 7389 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7390 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7391 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7392 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7393 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
sahilmgandhi 18:6a4db94011d3 7394
sahilmgandhi 18:6a4db94011d3 7395 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
sahilmgandhi 18:6a4db94011d3 7396 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7397 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7398
sahilmgandhi 18:6a4db94011d3 7399 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
sahilmgandhi 18:6a4db94011d3 7400 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7401 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7402 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7403 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7404
sahilmgandhi 18:6a4db94011d3 7405 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
sahilmgandhi 18:6a4db94011d3 7406 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7407 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7408 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7409 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7410
sahilmgandhi 18:6a4db94011d3 7411 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
sahilmgandhi 18:6a4db94011d3 7412 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7413 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7414 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7415 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7416
sahilmgandhi 18:6a4db94011d3 7417 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 7418 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
sahilmgandhi 18:6a4db94011d3 7419
sahilmgandhi 18:6a4db94011d3 7420 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
sahilmgandhi 18:6a4db94011d3 7421 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
sahilmgandhi 18:6a4db94011d3 7422
sahilmgandhi 18:6a4db94011d3 7423 /******************** Bit definition for OTG register ********************/
sahilmgandhi 18:6a4db94011d3 7424 #define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
sahilmgandhi 18:6a4db94011d3 7425 #define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
sahilmgandhi 18:6a4db94011d3 7426 #define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
sahilmgandhi 18:6a4db94011d3 7427 #define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
sahilmgandhi 18:6a4db94011d3 7428
sahilmgandhi 18:6a4db94011d3 7429 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
sahilmgandhi 18:6a4db94011d3 7430 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
sahilmgandhi 18:6a4db94011d3 7431
sahilmgandhi 18:6a4db94011d3 7432 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
sahilmgandhi 18:6a4db94011d3 7433 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
sahilmgandhi 18:6a4db94011d3 7434
sahilmgandhi 18:6a4db94011d3 7435 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
sahilmgandhi 18:6a4db94011d3 7436 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7437 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7438 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7439 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7440 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 7441 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 7442 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 7443 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 7444
sahilmgandhi 18:6a4db94011d3 7445 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
sahilmgandhi 18:6a4db94011d3 7446 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7447 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7448 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7449 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7450 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 7451 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 7452 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 7453
sahilmgandhi 18:6a4db94011d3 7454 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
sahilmgandhi 18:6a4db94011d3 7455 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
sahilmgandhi 18:6a4db94011d3 7456 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
sahilmgandhi 18:6a4db94011d3 7457
sahilmgandhi 18:6a4db94011d3 7458 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
sahilmgandhi 18:6a4db94011d3 7459 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7460 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7461 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7462 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7463 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 7464 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 7465 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 7466 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 7467 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
sahilmgandhi 18:6a4db94011d3 7468 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
sahilmgandhi 18:6a4db94011d3 7469
sahilmgandhi 18:6a4db94011d3 7470 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
sahilmgandhi 18:6a4db94011d3 7471 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7472 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7473 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7474 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7475 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 7476 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 7477 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 7478 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 7479 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
sahilmgandhi 18:6a4db94011d3 7480 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
sahilmgandhi 18:6a4db94011d3 7481
sahilmgandhi 18:6a4db94011d3 7482 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
sahilmgandhi 18:6a4db94011d3 7483 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 7484
sahilmgandhi 18:6a4db94011d3 7485 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
sahilmgandhi 18:6a4db94011d3 7486 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
sahilmgandhi 18:6a4db94011d3 7487 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
sahilmgandhi 18:6a4db94011d3 7488
sahilmgandhi 18:6a4db94011d3 7489 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
sahilmgandhi 18:6a4db94011d3 7490 #define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
sahilmgandhi 18:6a4db94011d3 7491 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
sahilmgandhi 18:6a4db94011d3 7492 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
sahilmgandhi 18:6a4db94011d3 7493 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
sahilmgandhi 18:6a4db94011d3 7494 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
sahilmgandhi 18:6a4db94011d3 7495 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
sahilmgandhi 18:6a4db94011d3 7496
sahilmgandhi 18:6a4db94011d3 7497 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 7498 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
sahilmgandhi 18:6a4db94011d3 7499 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
sahilmgandhi 18:6a4db94011d3 7500
sahilmgandhi 18:6a4db94011d3 7501 /******************** Bit definition forUSB_OTG_CID register ********************/
sahilmgandhi 18:6a4db94011d3 7502 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
sahilmgandhi 18:6a4db94011d3 7503
sahilmgandhi 18:6a4db94011d3 7504 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
sahilmgandhi 18:6a4db94011d3 7505 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
sahilmgandhi 18:6a4db94011d3 7506 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
sahilmgandhi 18:6a4db94011d3 7507 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
sahilmgandhi 18:6a4db94011d3 7508 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 7509 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
sahilmgandhi 18:6a4db94011d3 7510 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
sahilmgandhi 18:6a4db94011d3 7511 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
sahilmgandhi 18:6a4db94011d3 7512 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
sahilmgandhi 18:6a4db94011d3 7513 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
sahilmgandhi 18:6a4db94011d3 7514
sahilmgandhi 18:6a4db94011d3 7515 /******************** Bit definition forUSB_OTG_HPRT register ********************/
sahilmgandhi 18:6a4db94011d3 7516 #define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
sahilmgandhi 18:6a4db94011d3 7517 #define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
sahilmgandhi 18:6a4db94011d3 7518 #define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
sahilmgandhi 18:6a4db94011d3 7519 #define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
sahilmgandhi 18:6a4db94011d3 7520 #define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
sahilmgandhi 18:6a4db94011d3 7521 #define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
sahilmgandhi 18:6a4db94011d3 7522 #define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
sahilmgandhi 18:6a4db94011d3 7523 #define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
sahilmgandhi 18:6a4db94011d3 7524 #define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
sahilmgandhi 18:6a4db94011d3 7525
sahilmgandhi 18:6a4db94011d3 7526 #define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
sahilmgandhi 18:6a4db94011d3 7527 #define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7528 #define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7529 #define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
sahilmgandhi 18:6a4db94011d3 7530
sahilmgandhi 18:6a4db94011d3 7531 #define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
sahilmgandhi 18:6a4db94011d3 7532 #define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7533 #define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7534 #define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7535 #define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7536
sahilmgandhi 18:6a4db94011d3 7537 #define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
sahilmgandhi 18:6a4db94011d3 7538 #define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7539 #define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7540
sahilmgandhi 18:6a4db94011d3 7541 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
sahilmgandhi 18:6a4db94011d3 7542 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
sahilmgandhi 18:6a4db94011d3 7543 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
sahilmgandhi 18:6a4db94011d3 7544 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
sahilmgandhi 18:6a4db94011d3 7545 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 7546 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
sahilmgandhi 18:6a4db94011d3 7547 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
sahilmgandhi 18:6a4db94011d3 7548 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
sahilmgandhi 18:6a4db94011d3 7549 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
sahilmgandhi 18:6a4db94011d3 7550 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
sahilmgandhi 18:6a4db94011d3 7551 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
sahilmgandhi 18:6a4db94011d3 7552 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
sahilmgandhi 18:6a4db94011d3 7553
sahilmgandhi 18:6a4db94011d3 7554 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 7555 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
sahilmgandhi 18:6a4db94011d3 7556 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
sahilmgandhi 18:6a4db94011d3 7557
sahilmgandhi 18:6a4db94011d3 7558 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
sahilmgandhi 18:6a4db94011d3 7559 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
sahilmgandhi 18:6a4db94011d3 7560 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
sahilmgandhi 18:6a4db94011d3 7561 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
sahilmgandhi 18:6a4db94011d3 7562 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
sahilmgandhi 18:6a4db94011d3 7563
sahilmgandhi 18:6a4db94011d3 7564 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
sahilmgandhi 18:6a4db94011d3 7565 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7566 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7567 #define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
sahilmgandhi 18:6a4db94011d3 7568
sahilmgandhi 18:6a4db94011d3 7569 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
sahilmgandhi 18:6a4db94011d3 7570 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7571 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7572 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7573 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7574 #define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
sahilmgandhi 18:6a4db94011d3 7575 #define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
sahilmgandhi 18:6a4db94011d3 7576 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
sahilmgandhi 18:6a4db94011d3 7577 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
sahilmgandhi 18:6a4db94011d3 7578 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
sahilmgandhi 18:6a4db94011d3 7579 #define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
sahilmgandhi 18:6a4db94011d3 7580
sahilmgandhi 18:6a4db94011d3 7581 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
sahilmgandhi 18:6a4db94011d3 7582 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
sahilmgandhi 18:6a4db94011d3 7583
sahilmgandhi 18:6a4db94011d3 7584 #define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
sahilmgandhi 18:6a4db94011d3 7585 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7586 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7587 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7588 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7589 #define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
sahilmgandhi 18:6a4db94011d3 7590 #define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
sahilmgandhi 18:6a4db94011d3 7591
sahilmgandhi 18:6a4db94011d3 7592 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
sahilmgandhi 18:6a4db94011d3 7593 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7594 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7595
sahilmgandhi 18:6a4db94011d3 7596 #define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
sahilmgandhi 18:6a4db94011d3 7597 #define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7598 #define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7599
sahilmgandhi 18:6a4db94011d3 7600 #define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
sahilmgandhi 18:6a4db94011d3 7601 #define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7602 #define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7603 #define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7604 #define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7605 #define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 7606 #define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 7607 #define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 7608 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
sahilmgandhi 18:6a4db94011d3 7609 #define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
sahilmgandhi 18:6a4db94011d3 7610 #define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
sahilmgandhi 18:6a4db94011d3 7611
sahilmgandhi 18:6a4db94011d3 7612 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
sahilmgandhi 18:6a4db94011d3 7613
sahilmgandhi 18:6a4db94011d3 7614 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
sahilmgandhi 18:6a4db94011d3 7615 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7616 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7617 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7618 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7619 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 7620 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 7621 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 7622
sahilmgandhi 18:6a4db94011d3 7623 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
sahilmgandhi 18:6a4db94011d3 7624 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7625 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7626 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 7627 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 7628 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 7629 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 7630 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 7631
sahilmgandhi 18:6a4db94011d3 7632 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
sahilmgandhi 18:6a4db94011d3 7633 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7634 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7635 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
sahilmgandhi 18:6a4db94011d3 7636 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
sahilmgandhi 18:6a4db94011d3 7637
sahilmgandhi 18:6a4db94011d3 7638 /******************** Bit definition forUSB_OTG_HCINT register ********************/
sahilmgandhi 18:6a4db94011d3 7639 #define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
sahilmgandhi 18:6a4db94011d3 7640 #define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
sahilmgandhi 18:6a4db94011d3 7641 #define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
sahilmgandhi 18:6a4db94011d3 7642 #define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
sahilmgandhi 18:6a4db94011d3 7643 #define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
sahilmgandhi 18:6a4db94011d3 7644 #define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
sahilmgandhi 18:6a4db94011d3 7645 #define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
sahilmgandhi 18:6a4db94011d3 7646 #define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
sahilmgandhi 18:6a4db94011d3 7647 #define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
sahilmgandhi 18:6a4db94011d3 7648 #define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
sahilmgandhi 18:6a4db94011d3 7649 #define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
sahilmgandhi 18:6a4db94011d3 7650
sahilmgandhi 18:6a4db94011d3 7651 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
sahilmgandhi 18:6a4db94011d3 7652 #define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
sahilmgandhi 18:6a4db94011d3 7653 #define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
sahilmgandhi 18:6a4db94011d3 7654 #define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
sahilmgandhi 18:6a4db94011d3 7655 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
sahilmgandhi 18:6a4db94011d3 7656 #define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
sahilmgandhi 18:6a4db94011d3 7657 #define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
sahilmgandhi 18:6a4db94011d3 7658 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
sahilmgandhi 18:6a4db94011d3 7659 #define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
sahilmgandhi 18:6a4db94011d3 7660 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
sahilmgandhi 18:6a4db94011d3 7661 #define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
sahilmgandhi 18:6a4db94011d3 7662 #define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
sahilmgandhi 18:6a4db94011d3 7663
sahilmgandhi 18:6a4db94011d3 7664 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 7665 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
sahilmgandhi 18:6a4db94011d3 7666 #define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
sahilmgandhi 18:6a4db94011d3 7667 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
sahilmgandhi 18:6a4db94011d3 7668 #define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
sahilmgandhi 18:6a4db94011d3 7669 #define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
sahilmgandhi 18:6a4db94011d3 7670 #define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
sahilmgandhi 18:6a4db94011d3 7671 #define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
sahilmgandhi 18:6a4db94011d3 7672 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
sahilmgandhi 18:6a4db94011d3 7673 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
sahilmgandhi 18:6a4db94011d3 7674 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
sahilmgandhi 18:6a4db94011d3 7675 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
sahilmgandhi 18:6a4db94011d3 7676
sahilmgandhi 18:6a4db94011d3 7677 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 7678
sahilmgandhi 18:6a4db94011d3 7679 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
sahilmgandhi 18:6a4db94011d3 7680 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
sahilmgandhi 18:6a4db94011d3 7681 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
sahilmgandhi 18:6a4db94011d3 7682 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 7683 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
sahilmgandhi 18:6a4db94011d3 7684 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
sahilmgandhi 18:6a4db94011d3 7685 #define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
sahilmgandhi 18:6a4db94011d3 7686 #define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
sahilmgandhi 18:6a4db94011d3 7687 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7688 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7689
sahilmgandhi 18:6a4db94011d3 7690 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
sahilmgandhi 18:6a4db94011d3 7691 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
sahilmgandhi 18:6a4db94011d3 7692
sahilmgandhi 18:6a4db94011d3 7693 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
sahilmgandhi 18:6a4db94011d3 7694 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
sahilmgandhi 18:6a4db94011d3 7695
sahilmgandhi 18:6a4db94011d3 7696 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
sahilmgandhi 18:6a4db94011d3 7697 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
sahilmgandhi 18:6a4db94011d3 7698
sahilmgandhi 18:6a4db94011d3 7699 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
sahilmgandhi 18:6a4db94011d3 7700 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
sahilmgandhi 18:6a4db94011d3 7701 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
sahilmgandhi 18:6a4db94011d3 7702
sahilmgandhi 18:6a4db94011d3 7703 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
sahilmgandhi 18:6a4db94011d3 7704
sahilmgandhi 18:6a4db94011d3 7705 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7706 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
sahilmgandhi 18:6a4db94011d3 7707 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
sahilmgandhi 18:6a4db94011d3 7708 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
sahilmgandhi 18:6a4db94011d3 7709 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
sahilmgandhi 18:6a4db94011d3 7710 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
sahilmgandhi 18:6a4db94011d3 7711 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7712 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7713 #define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
sahilmgandhi 18:6a4db94011d3 7714 #define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
sahilmgandhi 18:6a4db94011d3 7715 #define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
sahilmgandhi 18:6a4db94011d3 7716 #define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
sahilmgandhi 18:6a4db94011d3 7717 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
sahilmgandhi 18:6a4db94011d3 7718 #define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
sahilmgandhi 18:6a4db94011d3 7719
sahilmgandhi 18:6a4db94011d3 7720 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
sahilmgandhi 18:6a4db94011d3 7721 #define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
sahilmgandhi 18:6a4db94011d3 7722 #define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
sahilmgandhi 18:6a4db94011d3 7723 #define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
sahilmgandhi 18:6a4db94011d3 7724 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
sahilmgandhi 18:6a4db94011d3 7725 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
sahilmgandhi 18:6a4db94011d3 7726 #define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
sahilmgandhi 18:6a4db94011d3 7727
sahilmgandhi 18:6a4db94011d3 7728 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 7729
sahilmgandhi 18:6a4db94011d3 7730 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
sahilmgandhi 18:6a4db94011d3 7731 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
sahilmgandhi 18:6a4db94011d3 7732
sahilmgandhi 18:6a4db94011d3 7733 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
sahilmgandhi 18:6a4db94011d3 7734 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7735 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7736
sahilmgandhi 18:6a4db94011d3 7737 /******************** Bit definition for PCGCCTL register ********************/
sahilmgandhi 18:6a4db94011d3 7738 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
sahilmgandhi 18:6a4db94011d3 7739 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 7740 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 7741
sahilmgandhi 18:6a4db94011d3 7742 /**
sahilmgandhi 18:6a4db94011d3 7743 * @}
sahilmgandhi 18:6a4db94011d3 7744 */
sahilmgandhi 18:6a4db94011d3 7745
sahilmgandhi 18:6a4db94011d3 7746 /**
sahilmgandhi 18:6a4db94011d3 7747 * @}
sahilmgandhi 18:6a4db94011d3 7748 */
sahilmgandhi 18:6a4db94011d3 7749
sahilmgandhi 18:6a4db94011d3 7750 /** @addtogroup Exported_macros
sahilmgandhi 18:6a4db94011d3 7751 * @{
sahilmgandhi 18:6a4db94011d3 7752 */
sahilmgandhi 18:6a4db94011d3 7753
sahilmgandhi 18:6a4db94011d3 7754 /******************************* ADC Instances ********************************/
sahilmgandhi 18:6a4db94011d3 7755 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
sahilmgandhi 18:6a4db94011d3 7756 ((INSTANCE) == ADC2) || \
sahilmgandhi 18:6a4db94011d3 7757 ((INSTANCE) == ADC3))
sahilmgandhi 18:6a4db94011d3 7758
sahilmgandhi 18:6a4db94011d3 7759 /******************************* CAN Instances ********************************/
sahilmgandhi 18:6a4db94011d3 7760 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
sahilmgandhi 18:6a4db94011d3 7761 ((INSTANCE) == CAN2))
sahilmgandhi 18:6a4db94011d3 7762
sahilmgandhi 18:6a4db94011d3 7763 /******************************* CRC Instances ********************************/
sahilmgandhi 18:6a4db94011d3 7764 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
sahilmgandhi 18:6a4db94011d3 7765
sahilmgandhi 18:6a4db94011d3 7766 /******************************* DAC Instances ********************************/
sahilmgandhi 18:6a4db94011d3 7767 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
sahilmgandhi 18:6a4db94011d3 7768
sahilmgandhi 18:6a4db94011d3 7769 /******************************* DCMI Instances *******************************/
sahilmgandhi 18:6a4db94011d3 7770 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
sahilmgandhi 18:6a4db94011d3 7771
sahilmgandhi 18:6a4db94011d3 7772 /******************************** DMA Instances *******************************/
sahilmgandhi 18:6a4db94011d3 7773 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
sahilmgandhi 18:6a4db94011d3 7774 ((INSTANCE) == DMA1_Stream1) || \
sahilmgandhi 18:6a4db94011d3 7775 ((INSTANCE) == DMA1_Stream2) || \
sahilmgandhi 18:6a4db94011d3 7776 ((INSTANCE) == DMA1_Stream3) || \
sahilmgandhi 18:6a4db94011d3 7777 ((INSTANCE) == DMA1_Stream4) || \
sahilmgandhi 18:6a4db94011d3 7778 ((INSTANCE) == DMA1_Stream5) || \
sahilmgandhi 18:6a4db94011d3 7779 ((INSTANCE) == DMA1_Stream6) || \
sahilmgandhi 18:6a4db94011d3 7780 ((INSTANCE) == DMA1_Stream7) || \
sahilmgandhi 18:6a4db94011d3 7781 ((INSTANCE) == DMA2_Stream0) || \
sahilmgandhi 18:6a4db94011d3 7782 ((INSTANCE) == DMA2_Stream1) || \
sahilmgandhi 18:6a4db94011d3 7783 ((INSTANCE) == DMA2_Stream2) || \
sahilmgandhi 18:6a4db94011d3 7784 ((INSTANCE) == DMA2_Stream3) || \
sahilmgandhi 18:6a4db94011d3 7785 ((INSTANCE) == DMA2_Stream4) || \
sahilmgandhi 18:6a4db94011d3 7786 ((INSTANCE) == DMA2_Stream5) || \
sahilmgandhi 18:6a4db94011d3 7787 ((INSTANCE) == DMA2_Stream6) || \
sahilmgandhi 18:6a4db94011d3 7788 ((INSTANCE) == DMA2_Stream7))
sahilmgandhi 18:6a4db94011d3 7789
sahilmgandhi 18:6a4db94011d3 7790 /******************************* GPIO Instances *******************************/
sahilmgandhi 18:6a4db94011d3 7791 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
sahilmgandhi 18:6a4db94011d3 7792 ((INSTANCE) == GPIOB) || \
sahilmgandhi 18:6a4db94011d3 7793 ((INSTANCE) == GPIOC) || \
sahilmgandhi 18:6a4db94011d3 7794 ((INSTANCE) == GPIOD) || \
sahilmgandhi 18:6a4db94011d3 7795 ((INSTANCE) == GPIOE) || \
sahilmgandhi 18:6a4db94011d3 7796 ((INSTANCE) == GPIOF) || \
sahilmgandhi 18:6a4db94011d3 7797 ((INSTANCE) == GPIOG) || \
sahilmgandhi 18:6a4db94011d3 7798 ((INSTANCE) == GPIOH) || \
sahilmgandhi 18:6a4db94011d3 7799 ((INSTANCE) == GPIOI))
sahilmgandhi 18:6a4db94011d3 7800
sahilmgandhi 18:6a4db94011d3 7801 /******************************** I2C Instances *******************************/
sahilmgandhi 18:6a4db94011d3 7802 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
sahilmgandhi 18:6a4db94011d3 7803 ((INSTANCE) == I2C2) || \
sahilmgandhi 18:6a4db94011d3 7804 ((INSTANCE) == I2C3))
sahilmgandhi 18:6a4db94011d3 7805
sahilmgandhi 18:6a4db94011d3 7806 /******************************** I2S Instances *******************************/
sahilmgandhi 18:6a4db94011d3 7807 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
sahilmgandhi 18:6a4db94011d3 7808 ((INSTANCE) == SPI3))
sahilmgandhi 18:6a4db94011d3 7809
sahilmgandhi 18:6a4db94011d3 7810 /*************************** I2S Extended Instances ***************************/
sahilmgandhi 18:6a4db94011d3 7811 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
sahilmgandhi 18:6a4db94011d3 7812 ((INSTANCE) == SPI3) || \
sahilmgandhi 18:6a4db94011d3 7813 ((INSTANCE) == I2S2ext) || \
sahilmgandhi 18:6a4db94011d3 7814 ((INSTANCE) == I2S3ext))
sahilmgandhi 18:6a4db94011d3 7815
sahilmgandhi 18:6a4db94011d3 7816 /******************************* RNG Instances ********************************/
sahilmgandhi 18:6a4db94011d3 7817 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
sahilmgandhi 18:6a4db94011d3 7818
sahilmgandhi 18:6a4db94011d3 7819 /****************************** RTC Instances *********************************/
sahilmgandhi 18:6a4db94011d3 7820 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
sahilmgandhi 18:6a4db94011d3 7821
sahilmgandhi 18:6a4db94011d3 7822 /******************************** SPI Instances *******************************/
sahilmgandhi 18:6a4db94011d3 7823 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
sahilmgandhi 18:6a4db94011d3 7824 ((INSTANCE) == SPI2) || \
sahilmgandhi 18:6a4db94011d3 7825 ((INSTANCE) == SPI3))
sahilmgandhi 18:6a4db94011d3 7826
sahilmgandhi 18:6a4db94011d3 7827 /*************************** SPI Extended Instances ***************************/
sahilmgandhi 18:6a4db94011d3 7828 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
sahilmgandhi 18:6a4db94011d3 7829 ((INSTANCE) == SPI2) || \
sahilmgandhi 18:6a4db94011d3 7830 ((INSTANCE) == SPI3) || \
sahilmgandhi 18:6a4db94011d3 7831 ((INSTANCE) == I2S2ext) || \
sahilmgandhi 18:6a4db94011d3 7832 ((INSTANCE) == I2S3ext))
sahilmgandhi 18:6a4db94011d3 7833
sahilmgandhi 18:6a4db94011d3 7834 /****************** TIM Instances : All supported instances *******************/
sahilmgandhi 18:6a4db94011d3 7835 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7836 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7837 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7838 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 7839 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7840 ((INSTANCE) == TIM6) || \
sahilmgandhi 18:6a4db94011d3 7841 ((INSTANCE) == TIM7) || \
sahilmgandhi 18:6a4db94011d3 7842 ((INSTANCE) == TIM8) || \
sahilmgandhi 18:6a4db94011d3 7843 ((INSTANCE) == TIM9) || \
sahilmgandhi 18:6a4db94011d3 7844 ((INSTANCE) == TIM10) || \
sahilmgandhi 18:6a4db94011d3 7845 ((INSTANCE) == TIM11) || \
sahilmgandhi 18:6a4db94011d3 7846 ((INSTANCE) == TIM12) || \
sahilmgandhi 18:6a4db94011d3 7847 ((INSTANCE) == TIM13) || \
sahilmgandhi 18:6a4db94011d3 7848 ((INSTANCE) == TIM14))
sahilmgandhi 18:6a4db94011d3 7849
sahilmgandhi 18:6a4db94011d3 7850 /************* TIM Instances : at least 1 capture/compare channel *************/
sahilmgandhi 18:6a4db94011d3 7851 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7852 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7853 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7854 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 7855 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7856 ((INSTANCE) == TIM8) || \
sahilmgandhi 18:6a4db94011d3 7857 ((INSTANCE) == TIM9) || \
sahilmgandhi 18:6a4db94011d3 7858 ((INSTANCE) == TIM10) || \
sahilmgandhi 18:6a4db94011d3 7859 ((INSTANCE) == TIM11) || \
sahilmgandhi 18:6a4db94011d3 7860 ((INSTANCE) == TIM12) || \
sahilmgandhi 18:6a4db94011d3 7861 ((INSTANCE) == TIM13) || \
sahilmgandhi 18:6a4db94011d3 7862 ((INSTANCE) == TIM14))
sahilmgandhi 18:6a4db94011d3 7863
sahilmgandhi 18:6a4db94011d3 7864 /************ TIM Instances : at least 2 capture/compare channels *************/
sahilmgandhi 18:6a4db94011d3 7865 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7866 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7867 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7868 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 7869 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7870 ((INSTANCE) == TIM8) || \
sahilmgandhi 18:6a4db94011d3 7871 ((INSTANCE) == TIM9) || \
sahilmgandhi 18:6a4db94011d3 7872 ((INSTANCE) == TIM12))
sahilmgandhi 18:6a4db94011d3 7873
sahilmgandhi 18:6a4db94011d3 7874 /************ TIM Instances : at least 3 capture/compare channels *************/
sahilmgandhi 18:6a4db94011d3 7875 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7876 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7877 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7878 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 7879 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7880 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 7881
sahilmgandhi 18:6a4db94011d3 7882 /************ TIM Instances : at least 4 capture/compare channels *************/
sahilmgandhi 18:6a4db94011d3 7883 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7884 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7885 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7886 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 7887 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7888 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 7889
sahilmgandhi 18:6a4db94011d3 7890 /******************** TIM Instances : Advanced-control timers *****************/
sahilmgandhi 18:6a4db94011d3 7891 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7892 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 7893
sahilmgandhi 18:6a4db94011d3 7894 /******************* TIM Instances : Timer input XOR function *****************/
sahilmgandhi 18:6a4db94011d3 7895 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7896 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7897 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7898 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 7899 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7900 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 7901
sahilmgandhi 18:6a4db94011d3 7902 /****************** TIM Instances : DMA requests generation (UDE) *************/
sahilmgandhi 18:6a4db94011d3 7903 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7904 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7905 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7906 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 7907 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7908 ((INSTANCE) == TIM6) || \
sahilmgandhi 18:6a4db94011d3 7909 ((INSTANCE) == TIM7) || \
sahilmgandhi 18:6a4db94011d3 7910 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 7911
sahilmgandhi 18:6a4db94011d3 7912 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
sahilmgandhi 18:6a4db94011d3 7913 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7914 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7915 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7916 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 7917 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7918 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 7919
sahilmgandhi 18:6a4db94011d3 7920 /************ TIM Instances : DMA requests generation (COMDE) *****************/
sahilmgandhi 18:6a4db94011d3 7921 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7922 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7923 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7924 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 7925 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7926 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 7927
sahilmgandhi 18:6a4db94011d3 7928 /******************** TIM Instances : DMA burst feature ***********************/
sahilmgandhi 18:6a4db94011d3 7929 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7930 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7931 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7932 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 7933 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7934 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 7935
sahilmgandhi 18:6a4db94011d3 7936 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
sahilmgandhi 18:6a4db94011d3 7937 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7938 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7939 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7940 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 7941 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7942 ((INSTANCE) == TIM6) || \
sahilmgandhi 18:6a4db94011d3 7943 ((INSTANCE) == TIM7) || \
sahilmgandhi 18:6a4db94011d3 7944 ((INSTANCE) == TIM8) || \
sahilmgandhi 18:6a4db94011d3 7945 ((INSTANCE) == TIM9) || \
sahilmgandhi 18:6a4db94011d3 7946 ((INSTANCE) == TIM12))
sahilmgandhi 18:6a4db94011d3 7947
sahilmgandhi 18:6a4db94011d3 7948 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
sahilmgandhi 18:6a4db94011d3 7949 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7950 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7951 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7952 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 7953 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7954 ((INSTANCE) == TIM8) || \
sahilmgandhi 18:6a4db94011d3 7955 ((INSTANCE) == TIM9) || \
sahilmgandhi 18:6a4db94011d3 7956 ((INSTANCE) == TIM12))
sahilmgandhi 18:6a4db94011d3 7957
sahilmgandhi 18:6a4db94011d3 7958 /********************** TIM Instances : 32 bit Counter ************************/
sahilmgandhi 18:6a4db94011d3 7959 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7960 ((INSTANCE) == TIM5))
sahilmgandhi 18:6a4db94011d3 7961
sahilmgandhi 18:6a4db94011d3 7962 /***************** TIM Instances : external trigger input availabe ************/
sahilmgandhi 18:6a4db94011d3 7963 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 7964 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7965 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 7966 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 7967 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7968 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 7969
sahilmgandhi 18:6a4db94011d3 7970 /****************** TIM Instances : remapping capability **********************/
sahilmgandhi 18:6a4db94011d3 7971 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 7972 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 7973 ((INSTANCE) == TIM11))
sahilmgandhi 18:6a4db94011d3 7974
sahilmgandhi 18:6a4db94011d3 7975 /******************* TIM Instances : output(s) available **********************/
sahilmgandhi 18:6a4db94011d3 7976 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
sahilmgandhi 18:6a4db94011d3 7977 ((((INSTANCE) == TIM1) && \
sahilmgandhi 18:6a4db94011d3 7978 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 7979 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 7980 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 7981 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 7982 || \
sahilmgandhi 18:6a4db94011d3 7983 (((INSTANCE) == TIM2) && \
sahilmgandhi 18:6a4db94011d3 7984 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 7985 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 7986 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 7987 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 7988 || \
sahilmgandhi 18:6a4db94011d3 7989 (((INSTANCE) == TIM3) && \
sahilmgandhi 18:6a4db94011d3 7990 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 7991 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 7992 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 7993 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 7994 || \
sahilmgandhi 18:6a4db94011d3 7995 (((INSTANCE) == TIM4) && \
sahilmgandhi 18:6a4db94011d3 7996 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 7997 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 7998 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 7999 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 8000 || \
sahilmgandhi 18:6a4db94011d3 8001 (((INSTANCE) == TIM5) && \
sahilmgandhi 18:6a4db94011d3 8002 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 8003 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 8004 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 8005 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 8006 || \
sahilmgandhi 18:6a4db94011d3 8007 (((INSTANCE) == TIM8) && \
sahilmgandhi 18:6a4db94011d3 8008 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 8009 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 8010 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 8011 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 8012 || \
sahilmgandhi 18:6a4db94011d3 8013 (((INSTANCE) == TIM9) && \
sahilmgandhi 18:6a4db94011d3 8014 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 8015 ((CHANNEL) == TIM_CHANNEL_2))) \
sahilmgandhi 18:6a4db94011d3 8016 || \
sahilmgandhi 18:6a4db94011d3 8017 (((INSTANCE) == TIM10) && \
sahilmgandhi 18:6a4db94011d3 8018 (((CHANNEL) == TIM_CHANNEL_1))) \
sahilmgandhi 18:6a4db94011d3 8019 || \
sahilmgandhi 18:6a4db94011d3 8020 (((INSTANCE) == TIM11) && \
sahilmgandhi 18:6a4db94011d3 8021 (((CHANNEL) == TIM_CHANNEL_1))) \
sahilmgandhi 18:6a4db94011d3 8022 || \
sahilmgandhi 18:6a4db94011d3 8023 (((INSTANCE) == TIM12) && \
sahilmgandhi 18:6a4db94011d3 8024 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 8025 ((CHANNEL) == TIM_CHANNEL_2))) \
sahilmgandhi 18:6a4db94011d3 8026 || \
sahilmgandhi 18:6a4db94011d3 8027 (((INSTANCE) == TIM13) && \
sahilmgandhi 18:6a4db94011d3 8028 (((CHANNEL) == TIM_CHANNEL_1))) \
sahilmgandhi 18:6a4db94011d3 8029 || \
sahilmgandhi 18:6a4db94011d3 8030 (((INSTANCE) == TIM14) && \
sahilmgandhi 18:6a4db94011d3 8031 (((CHANNEL) == TIM_CHANNEL_1))))
sahilmgandhi 18:6a4db94011d3 8032
sahilmgandhi 18:6a4db94011d3 8033 /************ TIM Instances : complementary output(s) available ***************/
sahilmgandhi 18:6a4db94011d3 8034 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
sahilmgandhi 18:6a4db94011d3 8035 ((((INSTANCE) == TIM1) && \
sahilmgandhi 18:6a4db94011d3 8036 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 8037 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 8038 ((CHANNEL) == TIM_CHANNEL_3))) \
sahilmgandhi 18:6a4db94011d3 8039 || \
sahilmgandhi 18:6a4db94011d3 8040 (((INSTANCE) == TIM8) && \
sahilmgandhi 18:6a4db94011d3 8041 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 8042 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 8043 ((CHANNEL) == TIM_CHANNEL_3))))
sahilmgandhi 18:6a4db94011d3 8044
sahilmgandhi 18:6a4db94011d3 8045 /******************** USART Instances : Synchronous mode **********************/
sahilmgandhi 18:6a4db94011d3 8046 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 8047 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 8048 ((INSTANCE) == USART3) || \
sahilmgandhi 18:6a4db94011d3 8049 ((INSTANCE) == USART6))
sahilmgandhi 18:6a4db94011d3 8050
sahilmgandhi 18:6a4db94011d3 8051 /******************** UART Instances : Asynchronous mode **********************/
sahilmgandhi 18:6a4db94011d3 8052 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 8053 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 8054 ((INSTANCE) == USART3) || \
sahilmgandhi 18:6a4db94011d3 8055 ((INSTANCE) == UART4) || \
sahilmgandhi 18:6a4db94011d3 8056 ((INSTANCE) == UART5) || \
sahilmgandhi 18:6a4db94011d3 8057 ((INSTANCE) == USART6))
sahilmgandhi 18:6a4db94011d3 8058
sahilmgandhi 18:6a4db94011d3 8059 /****************** UART Instances : Hardware Flow control ********************/
sahilmgandhi 18:6a4db94011d3 8060 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 8061 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 8062 ((INSTANCE) == USART3) || \
sahilmgandhi 18:6a4db94011d3 8063 ((INSTANCE) == USART6))
sahilmgandhi 18:6a4db94011d3 8064
sahilmgandhi 18:6a4db94011d3 8065 /********************* UART Instances : Smard card mode ***********************/
sahilmgandhi 18:6a4db94011d3 8066 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 8067 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 8068 ((INSTANCE) == USART3) || \
sahilmgandhi 18:6a4db94011d3 8069 ((INSTANCE) == USART6))
sahilmgandhi 18:6a4db94011d3 8070
sahilmgandhi 18:6a4db94011d3 8071 /*********************** UART Instances : IRDA mode ***************************/
sahilmgandhi 18:6a4db94011d3 8072 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 8073 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 8074 ((INSTANCE) == USART3) || \
sahilmgandhi 18:6a4db94011d3 8075 ((INSTANCE) == UART4) || \
sahilmgandhi 18:6a4db94011d3 8076 ((INSTANCE) == UART5) || \
sahilmgandhi 18:6a4db94011d3 8077 ((INSTANCE) == USART6))
sahilmgandhi 18:6a4db94011d3 8078
sahilmgandhi 18:6a4db94011d3 8079 /*********************** PCD Instances ****************************************/
sahilmgandhi 18:6a4db94011d3 8080 /*********************** PCD Instances ****************************************/
sahilmgandhi 18:6a4db94011d3 8081 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
sahilmgandhi 18:6a4db94011d3 8082 ((INSTANCE) == USB_OTG_HS))
sahilmgandhi 18:6a4db94011d3 8083
sahilmgandhi 18:6a4db94011d3 8084 /*********************** HCD Instances ****************************************/
sahilmgandhi 18:6a4db94011d3 8085 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
sahilmgandhi 18:6a4db94011d3 8086 ((INSTANCE) == USB_OTG_HS))
sahilmgandhi 18:6a4db94011d3 8087
sahilmgandhi 18:6a4db94011d3 8088 /****************************** IWDG Instances ********************************/
sahilmgandhi 18:6a4db94011d3 8089 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
sahilmgandhi 18:6a4db94011d3 8090
sahilmgandhi 18:6a4db94011d3 8091 /****************************** WWDG Instances ********************************/
sahilmgandhi 18:6a4db94011d3 8092 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
sahilmgandhi 18:6a4db94011d3 8093
sahilmgandhi 18:6a4db94011d3 8094 /****************************** SDIO Instances ********************************/
sahilmgandhi 18:6a4db94011d3 8095 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
sahilmgandhi 18:6a4db94011d3 8096
sahilmgandhi 18:6a4db94011d3 8097 /****************************** USB Exported Constants ************************/
sahilmgandhi 18:6a4db94011d3 8098 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
sahilmgandhi 18:6a4db94011d3 8099 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
sahilmgandhi 18:6a4db94011d3 8100 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
sahilmgandhi 18:6a4db94011d3 8101 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
sahilmgandhi 18:6a4db94011d3 8102
sahilmgandhi 18:6a4db94011d3 8103 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
sahilmgandhi 18:6a4db94011d3 8104 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
sahilmgandhi 18:6a4db94011d3 8105 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
sahilmgandhi 18:6a4db94011d3 8106 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
sahilmgandhi 18:6a4db94011d3 8107
sahilmgandhi 18:6a4db94011d3 8108 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 8109 /* For a painless codes migration between the STM32F4xx device product */
sahilmgandhi 18:6a4db94011d3 8110 /* lines, the aliases defined below are put in place to overcome the */
sahilmgandhi 18:6a4db94011d3 8111 /* differences in the interrupt handlers and IRQn definitions. */
sahilmgandhi 18:6a4db94011d3 8112 /* No need to update developed interrupt code when moving across */
sahilmgandhi 18:6a4db94011d3 8113 /* product lines within the same STM32F4 Family */
sahilmgandhi 18:6a4db94011d3 8114 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 8115
sahilmgandhi 18:6a4db94011d3 8116 /* Aliases for __IRQn */
sahilmgandhi 18:6a4db94011d3 8117 #define FMC_IRQn FSMC_IRQn
sahilmgandhi 18:6a4db94011d3 8118
sahilmgandhi 18:6a4db94011d3 8119 /* Aliases for __IRQHandler */
sahilmgandhi 18:6a4db94011d3 8120 #define FMC_IRQHandler FSMC_IRQHandler
sahilmgandhi 18:6a4db94011d3 8121
sahilmgandhi 18:6a4db94011d3 8122 /**
sahilmgandhi 18:6a4db94011d3 8123 * @}
sahilmgandhi 18:6a4db94011d3 8124 */
sahilmgandhi 18:6a4db94011d3 8125
sahilmgandhi 18:6a4db94011d3 8126 /**
sahilmgandhi 18:6a4db94011d3 8127 * @}
sahilmgandhi 18:6a4db94011d3 8128 */
sahilmgandhi 18:6a4db94011d3 8129
sahilmgandhi 18:6a4db94011d3 8130 /**
sahilmgandhi 18:6a4db94011d3 8131 * @}
sahilmgandhi 18:6a4db94011d3 8132 */
sahilmgandhi 18:6a4db94011d3 8133
sahilmgandhi 18:6a4db94011d3 8134 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 8135 }
sahilmgandhi 18:6a4db94011d3 8136 #endif /* __cplusplus */
sahilmgandhi 18:6a4db94011d3 8137
sahilmgandhi 18:6a4db94011d3 8138 #endif /* __STM32F407xx_H */
sahilmgandhi 18:6a4db94011d3 8139
sahilmgandhi 18:6a4db94011d3 8140
sahilmgandhi 18:6a4db94011d3 8141
sahilmgandhi 18:6a4db94011d3 8142 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/