MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* File: startup_STM32F40x.S
sahilmgandhi 18:6a4db94011d3 2 * Purpose: startup file for Cortex-M4 devices. Should use with
sahilmgandhi 18:6a4db94011d3 3 * GCC for ARM Embedded Processors
sahilmgandhi 18:6a4db94011d3 4 * Version: V1.4
sahilmgandhi 18:6a4db94011d3 5 * Date: 09 July 2012
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * Copyright (c) 2011, 2012, ARM Limited
sahilmgandhi 18:6a4db94011d3 8 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 11 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 12 * Redistributions of source code must retain the above copyright
sahilmgandhi 18:6a4db94011d3 13 notice, this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 14 * Redistributions in binary form must reproduce the above copyright
sahilmgandhi 18:6a4db94011d3 15 notice, this list of conditions and the following disclaimer in the
sahilmgandhi 18:6a4db94011d3 16 documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 17 * Neither the name of the ARM Limited nor the
sahilmgandhi 18:6a4db94011d3 18 names of its contributors may be used to endorse or promote products
sahilmgandhi 18:6a4db94011d3 19 derived from this software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 20 *
sahilmgandhi 18:6a4db94011d3 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
sahilmgandhi 18:6a4db94011d3 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
sahilmgandhi 18:6a4db94011d3 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 24 * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
sahilmgandhi 18:6a4db94011d3 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
sahilmgandhi 18:6a4db94011d3 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
sahilmgandhi 18:6a4db94011d3 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
sahilmgandhi 18:6a4db94011d3 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
sahilmgandhi 18:6a4db94011d3 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
sahilmgandhi 18:6a4db94011d3 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 31 */
sahilmgandhi 18:6a4db94011d3 32 .syntax unified
sahilmgandhi 18:6a4db94011d3 33 .arch armv7-m
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 .section .stack
sahilmgandhi 18:6a4db94011d3 36 .align 3
sahilmgandhi 18:6a4db94011d3 37 #ifdef __STACK_SIZE
sahilmgandhi 18:6a4db94011d3 38 .equ Stack_Size, __STACK_SIZE
sahilmgandhi 18:6a4db94011d3 39 #else
sahilmgandhi 18:6a4db94011d3 40 .equ Stack_Size, 0xc00
sahilmgandhi 18:6a4db94011d3 41 #endif
sahilmgandhi 18:6a4db94011d3 42 .globl __StackTop
sahilmgandhi 18:6a4db94011d3 43 .globl __StackLimit
sahilmgandhi 18:6a4db94011d3 44 __StackLimit:
sahilmgandhi 18:6a4db94011d3 45 .space Stack_Size
sahilmgandhi 18:6a4db94011d3 46 .size __StackLimit, . - __StackLimit
sahilmgandhi 18:6a4db94011d3 47 __StackTop:
sahilmgandhi 18:6a4db94011d3 48 .size __StackTop, . - __StackTop
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 .section .heap
sahilmgandhi 18:6a4db94011d3 51 .align 3
sahilmgandhi 18:6a4db94011d3 52 #ifdef __HEAP_SIZE
sahilmgandhi 18:6a4db94011d3 53 .equ Heap_Size, __HEAP_SIZE
sahilmgandhi 18:6a4db94011d3 54 #else
sahilmgandhi 18:6a4db94011d3 55 .equ Heap_Size, 0x400
sahilmgandhi 18:6a4db94011d3 56 #endif
sahilmgandhi 18:6a4db94011d3 57 .globl __HeapBase
sahilmgandhi 18:6a4db94011d3 58 .globl __HeapLimit
sahilmgandhi 18:6a4db94011d3 59 __HeapBase:
sahilmgandhi 18:6a4db94011d3 60 .if Heap_Size
sahilmgandhi 18:6a4db94011d3 61 .space Heap_Size
sahilmgandhi 18:6a4db94011d3 62 .endif
sahilmgandhi 18:6a4db94011d3 63 .size __HeapBase, . - __HeapBase
sahilmgandhi 18:6a4db94011d3 64 __HeapLimit:
sahilmgandhi 18:6a4db94011d3 65 .size __HeapLimit, . - __HeapLimit
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 .section .isr_vector
sahilmgandhi 18:6a4db94011d3 68 .align 2
sahilmgandhi 18:6a4db94011d3 69 .globl __isr_vector
sahilmgandhi 18:6a4db94011d3 70 __isr_vector:
sahilmgandhi 18:6a4db94011d3 71 .long __StackTop /* Top of Stack */
sahilmgandhi 18:6a4db94011d3 72 .long Reset_Handler /* Reset Handler */
sahilmgandhi 18:6a4db94011d3 73 .long NMI_Handler /* NMI Handler */
sahilmgandhi 18:6a4db94011d3 74 .long HardFault_Handler /* Hard Fault Handler */
sahilmgandhi 18:6a4db94011d3 75 .long MemManage_Handler /* MPU Fault Handler */
sahilmgandhi 18:6a4db94011d3 76 .long BusFault_Handler /* Bus Fault Handler */
sahilmgandhi 18:6a4db94011d3 77 .long UsageFault_Handler /* Usage Fault Handler */
sahilmgandhi 18:6a4db94011d3 78 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 79 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 80 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 81 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 82 .long SVC_Handler /* SVCall Handler */
sahilmgandhi 18:6a4db94011d3 83 .long DebugMon_Handler /* Debug Monitor Handler */
sahilmgandhi 18:6a4db94011d3 84 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 85 .long PendSV_Handler /* PendSV Handler */
sahilmgandhi 18:6a4db94011d3 86 .long SysTick_Handler /* SysTick Handler */
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /* External interrupts */
sahilmgandhi 18:6a4db94011d3 89 .long WWDG_IRQHandler /* Window WatchDog */
sahilmgandhi 18:6a4db94011d3 90 .long PVD_IRQHandler /* PVD through EXTI Line detection */
sahilmgandhi 18:6a4db94011d3 91 .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
sahilmgandhi 18:6a4db94011d3 92 .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
sahilmgandhi 18:6a4db94011d3 93 .long FLASH_IRQHandler /* FLASH */
sahilmgandhi 18:6a4db94011d3 94 .long RCC_IRQHandler /* RCC */
sahilmgandhi 18:6a4db94011d3 95 .long EXTI0_IRQHandler /* EXTI Line0 */
sahilmgandhi 18:6a4db94011d3 96 .long EXTI1_IRQHandler /* EXTI Line1 */
sahilmgandhi 18:6a4db94011d3 97 .long EXTI2_IRQHandler /* EXTI Line2 */
sahilmgandhi 18:6a4db94011d3 98 .long EXTI3_IRQHandler /* EXTI Line3 */
sahilmgandhi 18:6a4db94011d3 99 .long EXTI4_IRQHandler /* EXTI Line4 */
sahilmgandhi 18:6a4db94011d3 100 .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
sahilmgandhi 18:6a4db94011d3 101 .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
sahilmgandhi 18:6a4db94011d3 102 .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
sahilmgandhi 18:6a4db94011d3 103 .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
sahilmgandhi 18:6a4db94011d3 104 .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
sahilmgandhi 18:6a4db94011d3 105 .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
sahilmgandhi 18:6a4db94011d3 106 .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
sahilmgandhi 18:6a4db94011d3 107 .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
sahilmgandhi 18:6a4db94011d3 108 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 109 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 110 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 111 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 112 .long EXTI9_5_IRQHandler /* External Line[9:5]s */
sahilmgandhi 18:6a4db94011d3 113 .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
sahilmgandhi 18:6a4db94011d3 114 .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
sahilmgandhi 18:6a4db94011d3 115 .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
sahilmgandhi 18:6a4db94011d3 116 .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
sahilmgandhi 18:6a4db94011d3 117 .long TIM2_IRQHandler /* TIM2 */
sahilmgandhi 18:6a4db94011d3 118 .long TIM3_IRQHandler /* TIM3 */
sahilmgandhi 18:6a4db94011d3 119 .long TIM4_IRQHandler /* TIM4 */
sahilmgandhi 18:6a4db94011d3 120 .long I2C1_EV_IRQHandler /* I2C1 Event */
sahilmgandhi 18:6a4db94011d3 121 .long I2C1_ER_IRQHandler /* I2C1 Error */
sahilmgandhi 18:6a4db94011d3 122 .long I2C2_EV_IRQHandler /* I2C2 Event */
sahilmgandhi 18:6a4db94011d3 123 .long I2C2_ER_IRQHandler /* I2C2 Error */
sahilmgandhi 18:6a4db94011d3 124 .long SPI1_IRQHandler /* SPI1 */
sahilmgandhi 18:6a4db94011d3 125 .long SPI2_IRQHandler /* SPI2 */
sahilmgandhi 18:6a4db94011d3 126 .long USART1_IRQHandler /* USART1 */
sahilmgandhi 18:6a4db94011d3 127 .long USART2_IRQHandler /* USART2 */
sahilmgandhi 18:6a4db94011d3 128 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 129 .long EXTI15_10_IRQHandler /* External Line[15:10]s */
sahilmgandhi 18:6a4db94011d3 130 .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
sahilmgandhi 18:6a4db94011d3 131 .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
sahilmgandhi 18:6a4db94011d3 132 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 133 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 134 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 135 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 136 .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
sahilmgandhi 18:6a4db94011d3 137 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 138 .long SDIO_IRQHandler /* SDIO */
sahilmgandhi 18:6a4db94011d3 139 .long TIM5_IRQHandler /* TIM5 */
sahilmgandhi 18:6a4db94011d3 140 .long SPI3_IRQHandler /* SPI3 */
sahilmgandhi 18:6a4db94011d3 141 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 142 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 143 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 144 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 145 .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
sahilmgandhi 18:6a4db94011d3 146 .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
sahilmgandhi 18:6a4db94011d3 147 .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
sahilmgandhi 18:6a4db94011d3 148 .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
sahilmgandhi 18:6a4db94011d3 149 .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
sahilmgandhi 18:6a4db94011d3 150 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 151 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 152 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 153 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 154 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 155 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 156 .long OTG_FS_IRQHandler /* USB OTG FS */
sahilmgandhi 18:6a4db94011d3 157 .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
sahilmgandhi 18:6a4db94011d3 158 .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
sahilmgandhi 18:6a4db94011d3 159 .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
sahilmgandhi 18:6a4db94011d3 160 .long USART6_IRQHandler /* USART6 */
sahilmgandhi 18:6a4db94011d3 161 .long I2C3_EV_IRQHandler /* I2C3 event */
sahilmgandhi 18:6a4db94011d3 162 .long I2C3_ER_IRQHandler /* I2C3 error */
sahilmgandhi 18:6a4db94011d3 163 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 164 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 165 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 166 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 167 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 168 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 169 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 170 .long FPU_IRQHandler /* FPU */
sahilmgandhi 18:6a4db94011d3 171 .long SPI4_IRQHandler /* SPI4 */
sahilmgandhi 18:6a4db94011d3 172 .long SPI5_IRQHandler /* SPI5 */
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 .size __isr_vector, . - __isr_vector
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 .text
sahilmgandhi 18:6a4db94011d3 177 .thumb
sahilmgandhi 18:6a4db94011d3 178 .thumb_func
sahilmgandhi 18:6a4db94011d3 179 .align 2
sahilmgandhi 18:6a4db94011d3 180 .globl Reset_Handler
sahilmgandhi 18:6a4db94011d3 181 .type Reset_Handler, %function
sahilmgandhi 18:6a4db94011d3 182 Reset_Handler:
sahilmgandhi 18:6a4db94011d3 183 /* Loop to copy data from read only memory to RAM. The ranges
sahilmgandhi 18:6a4db94011d3 184 * of copy from/to are specified by following symbols evaluated in
sahilmgandhi 18:6a4db94011d3 185 * linker script.
sahilmgandhi 18:6a4db94011d3 186 * __etext: End of code section, i.e., begin of data sections to copy from.
sahilmgandhi 18:6a4db94011d3 187 * __data_start__/__data_end__: RAM address range that data should be
sahilmgandhi 18:6a4db94011d3 188 * copied to. Both must be aligned to 4 bytes boundary. */
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 ldr r1, =__etext
sahilmgandhi 18:6a4db94011d3 191 ldr r2, =__data_start__
sahilmgandhi 18:6a4db94011d3 192 ldr r3, =__data_end__
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 .LC0:
sahilmgandhi 18:6a4db94011d3 195 cmp r2, r3
sahilmgandhi 18:6a4db94011d3 196 ittt lt
sahilmgandhi 18:6a4db94011d3 197 ldrlt r0, [r1], #4
sahilmgandhi 18:6a4db94011d3 198 strlt r0, [r2], #4
sahilmgandhi 18:6a4db94011d3 199 blt .LC0
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 ldr r0, =SystemInit
sahilmgandhi 18:6a4db94011d3 202 blx r0
sahilmgandhi 18:6a4db94011d3 203 ldr r0, =_start
sahilmgandhi 18:6a4db94011d3 204 bx r0
sahilmgandhi 18:6a4db94011d3 205 .pool
sahilmgandhi 18:6a4db94011d3 206 .size Reset_Handler, . - Reset_Handler
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 .text
sahilmgandhi 18:6a4db94011d3 209 /* Macro to define default handlers. Default handler
sahilmgandhi 18:6a4db94011d3 210 * will be weak symbol and just dead loops. They can be
sahilmgandhi 18:6a4db94011d3 211 * overwritten by other handlers */
sahilmgandhi 18:6a4db94011d3 212 .macro def_default_handler handler_name
sahilmgandhi 18:6a4db94011d3 213 .align 1
sahilmgandhi 18:6a4db94011d3 214 .thumb_func
sahilmgandhi 18:6a4db94011d3 215 .weak \handler_name
sahilmgandhi 18:6a4db94011d3 216 .type \handler_name, %function
sahilmgandhi 18:6a4db94011d3 217 \handler_name :
sahilmgandhi 18:6a4db94011d3 218 b .
sahilmgandhi 18:6a4db94011d3 219 .size \handler_name, . - \handler_name
sahilmgandhi 18:6a4db94011d3 220 .endm
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 def_default_handler NMI_Handler
sahilmgandhi 18:6a4db94011d3 223 def_default_handler HardFault_Handler
sahilmgandhi 18:6a4db94011d3 224 def_default_handler MemManage_Handler
sahilmgandhi 18:6a4db94011d3 225 def_default_handler BusFault_Handler
sahilmgandhi 18:6a4db94011d3 226 def_default_handler UsageFault_Handler
sahilmgandhi 18:6a4db94011d3 227 def_default_handler SVC_Handler
sahilmgandhi 18:6a4db94011d3 228 def_default_handler DebugMon_Handler
sahilmgandhi 18:6a4db94011d3 229 def_default_handler PendSV_Handler
sahilmgandhi 18:6a4db94011d3 230 def_default_handler SysTick_Handler
sahilmgandhi 18:6a4db94011d3 231 def_default_handler Default_Handler
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 .macro def_irq_default_handler handler_name
sahilmgandhi 18:6a4db94011d3 234 .weak \handler_name
sahilmgandhi 18:6a4db94011d3 235 .set \handler_name, Default_Handler
sahilmgandhi 18:6a4db94011d3 236 .endm
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 def_irq_default_handler WWDG_IRQHandler
sahilmgandhi 18:6a4db94011d3 239 def_irq_default_handler PVD_IRQHandler
sahilmgandhi 18:6a4db94011d3 240 def_irq_default_handler TAMP_STAMP_IRQHandler
sahilmgandhi 18:6a4db94011d3 241 def_irq_default_handler RTC_WKUP_IRQHandler
sahilmgandhi 18:6a4db94011d3 242 def_irq_default_handler FLASH_IRQHandler
sahilmgandhi 18:6a4db94011d3 243 def_irq_default_handler RCC_IRQHandler
sahilmgandhi 18:6a4db94011d3 244 def_irq_default_handler EXTI0_IRQHandler
sahilmgandhi 18:6a4db94011d3 245 def_irq_default_handler EXTI1_IRQHandler
sahilmgandhi 18:6a4db94011d3 246 def_irq_default_handler EXTI2_IRQHandler
sahilmgandhi 18:6a4db94011d3 247 def_irq_default_handler EXTI3_IRQHandler
sahilmgandhi 18:6a4db94011d3 248 def_irq_default_handler EXTI4_IRQHandler
sahilmgandhi 18:6a4db94011d3 249 def_irq_default_handler DMA1_Stream0_IRQHandler
sahilmgandhi 18:6a4db94011d3 250 def_irq_default_handler DMA1_Stream1_IRQHandler
sahilmgandhi 18:6a4db94011d3 251 def_irq_default_handler DMA1_Stream2_IRQHandler
sahilmgandhi 18:6a4db94011d3 252 def_irq_default_handler DMA1_Stream3_IRQHandler
sahilmgandhi 18:6a4db94011d3 253 def_irq_default_handler DMA1_Stream4_IRQHandler
sahilmgandhi 18:6a4db94011d3 254 def_irq_default_handler DMA1_Stream5_IRQHandler
sahilmgandhi 18:6a4db94011d3 255 def_irq_default_handler DMA1_Stream6_IRQHandler
sahilmgandhi 18:6a4db94011d3 256 def_irq_default_handler ADC_IRQHandler
sahilmgandhi 18:6a4db94011d3 257 def_irq_default_handler EXTI9_5_IRQHandler
sahilmgandhi 18:6a4db94011d3 258 def_irq_default_handler TIM1_BRK_TIM9_IRQHandler
sahilmgandhi 18:6a4db94011d3 259 def_irq_default_handler TIM1_UP_TIM10_IRQHandler
sahilmgandhi 18:6a4db94011d3 260 def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler
sahilmgandhi 18:6a4db94011d3 261 def_irq_default_handler TIM1_CC_IRQHandler
sahilmgandhi 18:6a4db94011d3 262 def_irq_default_handler TIM2_IRQHandler
sahilmgandhi 18:6a4db94011d3 263 def_irq_default_handler TIM3_IRQHandler
sahilmgandhi 18:6a4db94011d3 264 def_irq_default_handler TIM4_IRQHandler
sahilmgandhi 18:6a4db94011d3 265 def_irq_default_handler I2C1_EV_IRQHandler
sahilmgandhi 18:6a4db94011d3 266 def_irq_default_handler I2C1_ER_IRQHandler
sahilmgandhi 18:6a4db94011d3 267 def_irq_default_handler I2C2_EV_IRQHandler
sahilmgandhi 18:6a4db94011d3 268 def_irq_default_handler I2C2_ER_IRQHandler
sahilmgandhi 18:6a4db94011d3 269 def_irq_default_handler SPI1_IRQHandler
sahilmgandhi 18:6a4db94011d3 270 def_irq_default_handler SPI2_IRQHandler
sahilmgandhi 18:6a4db94011d3 271 def_irq_default_handler USART1_IRQHandler
sahilmgandhi 18:6a4db94011d3 272 def_irq_default_handler USART2_IRQHandler
sahilmgandhi 18:6a4db94011d3 273 def_irq_default_handler EXTI15_10_IRQHandler
sahilmgandhi 18:6a4db94011d3 274 def_irq_default_handler RTC_Alarm_IRQHandler
sahilmgandhi 18:6a4db94011d3 275 def_irq_default_handler OTG_FS_WKUP_IRQHandler
sahilmgandhi 18:6a4db94011d3 276 def_irq_default_handler DMA1_Stream7_IRQHandler
sahilmgandhi 18:6a4db94011d3 277 def_irq_default_handler SDIO_IRQHandler
sahilmgandhi 18:6a4db94011d3 278 def_irq_default_handler TIM5_IRQHandler
sahilmgandhi 18:6a4db94011d3 279 def_irq_default_handler SPI3_IRQHandler
sahilmgandhi 18:6a4db94011d3 280 def_irq_default_handler DMA2_Stream0_IRQHandler
sahilmgandhi 18:6a4db94011d3 281 def_irq_default_handler DMA2_Stream1_IRQHandler
sahilmgandhi 18:6a4db94011d3 282 def_irq_default_handler DMA2_Stream2_IRQHandler
sahilmgandhi 18:6a4db94011d3 283 def_irq_default_handler DMA2_Stream3_IRQHandler
sahilmgandhi 18:6a4db94011d3 284 def_irq_default_handler DMA2_Stream4_IRQHandler
sahilmgandhi 18:6a4db94011d3 285 def_irq_default_handler OTG_FS_IRQHandler
sahilmgandhi 18:6a4db94011d3 286 def_irq_default_handler DMA2_Stream5_IRQHandler
sahilmgandhi 18:6a4db94011d3 287 def_irq_default_handler DMA2_Stream6_IRQHandler
sahilmgandhi 18:6a4db94011d3 288 def_irq_default_handler DMA2_Stream7_IRQHandler
sahilmgandhi 18:6a4db94011d3 289 def_irq_default_handler USART6_IRQHandler
sahilmgandhi 18:6a4db94011d3 290 def_irq_default_handler I2C3_EV_IRQHandler
sahilmgandhi 18:6a4db94011d3 291 def_irq_default_handler I2C3_ER_IRQHandler
sahilmgandhi 18:6a4db94011d3 292 def_irq_default_handler FPU_IRQHandler
sahilmgandhi 18:6a4db94011d3 293 def_irq_default_handler SPI4_IRQHandler
sahilmgandhi 18:6a4db94011d3 294 def_irq_default_handler SPI5_IRQHandler
sahilmgandhi 18:6a4db94011d3 295 def_irq_default_handler DEF_IRQHandler
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 .end