MouseCode - Mouse code for the MacroRat

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Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_usb.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:: sahilmgandhi
Date:: Sat Jun 03 00:22:44 2017 +0000
Revision:: 46:b156ef445742
Parent:: 18:6a4db94011d3

Final code for internal battlebot competition.

Who changed what in which revision?

User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/**
sahilmgandhi	18:6a4db94011d3	2	******************************************************************************
sahilmgandhi	18:6a4db94011d3	3	* @file stm32f2xx_ll_usb.c
sahilmgandhi	18:6a4db94011d3	4	* @author MCD Application Team
sahilmgandhi	18:6a4db94011d3	5	* @version V1.1.2
sahilmgandhi	18:6a4db94011d3	6	* @date 11-December-2015
sahilmgandhi	18:6a4db94011d3	7	* @brief USB Low Layer HAL module driver.
sahilmgandhi	18:6a4db94011d3	8	*
sahilmgandhi	18:6a4db94011d3	9	* This file provides firmware functions to manage the following
sahilmgandhi	18:6a4db94011d3	10	* functionalities of the USB Peripheral Controller:
sahilmgandhi	18:6a4db94011d3	11	* + Initialization/de-initialization functions
sahilmgandhi	18:6a4db94011d3	12	* + I/O operation functions
sahilmgandhi	18:6a4db94011d3	13	* + Peripheral Control functions
sahilmgandhi	18:6a4db94011d3	14	* + Peripheral State functions
sahilmgandhi	18:6a4db94011d3	15	*
sahilmgandhi	18:6a4db94011d3	16	@verbatim
sahilmgandhi	18:6a4db94011d3	17	==============================================================================
sahilmgandhi	18:6a4db94011d3	18	##### How to use this driver #####
sahilmgandhi	18:6a4db94011d3	19	==============================================================================
sahilmgandhi	18:6a4db94011d3	20	[..]
sahilmgandhi	18:6a4db94011d3	21	(#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
sahilmgandhi	18:6a4db94011d3	22
sahilmgandhi	18:6a4db94011d3	23	(#) Call USB_CoreInit() API to initialize the USB Core peripheral.
sahilmgandhi	18:6a4db94011d3	24
sahilmgandhi	18:6a4db94011d3	25	(#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
sahilmgandhi	18:6a4db94011d3	26
sahilmgandhi	18:6a4db94011d3	27	@endverbatim
sahilmgandhi	18:6a4db94011d3	28	******************************************************************************
sahilmgandhi	18:6a4db94011d3	29	* @attention
sahilmgandhi	18:6a4db94011d3	30	*
sahilmgandhi	18:6a4db94011d3	31	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
sahilmgandhi	18:6a4db94011d3	32	*
sahilmgandhi	18:6a4db94011d3	33	* Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi	18:6a4db94011d3	34	* are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	35	* 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi	18:6a4db94011d3	36	* this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	37	* 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi	18:6a4db94011d3	38	* this list of conditions and the following disclaimer in the documentation
sahilmgandhi	18:6a4db94011d3	39	* and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	40	* 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi	18:6a4db94011d3	41	* may be used to endorse or promote products derived from this software
sahilmgandhi	18:6a4db94011d3	42	* without specific prior written permission.
sahilmgandhi	18:6a4db94011d3	43	*
sahilmgandhi	18:6a4db94011d3	44	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi	18:6a4db94011d3	45	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi	18:6a4db94011d3	46	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi	18:6a4db94011d3	47	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi	18:6a4db94011d3	48	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi	18:6a4db94011d3	49	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi	18:6a4db94011d3	50	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi	18:6a4db94011d3	51	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi	18:6a4db94011d3	52	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi	18:6a4db94011d3	53	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	54	*
sahilmgandhi	18:6a4db94011d3	55	******************************************************************************
sahilmgandhi	18:6a4db94011d3	56	*/
sahilmgandhi	18:6a4db94011d3	57
sahilmgandhi	18:6a4db94011d3	58	/* Includes ------------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	59	#include "stm32f2xx_hal.h"
sahilmgandhi	18:6a4db94011d3	60
sahilmgandhi	18:6a4db94011d3	61	/** @addtogroup STM32F2xx_LL_USB_DRIVER
sahilmgandhi	18:6a4db94011d3	62	* @{
sahilmgandhi	18:6a4db94011d3	63	*/
sahilmgandhi	18:6a4db94011d3	64
sahilmgandhi	18:6a4db94011d3	65	#if defined (HAL_PCD_MODULE_ENABLED) \|\| defined (HAL_HCD_MODULE_ENABLED)
sahilmgandhi	18:6a4db94011d3	66
sahilmgandhi	18:6a4db94011d3	67	/* Private typedef -----------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	68	/* Private define ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	69	/* Private macro -------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	70	/* Private variables ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	71	/* Private function prototypes -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	72	/* Private functions ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	73	static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
sahilmgandhi	18:6a4db94011d3	74
sahilmgandhi	18:6a4db94011d3	75	/* Exported functions --------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	76
sahilmgandhi	18:6a4db94011d3	77	/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
sahilmgandhi	18:6a4db94011d3	78	* @{
sahilmgandhi	18:6a4db94011d3	79	*/
sahilmgandhi	18:6a4db94011d3	80
sahilmgandhi	18:6a4db94011d3	81	/** @defgroup LL_USB_Group1 Initialization/de-initialization functions
sahilmgandhi	18:6a4db94011d3	82	* @brief Initialization and Configuration functions
sahilmgandhi	18:6a4db94011d3	83	*
sahilmgandhi	18:6a4db94011d3	84	@verbatim
sahilmgandhi	18:6a4db94011d3	85	===============================================================================
sahilmgandhi	18:6a4db94011d3	86	##### Initialization/de-initialization functions #####
sahilmgandhi	18:6a4db94011d3	87	===============================================================================
sahilmgandhi	18:6a4db94011d3	88	[..] This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	89
sahilmgandhi	18:6a4db94011d3	90	@endverbatim
sahilmgandhi	18:6a4db94011d3	91	* @{
sahilmgandhi	18:6a4db94011d3	92	*/
sahilmgandhi	18:6a4db94011d3	93
sahilmgandhi	18:6a4db94011d3	94	/**
sahilmgandhi	18:6a4db94011d3	95	* @brief Initializes the USB Core
sahilmgandhi	18:6a4db94011d3	96	* @param USBx: USB Instance
sahilmgandhi	18:6a4db94011d3	97	* @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	98	* the configuration information for the specified USBx peripheral.
sahilmgandhi	18:6a4db94011d3	99	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	100	*/
sahilmgandhi	18:6a4db94011d3	101	HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
sahilmgandhi	18:6a4db94011d3	102	{
sahilmgandhi	18:6a4db94011d3	103	if (cfg.phy_itface == USB_OTG_ULPI_PHY)
sahilmgandhi	18:6a4db94011d3	104	{
sahilmgandhi	18:6a4db94011d3	105
sahilmgandhi	18:6a4db94011d3	106	USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
sahilmgandhi	18:6a4db94011d3	107
sahilmgandhi	18:6a4db94011d3	108	/* Init The ULPI Interface */
sahilmgandhi	18:6a4db94011d3	109	USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS \| USB_OTG_GUSBCFG_ULPIFSLS \| USB_OTG_GUSBCFG_PHYSEL);
sahilmgandhi	18:6a4db94011d3	110
sahilmgandhi	18:6a4db94011d3	111	/* Select vbus source */
sahilmgandhi	18:6a4db94011d3	112	USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD \| USB_OTG_GUSBCFG_ULPIEVBUSI);
sahilmgandhi	18:6a4db94011d3	113	if(cfg.use_external_vbus == 1)
sahilmgandhi	18:6a4db94011d3	114	{
sahilmgandhi	18:6a4db94011d3	115	USBx->GUSBCFG \|= USB_OTG_GUSBCFG_ULPIEVBUSD;
sahilmgandhi	18:6a4db94011d3	116	}
sahilmgandhi	18:6a4db94011d3	117	/* Reset after a PHY select */
sahilmgandhi	18:6a4db94011d3	118	USB_CoreReset(USBx);
sahilmgandhi	18:6a4db94011d3	119	}
sahilmgandhi	18:6a4db94011d3	120	else /* FS interface (embedded Phy) */
sahilmgandhi	18:6a4db94011d3	121	{
sahilmgandhi	18:6a4db94011d3	122	/* Select FS Embedded PHY */
sahilmgandhi	18:6a4db94011d3	123	USBx->GUSBCFG \|= USB_OTG_GUSBCFG_PHYSEL;
sahilmgandhi	18:6a4db94011d3	124
sahilmgandhi	18:6a4db94011d3	125	/* Reset after a PHY select and set Host mode */
sahilmgandhi	18:6a4db94011d3	126	USB_CoreReset(USBx);
sahilmgandhi	18:6a4db94011d3	127
sahilmgandhi	18:6a4db94011d3	128	/* Deactivate the power down*/
sahilmgandhi	18:6a4db94011d3	129	USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
sahilmgandhi	18:6a4db94011d3	130	}
sahilmgandhi	18:6a4db94011d3	131
sahilmgandhi	18:6a4db94011d3	132	if(cfg.dma_enable == ENABLE)
sahilmgandhi	18:6a4db94011d3	133	{
sahilmgandhi	18:6a4db94011d3	134	USBx->GAHBCFG \|= (USB_OTG_GAHBCFG_HBSTLEN_1 \| USB_OTG_GAHBCFG_HBSTLEN_2);
sahilmgandhi	18:6a4db94011d3	135	USBx->GAHBCFG \|= USB_OTG_GAHBCFG_DMAEN;
sahilmgandhi	18:6a4db94011d3	136	}
sahilmgandhi	18:6a4db94011d3	137
sahilmgandhi	18:6a4db94011d3	138	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	139	}
sahilmgandhi	18:6a4db94011d3	140
sahilmgandhi	18:6a4db94011d3	141	/**
sahilmgandhi	18:6a4db94011d3	142	* @brief USB_EnableGlobalInt
sahilmgandhi	18:6a4db94011d3	143	* Enables the controller's Global Int in the AHB Config reg
sahilmgandhi	18:6a4db94011d3	144	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	145	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	146	*/
sahilmgandhi	18:6a4db94011d3	147	HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	148	{
sahilmgandhi	18:6a4db94011d3	149	USBx->GAHBCFG \|= USB_OTG_GAHBCFG_GINT;
sahilmgandhi	18:6a4db94011d3	150	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	151	}
sahilmgandhi	18:6a4db94011d3	152
sahilmgandhi	18:6a4db94011d3	153
sahilmgandhi	18:6a4db94011d3	154	/**
sahilmgandhi	18:6a4db94011d3	155	* @brief USB_DisableGlobalInt
sahilmgandhi	18:6a4db94011d3	156	* Disable the controller's Global Int in the AHB Config reg
sahilmgandhi	18:6a4db94011d3	157	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	158	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	159	*/
sahilmgandhi	18:6a4db94011d3	160	HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	161	{
sahilmgandhi	18:6a4db94011d3	162	USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
sahilmgandhi	18:6a4db94011d3	163	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	164	}
sahilmgandhi	18:6a4db94011d3	165
sahilmgandhi	18:6a4db94011d3	166	/**
sahilmgandhi	18:6a4db94011d3	167	* @brief USB_SetCurrentMode : Set functional mode
sahilmgandhi	18:6a4db94011d3	168	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	169	* @param mode : current core mode
sahilmgandhi	18:6a4db94011d3	170	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	171	* @arg USB_OTG_DEVICE_MODE: Peripheral mode
sahilmgandhi	18:6a4db94011d3	172	* @arg USB_OTG_HOST_MODE: Host mode
sahilmgandhi	18:6a4db94011d3	173	* @arg USB_OTG_DRD_MODE: Dual Role Device mode
sahilmgandhi	18:6a4db94011d3	174	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	175	*/
sahilmgandhi	18:6a4db94011d3	176	HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
sahilmgandhi	18:6a4db94011d3	177	{
sahilmgandhi	18:6a4db94011d3	178	USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD \| USB_OTG_GUSBCFG_FDMOD);
sahilmgandhi	18:6a4db94011d3	179
sahilmgandhi	18:6a4db94011d3	180	if ( mode == USB_OTG_HOST_MODE)
sahilmgandhi	18:6a4db94011d3	181	{
sahilmgandhi	18:6a4db94011d3	182	USBx->GUSBCFG \|= USB_OTG_GUSBCFG_FHMOD;
sahilmgandhi	18:6a4db94011d3	183	}
sahilmgandhi	18:6a4db94011d3	184	else if ( mode == USB_OTG_DEVICE_MODE)
sahilmgandhi	18:6a4db94011d3	185	{
sahilmgandhi	18:6a4db94011d3	186	USBx->GUSBCFG \|= USB_OTG_GUSBCFG_FDMOD;
sahilmgandhi	18:6a4db94011d3	187	}
sahilmgandhi	18:6a4db94011d3	188	HAL_Delay(50);
sahilmgandhi	18:6a4db94011d3	189
sahilmgandhi	18:6a4db94011d3	190	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	191	}
sahilmgandhi	18:6a4db94011d3	192
sahilmgandhi	18:6a4db94011d3	193	/**
sahilmgandhi	18:6a4db94011d3	194	* @brief USB_DevInit : Initializes the USB_OTG controller registers
sahilmgandhi	18:6a4db94011d3	195	* for device mode
sahilmgandhi	18:6a4db94011d3	196	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	197	* @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	198	* the configuration information for the specified USBx peripheral.
sahilmgandhi	18:6a4db94011d3	199	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	200	*/
sahilmgandhi	18:6a4db94011d3	201	HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
sahilmgandhi	18:6a4db94011d3	202	{
sahilmgandhi	18:6a4db94011d3	203	uint32_t i = 0;
sahilmgandhi	18:6a4db94011d3	204
sahilmgandhi	18:6a4db94011d3	205	/Activate VBUS Sensing B /
sahilmgandhi	18:6a4db94011d3	206	USBx->GCCFG \|= USB_OTG_GCCFG_VBUSBSEN;
sahilmgandhi	18:6a4db94011d3	207
sahilmgandhi	18:6a4db94011d3	208	if (cfg.vbus_sensing_enable == 0)
sahilmgandhi	18:6a4db94011d3	209	{
sahilmgandhi	18:6a4db94011d3	210	USBx->GCCFG \|= USB_OTG_GCCFG_NOVBUSSENS;
sahilmgandhi	18:6a4db94011d3	211	}
sahilmgandhi	18:6a4db94011d3	212
sahilmgandhi	18:6a4db94011d3	213	/* Restart the Phy Clock */
sahilmgandhi	18:6a4db94011d3	214	USBx_PCGCCTL = 0;
sahilmgandhi	18:6a4db94011d3	215
sahilmgandhi	18:6a4db94011d3	216	/* Device mode configuration */
sahilmgandhi	18:6a4db94011d3	217	USBx_DEVICE->DCFG \|= DCFG_FRAME_INTERVAL_80;
sahilmgandhi	18:6a4db94011d3	218
sahilmgandhi	18:6a4db94011d3	219	if(cfg.phy_itface == USB_OTG_ULPI_PHY)
sahilmgandhi	18:6a4db94011d3	220	{
sahilmgandhi	18:6a4db94011d3	221	if(cfg.speed == USB_OTG_SPEED_HIGH)
sahilmgandhi	18:6a4db94011d3	222	{
sahilmgandhi	18:6a4db94011d3	223	/* Set High speed phy */
sahilmgandhi	18:6a4db94011d3	224	USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
sahilmgandhi	18:6a4db94011d3	225	}
sahilmgandhi	18:6a4db94011d3	226	else
sahilmgandhi	18:6a4db94011d3	227	{
sahilmgandhi	18:6a4db94011d3	228	/* set High speed phy in Full speed mode */
sahilmgandhi	18:6a4db94011d3	229	USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
sahilmgandhi	18:6a4db94011d3	230	}
sahilmgandhi	18:6a4db94011d3	231	}
sahilmgandhi	18:6a4db94011d3	232	else
sahilmgandhi	18:6a4db94011d3	233	{
sahilmgandhi	18:6a4db94011d3	234	/* Set Full speed phy */
sahilmgandhi	18:6a4db94011d3	235	USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
sahilmgandhi	18:6a4db94011d3	236	}
sahilmgandhi	18:6a4db94011d3	237
sahilmgandhi	18:6a4db94011d3	238	/* Flush the FIFOs */
sahilmgandhi	18:6a4db94011d3	239	USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
sahilmgandhi	18:6a4db94011d3	240	USB_FlushRxFifo(USBx);
sahilmgandhi	18:6a4db94011d3	241
sahilmgandhi	18:6a4db94011d3	242	/* Clear all pending Device Interrupts */
sahilmgandhi	18:6a4db94011d3	243	USBx_DEVICE->DIEPMSK = 0;
sahilmgandhi	18:6a4db94011d3	244	USBx_DEVICE->DOEPMSK = 0;
sahilmgandhi	18:6a4db94011d3	245	USBx_DEVICE->DAINT = 0xFFFFFFFF;
sahilmgandhi	18:6a4db94011d3	246	USBx_DEVICE->DAINTMSK = 0;
sahilmgandhi	18:6a4db94011d3	247
sahilmgandhi	18:6a4db94011d3	248	for (i = 0; i < cfg.dev_endpoints; i++)
sahilmgandhi	18:6a4db94011d3	249	{
sahilmgandhi	18:6a4db94011d3	250	if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
sahilmgandhi	18:6a4db94011d3	251	{
sahilmgandhi	18:6a4db94011d3	252	USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS \| USB_OTG_DIEPCTL_SNAK);
sahilmgandhi	18:6a4db94011d3	253	}
sahilmgandhi	18:6a4db94011d3	254	else
sahilmgandhi	18:6a4db94011d3	255	{
sahilmgandhi	18:6a4db94011d3	256	USBx_INEP(i)->DIEPCTL = 0;
sahilmgandhi	18:6a4db94011d3	257	}
sahilmgandhi	18:6a4db94011d3	258
sahilmgandhi	18:6a4db94011d3	259	USBx_INEP(i)->DIEPTSIZ = 0;
sahilmgandhi	18:6a4db94011d3	260	USBx_INEP(i)->DIEPINT = 0xFF;
sahilmgandhi	18:6a4db94011d3	261	}
sahilmgandhi	18:6a4db94011d3	262
sahilmgandhi	18:6a4db94011d3	263	for (i = 0; i < cfg.dev_endpoints; i++)
sahilmgandhi	18:6a4db94011d3	264	{
sahilmgandhi	18:6a4db94011d3	265	if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
sahilmgandhi	18:6a4db94011d3	266	{
sahilmgandhi	18:6a4db94011d3	267	USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS \| USB_OTG_DOEPCTL_SNAK);
sahilmgandhi	18:6a4db94011d3	268	}
sahilmgandhi	18:6a4db94011d3	269	else
sahilmgandhi	18:6a4db94011d3	270	{
sahilmgandhi	18:6a4db94011d3	271	USBx_OUTEP(i)->DOEPCTL = 0;
sahilmgandhi	18:6a4db94011d3	272	}
sahilmgandhi	18:6a4db94011d3	273
sahilmgandhi	18:6a4db94011d3	274	USBx_OUTEP(i)->DOEPTSIZ = 0;
sahilmgandhi	18:6a4db94011d3	275	USBx_OUTEP(i)->DOEPINT = 0xFF;
sahilmgandhi	18:6a4db94011d3	276	}
sahilmgandhi	18:6a4db94011d3	277
sahilmgandhi	18:6a4db94011d3	278	USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
sahilmgandhi	18:6a4db94011d3	279
sahilmgandhi	18:6a4db94011d3	280	if (cfg.dma_enable == 1)
sahilmgandhi	18:6a4db94011d3	281	{
sahilmgandhi	18:6a4db94011d3	282	/Set threshold parameters /
sahilmgandhi	18:6a4db94011d3	283	USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 \| USB_OTG_DTHRCTL_RXTHRLEN_6);
sahilmgandhi	18:6a4db94011d3	284	USBx_DEVICE->DTHRCTL \|= (USB_OTG_DTHRCTL_RXTHREN \| USB_OTG_DTHRCTL_ISOTHREN \| USB_OTG_DTHRCTL_NONISOTHREN);
sahilmgandhi	18:6a4db94011d3	285
sahilmgandhi	18:6a4db94011d3	286	i= USBx_DEVICE->DTHRCTL;
sahilmgandhi	18:6a4db94011d3	287	}
sahilmgandhi	18:6a4db94011d3	288
sahilmgandhi	18:6a4db94011d3	289	/* Disable all interrupts. */
sahilmgandhi	18:6a4db94011d3	290	USBx->GINTMSK = 0;
sahilmgandhi	18:6a4db94011d3	291
sahilmgandhi	18:6a4db94011d3	292	/* Clear any pending interrupts */
sahilmgandhi	18:6a4db94011d3	293	USBx->GINTSTS = 0xBFFFFFFF;
sahilmgandhi	18:6a4db94011d3	294
sahilmgandhi	18:6a4db94011d3	295	/* Enable the common interrupts */
sahilmgandhi	18:6a4db94011d3	296	if (cfg.dma_enable == DISABLE)
sahilmgandhi	18:6a4db94011d3	297	{
sahilmgandhi	18:6a4db94011d3	298	USBx->GINTMSK \|= USB_OTG_GINTMSK_RXFLVLM;
sahilmgandhi	18:6a4db94011d3	299	}
sahilmgandhi	18:6a4db94011d3	300
sahilmgandhi	18:6a4db94011d3	301	/* Enable interrupts matching to the Device mode ONLY */
sahilmgandhi	18:6a4db94011d3	302	USBx->GINTMSK \|= (USB_OTG_GINTMSK_USBSUSPM \| USB_OTG_GINTMSK_USBRST \|\
sahilmgandhi	18:6a4db94011d3	303	USB_OTG_GINTMSK_ENUMDNEM \| USB_OTG_GINTMSK_IEPINT \|\
sahilmgandhi	18:6a4db94011d3	304	USB_OTG_GINTMSK_OEPINT \| USB_OTG_GINTMSK_IISOIXFRM\|\
sahilmgandhi	18:6a4db94011d3	305	USB_OTG_GINTMSK_PXFRM_IISOOXFRM \| USB_OTG_GINTMSK_WUIM);
sahilmgandhi	18:6a4db94011d3	306
sahilmgandhi	18:6a4db94011d3	307	if(cfg.Sof_enable)
sahilmgandhi	18:6a4db94011d3	308	{
sahilmgandhi	18:6a4db94011d3	309	USBx->GINTMSK \|= USB_OTG_GINTMSK_SOFM;
sahilmgandhi	18:6a4db94011d3	310	}
sahilmgandhi	18:6a4db94011d3	311
sahilmgandhi	18:6a4db94011d3	312	if (cfg.vbus_sensing_enable == ENABLE)
sahilmgandhi	18:6a4db94011d3	313	{
sahilmgandhi	18:6a4db94011d3	314	USBx->GINTMSK \|= (USB_OTG_GINTMSK_SRQIM \| USB_OTG_GINTMSK_OTGINT);
sahilmgandhi	18:6a4db94011d3	315	}
sahilmgandhi	18:6a4db94011d3	316
sahilmgandhi	18:6a4db94011d3	317	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	318	}
sahilmgandhi	18:6a4db94011d3	319
sahilmgandhi	18:6a4db94011d3	320
sahilmgandhi	18:6a4db94011d3	321	/**
sahilmgandhi	18:6a4db94011d3	322	* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
sahilmgandhi	18:6a4db94011d3	323	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	324	* @param num : FIFO number
sahilmgandhi	18:6a4db94011d3	325	* This parameter can be a value from 1 to 15
sahilmgandhi	18:6a4db94011d3	326	15 means Flush all Tx FIFOs
sahilmgandhi	18:6a4db94011d3	327	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	328	*/
sahilmgandhi	18:6a4db94011d3	329	HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
sahilmgandhi	18:6a4db94011d3	330	{
sahilmgandhi	18:6a4db94011d3	331	uint32_t count = 0;
sahilmgandhi	18:6a4db94011d3	332
sahilmgandhi	18:6a4db94011d3	333	USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH \|(uint32_t)( num << 6));
sahilmgandhi	18:6a4db94011d3	334
sahilmgandhi	18:6a4db94011d3	335	do
sahilmgandhi	18:6a4db94011d3	336	{
sahilmgandhi	18:6a4db94011d3	337	if (++count > 200000)
sahilmgandhi	18:6a4db94011d3	338	{
sahilmgandhi	18:6a4db94011d3	339	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	340	}
sahilmgandhi	18:6a4db94011d3	341	}
sahilmgandhi	18:6a4db94011d3	342	while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
sahilmgandhi	18:6a4db94011d3	343
sahilmgandhi	18:6a4db94011d3	344	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	345	}
sahilmgandhi	18:6a4db94011d3	346
sahilmgandhi	18:6a4db94011d3	347
sahilmgandhi	18:6a4db94011d3	348	/**
sahilmgandhi	18:6a4db94011d3	349	* @brief USB_FlushRxFifo : Flush Rx FIFO
sahilmgandhi	18:6a4db94011d3	350	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	351	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	352	*/
sahilmgandhi	18:6a4db94011d3	353	HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	354	{
sahilmgandhi	18:6a4db94011d3	355	uint32_t count = 0;
sahilmgandhi	18:6a4db94011d3	356
sahilmgandhi	18:6a4db94011d3	357	USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
sahilmgandhi	18:6a4db94011d3	358
sahilmgandhi	18:6a4db94011d3	359	do
sahilmgandhi	18:6a4db94011d3	360	{
sahilmgandhi	18:6a4db94011d3	361	if (++count > 200000)
sahilmgandhi	18:6a4db94011d3	362	{
sahilmgandhi	18:6a4db94011d3	363	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	364	}
sahilmgandhi	18:6a4db94011d3	365	}
sahilmgandhi	18:6a4db94011d3	366	while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
sahilmgandhi	18:6a4db94011d3	367
sahilmgandhi	18:6a4db94011d3	368	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	369	}
sahilmgandhi	18:6a4db94011d3	370
sahilmgandhi	18:6a4db94011d3	371	/**
sahilmgandhi	18:6a4db94011d3	372	* @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
sahilmgandhi	18:6a4db94011d3	373	* depending the PHY type and the enumeration speed of the device.
sahilmgandhi	18:6a4db94011d3	374	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	375	* @param speed : device speed
sahilmgandhi	18:6a4db94011d3	376	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	377	* @arg USB_OTG_SPEED_HIGH: High speed mode
sahilmgandhi	18:6a4db94011d3	378	* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
sahilmgandhi	18:6a4db94011d3	379	* @arg USB_OTG_SPEED_FULL: Full speed mode
sahilmgandhi	18:6a4db94011d3	380	* @arg USB_OTG_SPEED_LOW: Low speed mode
sahilmgandhi	18:6a4db94011d3	381	* @retval Hal status
sahilmgandhi	18:6a4db94011d3	382	*/
sahilmgandhi	18:6a4db94011d3	383	HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
sahilmgandhi	18:6a4db94011d3	384	{
sahilmgandhi	18:6a4db94011d3	385	USBx_DEVICE->DCFG \|= speed;
sahilmgandhi	18:6a4db94011d3	386	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	387	}
sahilmgandhi	18:6a4db94011d3	388
sahilmgandhi	18:6a4db94011d3	389	/**
sahilmgandhi	18:6a4db94011d3	390	* @brief USB_GetDevSpeed :Return the Dev Speed
sahilmgandhi	18:6a4db94011d3	391	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	392	* @retval speed : device speed
sahilmgandhi	18:6a4db94011d3	393	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	394	* @arg USB_OTG_SPEED_HIGH: High speed mode
sahilmgandhi	18:6a4db94011d3	395	* @arg USB_OTG_SPEED_FULL: Full speed mode
sahilmgandhi	18:6a4db94011d3	396	* @arg USB_OTG_SPEED_LOW: Low speed mode
sahilmgandhi	18:6a4db94011d3	397	*/
sahilmgandhi	18:6a4db94011d3	398	uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	399	{
sahilmgandhi	18:6a4db94011d3	400	uint8_t speed = 0;
sahilmgandhi	18:6a4db94011d3	401
sahilmgandhi	18:6a4db94011d3	402	if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
sahilmgandhi	18:6a4db94011d3	403	{
sahilmgandhi	18:6a4db94011d3	404	speed = USB_OTG_SPEED_HIGH;
sahilmgandhi	18:6a4db94011d3	405	}
sahilmgandhi	18:6a4db94011d3	406	else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)\|\|
sahilmgandhi	18:6a4db94011d3	407	((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
sahilmgandhi	18:6a4db94011d3	408	{
sahilmgandhi	18:6a4db94011d3	409	speed = USB_OTG_SPEED_FULL;
sahilmgandhi	18:6a4db94011d3	410	}
sahilmgandhi	18:6a4db94011d3	411	else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
sahilmgandhi	18:6a4db94011d3	412	{
sahilmgandhi	18:6a4db94011d3	413	speed = USB_OTG_SPEED_LOW;
sahilmgandhi	18:6a4db94011d3	414	}
sahilmgandhi	18:6a4db94011d3	415
sahilmgandhi	18:6a4db94011d3	416	return speed;
sahilmgandhi	18:6a4db94011d3	417	}
sahilmgandhi	18:6a4db94011d3	418
sahilmgandhi	18:6a4db94011d3	419	/**
sahilmgandhi	18:6a4db94011d3	420	* @brief Activate and configure an endpoint
sahilmgandhi	18:6a4db94011d3	421	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	422	* @param ep: pointer to endpoint structure
sahilmgandhi	18:6a4db94011d3	423	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	424	*/
sahilmgandhi	18:6a4db94011d3	425	HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef USBx, USB_OTG_EPTypeDef ep)
sahilmgandhi	18:6a4db94011d3	426	{
sahilmgandhi	18:6a4db94011d3	427	if (ep->is_in == 1)
sahilmgandhi	18:6a4db94011d3	428	{
sahilmgandhi	18:6a4db94011d3	429	USBx_DEVICE->DAINTMSK \|= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
sahilmgandhi	18:6a4db94011d3	430
sahilmgandhi	18:6a4db94011d3	431	if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
sahilmgandhi	18:6a4db94011d3	432	{
sahilmgandhi	18:6a4db94011d3	433	USBx_INEP(ep->num)->DIEPCTL \|= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) \| (ep->type << 18 ) \|\
sahilmgandhi	18:6a4db94011d3	434	((ep->num) << 22 ) \| (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) \| (USB_OTG_DIEPCTL_USBAEP));
sahilmgandhi	18:6a4db94011d3	435	}
sahilmgandhi	18:6a4db94011d3	436
sahilmgandhi	18:6a4db94011d3	437	}
sahilmgandhi	18:6a4db94011d3	438	else
sahilmgandhi	18:6a4db94011d3	439	{
sahilmgandhi	18:6a4db94011d3	440	USBx_DEVICE->DAINTMSK \|= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
sahilmgandhi	18:6a4db94011d3	441
sahilmgandhi	18:6a4db94011d3	442	if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
sahilmgandhi	18:6a4db94011d3	443	{
sahilmgandhi	18:6a4db94011d3	444	USBx_OUTEP(ep->num)->DOEPCTL \|= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) \| (ep->type << 18 ) \|\
sahilmgandhi	18:6a4db94011d3	445	(USB_OTG_DIEPCTL_SD0PID_SEVNFRM)\| (USB_OTG_DOEPCTL_USBAEP));
sahilmgandhi	18:6a4db94011d3	446	}
sahilmgandhi	18:6a4db94011d3	447	}
sahilmgandhi	18:6a4db94011d3	448	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	449	}
sahilmgandhi	18:6a4db94011d3	450	/**
sahilmgandhi	18:6a4db94011d3	451	* @brief Activate and configure a dedicated endpoint
sahilmgandhi	18:6a4db94011d3	452	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	453	* @param ep: pointer to endpoint structure
sahilmgandhi	18:6a4db94011d3	454	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	455	*/
sahilmgandhi	18:6a4db94011d3	456	HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef USBx, USB_OTG_EPTypeDef ep)
sahilmgandhi	18:6a4db94011d3	457	{
sahilmgandhi	18:6a4db94011d3	458	static __IO uint32_t debug = 0;
sahilmgandhi	18:6a4db94011d3	459
sahilmgandhi	18:6a4db94011d3	460	/* Read DEPCTLn register */
sahilmgandhi	18:6a4db94011d3	461	if (ep->is_in == 1)
sahilmgandhi	18:6a4db94011d3	462	{
sahilmgandhi	18:6a4db94011d3	463	if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
sahilmgandhi	18:6a4db94011d3	464	{
sahilmgandhi	18:6a4db94011d3	465	USBx_INEP(ep->num)->DIEPCTL \|= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) \| (ep->type << 18 ) \|\
sahilmgandhi	18:6a4db94011d3	466	((ep->num) << 22 ) \| (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) \| (USB_OTG_DIEPCTL_USBAEP));
sahilmgandhi	18:6a4db94011d3	467	}
sahilmgandhi	18:6a4db94011d3	468
sahilmgandhi	18:6a4db94011d3	469
sahilmgandhi	18:6a4db94011d3	470	debug \|= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) \| (ep->type << 18 ) \|\
sahilmgandhi	18:6a4db94011d3	471	((ep->num) << 22 ) \| (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) \| (USB_OTG_DIEPCTL_USBAEP));
sahilmgandhi	18:6a4db94011d3	472
sahilmgandhi	18:6a4db94011d3	473	USBx_DEVICE->DEACHMSK \|= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
sahilmgandhi	18:6a4db94011d3	474	}
sahilmgandhi	18:6a4db94011d3	475	else
sahilmgandhi	18:6a4db94011d3	476	{
sahilmgandhi	18:6a4db94011d3	477	if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
sahilmgandhi	18:6a4db94011d3	478	{
sahilmgandhi	18:6a4db94011d3	479	USBx_OUTEP(ep->num)->DOEPCTL \|= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) \| (ep->type << 18 ) \|\
sahilmgandhi	18:6a4db94011d3	480	((ep->num) << 22 ) \| (USB_OTG_DOEPCTL_USBAEP));
sahilmgandhi	18:6a4db94011d3	481
sahilmgandhi	18:6a4db94011d3	482	debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);
sahilmgandhi	18:6a4db94011d3	483	debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
sahilmgandhi	18:6a4db94011d3	484	debug \|= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) \| (ep->type << 18 ) \|\
sahilmgandhi	18:6a4db94011d3	485	((ep->num) << 22 ) \| (USB_OTG_DOEPCTL_USBAEP));
sahilmgandhi	18:6a4db94011d3	486	}
sahilmgandhi	18:6a4db94011d3	487
sahilmgandhi	18:6a4db94011d3	488	USBx_DEVICE->DEACHMSK \|= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
sahilmgandhi	18:6a4db94011d3	489	}
sahilmgandhi	18:6a4db94011d3	490
sahilmgandhi	18:6a4db94011d3	491	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	492	}
sahilmgandhi	18:6a4db94011d3	493	/**
sahilmgandhi	18:6a4db94011d3	494	* @brief De-activate and de-initialize an endpoint
sahilmgandhi	18:6a4db94011d3	495	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	496	* @param ep: pointer to endpoint structure
sahilmgandhi	18:6a4db94011d3	497	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	498	*/
sahilmgandhi	18:6a4db94011d3	499	HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef USBx, USB_OTG_EPTypeDef ep)
sahilmgandhi	18:6a4db94011d3	500	{
sahilmgandhi	18:6a4db94011d3	501	/* Read DEPCTLn register */
sahilmgandhi	18:6a4db94011d3	502	if (ep->is_in == 1)
sahilmgandhi	18:6a4db94011d3	503	{
sahilmgandhi	18:6a4db94011d3	504	USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
sahilmgandhi	18:6a4db94011d3	505	USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
sahilmgandhi	18:6a4db94011d3	506	USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
sahilmgandhi	18:6a4db94011d3	507	}
sahilmgandhi	18:6a4db94011d3	508	else
sahilmgandhi	18:6a4db94011d3	509	{
sahilmgandhi	18:6a4db94011d3	510	USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
sahilmgandhi	18:6a4db94011d3	511	USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
sahilmgandhi	18:6a4db94011d3	512	USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
sahilmgandhi	18:6a4db94011d3	513	}
sahilmgandhi	18:6a4db94011d3	514	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	515	}
sahilmgandhi	18:6a4db94011d3	516
sahilmgandhi	18:6a4db94011d3	517	/**
sahilmgandhi	18:6a4db94011d3	518	* @brief De-activate and de-initialize a dedicated endpoint
sahilmgandhi	18:6a4db94011d3	519	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	520	* @param ep: pointer to endpoint structure
sahilmgandhi	18:6a4db94011d3	521	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	522	*/
sahilmgandhi	18:6a4db94011d3	523	HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef USBx, USB_OTG_EPTypeDef ep)
sahilmgandhi	18:6a4db94011d3	524	{
sahilmgandhi	18:6a4db94011d3	525	/* Read DEPCTLn register */
sahilmgandhi	18:6a4db94011d3	526	if (ep->is_in == 1)
sahilmgandhi	18:6a4db94011d3	527	{
sahilmgandhi	18:6a4db94011d3	528	USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
sahilmgandhi	18:6a4db94011d3	529	USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
sahilmgandhi	18:6a4db94011d3	530	}
sahilmgandhi	18:6a4db94011d3	531	else
sahilmgandhi	18:6a4db94011d3	532	{
sahilmgandhi	18:6a4db94011d3	533	USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
sahilmgandhi	18:6a4db94011d3	534	USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
sahilmgandhi	18:6a4db94011d3	535	}
sahilmgandhi	18:6a4db94011d3	536	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	537	}
sahilmgandhi	18:6a4db94011d3	538
sahilmgandhi	18:6a4db94011d3	539	/**
sahilmgandhi	18:6a4db94011d3	540	* @brief USB_EPStartXfer : setup and starts a transfer over an EP
sahilmgandhi	18:6a4db94011d3	541	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	542	* @param ep: pointer to endpoint structure
sahilmgandhi	18:6a4db94011d3	543	* @param dma: USB dma enabled or disabled
sahilmgandhi	18:6a4db94011d3	544	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	545	* 0 : DMA feature not used
sahilmgandhi	18:6a4db94011d3	546	* 1 : DMA feature used
sahilmgandhi	18:6a4db94011d3	547	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	548	*/
sahilmgandhi	18:6a4db94011d3	549	HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef USBx , USB_OTG_EPTypeDef ep, uint8_t dma)
sahilmgandhi	18:6a4db94011d3	550	{
sahilmgandhi	18:6a4db94011d3	551	uint16_t pktcnt = 0;
sahilmgandhi	18:6a4db94011d3	552
sahilmgandhi	18:6a4db94011d3	553	/* IN endpoint */
sahilmgandhi	18:6a4db94011d3	554	if (ep->is_in == 1)
sahilmgandhi	18:6a4db94011d3	555	{
sahilmgandhi	18:6a4db94011d3	556	/* Zero Length Packet? */
sahilmgandhi	18:6a4db94011d3	557	if (ep->xfer_len == 0)
sahilmgandhi	18:6a4db94011d3	558	{
sahilmgandhi	18:6a4db94011d3	559	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
sahilmgandhi	18:6a4db94011d3	560	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
sahilmgandhi	18:6a4db94011d3	561	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
sahilmgandhi	18:6a4db94011d3	562	}
sahilmgandhi	18:6a4db94011d3	563	else
sahilmgandhi	18:6a4db94011d3	564	{
sahilmgandhi	18:6a4db94011d3	565	/* Program the transfer size and packet count
sahilmgandhi	18:6a4db94011d3	566	* as follows: xfersize = N * maxpacket +
sahilmgandhi	18:6a4db94011d3	567	* short_packet pktcnt = N + (short_packet
sahilmgandhi	18:6a4db94011d3	568	* exist ? 1 : 0)
sahilmgandhi	18:6a4db94011d3	569	*/
sahilmgandhi	18:6a4db94011d3	570	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
sahilmgandhi	18:6a4db94011d3	571	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
sahilmgandhi	18:6a4db94011d3	572	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;
sahilmgandhi	18:6a4db94011d3	573	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
sahilmgandhi	18:6a4db94011d3	574
sahilmgandhi	18:6a4db94011d3	575	if (ep->type == EP_TYPE_ISOC)
sahilmgandhi	18:6a4db94011d3	576	{
sahilmgandhi	18:6a4db94011d3	577	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
sahilmgandhi	18:6a4db94011d3	578	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29));
sahilmgandhi	18:6a4db94011d3	579	}
sahilmgandhi	18:6a4db94011d3	580	}
sahilmgandhi	18:6a4db94011d3	581
sahilmgandhi	18:6a4db94011d3	582	if (dma == 1)
sahilmgandhi	18:6a4db94011d3	583	{
sahilmgandhi	18:6a4db94011d3	584	USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
sahilmgandhi	18:6a4db94011d3	585	}
sahilmgandhi	18:6a4db94011d3	586	else
sahilmgandhi	18:6a4db94011d3	587	{
sahilmgandhi	18:6a4db94011d3	588	if (ep->type != EP_TYPE_ISOC)
sahilmgandhi	18:6a4db94011d3	589	{
sahilmgandhi	18:6a4db94011d3	590	/* Enable the Tx FIFO Empty Interrupt for this EP */
sahilmgandhi	18:6a4db94011d3	591	if (ep->xfer_len > 0)
sahilmgandhi	18:6a4db94011d3	592	{
sahilmgandhi	18:6a4db94011d3	593	atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << ep->num);
sahilmgandhi	18:6a4db94011d3	594	}
sahilmgandhi	18:6a4db94011d3	595	}
sahilmgandhi	18:6a4db94011d3	596	}
sahilmgandhi	18:6a4db94011d3	597
sahilmgandhi	18:6a4db94011d3	598	if (ep->type == EP_TYPE_ISOC)
sahilmgandhi	18:6a4db94011d3	599	{
sahilmgandhi	18:6a4db94011d3	600	if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
sahilmgandhi	18:6a4db94011d3	601	{
sahilmgandhi	18:6a4db94011d3	602	USBx_INEP(ep->num)->DIEPCTL \|= USB_OTG_DIEPCTL_SODDFRM;
sahilmgandhi	18:6a4db94011d3	603	}
sahilmgandhi	18:6a4db94011d3	604	else
sahilmgandhi	18:6a4db94011d3	605	{
sahilmgandhi	18:6a4db94011d3	606	USBx_INEP(ep->num)->DIEPCTL \|= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
sahilmgandhi	18:6a4db94011d3	607	}
sahilmgandhi	18:6a4db94011d3	608	}
sahilmgandhi	18:6a4db94011d3	609
sahilmgandhi	18:6a4db94011d3	610	/* EP enable, IN data in FIFO */
sahilmgandhi	18:6a4db94011d3	611	USBx_INEP(ep->num)->DIEPCTL \|= (USB_OTG_DIEPCTL_CNAK \| USB_OTG_DIEPCTL_EPENA);
sahilmgandhi	18:6a4db94011d3	612
sahilmgandhi	18:6a4db94011d3	613	if (ep->type == EP_TYPE_ISOC)
sahilmgandhi	18:6a4db94011d3	614	{
sahilmgandhi	18:6a4db94011d3	615	USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);
sahilmgandhi	18:6a4db94011d3	616	}
sahilmgandhi	18:6a4db94011d3	617	}
sahilmgandhi	18:6a4db94011d3	618	else /* OUT endpoint */
sahilmgandhi	18:6a4db94011d3	619	{
sahilmgandhi	18:6a4db94011d3	620	/* Program the transfer size and packet count as follows:
sahilmgandhi	18:6a4db94011d3	621	* pktcnt = N
sahilmgandhi	18:6a4db94011d3	622	* xfersize = N * maxpacket
sahilmgandhi	18:6a4db94011d3	623	*/
sahilmgandhi	18:6a4db94011d3	624	USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
sahilmgandhi	18:6a4db94011d3	625	USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
sahilmgandhi	18:6a4db94011d3	626
sahilmgandhi	18:6a4db94011d3	627	if (ep->xfer_len == 0)
sahilmgandhi	18:6a4db94011d3	628	{
sahilmgandhi	18:6a4db94011d3	629	USBx_OUTEP(ep->num)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
sahilmgandhi	18:6a4db94011d3	630	USBx_OUTEP(ep->num)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
sahilmgandhi	18:6a4db94011d3	631	}
sahilmgandhi	18:6a4db94011d3	632	else
sahilmgandhi	18:6a4db94011d3	633	{
sahilmgandhi	18:6a4db94011d3	634	pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket;
sahilmgandhi	18:6a4db94011d3	635	USBx_OUTEP(ep->num)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); ;
sahilmgandhi	18:6a4db94011d3	636	USBx_OUTEP(ep->num)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
sahilmgandhi	18:6a4db94011d3	637	}
sahilmgandhi	18:6a4db94011d3	638
sahilmgandhi	18:6a4db94011d3	639	if (dma == 1)
sahilmgandhi	18:6a4db94011d3	640	{
sahilmgandhi	18:6a4db94011d3	641	USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
sahilmgandhi	18:6a4db94011d3	642	}
sahilmgandhi	18:6a4db94011d3	643
sahilmgandhi	18:6a4db94011d3	644	if (ep->type == EP_TYPE_ISOC)
sahilmgandhi	18:6a4db94011d3	645	{
sahilmgandhi	18:6a4db94011d3	646	if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
sahilmgandhi	18:6a4db94011d3	647	{
sahilmgandhi	18:6a4db94011d3	648	USBx_OUTEP(ep->num)->DOEPCTL \|= USB_OTG_DOEPCTL_SODDFRM;
sahilmgandhi	18:6a4db94011d3	649	}
sahilmgandhi	18:6a4db94011d3	650	else
sahilmgandhi	18:6a4db94011d3	651	{
sahilmgandhi	18:6a4db94011d3	652	USBx_OUTEP(ep->num)->DOEPCTL \|= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
sahilmgandhi	18:6a4db94011d3	653	}
sahilmgandhi	18:6a4db94011d3	654	}
sahilmgandhi	18:6a4db94011d3	655	/* EP enable */
sahilmgandhi	18:6a4db94011d3	656	USBx_OUTEP(ep->num)->DOEPCTL \|= (USB_OTG_DOEPCTL_CNAK \| USB_OTG_DOEPCTL_EPENA);
sahilmgandhi	18:6a4db94011d3	657	}
sahilmgandhi	18:6a4db94011d3	658	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	659	}
sahilmgandhi	18:6a4db94011d3	660
sahilmgandhi	18:6a4db94011d3	661	/**
sahilmgandhi	18:6a4db94011d3	662	* @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
sahilmgandhi	18:6a4db94011d3	663	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	664	* @param ep: pointer to endpoint structure
sahilmgandhi	18:6a4db94011d3	665	* @param dma: USB dma enabled or disabled
sahilmgandhi	18:6a4db94011d3	666	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	667	* 0 : DMA feature not used
sahilmgandhi	18:6a4db94011d3	668	* 1 : DMA feature used
sahilmgandhi	18:6a4db94011d3	669	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	670	*/
sahilmgandhi	18:6a4db94011d3	671	HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef USBx , USB_OTG_EPTypeDef ep, uint8_t dma)
sahilmgandhi	18:6a4db94011d3	672	{
sahilmgandhi	18:6a4db94011d3	673	/* IN endpoint */
sahilmgandhi	18:6a4db94011d3	674	if (ep->is_in == 1)
sahilmgandhi	18:6a4db94011d3	675	{
sahilmgandhi	18:6a4db94011d3	676	/* Zero Length Packet? */
sahilmgandhi	18:6a4db94011d3	677	if (ep->xfer_len == 0)
sahilmgandhi	18:6a4db94011d3	678	{
sahilmgandhi	18:6a4db94011d3	679	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
sahilmgandhi	18:6a4db94011d3	680	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
sahilmgandhi	18:6a4db94011d3	681	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
sahilmgandhi	18:6a4db94011d3	682	}
sahilmgandhi	18:6a4db94011d3	683	else
sahilmgandhi	18:6a4db94011d3	684	{
sahilmgandhi	18:6a4db94011d3	685	/* Program the transfer size and packet count
sahilmgandhi	18:6a4db94011d3	686	* as follows: xfersize = N * maxpacket +
sahilmgandhi	18:6a4db94011d3	687	* short_packet pktcnt = N + (short_packet
sahilmgandhi	18:6a4db94011d3	688	* exist ? 1 : 0)
sahilmgandhi	18:6a4db94011d3	689	*/
sahilmgandhi	18:6a4db94011d3	690	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
sahilmgandhi	18:6a4db94011d3	691	USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
sahilmgandhi	18:6a4db94011d3	692
sahilmgandhi	18:6a4db94011d3	693	if(ep->xfer_len > ep->maxpacket)
sahilmgandhi	18:6a4db94011d3	694	{
sahilmgandhi	18:6a4db94011d3	695	ep->xfer_len = ep->maxpacket;
sahilmgandhi	18:6a4db94011d3	696	}
sahilmgandhi	18:6a4db94011d3	697	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
sahilmgandhi	18:6a4db94011d3	698	USBx_INEP(ep->num)->DIEPTSIZ \|= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
sahilmgandhi	18:6a4db94011d3	699
sahilmgandhi	18:6a4db94011d3	700	}
sahilmgandhi	18:6a4db94011d3	701
sahilmgandhi	18:6a4db94011d3	702	if (dma == 1)
sahilmgandhi	18:6a4db94011d3	703	{
sahilmgandhi	18:6a4db94011d3	704	USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
sahilmgandhi	18:6a4db94011d3	705	}
sahilmgandhi	18:6a4db94011d3	706	else
sahilmgandhi	18:6a4db94011d3	707	{
sahilmgandhi	18:6a4db94011d3	708	/* Enable the Tx FIFO Empty Interrupt for this EP */
sahilmgandhi	18:6a4db94011d3	709	if (ep->xfer_len > 0)
sahilmgandhi	18:6a4db94011d3	710	{
sahilmgandhi	18:6a4db94011d3	711	atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << (ep->num));
sahilmgandhi	18:6a4db94011d3	712	}
sahilmgandhi	18:6a4db94011d3	713	}
sahilmgandhi	18:6a4db94011d3	714
sahilmgandhi	18:6a4db94011d3	715	/* EP enable, IN data in FIFO */
sahilmgandhi	18:6a4db94011d3	716	USBx_INEP(ep->num)->DIEPCTL \|= (USB_OTG_DIEPCTL_CNAK \| USB_OTG_DIEPCTL_EPENA);
sahilmgandhi	18:6a4db94011d3	717	}
sahilmgandhi	18:6a4db94011d3	718	else /* OUT endpoint */
sahilmgandhi	18:6a4db94011d3	719	{
sahilmgandhi	18:6a4db94011d3	720	/* Program the transfer size and packet count as follows:
sahilmgandhi	18:6a4db94011d3	721	* pktcnt = N
sahilmgandhi	18:6a4db94011d3	722	* xfersize = N * maxpacket
sahilmgandhi	18:6a4db94011d3	723	*/
sahilmgandhi	18:6a4db94011d3	724	USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
sahilmgandhi	18:6a4db94011d3	725	USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
sahilmgandhi	18:6a4db94011d3	726
sahilmgandhi	18:6a4db94011d3	727	if (ep->xfer_len > 0)
sahilmgandhi	18:6a4db94011d3	728	{
sahilmgandhi	18:6a4db94011d3	729	ep->xfer_len = ep->maxpacket;
sahilmgandhi	18:6a4db94011d3	730	}
sahilmgandhi	18:6a4db94011d3	731
sahilmgandhi	18:6a4db94011d3	732	USBx_OUTEP(ep->num)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
sahilmgandhi	18:6a4db94011d3	733	USBx_OUTEP(ep->num)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
sahilmgandhi	18:6a4db94011d3	734
sahilmgandhi	18:6a4db94011d3	735
sahilmgandhi	18:6a4db94011d3	736	if (dma == 1)
sahilmgandhi	18:6a4db94011d3	737	{
sahilmgandhi	18:6a4db94011d3	738	USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
sahilmgandhi	18:6a4db94011d3	739	}
sahilmgandhi	18:6a4db94011d3	740
sahilmgandhi	18:6a4db94011d3	741	/* EP enable */
sahilmgandhi	18:6a4db94011d3	742	USBx_OUTEP(ep->num)->DOEPCTL \|= (USB_OTG_DOEPCTL_CNAK \| USB_OTG_DOEPCTL_EPENA);
sahilmgandhi	18:6a4db94011d3	743	}
sahilmgandhi	18:6a4db94011d3	744	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	745	}
sahilmgandhi	18:6a4db94011d3	746
sahilmgandhi	18:6a4db94011d3	747	/**
sahilmgandhi	18:6a4db94011d3	748	* @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
sahilmgandhi	18:6a4db94011d3	749	* with the EP/channel
sahilmgandhi	18:6a4db94011d3	750	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	751	* @param src : pointer to source buffer
sahilmgandhi	18:6a4db94011d3	752	* @param ch_ep_num : endpoint or host channel number
sahilmgandhi	18:6a4db94011d3	753	* @param len : Number of bytes to write
sahilmgandhi	18:6a4db94011d3	754	* @param dma: USB dma enabled or disabled
sahilmgandhi	18:6a4db94011d3	755	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	756	* 0 : DMA feature not used
sahilmgandhi	18:6a4db94011d3	757	* 1 : DMA feature used
sahilmgandhi	18:6a4db94011d3	758	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	759	*/
sahilmgandhi	18:6a4db94011d3	760	HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef USBx, uint8_t src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
sahilmgandhi	18:6a4db94011d3	761	{
sahilmgandhi	18:6a4db94011d3	762	uint32_t count32b= 0 , i= 0;
sahilmgandhi	18:6a4db94011d3	763
sahilmgandhi	18:6a4db94011d3	764	if (dma == 0)
sahilmgandhi	18:6a4db94011d3	765	{
sahilmgandhi	18:6a4db94011d3	766	count32b = (len + 3) / 4;
sahilmgandhi	18:6a4db94011d3	767	for (i = 0; i < count32b; i++, src += 4)
sahilmgandhi	18:6a4db94011d3	768	{
sahilmgandhi	18:6a4db94011d3	769	USBx_DFIFO(ch_ep_num) = ((__packed uint32_t )src);
sahilmgandhi	18:6a4db94011d3	770	}
sahilmgandhi	18:6a4db94011d3	771	}
sahilmgandhi	18:6a4db94011d3	772	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	773	}
sahilmgandhi	18:6a4db94011d3	774
sahilmgandhi	18:6a4db94011d3	775	/**
sahilmgandhi	18:6a4db94011d3	776	* @brief USB_ReadPacket : read a packet from the Tx FIFO associated
sahilmgandhi	18:6a4db94011d3	777	* with the EP/channel
sahilmgandhi	18:6a4db94011d3	778	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	779	* @param src : source pointer
sahilmgandhi	18:6a4db94011d3	780	* @param ch_ep_num : endpoint or host channel number
sahilmgandhi	18:6a4db94011d3	781	* @param len : Number of bytes to read
sahilmgandhi	18:6a4db94011d3	782	* @param dma: USB dma enabled or disabled
sahilmgandhi	18:6a4db94011d3	783	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	784	* 0 : DMA feature not used
sahilmgandhi	18:6a4db94011d3	785	* 1 : DMA feature used
sahilmgandhi	18:6a4db94011d3	786	* @retval pointer to destination buffer
sahilmgandhi	18:6a4db94011d3	787	*/
sahilmgandhi	18:6a4db94011d3	788	void USB_ReadPacket(USB_OTG_GlobalTypeDef USBx, uint8_t *dest, uint16_t len)
sahilmgandhi	18:6a4db94011d3	789	{
sahilmgandhi	18:6a4db94011d3	790	uint32_t i=0;
sahilmgandhi	18:6a4db94011d3	791	uint32_t count32b = (len + 3) / 4;
sahilmgandhi	18:6a4db94011d3	792
sahilmgandhi	18:6a4db94011d3	793	for ( i = 0; i < count32b; i++, dest += 4 )
sahilmgandhi	18:6a4db94011d3	794	{
sahilmgandhi	18:6a4db94011d3	795	(__packed uint32_t )dest = USBx_DFIFO(0);
sahilmgandhi	18:6a4db94011d3	796
sahilmgandhi	18:6a4db94011d3	797	}
sahilmgandhi	18:6a4db94011d3	798	return ((void *)dest);
sahilmgandhi	18:6a4db94011d3	799	}
sahilmgandhi	18:6a4db94011d3	800
sahilmgandhi	18:6a4db94011d3	801	/**
sahilmgandhi	18:6a4db94011d3	802	* @brief USB_EPSetStall : set a stall condition over an EP
sahilmgandhi	18:6a4db94011d3	803	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	804	* @param ep: pointer to endpoint structure
sahilmgandhi	18:6a4db94011d3	805	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	806	*/
sahilmgandhi	18:6a4db94011d3	807	HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef USBx , USB_OTG_EPTypeDef ep)
sahilmgandhi	18:6a4db94011d3	808	{
sahilmgandhi	18:6a4db94011d3	809	if (ep->is_in == 1)
sahilmgandhi	18:6a4db94011d3	810	{
sahilmgandhi	18:6a4db94011d3	811	if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
sahilmgandhi	18:6a4db94011d3	812	{
sahilmgandhi	18:6a4db94011d3	813	USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
sahilmgandhi	18:6a4db94011d3	814	}
sahilmgandhi	18:6a4db94011d3	815	USBx_INEP(ep->num)->DIEPCTL \|= USB_OTG_DIEPCTL_STALL;
sahilmgandhi	18:6a4db94011d3	816	}
sahilmgandhi	18:6a4db94011d3	817	else
sahilmgandhi	18:6a4db94011d3	818	{
sahilmgandhi	18:6a4db94011d3	819	if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)
sahilmgandhi	18:6a4db94011d3	820	{
sahilmgandhi	18:6a4db94011d3	821	USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
sahilmgandhi	18:6a4db94011d3	822	}
sahilmgandhi	18:6a4db94011d3	823	USBx_OUTEP(ep->num)->DOEPCTL \|= USB_OTG_DOEPCTL_STALL;
sahilmgandhi	18:6a4db94011d3	824	}
sahilmgandhi	18:6a4db94011d3	825	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	826	}
sahilmgandhi	18:6a4db94011d3	827
sahilmgandhi	18:6a4db94011d3	828
sahilmgandhi	18:6a4db94011d3	829	/**
sahilmgandhi	18:6a4db94011d3	830	* @brief USB_EPClearStall : Clear a stall condition over an EP
sahilmgandhi	18:6a4db94011d3	831	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	832	* @param ep: pointer to endpoint structure
sahilmgandhi	18:6a4db94011d3	833	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	834	*/
sahilmgandhi	18:6a4db94011d3	835	HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef USBx, USB_OTG_EPTypeDef ep)
sahilmgandhi	18:6a4db94011d3	836	{
sahilmgandhi	18:6a4db94011d3	837	if (ep->is_in == 1)
sahilmgandhi	18:6a4db94011d3	838	{
sahilmgandhi	18:6a4db94011d3	839	USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
sahilmgandhi	18:6a4db94011d3	840	if (ep->type == EP_TYPE_INTR \|\| ep->type == EP_TYPE_BULK)
sahilmgandhi	18:6a4db94011d3	841	{
sahilmgandhi	18:6a4db94011d3	842	USBx_INEP(ep->num)->DIEPCTL \|= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
sahilmgandhi	18:6a4db94011d3	843	}
sahilmgandhi	18:6a4db94011d3	844	}
sahilmgandhi	18:6a4db94011d3	845	else
sahilmgandhi	18:6a4db94011d3	846	{
sahilmgandhi	18:6a4db94011d3	847	USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
sahilmgandhi	18:6a4db94011d3	848	if (ep->type == EP_TYPE_INTR \|\| ep->type == EP_TYPE_BULK)
sahilmgandhi	18:6a4db94011d3	849	{
sahilmgandhi	18:6a4db94011d3	850	USBx_OUTEP(ep->num)->DOEPCTL \|= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
sahilmgandhi	18:6a4db94011d3	851	}
sahilmgandhi	18:6a4db94011d3	852	}
sahilmgandhi	18:6a4db94011d3	853	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	854	}
sahilmgandhi	18:6a4db94011d3	855
sahilmgandhi	18:6a4db94011d3	856	/**
sahilmgandhi	18:6a4db94011d3	857	* @brief USB_StopDevice : Stop the usb device mode
sahilmgandhi	18:6a4db94011d3	858	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	859	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	860	*/
sahilmgandhi	18:6a4db94011d3	861	HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	862	{
sahilmgandhi	18:6a4db94011d3	863	uint32_t i;
sahilmgandhi	18:6a4db94011d3	864
sahilmgandhi	18:6a4db94011d3	865	/* Clear Pending interrupt */
sahilmgandhi	18:6a4db94011d3	866	for (i = 0; i < 15 ; i++)
sahilmgandhi	18:6a4db94011d3	867	{
sahilmgandhi	18:6a4db94011d3	868	USBx_INEP(i)->DIEPINT = 0xFF;
sahilmgandhi	18:6a4db94011d3	869	USBx_OUTEP(i)->DOEPINT = 0xFF;
sahilmgandhi	18:6a4db94011d3	870	}
sahilmgandhi	18:6a4db94011d3	871	USBx_DEVICE->DAINT = 0xFFFFFFFF;
sahilmgandhi	18:6a4db94011d3	872
sahilmgandhi	18:6a4db94011d3	873	/* Clear interrupt masks */
sahilmgandhi	18:6a4db94011d3	874	USBx_DEVICE->DIEPMSK = 0;
sahilmgandhi	18:6a4db94011d3	875	USBx_DEVICE->DOEPMSK = 0;
sahilmgandhi	18:6a4db94011d3	876	USBx_DEVICE->DAINTMSK = 0;
sahilmgandhi	18:6a4db94011d3	877
sahilmgandhi	18:6a4db94011d3	878	/* Flush the FIFO */
sahilmgandhi	18:6a4db94011d3	879	USB_FlushRxFifo(USBx);
sahilmgandhi	18:6a4db94011d3	880	USB_FlushTxFifo(USBx , 0x10 );
sahilmgandhi	18:6a4db94011d3	881
sahilmgandhi	18:6a4db94011d3	882	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	883	}
sahilmgandhi	18:6a4db94011d3	884
sahilmgandhi	18:6a4db94011d3	885	/**
sahilmgandhi	18:6a4db94011d3	886	* @brief USB_SetDevAddress : Stop the usb device mode
sahilmgandhi	18:6a4db94011d3	887	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	888	* @param address : new device address to be assigned
sahilmgandhi	18:6a4db94011d3	889	* This parameter can be a value from 0 to 255
sahilmgandhi	18:6a4db94011d3	890	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	891	*/
sahilmgandhi	18:6a4db94011d3	892	HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
sahilmgandhi	18:6a4db94011d3	893	{
sahilmgandhi	18:6a4db94011d3	894	USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
sahilmgandhi	18:6a4db94011d3	895	USBx_DEVICE->DCFG \|= (address << 4) & USB_OTG_DCFG_DAD ;
sahilmgandhi	18:6a4db94011d3	896
sahilmgandhi	18:6a4db94011d3	897	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	898	}
sahilmgandhi	18:6a4db94011d3	899
sahilmgandhi	18:6a4db94011d3	900	/**
sahilmgandhi	18:6a4db94011d3	901	* @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
sahilmgandhi	18:6a4db94011d3	902	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	903	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	904	*/
sahilmgandhi	18:6a4db94011d3	905	HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	906	{
sahilmgandhi	18:6a4db94011d3	907	USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
sahilmgandhi	18:6a4db94011d3	908	HAL_Delay(3);
sahilmgandhi	18:6a4db94011d3	909
sahilmgandhi	18:6a4db94011d3	910	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	911	}
sahilmgandhi	18:6a4db94011d3	912
sahilmgandhi	18:6a4db94011d3	913	/**
sahilmgandhi	18:6a4db94011d3	914	* @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
sahilmgandhi	18:6a4db94011d3	915	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	916	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	917	*/
sahilmgandhi	18:6a4db94011d3	918	HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	919	{
sahilmgandhi	18:6a4db94011d3	920	USBx_DEVICE->DCTL \|= USB_OTG_DCTL_SDIS ;
sahilmgandhi	18:6a4db94011d3	921	HAL_Delay(3);
sahilmgandhi	18:6a4db94011d3	922
sahilmgandhi	18:6a4db94011d3	923	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	924	}
sahilmgandhi	18:6a4db94011d3	925
sahilmgandhi	18:6a4db94011d3	926	/**
sahilmgandhi	18:6a4db94011d3	927	* @brief USB_ReadInterrupts: return the global USB interrupt status
sahilmgandhi	18:6a4db94011d3	928	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	929	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	930	*/
sahilmgandhi	18:6a4db94011d3	931	uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	932	{
sahilmgandhi	18:6a4db94011d3	933	uint32_t v = 0;
sahilmgandhi	18:6a4db94011d3	934
sahilmgandhi	18:6a4db94011d3	935	v = USBx->GINTSTS;
sahilmgandhi	18:6a4db94011d3	936	v &= USBx->GINTMSK;
sahilmgandhi	18:6a4db94011d3	937	return v;
sahilmgandhi	18:6a4db94011d3	938	}
sahilmgandhi	18:6a4db94011d3	939
sahilmgandhi	18:6a4db94011d3	940	/**
sahilmgandhi	18:6a4db94011d3	941	* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
sahilmgandhi	18:6a4db94011d3	942	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	943	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	944	*/
sahilmgandhi	18:6a4db94011d3	945	uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	946	{
sahilmgandhi	18:6a4db94011d3	947	uint32_t v;
sahilmgandhi	18:6a4db94011d3	948	v = USBx_DEVICE->DAINT;
sahilmgandhi	18:6a4db94011d3	949	v &= USBx_DEVICE->DAINTMSK;
sahilmgandhi	18:6a4db94011d3	950	return ((v & 0xffff0000) >> 16);
sahilmgandhi	18:6a4db94011d3	951	}
sahilmgandhi	18:6a4db94011d3	952
sahilmgandhi	18:6a4db94011d3	953	/**
sahilmgandhi	18:6a4db94011d3	954	* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
sahilmgandhi	18:6a4db94011d3	955	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	956	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	957	*/
sahilmgandhi	18:6a4db94011d3	958	uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	959	{
sahilmgandhi	18:6a4db94011d3	960	uint32_t v;
sahilmgandhi	18:6a4db94011d3	961	v = USBx_DEVICE->DAINT;
sahilmgandhi	18:6a4db94011d3	962	v &= USBx_DEVICE->DAINTMSK;
sahilmgandhi	18:6a4db94011d3	963	return ((v & 0xFFFF));
sahilmgandhi	18:6a4db94011d3	964	}
sahilmgandhi	18:6a4db94011d3	965
sahilmgandhi	18:6a4db94011d3	966	/**
sahilmgandhi	18:6a4db94011d3	967	* @brief Returns Device OUT EP Interrupt register
sahilmgandhi	18:6a4db94011d3	968	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	969	* @param epnum : endpoint number
sahilmgandhi	18:6a4db94011d3	970	* This parameter can be a value from 0 to 15
sahilmgandhi	18:6a4db94011d3	971	* @retval Device OUT EP Interrupt register
sahilmgandhi	18:6a4db94011d3	972	*/
sahilmgandhi	18:6a4db94011d3	973	uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
sahilmgandhi	18:6a4db94011d3	974	{
sahilmgandhi	18:6a4db94011d3	975	uint32_t v;
sahilmgandhi	18:6a4db94011d3	976	v = USBx_OUTEP(epnum)->DOEPINT;
sahilmgandhi	18:6a4db94011d3	977	v &= USBx_DEVICE->DOEPMSK;
sahilmgandhi	18:6a4db94011d3	978	return v;
sahilmgandhi	18:6a4db94011d3	979	}
sahilmgandhi	18:6a4db94011d3	980
sahilmgandhi	18:6a4db94011d3	981	/**
sahilmgandhi	18:6a4db94011d3	982	* @brief Returns Device IN EP Interrupt register
sahilmgandhi	18:6a4db94011d3	983	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	984	* @param epnum : endpoint number
sahilmgandhi	18:6a4db94011d3	985	* This parameter can be a value from 0 to 15
sahilmgandhi	18:6a4db94011d3	986	* @retval Device IN EP Interrupt register
sahilmgandhi	18:6a4db94011d3	987	*/
sahilmgandhi	18:6a4db94011d3	988	uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
sahilmgandhi	18:6a4db94011d3	989	{
sahilmgandhi	18:6a4db94011d3	990	uint32_t v, msk, emp;
sahilmgandhi	18:6a4db94011d3	991
sahilmgandhi	18:6a4db94011d3	992	msk = USBx_DEVICE->DIEPMSK;
sahilmgandhi	18:6a4db94011d3	993	emp = USBx_DEVICE->DIEPEMPMSK;
sahilmgandhi	18:6a4db94011d3	994	msk \|= ((emp >> epnum) & 0x1) << 7;
sahilmgandhi	18:6a4db94011d3	995	v = USBx_INEP(epnum)->DIEPINT & msk;
sahilmgandhi	18:6a4db94011d3	996	return v;
sahilmgandhi	18:6a4db94011d3	997	}
sahilmgandhi	18:6a4db94011d3	998
sahilmgandhi	18:6a4db94011d3	999	/**
sahilmgandhi	18:6a4db94011d3	1000	* @brief USB_ClearInterrupts: clear a USB interrupt
sahilmgandhi	18:6a4db94011d3	1001	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1002	* @param interrupt : interrupt flag
sahilmgandhi	18:6a4db94011d3	1003	* @retval None
sahilmgandhi	18:6a4db94011d3	1004	*/
sahilmgandhi	18:6a4db94011d3	1005	void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
sahilmgandhi	18:6a4db94011d3	1006	{
sahilmgandhi	18:6a4db94011d3	1007	USBx->GINTSTS \|= interrupt;
sahilmgandhi	18:6a4db94011d3	1008	}
sahilmgandhi	18:6a4db94011d3	1009
sahilmgandhi	18:6a4db94011d3	1010	/**
sahilmgandhi	18:6a4db94011d3	1011	* @brief Returns USB core mode
sahilmgandhi	18:6a4db94011d3	1012	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1013	* @retval return core mode : Host or Device
sahilmgandhi	18:6a4db94011d3	1014	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	1015	* 0 : Host
sahilmgandhi	18:6a4db94011d3	1016	* 1 : Device
sahilmgandhi	18:6a4db94011d3	1017	*/
sahilmgandhi	18:6a4db94011d3	1018	uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	1019	{
sahilmgandhi	18:6a4db94011d3	1020	return ((USBx->GINTSTS ) & 0x1);
sahilmgandhi	18:6a4db94011d3	1021	}
sahilmgandhi	18:6a4db94011d3	1022
sahilmgandhi	18:6a4db94011d3	1023
sahilmgandhi	18:6a4db94011d3	1024	/**
sahilmgandhi	18:6a4db94011d3	1025	* @brief Activate EP0 for Setup transactions
sahilmgandhi	18:6a4db94011d3	1026	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1027	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1028	*/
sahilmgandhi	18:6a4db94011d3	1029	HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	1030	{
sahilmgandhi	18:6a4db94011d3	1031	/* Set the MPS of the IN EP based on the enumeration speed */
sahilmgandhi	18:6a4db94011d3	1032	USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
sahilmgandhi	18:6a4db94011d3	1033
sahilmgandhi	18:6a4db94011d3	1034	if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
sahilmgandhi	18:6a4db94011d3	1035	{
sahilmgandhi	18:6a4db94011d3	1036	USBx_INEP(0)->DIEPCTL \|= 3;
sahilmgandhi	18:6a4db94011d3	1037	}
sahilmgandhi	18:6a4db94011d3	1038	USBx_DEVICE->DCTL \|= USB_OTG_DCTL_CGINAK;
sahilmgandhi	18:6a4db94011d3	1039
sahilmgandhi	18:6a4db94011d3	1040	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1041	}
sahilmgandhi	18:6a4db94011d3	1042
sahilmgandhi	18:6a4db94011d3	1043
sahilmgandhi	18:6a4db94011d3	1044	/**
sahilmgandhi	18:6a4db94011d3	1045	* @brief Prepare the EP0 to start the first control setup
sahilmgandhi	18:6a4db94011d3	1046	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1047	* @param dma: USB dma enabled or disabled
sahilmgandhi	18:6a4db94011d3	1048	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	1049	* 0 : DMA feature not used
sahilmgandhi	18:6a4db94011d3	1050	* 1 : DMA feature used
sahilmgandhi	18:6a4db94011d3	1051	* @param psetup : pointer to setup packet
sahilmgandhi	18:6a4db94011d3	1052	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1053	*/
sahilmgandhi	18:6a4db94011d3	1054	HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef USBx, uint8_t dma, uint8_t psetup)
sahilmgandhi	18:6a4db94011d3	1055	{
sahilmgandhi	18:6a4db94011d3	1056	USBx_OUTEP(0)->DOEPTSIZ = 0;
sahilmgandhi	18:6a4db94011d3	1057	USBx_OUTEP(0)->DOEPTSIZ \|= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
sahilmgandhi	18:6a4db94011d3	1058	USBx_OUTEP(0)->DOEPTSIZ \|= (3 * 8);
sahilmgandhi	18:6a4db94011d3	1059	USBx_OUTEP(0)->DOEPTSIZ \|= USB_OTG_DOEPTSIZ_STUPCNT;
sahilmgandhi	18:6a4db94011d3	1060
sahilmgandhi	18:6a4db94011d3	1061	if (dma == 1)
sahilmgandhi	18:6a4db94011d3	1062	{
sahilmgandhi	18:6a4db94011d3	1063	USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;
sahilmgandhi	18:6a4db94011d3	1064	/* EP enable */
sahilmgandhi	18:6a4db94011d3	1065	USBx_OUTEP(0)->DOEPCTL = 0x80008000;
sahilmgandhi	18:6a4db94011d3	1066	}
sahilmgandhi	18:6a4db94011d3	1067
sahilmgandhi	18:6a4db94011d3	1068	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1069	}
sahilmgandhi	18:6a4db94011d3	1070
sahilmgandhi	18:6a4db94011d3	1071
sahilmgandhi	18:6a4db94011d3	1072	/**
sahilmgandhi	18:6a4db94011d3	1073	* @brief Reset the USB Core (needed after USB clock settings change)
sahilmgandhi	18:6a4db94011d3	1074	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1075	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1076	*/
sahilmgandhi	18:6a4db94011d3	1077	static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	1078	{
sahilmgandhi	18:6a4db94011d3	1079	uint32_t count = 0;
sahilmgandhi	18:6a4db94011d3	1080
sahilmgandhi	18:6a4db94011d3	1081	/* Wait for AHB master IDLE state. */
sahilmgandhi	18:6a4db94011d3	1082	do
sahilmgandhi	18:6a4db94011d3	1083	{
sahilmgandhi	18:6a4db94011d3	1084	if (++count > 200000)
sahilmgandhi	18:6a4db94011d3	1085	{
sahilmgandhi	18:6a4db94011d3	1086	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1087	}
sahilmgandhi	18:6a4db94011d3	1088	}
sahilmgandhi	18:6a4db94011d3	1089	while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
sahilmgandhi	18:6a4db94011d3	1090
sahilmgandhi	18:6a4db94011d3	1091	/* Core Soft Reset */
sahilmgandhi	18:6a4db94011d3	1092	count = 0;
sahilmgandhi	18:6a4db94011d3	1093	USBx->GRSTCTL \|= USB_OTG_GRSTCTL_CSRST;
sahilmgandhi	18:6a4db94011d3	1094
sahilmgandhi	18:6a4db94011d3	1095	do
sahilmgandhi	18:6a4db94011d3	1096	{
sahilmgandhi	18:6a4db94011d3	1097	if (++count > 200000)
sahilmgandhi	18:6a4db94011d3	1098	{
sahilmgandhi	18:6a4db94011d3	1099	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1100	}
sahilmgandhi	18:6a4db94011d3	1101	}
sahilmgandhi	18:6a4db94011d3	1102	while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
sahilmgandhi	18:6a4db94011d3	1103
sahilmgandhi	18:6a4db94011d3	1104	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1105	}
sahilmgandhi	18:6a4db94011d3	1106
sahilmgandhi	18:6a4db94011d3	1107
sahilmgandhi	18:6a4db94011d3	1108	/**
sahilmgandhi	18:6a4db94011d3	1109	* @brief USB_HostInit : Initializes the USB OTG controller registers
sahilmgandhi	18:6a4db94011d3	1110	* for Host mode
sahilmgandhi	18:6a4db94011d3	1111	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1112	* @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1113	* the configuration information for the specified USBx peripheral.
sahilmgandhi	18:6a4db94011d3	1114	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1115	*/
sahilmgandhi	18:6a4db94011d3	1116	HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
sahilmgandhi	18:6a4db94011d3	1117	{
sahilmgandhi	18:6a4db94011d3	1118	uint32_t i;
sahilmgandhi	18:6a4db94011d3	1119
sahilmgandhi	18:6a4db94011d3	1120	/* Restart the Phy Clock */
sahilmgandhi	18:6a4db94011d3	1121	USBx_PCGCCTL = 0;
sahilmgandhi	18:6a4db94011d3	1122
sahilmgandhi	18:6a4db94011d3	1123	/* no VBUS sensing*/
sahilmgandhi	18:6a4db94011d3	1124	USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
sahilmgandhi	18:6a4db94011d3	1125	USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
sahilmgandhi	18:6a4db94011d3	1126	USBx->GCCFG \|= USB_OTG_GCCFG_NOVBUSSENS;
sahilmgandhi	18:6a4db94011d3	1127
sahilmgandhi	18:6a4db94011d3	1128	/* Disable the FS/LS support mode only */
sahilmgandhi	18:6a4db94011d3	1129	if((cfg.speed == USB_OTG_SPEED_FULL)&&
sahilmgandhi	18:6a4db94011d3	1130	(USBx != USB_OTG_FS))
sahilmgandhi	18:6a4db94011d3	1131	{
sahilmgandhi	18:6a4db94011d3	1132	USBx_HOST->HCFG \|= USB_OTG_HCFG_FSLSS;
sahilmgandhi	18:6a4db94011d3	1133	}
sahilmgandhi	18:6a4db94011d3	1134	else
sahilmgandhi	18:6a4db94011d3	1135	{
sahilmgandhi	18:6a4db94011d3	1136	USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
sahilmgandhi	18:6a4db94011d3	1137	}
sahilmgandhi	18:6a4db94011d3	1138
sahilmgandhi	18:6a4db94011d3	1139	/* Make sure the FIFOs are flushed. */
sahilmgandhi	18:6a4db94011d3	1140	USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */
sahilmgandhi	18:6a4db94011d3	1141	USB_FlushRxFifo(USBx);
sahilmgandhi	18:6a4db94011d3	1142
sahilmgandhi	18:6a4db94011d3	1143	/* Clear all pending HC Interrupts */
sahilmgandhi	18:6a4db94011d3	1144	for (i = 0; i < cfg.Host_channels; i++)
sahilmgandhi	18:6a4db94011d3	1145	{
sahilmgandhi	18:6a4db94011d3	1146	USBx_HC(i)->HCINT = 0xFFFFFFFF;
sahilmgandhi	18:6a4db94011d3	1147	USBx_HC(i)->HCINTMSK = 0;
sahilmgandhi	18:6a4db94011d3	1148	}
sahilmgandhi	18:6a4db94011d3	1149
sahilmgandhi	18:6a4db94011d3	1150	/* Enable VBUS driving */
sahilmgandhi	18:6a4db94011d3	1151	USB_DriveVbus(USBx, 1);
sahilmgandhi	18:6a4db94011d3	1152
sahilmgandhi	18:6a4db94011d3	1153	HAL_Delay(200);
sahilmgandhi	18:6a4db94011d3	1154
sahilmgandhi	18:6a4db94011d3	1155	/* Disable all interrupts. */
sahilmgandhi	18:6a4db94011d3	1156	USBx->GINTMSK = 0;
sahilmgandhi	18:6a4db94011d3	1157
sahilmgandhi	18:6a4db94011d3	1158	/* Clear any pending interrupts */
sahilmgandhi	18:6a4db94011d3	1159	USBx->GINTSTS = 0xFFFFFFFF;
sahilmgandhi	18:6a4db94011d3	1160
sahilmgandhi	18:6a4db94011d3	1161	if(USBx == USB_OTG_FS)
sahilmgandhi	18:6a4db94011d3	1162	{
sahilmgandhi	18:6a4db94011d3	1163	/* set Rx FIFO size */
sahilmgandhi	18:6a4db94011d3	1164	USBx->GRXFSIZ = (uint32_t )0x80;
sahilmgandhi	18:6a4db94011d3	1165	USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) \| 0x80);
sahilmgandhi	18:6a4db94011d3	1166	USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) \| 0xE0);
sahilmgandhi	18:6a4db94011d3	1167	}
sahilmgandhi	18:6a4db94011d3	1168	else
sahilmgandhi	18:6a4db94011d3	1169	{
sahilmgandhi	18:6a4db94011d3	1170	/* set Rx FIFO size */
sahilmgandhi	18:6a4db94011d3	1171	USBx->GRXFSIZ = (uint32_t )0x200;
sahilmgandhi	18:6a4db94011d3	1172	USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) \| 0x200);
sahilmgandhi	18:6a4db94011d3	1173	USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) \| 0x300);
sahilmgandhi	18:6a4db94011d3	1174	}
sahilmgandhi	18:6a4db94011d3	1175
sahilmgandhi	18:6a4db94011d3	1176	/* Enable the common interrupts */
sahilmgandhi	18:6a4db94011d3	1177	if (cfg.dma_enable == DISABLE)
sahilmgandhi	18:6a4db94011d3	1178	{
sahilmgandhi	18:6a4db94011d3	1179	USBx->GINTMSK \|= USB_OTG_GINTMSK_RXFLVLM;
sahilmgandhi	18:6a4db94011d3	1180	}
sahilmgandhi	18:6a4db94011d3	1181
sahilmgandhi	18:6a4db94011d3	1182	/* Enable interrupts matching to the Host mode ONLY */
sahilmgandhi	18:6a4db94011d3	1183	USBx->GINTMSK \|= (USB_OTG_GINTMSK_PRTIM \| USB_OTG_GINTMSK_HCIM \|\
sahilmgandhi	18:6a4db94011d3	1184	USB_OTG_GINTMSK_SOFM \|USB_OTG_GINTSTS_DISCINT\|\
sahilmgandhi	18:6a4db94011d3	1185	USB_OTG_GINTMSK_PXFRM_IISOOXFRM \| USB_OTG_GINTMSK_WUIM);
sahilmgandhi	18:6a4db94011d3	1186
sahilmgandhi	18:6a4db94011d3	1187	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1188	}
sahilmgandhi	18:6a4db94011d3	1189
sahilmgandhi	18:6a4db94011d3	1190	/**
sahilmgandhi	18:6a4db94011d3	1191	* @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
sahilmgandhi	18:6a4db94011d3	1192	* HCFG register on the PHY type and set the right frame interval
sahilmgandhi	18:6a4db94011d3	1193	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1194	* @param freq : clock frequency
sahilmgandhi	18:6a4db94011d3	1195	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	1196	* HCFG_48_MHZ : Full Speed 48 MHz Clock
sahilmgandhi	18:6a4db94011d3	1197	* HCFG_6_MHZ : Low Speed 6 MHz Clock
sahilmgandhi	18:6a4db94011d3	1198	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1199	*/
sahilmgandhi	18:6a4db94011d3	1200	HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
sahilmgandhi	18:6a4db94011d3	1201	{
sahilmgandhi	18:6a4db94011d3	1202	USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
sahilmgandhi	18:6a4db94011d3	1203	USBx_HOST->HCFG \|= (freq & USB_OTG_HCFG_FSLSPCS);
sahilmgandhi	18:6a4db94011d3	1204
sahilmgandhi	18:6a4db94011d3	1205	if (freq == HCFG_48_MHZ)
sahilmgandhi	18:6a4db94011d3	1206	{
sahilmgandhi	18:6a4db94011d3	1207	USBx_HOST->HFIR = (uint32_t)48000;
sahilmgandhi	18:6a4db94011d3	1208	}
sahilmgandhi	18:6a4db94011d3	1209	else if (freq == HCFG_6_MHZ)
sahilmgandhi	18:6a4db94011d3	1210	{
sahilmgandhi	18:6a4db94011d3	1211	USBx_HOST->HFIR = (uint32_t)6000;
sahilmgandhi	18:6a4db94011d3	1212	}
sahilmgandhi	18:6a4db94011d3	1213	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1214	}
sahilmgandhi	18:6a4db94011d3	1215
sahilmgandhi	18:6a4db94011d3	1216	/**
sahilmgandhi	18:6a4db94011d3	1217	* @brief USB_OTG_ResetPort : Reset Host Port
sahilmgandhi	18:6a4db94011d3	1218	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1219	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1220	* @note (1)The application must wait at least 10 ms
sahilmgandhi	18:6a4db94011d3	1221	* before clearing the reset bit.
sahilmgandhi	18:6a4db94011d3	1222	*/
sahilmgandhi	18:6a4db94011d3	1223	HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	1224	{
sahilmgandhi	18:6a4db94011d3	1225	__IO uint32_t hprt0;
sahilmgandhi	18:6a4db94011d3	1226
sahilmgandhi	18:6a4db94011d3	1227	hprt0 = USBx_HPRT0;
sahilmgandhi	18:6a4db94011d3	1228
sahilmgandhi	18:6a4db94011d3	1229	hprt0 &= ~(USB_OTG_HPRT_PENA \| USB_OTG_HPRT_PCDET \|\
sahilmgandhi	18:6a4db94011d3	1230	USB_OTG_HPRT_PENCHNG \| USB_OTG_HPRT_POCCHNG );
sahilmgandhi	18:6a4db94011d3	1231
sahilmgandhi	18:6a4db94011d3	1232	USBx_HPRT0 = (USB_OTG_HPRT_PRST \| hprt0);
sahilmgandhi	18:6a4db94011d3	1233	HAL_Delay (10); /* See Note #1 */
sahilmgandhi	18:6a4db94011d3	1234	USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
sahilmgandhi	18:6a4db94011d3	1235	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1236	}
sahilmgandhi	18:6a4db94011d3	1237
sahilmgandhi	18:6a4db94011d3	1238	/**
sahilmgandhi	18:6a4db94011d3	1239	* @brief USB_DriveVbus : activate or de-activate vbus
sahilmgandhi	18:6a4db94011d3	1240	* @param state : VBUS state
sahilmgandhi	18:6a4db94011d3	1241	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	1242	* 0 : VBUS Active
sahilmgandhi	18:6a4db94011d3	1243	* 1 : VBUS Inactive
sahilmgandhi	18:6a4db94011d3	1244	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1245	*/
sahilmgandhi	18:6a4db94011d3	1246	HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
sahilmgandhi	18:6a4db94011d3	1247	{
sahilmgandhi	18:6a4db94011d3	1248	__IO uint32_t hprt0;
sahilmgandhi	18:6a4db94011d3	1249
sahilmgandhi	18:6a4db94011d3	1250	hprt0 = USBx_HPRT0;
sahilmgandhi	18:6a4db94011d3	1251	hprt0 &= ~(USB_OTG_HPRT_PENA \| USB_OTG_HPRT_PCDET \|\
sahilmgandhi	18:6a4db94011d3	1252	USB_OTG_HPRT_PENCHNG \| USB_OTG_HPRT_POCCHNG );
sahilmgandhi	18:6a4db94011d3	1253
sahilmgandhi	18:6a4db94011d3	1254	if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
sahilmgandhi	18:6a4db94011d3	1255	{
sahilmgandhi	18:6a4db94011d3	1256	USBx_HPRT0 = (USB_OTG_HPRT_PPWR \| hprt0);
sahilmgandhi	18:6a4db94011d3	1257	}
sahilmgandhi	18:6a4db94011d3	1258	if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))
sahilmgandhi	18:6a4db94011d3	1259	{
sahilmgandhi	18:6a4db94011d3	1260	USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
sahilmgandhi	18:6a4db94011d3	1261	}
sahilmgandhi	18:6a4db94011d3	1262	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1263	}
sahilmgandhi	18:6a4db94011d3	1264
sahilmgandhi	18:6a4db94011d3	1265	/**
sahilmgandhi	18:6a4db94011d3	1266	* @brief Return Host Core speed
sahilmgandhi	18:6a4db94011d3	1267	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1268	* @retval speed : Host speed
sahilmgandhi	18:6a4db94011d3	1269	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	1270	* @arg USB_OTG_SPEED_HIGH: High speed mode
sahilmgandhi	18:6a4db94011d3	1271	* @arg USB_OTG_SPEED_FULL: Full speed mode
sahilmgandhi	18:6a4db94011d3	1272	* @arg USB_OTG_SPEED_LOW: Low speed mode
sahilmgandhi	18:6a4db94011d3	1273	*/
sahilmgandhi	18:6a4db94011d3	1274	uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	1275	{
sahilmgandhi	18:6a4db94011d3	1276	__IO uint32_t hprt0;
sahilmgandhi	18:6a4db94011d3	1277
sahilmgandhi	18:6a4db94011d3	1278	hprt0 = USBx_HPRT0;
sahilmgandhi	18:6a4db94011d3	1279	return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
sahilmgandhi	18:6a4db94011d3	1280	}
sahilmgandhi	18:6a4db94011d3	1281
sahilmgandhi	18:6a4db94011d3	1282	/**
sahilmgandhi	18:6a4db94011d3	1283	* @brief Return Host Current Frame number
sahilmgandhi	18:6a4db94011d3	1284	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1285	* @retval current frame number
sahilmgandhi	18:6a4db94011d3	1286	*/
sahilmgandhi	18:6a4db94011d3	1287	uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	1288	{
sahilmgandhi	18:6a4db94011d3	1289	return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
sahilmgandhi	18:6a4db94011d3	1290	}
sahilmgandhi	18:6a4db94011d3	1291
sahilmgandhi	18:6a4db94011d3	1292	/**
sahilmgandhi	18:6a4db94011d3	1293	* @brief Initialize a host channel
sahilmgandhi	18:6a4db94011d3	1294	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1295	* @param ch_num : Channel number
sahilmgandhi	18:6a4db94011d3	1296	* This parameter can be a value from 1 to 15
sahilmgandhi	18:6a4db94011d3	1297	* @param epnum : Endpoint number
sahilmgandhi	18:6a4db94011d3	1298	* This parameter can be a value from 1 to 15
sahilmgandhi	18:6a4db94011d3	1299	* @param dev_address : Current device address
sahilmgandhi	18:6a4db94011d3	1300	* This parameter can be a value from 0 to 255
sahilmgandhi	18:6a4db94011d3	1301	* @param speed : Current device speed
sahilmgandhi	18:6a4db94011d3	1302	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	1303	* @arg USB_OTG_SPEED_HIGH: High speed mode
sahilmgandhi	18:6a4db94011d3	1304	* @arg USB_OTG_SPEED_FULL: Full speed mode
sahilmgandhi	18:6a4db94011d3	1305	* @arg USB_OTG_SPEED_LOW: Low speed mode
sahilmgandhi	18:6a4db94011d3	1306	* @param ep_type : Endpoint Type
sahilmgandhi	18:6a4db94011d3	1307	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	1308	* @arg EP_TYPE_CTRL: Control type
sahilmgandhi	18:6a4db94011d3	1309	* @arg EP_TYPE_ISOC: Isochronous type
sahilmgandhi	18:6a4db94011d3	1310	* @arg EP_TYPE_BULK: Bulk type
sahilmgandhi	18:6a4db94011d3	1311	* @arg EP_TYPE_INTR: Interrupt type
sahilmgandhi	18:6a4db94011d3	1312	* @param mps : Max Packet Size
sahilmgandhi	18:6a4db94011d3	1313	* This parameter can be a value from 0 to32K
sahilmgandhi	18:6a4db94011d3	1314	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	1315	*/
sahilmgandhi	18:6a4db94011d3	1316	HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
sahilmgandhi	18:6a4db94011d3	1317	uint8_t ch_num,
sahilmgandhi	18:6a4db94011d3	1318	uint8_t epnum,
sahilmgandhi	18:6a4db94011d3	1319	uint8_t dev_address,
sahilmgandhi	18:6a4db94011d3	1320	uint8_t speed,
sahilmgandhi	18:6a4db94011d3	1321	uint8_t ep_type,
sahilmgandhi	18:6a4db94011d3	1322	uint16_t mps)
sahilmgandhi	18:6a4db94011d3	1323	{
sahilmgandhi	18:6a4db94011d3	1324
sahilmgandhi	18:6a4db94011d3	1325	/* Clear old interrupt conditions for this host channel. */
sahilmgandhi	18:6a4db94011d3	1326	USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;
sahilmgandhi	18:6a4db94011d3	1327
sahilmgandhi	18:6a4db94011d3	1328	/* Enable channel interrupts required for this transfer. */
sahilmgandhi	18:6a4db94011d3	1329	switch (ep_type)
sahilmgandhi	18:6a4db94011d3	1330	{
sahilmgandhi	18:6a4db94011d3	1331	case EP_TYPE_CTRL:
sahilmgandhi	18:6a4db94011d3	1332	case EP_TYPE_BULK:
sahilmgandhi	18:6a4db94011d3	1333
sahilmgandhi	18:6a4db94011d3	1334	USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM \|\
sahilmgandhi	18:6a4db94011d3	1335	USB_OTG_HCINTMSK_STALLM \|\
sahilmgandhi	18:6a4db94011d3	1336	USB_OTG_HCINTMSK_TXERRM \|\
sahilmgandhi	18:6a4db94011d3	1337	USB_OTG_HCINTMSK_DTERRM \|\
sahilmgandhi	18:6a4db94011d3	1338	USB_OTG_HCINTMSK_AHBERR \|\
sahilmgandhi	18:6a4db94011d3	1339	USB_OTG_HCINTMSK_NAKM ;
sahilmgandhi	18:6a4db94011d3	1340
sahilmgandhi	18:6a4db94011d3	1341	if (epnum & 0x80)
sahilmgandhi	18:6a4db94011d3	1342	{
sahilmgandhi	18:6a4db94011d3	1343	USBx_HC(ch_num)->HCINTMSK \|= USB_OTG_HCINTMSK_BBERRM;
sahilmgandhi	18:6a4db94011d3	1344	}
sahilmgandhi	18:6a4db94011d3	1345	else
sahilmgandhi	18:6a4db94011d3	1346	{
sahilmgandhi	18:6a4db94011d3	1347	if(USBx != USB_OTG_FS)
sahilmgandhi	18:6a4db94011d3	1348	{
sahilmgandhi	18:6a4db94011d3	1349	USBx_HC(ch_num)->HCINTMSK \|= (USB_OTG_HCINTMSK_NYET \| USB_OTG_HCINTMSK_ACKM);
sahilmgandhi	18:6a4db94011d3	1350	}
sahilmgandhi	18:6a4db94011d3	1351	}
sahilmgandhi	18:6a4db94011d3	1352	break;
sahilmgandhi	18:6a4db94011d3	1353
sahilmgandhi	18:6a4db94011d3	1354	case EP_TYPE_INTR:
sahilmgandhi	18:6a4db94011d3	1355
sahilmgandhi	18:6a4db94011d3	1356	USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM \|\
sahilmgandhi	18:6a4db94011d3	1357	USB_OTG_HCINTMSK_STALLM \|\
sahilmgandhi	18:6a4db94011d3	1358	USB_OTG_HCINTMSK_TXERRM \|\
sahilmgandhi	18:6a4db94011d3	1359	USB_OTG_HCINTMSK_DTERRM \|\
sahilmgandhi	18:6a4db94011d3	1360	USB_OTG_HCINTMSK_NAKM \|\
sahilmgandhi	18:6a4db94011d3	1361	USB_OTG_HCINTMSK_AHBERR \|\
sahilmgandhi	18:6a4db94011d3	1362	USB_OTG_HCINTMSK_FRMORM ;
sahilmgandhi	18:6a4db94011d3	1363
sahilmgandhi	18:6a4db94011d3	1364	if (epnum & 0x80)
sahilmgandhi	18:6a4db94011d3	1365	{
sahilmgandhi	18:6a4db94011d3	1366	USBx_HC(ch_num)->HCINTMSK \|= USB_OTG_HCINTMSK_BBERRM;
sahilmgandhi	18:6a4db94011d3	1367	}
sahilmgandhi	18:6a4db94011d3	1368
sahilmgandhi	18:6a4db94011d3	1369	break;
sahilmgandhi	18:6a4db94011d3	1370	case EP_TYPE_ISOC:
sahilmgandhi	18:6a4db94011d3	1371
sahilmgandhi	18:6a4db94011d3	1372	USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM \|\
sahilmgandhi	18:6a4db94011d3	1373	USB_OTG_HCINTMSK_ACKM \|\
sahilmgandhi	18:6a4db94011d3	1374	USB_OTG_HCINTMSK_AHBERR \|\
sahilmgandhi	18:6a4db94011d3	1375	USB_OTG_HCINTMSK_FRMORM ;
sahilmgandhi	18:6a4db94011d3	1376
sahilmgandhi	18:6a4db94011d3	1377	if (epnum & 0x80)
sahilmgandhi	18:6a4db94011d3	1378	{
sahilmgandhi	18:6a4db94011d3	1379	USBx_HC(ch_num)->HCINTMSK \|= (USB_OTG_HCINTMSK_TXERRM \| USB_OTG_HCINTMSK_BBERRM);
sahilmgandhi	18:6a4db94011d3	1380	}
sahilmgandhi	18:6a4db94011d3	1381	break;
sahilmgandhi	18:6a4db94011d3	1382	}
sahilmgandhi	18:6a4db94011d3	1383
sahilmgandhi	18:6a4db94011d3	1384	/* Enable the top level host channel interrupt. */
sahilmgandhi	18:6a4db94011d3	1385	USBx_HOST->HAINTMSK \|= (1 << ch_num);
sahilmgandhi	18:6a4db94011d3	1386
sahilmgandhi	18:6a4db94011d3	1387	/* Make sure host channel interrupts are enabled. */
sahilmgandhi	18:6a4db94011d3	1388	USBx->GINTMSK \|= USB_OTG_GINTMSK_HCIM;
sahilmgandhi	18:6a4db94011d3	1389
sahilmgandhi	18:6a4db94011d3	1390	/* Program the HCCHAR register */
sahilmgandhi	18:6a4db94011d3	1391	USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) \|\
sahilmgandhi	18:6a4db94011d3	1392	(((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)\|\
sahilmgandhi	18:6a4db94011d3	1393	((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)\|\
sahilmgandhi	18:6a4db94011d3	1394	(((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)\|\
sahilmgandhi	18:6a4db94011d3	1395	((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)\|\
sahilmgandhi	18:6a4db94011d3	1396	(mps & USB_OTG_HCCHAR_MPSIZ));
sahilmgandhi	18:6a4db94011d3	1397
sahilmgandhi	18:6a4db94011d3	1398	if (ep_type == EP_TYPE_INTR)
sahilmgandhi	18:6a4db94011d3	1399	{
sahilmgandhi	18:6a4db94011d3	1400	USBx_HC(ch_num)->HCCHAR \|= USB_OTG_HCCHAR_ODDFRM ;
sahilmgandhi	18:6a4db94011d3	1401	}
sahilmgandhi	18:6a4db94011d3	1402
sahilmgandhi	18:6a4db94011d3	1403	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1404	}
sahilmgandhi	18:6a4db94011d3	1405
sahilmgandhi	18:6a4db94011d3	1406	/**
sahilmgandhi	18:6a4db94011d3	1407	* @brief Start a transfer over a host channel
sahilmgandhi	18:6a4db94011d3	1408	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1409	* @param hc : pointer to host channel structure
sahilmgandhi	18:6a4db94011d3	1410	* @param dma: USB dma enabled or disabled
sahilmgandhi	18:6a4db94011d3	1411	* This parameter can be one of these values:
sahilmgandhi	18:6a4db94011d3	1412	* 0 : DMA feature not used
sahilmgandhi	18:6a4db94011d3	1413	* 1 : DMA feature used
sahilmgandhi	18:6a4db94011d3	1414	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	1415	*/
sahilmgandhi	18:6a4db94011d3	1416	#if defined (__CC_ARM) /!< ARM Compiler /
sahilmgandhi	18:6a4db94011d3	1417	#pragma O0
sahilmgandhi	18:6a4db94011d3	1418	#elif defined (__GNUC__) /!< GNU Compiler /
sahilmgandhi	18:6a4db94011d3	1419	#pragma GCC optimize ("O0")
sahilmgandhi	18:6a4db94011d3	1420	#endif /* __CC_ARM */
sahilmgandhi	18:6a4db94011d3	1421	HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef USBx, USB_OTG_HCTypeDef hc, uint8_t dma)
sahilmgandhi	18:6a4db94011d3	1422	{
sahilmgandhi	18:6a4db94011d3	1423	uint8_t is_oddframe = 0;
sahilmgandhi	18:6a4db94011d3	1424	uint16_t len_words = 0;
sahilmgandhi	18:6a4db94011d3	1425	uint16_t num_packets = 0;
sahilmgandhi	18:6a4db94011d3	1426	uint16_t max_hc_pkt_count = 256;
sahilmgandhi	18:6a4db94011d3	1427	uint32_t tmpreg = 0;
sahilmgandhi	18:6a4db94011d3	1428
sahilmgandhi	18:6a4db94011d3	1429	if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
sahilmgandhi	18:6a4db94011d3	1430	{
sahilmgandhi	18:6a4db94011d3	1431	if((dma == 0) && (hc->do_ping == 1))
sahilmgandhi	18:6a4db94011d3	1432	{
sahilmgandhi	18:6a4db94011d3	1433	USB_DoPing(USBx, hc->ch_num);
sahilmgandhi	18:6a4db94011d3	1434	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1435	}
sahilmgandhi	18:6a4db94011d3	1436	else if(dma == 1)
sahilmgandhi	18:6a4db94011d3	1437	{
sahilmgandhi	18:6a4db94011d3	1438	USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET \| USB_OTG_HCINTMSK_ACKM);
sahilmgandhi	18:6a4db94011d3	1439	hc->do_ping = 0;
sahilmgandhi	18:6a4db94011d3	1440	}
sahilmgandhi	18:6a4db94011d3	1441	}
sahilmgandhi	18:6a4db94011d3	1442
sahilmgandhi	18:6a4db94011d3	1443	/* Compute the expected number of packets associated to the transfer */
sahilmgandhi	18:6a4db94011d3	1444	if (hc->xfer_len > 0)
sahilmgandhi	18:6a4db94011d3	1445	{
sahilmgandhi	18:6a4db94011d3	1446	num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
sahilmgandhi	18:6a4db94011d3	1447
sahilmgandhi	18:6a4db94011d3	1448	if (num_packets > max_hc_pkt_count)
sahilmgandhi	18:6a4db94011d3	1449	{
sahilmgandhi	18:6a4db94011d3	1450	num_packets = max_hc_pkt_count;
sahilmgandhi	18:6a4db94011d3	1451	hc->xfer_len = num_packets * hc->max_packet;
sahilmgandhi	18:6a4db94011d3	1452	}
sahilmgandhi	18:6a4db94011d3	1453	}
sahilmgandhi	18:6a4db94011d3	1454	else
sahilmgandhi	18:6a4db94011d3	1455	{
sahilmgandhi	18:6a4db94011d3	1456	num_packets = 1;
sahilmgandhi	18:6a4db94011d3	1457	}
sahilmgandhi	18:6a4db94011d3	1458	if (hc->ep_is_in)
sahilmgandhi	18:6a4db94011d3	1459	{
sahilmgandhi	18:6a4db94011d3	1460	hc->xfer_len = num_packets * hc->max_packet;
sahilmgandhi	18:6a4db94011d3	1461	}
sahilmgandhi	18:6a4db94011d3	1462
sahilmgandhi	18:6a4db94011d3	1463	/* Initialize the HCTSIZn register */
sahilmgandhi	18:6a4db94011d3	1464	USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) \|\
sahilmgandhi	18:6a4db94011d3	1465	((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) \|\
sahilmgandhi	18:6a4db94011d3	1466	(((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
sahilmgandhi	18:6a4db94011d3	1467
sahilmgandhi	18:6a4db94011d3	1468	if (dma)
sahilmgandhi	18:6a4db94011d3	1469	{
sahilmgandhi	18:6a4db94011d3	1470	/* xfer_buff MUST be 32-bits aligned */
sahilmgandhi	18:6a4db94011d3	1471	USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
sahilmgandhi	18:6a4db94011d3	1472	}
sahilmgandhi	18:6a4db94011d3	1473
sahilmgandhi	18:6a4db94011d3	1474	is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
sahilmgandhi	18:6a4db94011d3	1475	USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
sahilmgandhi	18:6a4db94011d3	1476	USBx_HC(hc->ch_num)->HCCHAR \|= (is_oddframe << 29);
sahilmgandhi	18:6a4db94011d3	1477
sahilmgandhi	18:6a4db94011d3	1478	/* Set host channel enable */
sahilmgandhi	18:6a4db94011d3	1479	tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
sahilmgandhi	18:6a4db94011d3	1480	tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
sahilmgandhi	18:6a4db94011d3	1481	tmpreg \|= USB_OTG_HCCHAR_CHENA;
sahilmgandhi	18:6a4db94011d3	1482	USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
sahilmgandhi	18:6a4db94011d3	1483
sahilmgandhi	18:6a4db94011d3	1484	if (dma == 0) /* Slave mode */
sahilmgandhi	18:6a4db94011d3	1485	{
sahilmgandhi	18:6a4db94011d3	1486	if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
sahilmgandhi	18:6a4db94011d3	1487	{
sahilmgandhi	18:6a4db94011d3	1488	switch(hc->ep_type)
sahilmgandhi	18:6a4db94011d3	1489	{
sahilmgandhi	18:6a4db94011d3	1490	/* Non periodic transfer */
sahilmgandhi	18:6a4db94011d3	1491	case EP_TYPE_CTRL:
sahilmgandhi	18:6a4db94011d3	1492	case EP_TYPE_BULK:
sahilmgandhi	18:6a4db94011d3	1493
sahilmgandhi	18:6a4db94011d3	1494	len_words = (hc->xfer_len + 3) / 4;
sahilmgandhi	18:6a4db94011d3	1495
sahilmgandhi	18:6a4db94011d3	1496	/* check if there is enough space in FIFO space */
sahilmgandhi	18:6a4db94011d3	1497	if(len_words > (USBx->HNPTXSTS & 0xFFFF))
sahilmgandhi	18:6a4db94011d3	1498	{
sahilmgandhi	18:6a4db94011d3	1499	/* need to process data in nptxfempty interrupt */
sahilmgandhi	18:6a4db94011d3	1500	USBx->GINTMSK \|= USB_OTG_GINTMSK_NPTXFEM;
sahilmgandhi	18:6a4db94011d3	1501	}
sahilmgandhi	18:6a4db94011d3	1502	break;
sahilmgandhi	18:6a4db94011d3	1503	/* Periodic transfer */
sahilmgandhi	18:6a4db94011d3	1504	case EP_TYPE_INTR:
sahilmgandhi	18:6a4db94011d3	1505	case EP_TYPE_ISOC:
sahilmgandhi	18:6a4db94011d3	1506	len_words = (hc->xfer_len + 3) / 4;
sahilmgandhi	18:6a4db94011d3	1507	/* check if there is enough space in FIFO space */
sahilmgandhi	18:6a4db94011d3	1508	if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
sahilmgandhi	18:6a4db94011d3	1509	{
sahilmgandhi	18:6a4db94011d3	1510	/* need to process data in ptxfempty interrupt */
sahilmgandhi	18:6a4db94011d3	1511	USBx->GINTMSK \|= USB_OTG_GINTMSK_PTXFEM;
sahilmgandhi	18:6a4db94011d3	1512	}
sahilmgandhi	18:6a4db94011d3	1513	break;
sahilmgandhi	18:6a4db94011d3	1514
sahilmgandhi	18:6a4db94011d3	1515	default:
sahilmgandhi	18:6a4db94011d3	1516	break;
sahilmgandhi	18:6a4db94011d3	1517	}
sahilmgandhi	18:6a4db94011d3	1518
sahilmgandhi	18:6a4db94011d3	1519	/* Write packet into the Tx FIFO. */
sahilmgandhi	18:6a4db94011d3	1520	USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
sahilmgandhi	18:6a4db94011d3	1521	hc->xfer_count = hc->xfer_len;
sahilmgandhi	18:6a4db94011d3	1522	}
sahilmgandhi	18:6a4db94011d3	1523	}
sahilmgandhi	18:6a4db94011d3	1524
sahilmgandhi	18:6a4db94011d3	1525	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1526	}
sahilmgandhi	18:6a4db94011d3	1527
sahilmgandhi	18:6a4db94011d3	1528	/**
sahilmgandhi	18:6a4db94011d3	1529	* @brief Read all host channel interrupts status
sahilmgandhi	18:6a4db94011d3	1530	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1531	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	1532	*/
sahilmgandhi	18:6a4db94011d3	1533	uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	1534	{
sahilmgandhi	18:6a4db94011d3	1535	return ((USBx_HOST->HAINT) & 0xFFFF);
sahilmgandhi	18:6a4db94011d3	1536	}
sahilmgandhi	18:6a4db94011d3	1537
sahilmgandhi	18:6a4db94011d3	1538	/**
sahilmgandhi	18:6a4db94011d3	1539	* @brief Halt a host channel
sahilmgandhi	18:6a4db94011d3	1540	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1541	* @param hc_num : Host Channel number
sahilmgandhi	18:6a4db94011d3	1542	* This parameter can be a value from 1 to 15
sahilmgandhi	18:6a4db94011d3	1543	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	1544	*/
sahilmgandhi	18:6a4db94011d3	1545	HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
sahilmgandhi	18:6a4db94011d3	1546	{
sahilmgandhi	18:6a4db94011d3	1547	uint32_t count = 0;
sahilmgandhi	18:6a4db94011d3	1548
sahilmgandhi	18:6a4db94011d3	1549	/* Check for space in the request queue to issue the halt. */
sahilmgandhi	18:6a4db94011d3	1550	if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) \|\| ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))
sahilmgandhi	18:6a4db94011d3	1551	{
sahilmgandhi	18:6a4db94011d3	1552	USBx_HC(hc_num)->HCCHAR \|= USB_OTG_HCCHAR_CHDIS;
sahilmgandhi	18:6a4db94011d3	1553
sahilmgandhi	18:6a4db94011d3	1554	if ((USBx->HNPTXSTS & 0xFFFF) == 0)
sahilmgandhi	18:6a4db94011d3	1555	{
sahilmgandhi	18:6a4db94011d3	1556	USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
sahilmgandhi	18:6a4db94011d3	1557	USBx_HC(hc_num)->HCCHAR \|= USB_OTG_HCCHAR_CHENA;
sahilmgandhi	18:6a4db94011d3	1558	USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
sahilmgandhi	18:6a4db94011d3	1559	do
sahilmgandhi	18:6a4db94011d3	1560	{
sahilmgandhi	18:6a4db94011d3	1561	if (++count > 1000)
sahilmgandhi	18:6a4db94011d3	1562	{
sahilmgandhi	18:6a4db94011d3	1563	break;
sahilmgandhi	18:6a4db94011d3	1564	}
sahilmgandhi	18:6a4db94011d3	1565	}
sahilmgandhi	18:6a4db94011d3	1566	while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
sahilmgandhi	18:6a4db94011d3	1567	}
sahilmgandhi	18:6a4db94011d3	1568	else
sahilmgandhi	18:6a4db94011d3	1569	{
sahilmgandhi	18:6a4db94011d3	1570	USBx_HC(hc_num)->HCCHAR \|= USB_OTG_HCCHAR_CHENA;
sahilmgandhi	18:6a4db94011d3	1571	}
sahilmgandhi	18:6a4db94011d3	1572	}
sahilmgandhi	18:6a4db94011d3	1573	else
sahilmgandhi	18:6a4db94011d3	1574	{
sahilmgandhi	18:6a4db94011d3	1575	USBx_HC(hc_num)->HCCHAR \|= USB_OTG_HCCHAR_CHDIS;
sahilmgandhi	18:6a4db94011d3	1576
sahilmgandhi	18:6a4db94011d3	1577	if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)
sahilmgandhi	18:6a4db94011d3	1578	{
sahilmgandhi	18:6a4db94011d3	1579	USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
sahilmgandhi	18:6a4db94011d3	1580	USBx_HC(hc_num)->HCCHAR \|= USB_OTG_HCCHAR_CHENA;
sahilmgandhi	18:6a4db94011d3	1581	USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
sahilmgandhi	18:6a4db94011d3	1582	do
sahilmgandhi	18:6a4db94011d3	1583	{
sahilmgandhi	18:6a4db94011d3	1584	if (++count > 1000)
sahilmgandhi	18:6a4db94011d3	1585	{
sahilmgandhi	18:6a4db94011d3	1586	break;
sahilmgandhi	18:6a4db94011d3	1587	}
sahilmgandhi	18:6a4db94011d3	1588	}
sahilmgandhi	18:6a4db94011d3	1589	while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
sahilmgandhi	18:6a4db94011d3	1590	}
sahilmgandhi	18:6a4db94011d3	1591	else
sahilmgandhi	18:6a4db94011d3	1592	{
sahilmgandhi	18:6a4db94011d3	1593	USBx_HC(hc_num)->HCCHAR \|= USB_OTG_HCCHAR_CHENA;
sahilmgandhi	18:6a4db94011d3	1594	}
sahilmgandhi	18:6a4db94011d3	1595	}
sahilmgandhi	18:6a4db94011d3	1596
sahilmgandhi	18:6a4db94011d3	1597	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1598	}
sahilmgandhi	18:6a4db94011d3	1599
sahilmgandhi	18:6a4db94011d3	1600	/**
sahilmgandhi	18:6a4db94011d3	1601	* @brief Initiate Do Ping protocol
sahilmgandhi	18:6a4db94011d3	1602	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1603	* @param hc_num : Host Channel number
sahilmgandhi	18:6a4db94011d3	1604	* This parameter can be a value from 1 to 15
sahilmgandhi	18:6a4db94011d3	1605	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	1606	*/
sahilmgandhi	18:6a4db94011d3	1607	HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
sahilmgandhi	18:6a4db94011d3	1608	{
sahilmgandhi	18:6a4db94011d3	1609	uint8_t num_packets = 1;
sahilmgandhi	18:6a4db94011d3	1610	uint32_t tmpreg = 0;
sahilmgandhi	18:6a4db94011d3	1611
sahilmgandhi	18:6a4db94011d3	1612	USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) \|\
sahilmgandhi	18:6a4db94011d3	1613	USB_OTG_HCTSIZ_DOPING;
sahilmgandhi	18:6a4db94011d3	1614
sahilmgandhi	18:6a4db94011d3	1615	/* Set host channel enable */
sahilmgandhi	18:6a4db94011d3	1616	tmpreg = USBx_HC(ch_num)->HCCHAR;
sahilmgandhi	18:6a4db94011d3	1617	tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
sahilmgandhi	18:6a4db94011d3	1618	tmpreg \|= USB_OTG_HCCHAR_CHENA;
sahilmgandhi	18:6a4db94011d3	1619	USBx_HC(ch_num)->HCCHAR = tmpreg;
sahilmgandhi	18:6a4db94011d3	1620
sahilmgandhi	18:6a4db94011d3	1621	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1622	}
sahilmgandhi	18:6a4db94011d3	1623
sahilmgandhi	18:6a4db94011d3	1624	/**
sahilmgandhi	18:6a4db94011d3	1625	* @brief Stop Host Core
sahilmgandhi	18:6a4db94011d3	1626	* @param USBx : Selected device
sahilmgandhi	18:6a4db94011d3	1627	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	1628	*/
sahilmgandhi	18:6a4db94011d3	1629	HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi	18:6a4db94011d3	1630	{
sahilmgandhi	18:6a4db94011d3	1631	uint8_t i;
sahilmgandhi	18:6a4db94011d3	1632	uint32_t count = 0;
sahilmgandhi	18:6a4db94011d3	1633	uint32_t value;
sahilmgandhi	18:6a4db94011d3	1634
sahilmgandhi	18:6a4db94011d3	1635	USB_DisableGlobalInt(USBx);
sahilmgandhi	18:6a4db94011d3	1636
sahilmgandhi	18:6a4db94011d3	1637	/* Flush FIFO */
sahilmgandhi	18:6a4db94011d3	1638	USB_FlushTxFifo(USBx, 0x10);
sahilmgandhi	18:6a4db94011d3	1639	USB_FlushRxFifo(USBx);
sahilmgandhi	18:6a4db94011d3	1640
sahilmgandhi	18:6a4db94011d3	1641	/* Flush out any leftover queued requests. */
sahilmgandhi	18:6a4db94011d3	1642	for (i = 0; i <= 15; i++)
sahilmgandhi	18:6a4db94011d3	1643	{
sahilmgandhi	18:6a4db94011d3	1644
sahilmgandhi	18:6a4db94011d3	1645	value = USBx_HC(i)->HCCHAR ;
sahilmgandhi	18:6a4db94011d3	1646	value \|= USB_OTG_HCCHAR_CHDIS;
sahilmgandhi	18:6a4db94011d3	1647	value &= ~USB_OTG_HCCHAR_CHENA;
sahilmgandhi	18:6a4db94011d3	1648	value &= ~USB_OTG_HCCHAR_EPDIR;
sahilmgandhi	18:6a4db94011d3	1649	USBx_HC(i)->HCCHAR = value;
sahilmgandhi	18:6a4db94011d3	1650	}
sahilmgandhi	18:6a4db94011d3	1651
sahilmgandhi	18:6a4db94011d3	1652	/* Halt all channels to put them into a known state. */
sahilmgandhi	18:6a4db94011d3	1653	for (i = 0; i <= 15; i++)
sahilmgandhi	18:6a4db94011d3	1654	{
sahilmgandhi	18:6a4db94011d3	1655	value = USBx_HC(i)->HCCHAR ;
sahilmgandhi	18:6a4db94011d3	1656
sahilmgandhi	18:6a4db94011d3	1657	value \|= USB_OTG_HCCHAR_CHDIS;
sahilmgandhi	18:6a4db94011d3	1658	value \|= USB_OTG_HCCHAR_CHENA;
sahilmgandhi	18:6a4db94011d3	1659	value &= ~USB_OTG_HCCHAR_EPDIR;
sahilmgandhi	18:6a4db94011d3	1660
sahilmgandhi	18:6a4db94011d3	1661	USBx_HC(i)->HCCHAR = value;
sahilmgandhi	18:6a4db94011d3	1662	do
sahilmgandhi	18:6a4db94011d3	1663	{
sahilmgandhi	18:6a4db94011d3	1664	if (++count > 1000)
sahilmgandhi	18:6a4db94011d3	1665	{
sahilmgandhi	18:6a4db94011d3	1666	break;
sahilmgandhi	18:6a4db94011d3	1667	}
sahilmgandhi	18:6a4db94011d3	1668	}
sahilmgandhi	18:6a4db94011d3	1669	while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
sahilmgandhi	18:6a4db94011d3	1670	}
sahilmgandhi	18:6a4db94011d3	1671
sahilmgandhi	18:6a4db94011d3	1672	/* Clear any pending Host interrupts */
sahilmgandhi	18:6a4db94011d3	1673	USBx_HOST->HAINT = 0xFFFFFFFF;
sahilmgandhi	18:6a4db94011d3	1674	USBx->GINTSTS = 0xFFFFFFFF;
sahilmgandhi	18:6a4db94011d3	1675	USB_EnableGlobalInt(USBx);
sahilmgandhi	18:6a4db94011d3	1676	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1677	}
sahilmgandhi	18:6a4db94011d3	1678	/**
sahilmgandhi	18:6a4db94011d3	1679	* @}
sahilmgandhi	18:6a4db94011d3	1680	*/
sahilmgandhi	18:6a4db94011d3	1681
sahilmgandhi	18:6a4db94011d3	1682	#endif /* defined (HAL_PCD_MODULE_ENABLED) \|\| defined (HAL_HCD_MODULE_ENABLED) */
sahilmgandhi	18:6a4db94011d3	1683
sahilmgandhi	18:6a4db94011d3	1684	/**
sahilmgandhi	18:6a4db94011d3	1685	* @}
sahilmgandhi	18:6a4db94011d3	1686	*/
sahilmgandhi	18:6a4db94011d3	1687
sahilmgandhi	18:6a4db94011d3	1688	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_usb.c@46:b156ef445742, 2017-06-03 (annotated)

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