MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32_hal_legacy.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32_hal_legacy.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version $VERSION$
sahilmgandhi 18:6a4db94011d3 6 * @date $DATE$
sahilmgandhi 18:6a4db94011d3 7 * @brief This file contains aliases definition for the STM32Cube HAL constants
sahilmgandhi 18:6a4db94011d3 8 * macros and functions maintained for legacy purpose.
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * @attention
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 15 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 16 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 17 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 19 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 20 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 22 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 23 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 24 *
sahilmgandhi 18:6a4db94011d3 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 35 *
sahilmgandhi 18:6a4db94011d3 36 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 37 */
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 40 #ifndef __STM32_HAL_LEGACY
sahilmgandhi 18:6a4db94011d3 41 #define __STM32_HAL_LEGACY
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 44 extern "C" {
sahilmgandhi 18:6a4db94011d3 45 #endif
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 48 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 49 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 52 * @{
sahilmgandhi 18:6a4db94011d3 53 */
sahilmgandhi 18:6a4db94011d3 54 #define AES_FLAG_RDERR CRYP_FLAG_RDERR
sahilmgandhi 18:6a4db94011d3 55 #define AES_FLAG_WRERR CRYP_FLAG_WRERR
sahilmgandhi 18:6a4db94011d3 56 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
sahilmgandhi 18:6a4db94011d3 57 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
sahilmgandhi 18:6a4db94011d3 58 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 /**
sahilmgandhi 18:6a4db94011d3 61 * @}
sahilmgandhi 18:6a4db94011d3 62 */
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 65 * @{
sahilmgandhi 18:6a4db94011d3 66 */
sahilmgandhi 18:6a4db94011d3 67 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
sahilmgandhi 18:6a4db94011d3 68 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
sahilmgandhi 18:6a4db94011d3 69 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
sahilmgandhi 18:6a4db94011d3 70 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
sahilmgandhi 18:6a4db94011d3 71 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
sahilmgandhi 18:6a4db94011d3 72 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
sahilmgandhi 18:6a4db94011d3 73 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
sahilmgandhi 18:6a4db94011d3 74 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
sahilmgandhi 18:6a4db94011d3 75 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
sahilmgandhi 18:6a4db94011d3 76 #define REGULAR_GROUP ADC_REGULAR_GROUP
sahilmgandhi 18:6a4db94011d3 77 #define INJECTED_GROUP ADC_INJECTED_GROUP
sahilmgandhi 18:6a4db94011d3 78 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
sahilmgandhi 18:6a4db94011d3 79 #define AWD_EVENT ADC_AWD_EVENT
sahilmgandhi 18:6a4db94011d3 80 #define AWD1_EVENT ADC_AWD1_EVENT
sahilmgandhi 18:6a4db94011d3 81 #define AWD2_EVENT ADC_AWD2_EVENT
sahilmgandhi 18:6a4db94011d3 82 #define AWD3_EVENT ADC_AWD3_EVENT
sahilmgandhi 18:6a4db94011d3 83 #define OVR_EVENT ADC_OVR_EVENT
sahilmgandhi 18:6a4db94011d3 84 #define JQOVF_EVENT ADC_JQOVF_EVENT
sahilmgandhi 18:6a4db94011d3 85 #define ALL_CHANNELS ADC_ALL_CHANNELS
sahilmgandhi 18:6a4db94011d3 86 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
sahilmgandhi 18:6a4db94011d3 87 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
sahilmgandhi 18:6a4db94011d3 88 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
sahilmgandhi 18:6a4db94011d3 89 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
sahilmgandhi 18:6a4db94011d3 90 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
sahilmgandhi 18:6a4db94011d3 91 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
sahilmgandhi 18:6a4db94011d3 92 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
sahilmgandhi 18:6a4db94011d3 93 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
sahilmgandhi 18:6a4db94011d3 94 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
sahilmgandhi 18:6a4db94011d3 95 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
sahilmgandhi 18:6a4db94011d3 96 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
sahilmgandhi 18:6a4db94011d3 97 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
sahilmgandhi 18:6a4db94011d3 98 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
sahilmgandhi 18:6a4db94011d3 99 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
sahilmgandhi 18:6a4db94011d3 100 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
sahilmgandhi 18:6a4db94011d3 101 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
sahilmgandhi 18:6a4db94011d3 102 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
sahilmgandhi 18:6a4db94011d3 103 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
sahilmgandhi 18:6a4db94011d3 104 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
sahilmgandhi 18:6a4db94011d3 105 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
sahilmgandhi 18:6a4db94011d3 106 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
sahilmgandhi 18:6a4db94011d3 109 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
sahilmgandhi 18:6a4db94011d3 110 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
sahilmgandhi 18:6a4db94011d3 111 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
sahilmgandhi 18:6a4db94011d3 112 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
sahilmgandhi 18:6a4db94011d3 113 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
sahilmgandhi 18:6a4db94011d3 114 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
sahilmgandhi 18:6a4db94011d3 115 /**
sahilmgandhi 18:6a4db94011d3 116 * @}
sahilmgandhi 18:6a4db94011d3 117 */
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 120 * @{
sahilmgandhi 18:6a4db94011d3 121 */
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 /**
sahilmgandhi 18:6a4db94011d3 126 * @}
sahilmgandhi 18:6a4db94011d3 127 */
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 130 * @{
sahilmgandhi 18:6a4db94011d3 131 */
sahilmgandhi 18:6a4db94011d3 132 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
sahilmgandhi 18:6a4db94011d3 133 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
sahilmgandhi 18:6a4db94011d3 134 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
sahilmgandhi 18:6a4db94011d3 135 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
sahilmgandhi 18:6a4db94011d3 136 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
sahilmgandhi 18:6a4db94011d3 137 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
sahilmgandhi 18:6a4db94011d3 138 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
sahilmgandhi 18:6a4db94011d3 139 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
sahilmgandhi 18:6a4db94011d3 140 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
sahilmgandhi 18:6a4db94011d3 141 #define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
sahilmgandhi 18:6a4db94011d3 142 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
sahilmgandhi 18:6a4db94011d3 143 #if defined(STM32F373xC) || defined(STM32F378xx)
sahilmgandhi 18:6a4db94011d3 144 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
sahilmgandhi 18:6a4db94011d3 145 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
sahilmgandhi 18:6a4db94011d3 146 #endif /* STM32F373xC || STM32F378xx */
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 #if defined(STM32L0) || defined(STM32L4)
sahilmgandhi 18:6a4db94011d3 149 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
sahilmgandhi 18:6a4db94011d3 152 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
sahilmgandhi 18:6a4db94011d3 153 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
sahilmgandhi 18:6a4db94011d3 154 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
sahilmgandhi 18:6a4db94011d3 155 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
sahilmgandhi 18:6a4db94011d3 156 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
sahilmgandhi 18:6a4db94011d3 159 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
sahilmgandhi 18:6a4db94011d3 160 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
sahilmgandhi 18:6a4db94011d3 161 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
sahilmgandhi 18:6a4db94011d3 162 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
sahilmgandhi 18:6a4db94011d3 163 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
sahilmgandhi 18:6a4db94011d3 164 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
sahilmgandhi 18:6a4db94011d3 165 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
sahilmgandhi 18:6a4db94011d3 166 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
sahilmgandhi 18:6a4db94011d3 167 #if defined(STM32L0)
sahilmgandhi 18:6a4db94011d3 168 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
sahilmgandhi 18:6a4db94011d3 169 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
sahilmgandhi 18:6a4db94011d3 170 /* to the second dedicated IO (only for COMP2). */
sahilmgandhi 18:6a4db94011d3 171 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
sahilmgandhi 18:6a4db94011d3 172 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
sahilmgandhi 18:6a4db94011d3 173 #else
sahilmgandhi 18:6a4db94011d3 174 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
sahilmgandhi 18:6a4db94011d3 175 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
sahilmgandhi 18:6a4db94011d3 176 #endif
sahilmgandhi 18:6a4db94011d3 177 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
sahilmgandhi 18:6a4db94011d3 178 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
sahilmgandhi 18:6a4db94011d3 181 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
sahilmgandhi 18:6a4db94011d3 184 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
sahilmgandhi 18:6a4db94011d3 185 #if defined(COMP_CSR_LOCK)
sahilmgandhi 18:6a4db94011d3 186 #define COMP_FLAG_LOCK COMP_CSR_LOCK
sahilmgandhi 18:6a4db94011d3 187 #elif defined(COMP_CSR_COMP1LOCK)
sahilmgandhi 18:6a4db94011d3 188 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
sahilmgandhi 18:6a4db94011d3 189 #elif defined(COMP_CSR_COMPxLOCK)
sahilmgandhi 18:6a4db94011d3 190 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
sahilmgandhi 18:6a4db94011d3 191 #endif
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 #if defined(STM32L4)
sahilmgandhi 18:6a4db94011d3 194 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
sahilmgandhi 18:6a4db94011d3 195 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
sahilmgandhi 18:6a4db94011d3 196 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
sahilmgandhi 18:6a4db94011d3 197 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
sahilmgandhi 18:6a4db94011d3 198 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
sahilmgandhi 18:6a4db94011d3 199 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
sahilmgandhi 18:6a4db94011d3 200 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
sahilmgandhi 18:6a4db94011d3 201 #endif
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 #if defined(STM32L0)
sahilmgandhi 18:6a4db94011d3 204 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
sahilmgandhi 18:6a4db94011d3 205 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
sahilmgandhi 18:6a4db94011d3 206 #else
sahilmgandhi 18:6a4db94011d3 207 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
sahilmgandhi 18:6a4db94011d3 208 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
sahilmgandhi 18:6a4db94011d3 209 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
sahilmgandhi 18:6a4db94011d3 210 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
sahilmgandhi 18:6a4db94011d3 211 #endif
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 #endif
sahilmgandhi 18:6a4db94011d3 214 /**
sahilmgandhi 18:6a4db94011d3 215 * @}
sahilmgandhi 18:6a4db94011d3 216 */
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 219 * @{
sahilmgandhi 18:6a4db94011d3 220 */
sahilmgandhi 18:6a4db94011d3 221 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
sahilmgandhi 18:6a4db94011d3 222 /**
sahilmgandhi 18:6a4db94011d3 223 * @}
sahilmgandhi 18:6a4db94011d3 224 */
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 227 * @{
sahilmgandhi 18:6a4db94011d3 228 */
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
sahilmgandhi 18:6a4db94011d3 231 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 /**
sahilmgandhi 18:6a4db94011d3 234 * @}
sahilmgandhi 18:6a4db94011d3 235 */
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 238 * @{
sahilmgandhi 18:6a4db94011d3 239 */
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 #define DAC1_CHANNEL_1 DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 242 #define DAC1_CHANNEL_2 DAC_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 243 #define DAC2_CHANNEL_1 DAC_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 244 #define DAC_WAVE_NONE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 245 #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
sahilmgandhi 18:6a4db94011d3 246 #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
sahilmgandhi 18:6a4db94011d3 247 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
sahilmgandhi 18:6a4db94011d3 248 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
sahilmgandhi 18:6a4db94011d3 249 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 /**
sahilmgandhi 18:6a4db94011d3 252 * @}
sahilmgandhi 18:6a4db94011d3 253 */
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 256 * @{
sahilmgandhi 18:6a4db94011d3 257 */
sahilmgandhi 18:6a4db94011d3 258 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
sahilmgandhi 18:6a4db94011d3 259 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
sahilmgandhi 18:6a4db94011d3 260 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
sahilmgandhi 18:6a4db94011d3 261 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
sahilmgandhi 18:6a4db94011d3 262 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
sahilmgandhi 18:6a4db94011d3 263 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
sahilmgandhi 18:6a4db94011d3 264 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
sahilmgandhi 18:6a4db94011d3 265 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
sahilmgandhi 18:6a4db94011d3 266 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
sahilmgandhi 18:6a4db94011d3 267 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
sahilmgandhi 18:6a4db94011d3 268 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
sahilmgandhi 18:6a4db94011d3 269 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
sahilmgandhi 18:6a4db94011d3 270 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
sahilmgandhi 18:6a4db94011d3 271 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
sahilmgandhi 18:6a4db94011d3 272 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 #define IS_HAL_REMAPDMA IS_DMA_REMAP
sahilmgandhi 18:6a4db94011d3 275 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
sahilmgandhi 18:6a4db94011d3 276 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 /**
sahilmgandhi 18:6a4db94011d3 281 * @}
sahilmgandhi 18:6a4db94011d3 282 */
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 285 * @{
sahilmgandhi 18:6a4db94011d3 286 */
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
sahilmgandhi 18:6a4db94011d3 289 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
sahilmgandhi 18:6a4db94011d3 290 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
sahilmgandhi 18:6a4db94011d3 291 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
sahilmgandhi 18:6a4db94011d3 292 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
sahilmgandhi 18:6a4db94011d3 293 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
sahilmgandhi 18:6a4db94011d3 294 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
sahilmgandhi 18:6a4db94011d3 295 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
sahilmgandhi 18:6a4db94011d3 296 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
sahilmgandhi 18:6a4db94011d3 297 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
sahilmgandhi 18:6a4db94011d3 298 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
sahilmgandhi 18:6a4db94011d3 299 #define OBEX_PCROP OPTIONBYTE_PCROP
sahilmgandhi 18:6a4db94011d3 300 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
sahilmgandhi 18:6a4db94011d3 301 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
sahilmgandhi 18:6a4db94011d3 302 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
sahilmgandhi 18:6a4db94011d3 303 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
sahilmgandhi 18:6a4db94011d3 304 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
sahilmgandhi 18:6a4db94011d3 305 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
sahilmgandhi 18:6a4db94011d3 306 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
sahilmgandhi 18:6a4db94011d3 307 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
sahilmgandhi 18:6a4db94011d3 308 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
sahilmgandhi 18:6a4db94011d3 309 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
sahilmgandhi 18:6a4db94011d3 310 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
sahilmgandhi 18:6a4db94011d3 311 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
sahilmgandhi 18:6a4db94011d3 312 #define PAGESIZE FLASH_PAGE_SIZE
sahilmgandhi 18:6a4db94011d3 313 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
sahilmgandhi 18:6a4db94011d3 314 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
sahilmgandhi 18:6a4db94011d3 315 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
sahilmgandhi 18:6a4db94011d3 316 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
sahilmgandhi 18:6a4db94011d3 317 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
sahilmgandhi 18:6a4db94011d3 318 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
sahilmgandhi 18:6a4db94011d3 319 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
sahilmgandhi 18:6a4db94011d3 320 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
sahilmgandhi 18:6a4db94011d3 321 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
sahilmgandhi 18:6a4db94011d3 322 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
sahilmgandhi 18:6a4db94011d3 323 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
sahilmgandhi 18:6a4db94011d3 324 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
sahilmgandhi 18:6a4db94011d3 325 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
sahilmgandhi 18:6a4db94011d3 326 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
sahilmgandhi 18:6a4db94011d3 327 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
sahilmgandhi 18:6a4db94011d3 328 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
sahilmgandhi 18:6a4db94011d3 329 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
sahilmgandhi 18:6a4db94011d3 330 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
sahilmgandhi 18:6a4db94011d3 331 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
sahilmgandhi 18:6a4db94011d3 332 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
sahilmgandhi 18:6a4db94011d3 333 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
sahilmgandhi 18:6a4db94011d3 334 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
sahilmgandhi 18:6a4db94011d3 335 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
sahilmgandhi 18:6a4db94011d3 336 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
sahilmgandhi 18:6a4db94011d3 337 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
sahilmgandhi 18:6a4db94011d3 338 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
sahilmgandhi 18:6a4db94011d3 339 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
sahilmgandhi 18:6a4db94011d3 340 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
sahilmgandhi 18:6a4db94011d3 341 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
sahilmgandhi 18:6a4db94011d3 342 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
sahilmgandhi 18:6a4db94011d3 343 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
sahilmgandhi 18:6a4db94011d3 344 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
sahilmgandhi 18:6a4db94011d3 345 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
sahilmgandhi 18:6a4db94011d3 346 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
sahilmgandhi 18:6a4db94011d3 347 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
sahilmgandhi 18:6a4db94011d3 348 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
sahilmgandhi 18:6a4db94011d3 349 #define OB_WDG_SW OB_IWDG_SW
sahilmgandhi 18:6a4db94011d3 350 #define OB_WDG_HW OB_IWDG_HW
sahilmgandhi 18:6a4db94011d3 351 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
sahilmgandhi 18:6a4db94011d3 352 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
sahilmgandhi 18:6a4db94011d3 353 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
sahilmgandhi 18:6a4db94011d3 354 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
sahilmgandhi 18:6a4db94011d3 355 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
sahilmgandhi 18:6a4db94011d3 356 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
sahilmgandhi 18:6a4db94011d3 357 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
sahilmgandhi 18:6a4db94011d3 358 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
sahilmgandhi 18:6a4db94011d3 359 /**
sahilmgandhi 18:6a4db94011d3 360 * @}
sahilmgandhi 18:6a4db94011d3 361 */
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 364 * @{
sahilmgandhi 18:6a4db94011d3 365 */
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
sahilmgandhi 18:6a4db94011d3 368 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
sahilmgandhi 18:6a4db94011d3 369 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
sahilmgandhi 18:6a4db94011d3 370 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
sahilmgandhi 18:6a4db94011d3 371 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
sahilmgandhi 18:6a4db94011d3 372 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
sahilmgandhi 18:6a4db94011d3 373 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
sahilmgandhi 18:6a4db94011d3 374 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
sahilmgandhi 18:6a4db94011d3 375 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
sahilmgandhi 18:6a4db94011d3 376 /**
sahilmgandhi 18:6a4db94011d3 377 * @}
sahilmgandhi 18:6a4db94011d3 378 */
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380
sahilmgandhi 18:6a4db94011d3 381 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
sahilmgandhi 18:6a4db94011d3 382 * @{
sahilmgandhi 18:6a4db94011d3 383 */
sahilmgandhi 18:6a4db94011d3 384 #if defined(STM32L4) || defined(STM32F7)
sahilmgandhi 18:6a4db94011d3 385 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
sahilmgandhi 18:6a4db94011d3 386 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
sahilmgandhi 18:6a4db94011d3 387 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
sahilmgandhi 18:6a4db94011d3 388 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
sahilmgandhi 18:6a4db94011d3 389 #else
sahilmgandhi 18:6a4db94011d3 390 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
sahilmgandhi 18:6a4db94011d3 391 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
sahilmgandhi 18:6a4db94011d3 392 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
sahilmgandhi 18:6a4db94011d3 393 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
sahilmgandhi 18:6a4db94011d3 394 #endif
sahilmgandhi 18:6a4db94011d3 395 /**
sahilmgandhi 18:6a4db94011d3 396 * @}
sahilmgandhi 18:6a4db94011d3 397 */
sahilmgandhi 18:6a4db94011d3 398
sahilmgandhi 18:6a4db94011d3 399 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 400 * @{
sahilmgandhi 18:6a4db94011d3 401 */
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
sahilmgandhi 18:6a4db94011d3 404 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
sahilmgandhi 18:6a4db94011d3 405 /**
sahilmgandhi 18:6a4db94011d3 406 * @}
sahilmgandhi 18:6a4db94011d3 407 */
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 410 * @{
sahilmgandhi 18:6a4db94011d3 411 */
sahilmgandhi 18:6a4db94011d3 412 #define GET_GPIO_SOURCE GPIO_GET_INDEX
sahilmgandhi 18:6a4db94011d3 413 #define GET_GPIO_INDEX GPIO_GET_INDEX
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 #if defined(STM32F4)
sahilmgandhi 18:6a4db94011d3 416 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO
sahilmgandhi 18:6a4db94011d3 417 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
sahilmgandhi 18:6a4db94011d3 418 #endif
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 #if defined(STM32F7)
sahilmgandhi 18:6a4db94011d3 421 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
sahilmgandhi 18:6a4db94011d3 422 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
sahilmgandhi 18:6a4db94011d3 423 #endif
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 #if defined(STM32L4)
sahilmgandhi 18:6a4db94011d3 426 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
sahilmgandhi 18:6a4db94011d3 427 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
sahilmgandhi 18:6a4db94011d3 428 #endif
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
sahilmgandhi 18:6a4db94011d3 431 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
sahilmgandhi 18:6a4db94011d3 432 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
sahilmgandhi 18:6a4db94011d3 435 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
sahilmgandhi 18:6a4db94011d3 436 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
sahilmgandhi 18:6a4db94011d3 437 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
sahilmgandhi 18:6a4db94011d3 438 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
sahilmgandhi 18:6a4db94011d3 439 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
sahilmgandhi 18:6a4db94011d3 440
sahilmgandhi 18:6a4db94011d3 441 #if defined(STM32L1)
sahilmgandhi 18:6a4db94011d3 442 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
sahilmgandhi 18:6a4db94011d3 443 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
sahilmgandhi 18:6a4db94011d3 444 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
sahilmgandhi 18:6a4db94011d3 445 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
sahilmgandhi 18:6a4db94011d3 446 #endif /* STM32L1 */
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
sahilmgandhi 18:6a4db94011d3 449 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
sahilmgandhi 18:6a4db94011d3 450 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
sahilmgandhi 18:6a4db94011d3 451 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
sahilmgandhi 18:6a4db94011d3 452 #endif /* STM32F0 || STM32F3 || STM32F1 */
sahilmgandhi 18:6a4db94011d3 453
sahilmgandhi 18:6a4db94011d3 454 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
sahilmgandhi 18:6a4db94011d3 455 /**
sahilmgandhi 18:6a4db94011d3 456 * @}
sahilmgandhi 18:6a4db94011d3 457 */
sahilmgandhi 18:6a4db94011d3 458
sahilmgandhi 18:6a4db94011d3 459 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 460 * @{
sahilmgandhi 18:6a4db94011d3 461 */
sahilmgandhi 18:6a4db94011d3 462 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
sahilmgandhi 18:6a4db94011d3 463 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
sahilmgandhi 18:6a4db94011d3 464 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
sahilmgandhi 18:6a4db94011d3 465 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
sahilmgandhi 18:6a4db94011d3 466 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
sahilmgandhi 18:6a4db94011d3 467 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
sahilmgandhi 18:6a4db94011d3 468 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
sahilmgandhi 18:6a4db94011d3 469 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
sahilmgandhi 18:6a4db94011d3 470 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
sahilmgandhi 18:6a4db94011d3 473 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
sahilmgandhi 18:6a4db94011d3 474 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
sahilmgandhi 18:6a4db94011d3 475 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
sahilmgandhi 18:6a4db94011d3 476 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
sahilmgandhi 18:6a4db94011d3 477 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
sahilmgandhi 18:6a4db94011d3 478 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
sahilmgandhi 18:6a4db94011d3 479 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
sahilmgandhi 18:6a4db94011d3 480 /**
sahilmgandhi 18:6a4db94011d3 481 * @}
sahilmgandhi 18:6a4db94011d3 482 */
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 485 * @{
sahilmgandhi 18:6a4db94011d3 486 */
sahilmgandhi 18:6a4db94011d3 487 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
sahilmgandhi 18:6a4db94011d3 488 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
sahilmgandhi 18:6a4db94011d3 489 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
sahilmgandhi 18:6a4db94011d3 490 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
sahilmgandhi 18:6a4db94011d3 491 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
sahilmgandhi 18:6a4db94011d3 492 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
sahilmgandhi 18:6a4db94011d3 493 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
sahilmgandhi 18:6a4db94011d3 494 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
sahilmgandhi 18:6a4db94011d3 495 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
sahilmgandhi 18:6a4db94011d3 496 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
sahilmgandhi 18:6a4db94011d3 497 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
sahilmgandhi 18:6a4db94011d3 498 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
sahilmgandhi 18:6a4db94011d3 499 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
sahilmgandhi 18:6a4db94011d3 500 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
sahilmgandhi 18:6a4db94011d3 501 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
sahilmgandhi 18:6a4db94011d3 502 #endif
sahilmgandhi 18:6a4db94011d3 503 /**
sahilmgandhi 18:6a4db94011d3 504 * @}
sahilmgandhi 18:6a4db94011d3 505 */
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 508 * @{
sahilmgandhi 18:6a4db94011d3 509 */
sahilmgandhi 18:6a4db94011d3 510 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
sahilmgandhi 18:6a4db94011d3 511 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
sahilmgandhi 18:6a4db94011d3 512
sahilmgandhi 18:6a4db94011d3 513 /**
sahilmgandhi 18:6a4db94011d3 514 * @}
sahilmgandhi 18:6a4db94011d3 515 */
sahilmgandhi 18:6a4db94011d3 516
sahilmgandhi 18:6a4db94011d3 517 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 518 * @{
sahilmgandhi 18:6a4db94011d3 519 */
sahilmgandhi 18:6a4db94011d3 520 #define KR_KEY_RELOAD IWDG_KEY_RELOAD
sahilmgandhi 18:6a4db94011d3 521 #define KR_KEY_ENABLE IWDG_KEY_ENABLE
sahilmgandhi 18:6a4db94011d3 522 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
sahilmgandhi 18:6a4db94011d3 523 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
sahilmgandhi 18:6a4db94011d3 524 /**
sahilmgandhi 18:6a4db94011d3 525 * @}
sahilmgandhi 18:6a4db94011d3 526 */
sahilmgandhi 18:6a4db94011d3 527
sahilmgandhi 18:6a4db94011d3 528 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 529 * @{
sahilmgandhi 18:6a4db94011d3 530 */
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
sahilmgandhi 18:6a4db94011d3 533 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
sahilmgandhi 18:6a4db94011d3 534 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
sahilmgandhi 18:6a4db94011d3 535 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
sahilmgandhi 18:6a4db94011d3 536
sahilmgandhi 18:6a4db94011d3 537 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
sahilmgandhi 18:6a4db94011d3 538 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
sahilmgandhi 18:6a4db94011d3 539 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
sahilmgandhi 18:6a4db94011d3 540
sahilmgandhi 18:6a4db94011d3 541 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
sahilmgandhi 18:6a4db94011d3 542 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
sahilmgandhi 18:6a4db94011d3 543 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
sahilmgandhi 18:6a4db94011d3 544 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
sahilmgandhi 18:6a4db94011d3 545
sahilmgandhi 18:6a4db94011d3 546 /* The following 3 definition have also been present in a temporary version of lptim.h */
sahilmgandhi 18:6a4db94011d3 547 /* They need to be renamed also to the right name, just in case */
sahilmgandhi 18:6a4db94011d3 548 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
sahilmgandhi 18:6a4db94011d3 549 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
sahilmgandhi 18:6a4db94011d3 550 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
sahilmgandhi 18:6a4db94011d3 551
sahilmgandhi 18:6a4db94011d3 552 /**
sahilmgandhi 18:6a4db94011d3 553 * @}
sahilmgandhi 18:6a4db94011d3 554 */
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 557 * @{
sahilmgandhi 18:6a4db94011d3 558 */
sahilmgandhi 18:6a4db94011d3 559 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
sahilmgandhi 18:6a4db94011d3 560 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
sahilmgandhi 18:6a4db94011d3 561 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
sahilmgandhi 18:6a4db94011d3 562 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
sahilmgandhi 18:6a4db94011d3 563
sahilmgandhi 18:6a4db94011d3 564 #define NAND_AddressTypedef NAND_AddressTypeDef
sahilmgandhi 18:6a4db94011d3 565
sahilmgandhi 18:6a4db94011d3 566 #define __ARRAY_ADDRESS ARRAY_ADDRESS
sahilmgandhi 18:6a4db94011d3 567 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
sahilmgandhi 18:6a4db94011d3 568 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
sahilmgandhi 18:6a4db94011d3 569 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
sahilmgandhi 18:6a4db94011d3 570 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
sahilmgandhi 18:6a4db94011d3 571 /**
sahilmgandhi 18:6a4db94011d3 572 * @}
sahilmgandhi 18:6a4db94011d3 573 */
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 576 * @{
sahilmgandhi 18:6a4db94011d3 577 */
sahilmgandhi 18:6a4db94011d3 578 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
sahilmgandhi 18:6a4db94011d3 579 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
sahilmgandhi 18:6a4db94011d3 580 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
sahilmgandhi 18:6a4db94011d3 581 #define NOR_ERROR HAL_NOR_STATUS_ERROR
sahilmgandhi 18:6a4db94011d3 582 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
sahilmgandhi 18:6a4db94011d3 583
sahilmgandhi 18:6a4db94011d3 584 #define __NOR_WRITE NOR_WRITE
sahilmgandhi 18:6a4db94011d3 585 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
sahilmgandhi 18:6a4db94011d3 586 /**
sahilmgandhi 18:6a4db94011d3 587 * @}
sahilmgandhi 18:6a4db94011d3 588 */
sahilmgandhi 18:6a4db94011d3 589
sahilmgandhi 18:6a4db94011d3 590 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 591 * @{
sahilmgandhi 18:6a4db94011d3 592 */
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
sahilmgandhi 18:6a4db94011d3 595 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
sahilmgandhi 18:6a4db94011d3 596 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
sahilmgandhi 18:6a4db94011d3 597 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
sahilmgandhi 18:6a4db94011d3 598
sahilmgandhi 18:6a4db94011d3 599 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
sahilmgandhi 18:6a4db94011d3 600 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
sahilmgandhi 18:6a4db94011d3 601 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
sahilmgandhi 18:6a4db94011d3 602 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
sahilmgandhi 18:6a4db94011d3 603
sahilmgandhi 18:6a4db94011d3 604 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
sahilmgandhi 18:6a4db94011d3 605 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
sahilmgandhi 18:6a4db94011d3 606
sahilmgandhi 18:6a4db94011d3 607 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
sahilmgandhi 18:6a4db94011d3 608 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
sahilmgandhi 18:6a4db94011d3 609
sahilmgandhi 18:6a4db94011d3 610 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
sahilmgandhi 18:6a4db94011d3 611 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
sahilmgandhi 18:6a4db94011d3 612
sahilmgandhi 18:6a4db94011d3 613 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
sahilmgandhi 18:6a4db94011d3 614
sahilmgandhi 18:6a4db94011d3 615 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
sahilmgandhi 18:6a4db94011d3 616 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
sahilmgandhi 18:6a4db94011d3 617 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
sahilmgandhi 18:6a4db94011d3 618
sahilmgandhi 18:6a4db94011d3 619 /**
sahilmgandhi 18:6a4db94011d3 620 * @}
sahilmgandhi 18:6a4db94011d3 621 */
sahilmgandhi 18:6a4db94011d3 622
sahilmgandhi 18:6a4db94011d3 623 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 624 * @{
sahilmgandhi 18:6a4db94011d3 625 */
sahilmgandhi 18:6a4db94011d3 626 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
sahilmgandhi 18:6a4db94011d3 627 #if defined(STM32F7)
sahilmgandhi 18:6a4db94011d3 628 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
sahilmgandhi 18:6a4db94011d3 629 #endif
sahilmgandhi 18:6a4db94011d3 630 /**
sahilmgandhi 18:6a4db94011d3 631 * @}
sahilmgandhi 18:6a4db94011d3 632 */
sahilmgandhi 18:6a4db94011d3 633
sahilmgandhi 18:6a4db94011d3 634 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 635 * @{
sahilmgandhi 18:6a4db94011d3 636 */
sahilmgandhi 18:6a4db94011d3 637
sahilmgandhi 18:6a4db94011d3 638 /* Compact Flash-ATA registers description */
sahilmgandhi 18:6a4db94011d3 639 #define CF_DATA ATA_DATA
sahilmgandhi 18:6a4db94011d3 640 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
sahilmgandhi 18:6a4db94011d3 641 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
sahilmgandhi 18:6a4db94011d3 642 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
sahilmgandhi 18:6a4db94011d3 643 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
sahilmgandhi 18:6a4db94011d3 644 #define CF_CARD_HEAD ATA_CARD_HEAD
sahilmgandhi 18:6a4db94011d3 645 #define CF_STATUS_CMD ATA_STATUS_CMD
sahilmgandhi 18:6a4db94011d3 646 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
sahilmgandhi 18:6a4db94011d3 647 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
sahilmgandhi 18:6a4db94011d3 648
sahilmgandhi 18:6a4db94011d3 649 /* Compact Flash-ATA commands */
sahilmgandhi 18:6a4db94011d3 650 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
sahilmgandhi 18:6a4db94011d3 651 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
sahilmgandhi 18:6a4db94011d3 652 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
sahilmgandhi 18:6a4db94011d3 653 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
sahilmgandhi 18:6a4db94011d3 656 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
sahilmgandhi 18:6a4db94011d3 657 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
sahilmgandhi 18:6a4db94011d3 658 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
sahilmgandhi 18:6a4db94011d3 659 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
sahilmgandhi 18:6a4db94011d3 660 /**
sahilmgandhi 18:6a4db94011d3 661 * @}
sahilmgandhi 18:6a4db94011d3 662 */
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 665 * @{
sahilmgandhi 18:6a4db94011d3 666 */
sahilmgandhi 18:6a4db94011d3 667
sahilmgandhi 18:6a4db94011d3 668 #define FORMAT_BIN RTC_FORMAT_BIN
sahilmgandhi 18:6a4db94011d3 669 #define FORMAT_BCD RTC_FORMAT_BCD
sahilmgandhi 18:6a4db94011d3 670
sahilmgandhi 18:6a4db94011d3 671 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
sahilmgandhi 18:6a4db94011d3 672 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
sahilmgandhi 18:6a4db94011d3 673 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
sahilmgandhi 18:6a4db94011d3 674 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
sahilmgandhi 18:6a4db94011d3 675 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
sahilmgandhi 18:6a4db94011d3 676
sahilmgandhi 18:6a4db94011d3 677 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
sahilmgandhi 18:6a4db94011d3 678 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
sahilmgandhi 18:6a4db94011d3 679 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
sahilmgandhi 18:6a4db94011d3 680 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
sahilmgandhi 18:6a4db94011d3 681 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
sahilmgandhi 18:6a4db94011d3 682 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
sahilmgandhi 18:6a4db94011d3 683 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
sahilmgandhi 18:6a4db94011d3 684 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
sahilmgandhi 18:6a4db94011d3 685
sahilmgandhi 18:6a4db94011d3 686 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
sahilmgandhi 18:6a4db94011d3 687 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
sahilmgandhi 18:6a4db94011d3 688 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
sahilmgandhi 18:6a4db94011d3 689 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
sahilmgandhi 18:6a4db94011d3 690
sahilmgandhi 18:6a4db94011d3 691 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
sahilmgandhi 18:6a4db94011d3 692 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
sahilmgandhi 18:6a4db94011d3 693 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
sahilmgandhi 18:6a4db94011d3 694
sahilmgandhi 18:6a4db94011d3 695 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
sahilmgandhi 18:6a4db94011d3 696 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
sahilmgandhi 18:6a4db94011d3 697 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
sahilmgandhi 18:6a4db94011d3 698
sahilmgandhi 18:6a4db94011d3 699 /**
sahilmgandhi 18:6a4db94011d3 700 * @}
sahilmgandhi 18:6a4db94011d3 701 */
sahilmgandhi 18:6a4db94011d3 702
sahilmgandhi 18:6a4db94011d3 703
sahilmgandhi 18:6a4db94011d3 704 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 705 * @{
sahilmgandhi 18:6a4db94011d3 706 */
sahilmgandhi 18:6a4db94011d3 707 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
sahilmgandhi 18:6a4db94011d3 708 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
sahilmgandhi 18:6a4db94011d3 709
sahilmgandhi 18:6a4db94011d3 710 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
sahilmgandhi 18:6a4db94011d3 711 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
sahilmgandhi 18:6a4db94011d3 712 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
sahilmgandhi 18:6a4db94011d3 713 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
sahilmgandhi 18:6a4db94011d3 714
sahilmgandhi 18:6a4db94011d3 715 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
sahilmgandhi 18:6a4db94011d3 716 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
sahilmgandhi 18:6a4db94011d3 717
sahilmgandhi 18:6a4db94011d3 718 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
sahilmgandhi 18:6a4db94011d3 719 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
sahilmgandhi 18:6a4db94011d3 720 /**
sahilmgandhi 18:6a4db94011d3 721 * @}
sahilmgandhi 18:6a4db94011d3 722 */
sahilmgandhi 18:6a4db94011d3 723
sahilmgandhi 18:6a4db94011d3 724
sahilmgandhi 18:6a4db94011d3 725 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 726 * @{
sahilmgandhi 18:6a4db94011d3 727 */
sahilmgandhi 18:6a4db94011d3 728 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
sahilmgandhi 18:6a4db94011d3 729 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
sahilmgandhi 18:6a4db94011d3 730 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
sahilmgandhi 18:6a4db94011d3 731 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
sahilmgandhi 18:6a4db94011d3 732 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
sahilmgandhi 18:6a4db94011d3 733 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
sahilmgandhi 18:6a4db94011d3 734 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
sahilmgandhi 18:6a4db94011d3 735 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
sahilmgandhi 18:6a4db94011d3 736 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
sahilmgandhi 18:6a4db94011d3 737 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
sahilmgandhi 18:6a4db94011d3 738 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
sahilmgandhi 18:6a4db94011d3 739 /**
sahilmgandhi 18:6a4db94011d3 740 * @}
sahilmgandhi 18:6a4db94011d3 741 */
sahilmgandhi 18:6a4db94011d3 742
sahilmgandhi 18:6a4db94011d3 743 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 744 * @{
sahilmgandhi 18:6a4db94011d3 745 */
sahilmgandhi 18:6a4db94011d3 746 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
sahilmgandhi 18:6a4db94011d3 747 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
sahilmgandhi 18:6a4db94011d3 748
sahilmgandhi 18:6a4db94011d3 749 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
sahilmgandhi 18:6a4db94011d3 750 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
sahilmgandhi 18:6a4db94011d3 751
sahilmgandhi 18:6a4db94011d3 752 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
sahilmgandhi 18:6a4db94011d3 753 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755 /**
sahilmgandhi 18:6a4db94011d3 756 * @}
sahilmgandhi 18:6a4db94011d3 757 */
sahilmgandhi 18:6a4db94011d3 758
sahilmgandhi 18:6a4db94011d3 759 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 760 * @{
sahilmgandhi 18:6a4db94011d3 761 */
sahilmgandhi 18:6a4db94011d3 762 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
sahilmgandhi 18:6a4db94011d3 763 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
sahilmgandhi 18:6a4db94011d3 764
sahilmgandhi 18:6a4db94011d3 765 #define TIM_DMABase_CR1 TIM_DMABASE_CR1
sahilmgandhi 18:6a4db94011d3 766 #define TIM_DMABase_CR2 TIM_DMABASE_CR2
sahilmgandhi 18:6a4db94011d3 767 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
sahilmgandhi 18:6a4db94011d3 768 #define TIM_DMABase_DIER TIM_DMABASE_DIER
sahilmgandhi 18:6a4db94011d3 769 #define TIM_DMABase_SR TIM_DMABASE_SR
sahilmgandhi 18:6a4db94011d3 770 #define TIM_DMABase_EGR TIM_DMABASE_EGR
sahilmgandhi 18:6a4db94011d3 771 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
sahilmgandhi 18:6a4db94011d3 772 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
sahilmgandhi 18:6a4db94011d3 773 #define TIM_DMABase_CCER TIM_DMABASE_CCER
sahilmgandhi 18:6a4db94011d3 774 #define TIM_DMABase_CNT TIM_DMABASE_CNT
sahilmgandhi 18:6a4db94011d3 775 #define TIM_DMABase_PSC TIM_DMABASE_PSC
sahilmgandhi 18:6a4db94011d3 776 #define TIM_DMABase_ARR TIM_DMABASE_ARR
sahilmgandhi 18:6a4db94011d3 777 #define TIM_DMABase_RCR TIM_DMABASE_RCR
sahilmgandhi 18:6a4db94011d3 778 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
sahilmgandhi 18:6a4db94011d3 779 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
sahilmgandhi 18:6a4db94011d3 780 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
sahilmgandhi 18:6a4db94011d3 781 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
sahilmgandhi 18:6a4db94011d3 782 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
sahilmgandhi 18:6a4db94011d3 783 #define TIM_DMABase_DCR TIM_DMABASE_DCR
sahilmgandhi 18:6a4db94011d3 784 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
sahilmgandhi 18:6a4db94011d3 785 #define TIM_DMABase_OR1 TIM_DMABASE_OR1
sahilmgandhi 18:6a4db94011d3 786 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
sahilmgandhi 18:6a4db94011d3 787 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
sahilmgandhi 18:6a4db94011d3 788 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
sahilmgandhi 18:6a4db94011d3 789 #define TIM_DMABase_OR2 TIM_DMABASE_OR2
sahilmgandhi 18:6a4db94011d3 790 #define TIM_DMABase_OR3 TIM_DMABASE_OR3
sahilmgandhi 18:6a4db94011d3 791 #define TIM_DMABase_OR TIM_DMABASE_OR
sahilmgandhi 18:6a4db94011d3 792
sahilmgandhi 18:6a4db94011d3 793 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
sahilmgandhi 18:6a4db94011d3 794 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
sahilmgandhi 18:6a4db94011d3 795 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
sahilmgandhi 18:6a4db94011d3 796 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
sahilmgandhi 18:6a4db94011d3 797 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
sahilmgandhi 18:6a4db94011d3 798 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
sahilmgandhi 18:6a4db94011d3 799 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
sahilmgandhi 18:6a4db94011d3 800 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
sahilmgandhi 18:6a4db94011d3 801 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
sahilmgandhi 18:6a4db94011d3 802
sahilmgandhi 18:6a4db94011d3 803 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
sahilmgandhi 18:6a4db94011d3 804 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
sahilmgandhi 18:6a4db94011d3 805 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
sahilmgandhi 18:6a4db94011d3 806 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
sahilmgandhi 18:6a4db94011d3 807 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
sahilmgandhi 18:6a4db94011d3 808 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
sahilmgandhi 18:6a4db94011d3 809 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
sahilmgandhi 18:6a4db94011d3 810 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
sahilmgandhi 18:6a4db94011d3 811 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
sahilmgandhi 18:6a4db94011d3 812 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
sahilmgandhi 18:6a4db94011d3 813 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
sahilmgandhi 18:6a4db94011d3 814 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
sahilmgandhi 18:6a4db94011d3 815 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
sahilmgandhi 18:6a4db94011d3 816 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
sahilmgandhi 18:6a4db94011d3 817 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
sahilmgandhi 18:6a4db94011d3 818 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
sahilmgandhi 18:6a4db94011d3 819 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
sahilmgandhi 18:6a4db94011d3 820 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
sahilmgandhi 18:6a4db94011d3 821
sahilmgandhi 18:6a4db94011d3 822 /**
sahilmgandhi 18:6a4db94011d3 823 * @}
sahilmgandhi 18:6a4db94011d3 824 */
sahilmgandhi 18:6a4db94011d3 825
sahilmgandhi 18:6a4db94011d3 826 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 827 * @{
sahilmgandhi 18:6a4db94011d3 828 */
sahilmgandhi 18:6a4db94011d3 829 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
sahilmgandhi 18:6a4db94011d3 830 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
sahilmgandhi 18:6a4db94011d3 831 /**
sahilmgandhi 18:6a4db94011d3 832 * @}
sahilmgandhi 18:6a4db94011d3 833 */
sahilmgandhi 18:6a4db94011d3 834
sahilmgandhi 18:6a4db94011d3 835 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 836 * @{
sahilmgandhi 18:6a4db94011d3 837 */
sahilmgandhi 18:6a4db94011d3 838 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
sahilmgandhi 18:6a4db94011d3 839 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
sahilmgandhi 18:6a4db94011d3 840 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
sahilmgandhi 18:6a4db94011d3 841 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
sahilmgandhi 18:6a4db94011d3 842
sahilmgandhi 18:6a4db94011d3 843 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
sahilmgandhi 18:6a4db94011d3 844 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
sahilmgandhi 18:6a4db94011d3 845
sahilmgandhi 18:6a4db94011d3 846 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
sahilmgandhi 18:6a4db94011d3 847 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
sahilmgandhi 18:6a4db94011d3 848 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
sahilmgandhi 18:6a4db94011d3 849 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
sahilmgandhi 18:6a4db94011d3 850
sahilmgandhi 18:6a4db94011d3 851 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
sahilmgandhi 18:6a4db94011d3 852 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
sahilmgandhi 18:6a4db94011d3 853 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
sahilmgandhi 18:6a4db94011d3 854 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
sahilmgandhi 18:6a4db94011d3 855
sahilmgandhi 18:6a4db94011d3 856 #define __DIV_LPUART UART_DIV_LPUART
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
sahilmgandhi 18:6a4db94011d3 859 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
sahilmgandhi 18:6a4db94011d3 860
sahilmgandhi 18:6a4db94011d3 861 /**
sahilmgandhi 18:6a4db94011d3 862 * @}
sahilmgandhi 18:6a4db94011d3 863 */
sahilmgandhi 18:6a4db94011d3 864
sahilmgandhi 18:6a4db94011d3 865
sahilmgandhi 18:6a4db94011d3 866 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 867 * @{
sahilmgandhi 18:6a4db94011d3 868 */
sahilmgandhi 18:6a4db94011d3 869
sahilmgandhi 18:6a4db94011d3 870 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
sahilmgandhi 18:6a4db94011d3 871 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
sahilmgandhi 18:6a4db94011d3 872
sahilmgandhi 18:6a4db94011d3 873 #define USARTNACK_ENABLED USART_NACK_ENABLE
sahilmgandhi 18:6a4db94011d3 874 #define USARTNACK_DISABLED USART_NACK_DISABLE
sahilmgandhi 18:6a4db94011d3 875 /**
sahilmgandhi 18:6a4db94011d3 876 * @}
sahilmgandhi 18:6a4db94011d3 877 */
sahilmgandhi 18:6a4db94011d3 878
sahilmgandhi 18:6a4db94011d3 879 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 880 * @{
sahilmgandhi 18:6a4db94011d3 881 */
sahilmgandhi 18:6a4db94011d3 882 #define CFR_BASE WWDG_CFR_BASE
sahilmgandhi 18:6a4db94011d3 883
sahilmgandhi 18:6a4db94011d3 884 /**
sahilmgandhi 18:6a4db94011d3 885 * @}
sahilmgandhi 18:6a4db94011d3 886 */
sahilmgandhi 18:6a4db94011d3 887
sahilmgandhi 18:6a4db94011d3 888 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 889 * @{
sahilmgandhi 18:6a4db94011d3 890 */
sahilmgandhi 18:6a4db94011d3 891 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
sahilmgandhi 18:6a4db94011d3 892 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
sahilmgandhi 18:6a4db94011d3 893 #define CAN_IT_RQCP0 CAN_IT_TME
sahilmgandhi 18:6a4db94011d3 894 #define CAN_IT_RQCP1 CAN_IT_TME
sahilmgandhi 18:6a4db94011d3 895 #define CAN_IT_RQCP2 CAN_IT_TME
sahilmgandhi 18:6a4db94011d3 896 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
sahilmgandhi 18:6a4db94011d3 897 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
sahilmgandhi 18:6a4db94011d3 898 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 899 #define CAN_TXSTATUS_OK ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 900 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
sahilmgandhi 18:6a4db94011d3 901
sahilmgandhi 18:6a4db94011d3 902 /**
sahilmgandhi 18:6a4db94011d3 903 * @}
sahilmgandhi 18:6a4db94011d3 904 */
sahilmgandhi 18:6a4db94011d3 905
sahilmgandhi 18:6a4db94011d3 906 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 907 * @{
sahilmgandhi 18:6a4db94011d3 908 */
sahilmgandhi 18:6a4db94011d3 909
sahilmgandhi 18:6a4db94011d3 910 #define VLAN_TAG ETH_VLAN_TAG
sahilmgandhi 18:6a4db94011d3 911 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
sahilmgandhi 18:6a4db94011d3 912 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
sahilmgandhi 18:6a4db94011d3 913 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
sahilmgandhi 18:6a4db94011d3 914 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
sahilmgandhi 18:6a4db94011d3 915 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
sahilmgandhi 18:6a4db94011d3 916 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
sahilmgandhi 18:6a4db94011d3 917 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
sahilmgandhi 18:6a4db94011d3 918
sahilmgandhi 18:6a4db94011d3 919 #define ETH_MMCCR ((uint32_t)0x00000100U)
sahilmgandhi 18:6a4db94011d3 920 #define ETH_MMCRIR ((uint32_t)0x00000104U)
sahilmgandhi 18:6a4db94011d3 921 #define ETH_MMCTIR ((uint32_t)0x00000108U)
sahilmgandhi 18:6a4db94011d3 922 #define ETH_MMCRIMR ((uint32_t)0x0000010CU)
sahilmgandhi 18:6a4db94011d3 923 #define ETH_MMCTIMR ((uint32_t)0x00000110U)
sahilmgandhi 18:6a4db94011d3 924 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
sahilmgandhi 18:6a4db94011d3 925 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
sahilmgandhi 18:6a4db94011d3 926 #define ETH_MMCTGFCR ((uint32_t)0x00000168U)
sahilmgandhi 18:6a4db94011d3 927 #define ETH_MMCRFCECR ((uint32_t)0x00000194U)
sahilmgandhi 18:6a4db94011d3 928 #define ETH_MMCRFAECR ((uint32_t)0x00000198U)
sahilmgandhi 18:6a4db94011d3 929 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
sahilmgandhi 18:6a4db94011d3 930
sahilmgandhi 18:6a4db94011d3 931 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
sahilmgandhi 18:6a4db94011d3 932 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
sahilmgandhi 18:6a4db94011d3 933 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
sahilmgandhi 18:6a4db94011d3 934 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
sahilmgandhi 18:6a4db94011d3 935 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
sahilmgandhi 18:6a4db94011d3 936 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
sahilmgandhi 18:6a4db94011d3 937 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
sahilmgandhi 18:6a4db94011d3 938 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
sahilmgandhi 18:6a4db94011d3 939 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
sahilmgandhi 18:6a4db94011d3 940 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
sahilmgandhi 18:6a4db94011d3 941 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
sahilmgandhi 18:6a4db94011d3 942 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
sahilmgandhi 18:6a4db94011d3 943 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
sahilmgandhi 18:6a4db94011d3 944 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
sahilmgandhi 18:6a4db94011d3 945 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
sahilmgandhi 18:6a4db94011d3 946 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
sahilmgandhi 18:6a4db94011d3 947 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
sahilmgandhi 18:6a4db94011d3 948 #if defined(STM32F1)
sahilmgandhi 18:6a4db94011d3 949 #else
sahilmgandhi 18:6a4db94011d3 950 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
sahilmgandhi 18:6a4db94011d3 951 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
sahilmgandhi 18:6a4db94011d3 952 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
sahilmgandhi 18:6a4db94011d3 953 #endif
sahilmgandhi 18:6a4db94011d3 954 #define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
sahilmgandhi 18:6a4db94011d3 955 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
sahilmgandhi 18:6a4db94011d3 956 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
sahilmgandhi 18:6a4db94011d3 957 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
sahilmgandhi 18:6a4db94011d3 958 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
sahilmgandhi 18:6a4db94011d3 959 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
sahilmgandhi 18:6a4db94011d3 960 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
sahilmgandhi 18:6a4db94011d3 961
sahilmgandhi 18:6a4db94011d3 962 /**
sahilmgandhi 18:6a4db94011d3 963 * @}
sahilmgandhi 18:6a4db94011d3 964 */
sahilmgandhi 18:6a4db94011d3 965
sahilmgandhi 18:6a4db94011d3 966 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 967 * @{
sahilmgandhi 18:6a4db94011d3 968 */
sahilmgandhi 18:6a4db94011d3 969 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
sahilmgandhi 18:6a4db94011d3 970 #define DCMI_IT_OVF DCMI_IT_OVR
sahilmgandhi 18:6a4db94011d3 971 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
sahilmgandhi 18:6a4db94011d3 972 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
sahilmgandhi 18:6a4db94011d3 973
sahilmgandhi 18:6a4db94011d3 974 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
sahilmgandhi 18:6a4db94011d3 975 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
sahilmgandhi 18:6a4db94011d3 976 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
sahilmgandhi 18:6a4db94011d3 977
sahilmgandhi 18:6a4db94011d3 978 /**
sahilmgandhi 18:6a4db94011d3 979 * @}
sahilmgandhi 18:6a4db94011d3 980 */
sahilmgandhi 18:6a4db94011d3 981
sahilmgandhi 18:6a4db94011d3 982 #if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
sahilmgandhi 18:6a4db94011d3 983 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 984 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 985 * @{
sahilmgandhi 18:6a4db94011d3 986 */
sahilmgandhi 18:6a4db94011d3 987 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
sahilmgandhi 18:6a4db94011d3 988 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
sahilmgandhi 18:6a4db94011d3 989 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
sahilmgandhi 18:6a4db94011d3 990 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
sahilmgandhi 18:6a4db94011d3 991 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
sahilmgandhi 18:6a4db94011d3 992
sahilmgandhi 18:6a4db94011d3 993 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888
sahilmgandhi 18:6a4db94011d3 994 #define CM_RGB888 DMA2D_INPUT_RGB888
sahilmgandhi 18:6a4db94011d3 995 #define CM_RGB565 DMA2D_INPUT_RGB565
sahilmgandhi 18:6a4db94011d3 996 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555
sahilmgandhi 18:6a4db94011d3 997 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444
sahilmgandhi 18:6a4db94011d3 998 #define CM_L8 DMA2D_INPUT_L8
sahilmgandhi 18:6a4db94011d3 999 #define CM_AL44 DMA2D_INPUT_AL44
sahilmgandhi 18:6a4db94011d3 1000 #define CM_AL88 DMA2D_INPUT_AL88
sahilmgandhi 18:6a4db94011d3 1001 #define CM_L4 DMA2D_INPUT_L4
sahilmgandhi 18:6a4db94011d3 1002 #define CM_A8 DMA2D_INPUT_A8
sahilmgandhi 18:6a4db94011d3 1003 #define CM_A4 DMA2D_INPUT_A4
sahilmgandhi 18:6a4db94011d3 1004 /**
sahilmgandhi 18:6a4db94011d3 1005 * @}
sahilmgandhi 18:6a4db94011d3 1006 */
sahilmgandhi 18:6a4db94011d3 1007 #endif /* STM32L4xx || STM32F7*/
sahilmgandhi 18:6a4db94011d3 1008
sahilmgandhi 18:6a4db94011d3 1009 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1010 * @{
sahilmgandhi 18:6a4db94011d3 1011 */
sahilmgandhi 18:6a4db94011d3 1012
sahilmgandhi 18:6a4db94011d3 1013 /**
sahilmgandhi 18:6a4db94011d3 1014 * @}
sahilmgandhi 18:6a4db94011d3 1015 */
sahilmgandhi 18:6a4db94011d3 1016
sahilmgandhi 18:6a4db94011d3 1017 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1018
sahilmgandhi 18:6a4db94011d3 1019 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1020 * @{
sahilmgandhi 18:6a4db94011d3 1021 */
sahilmgandhi 18:6a4db94011d3 1022 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
sahilmgandhi 18:6a4db94011d3 1023 /**
sahilmgandhi 18:6a4db94011d3 1024 * @}
sahilmgandhi 18:6a4db94011d3 1025 */
sahilmgandhi 18:6a4db94011d3 1026
sahilmgandhi 18:6a4db94011d3 1027 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1028 * @{
sahilmgandhi 18:6a4db94011d3 1029 */
sahilmgandhi 18:6a4db94011d3 1030 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
sahilmgandhi 18:6a4db94011d3 1031 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
sahilmgandhi 18:6a4db94011d3 1032 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
sahilmgandhi 18:6a4db94011d3 1033 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
sahilmgandhi 18:6a4db94011d3 1034 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
sahilmgandhi 18:6a4db94011d3 1035 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
sahilmgandhi 18:6a4db94011d3 1036
sahilmgandhi 18:6a4db94011d3 1037 /*HASH Algorithm Selection*/
sahilmgandhi 18:6a4db94011d3 1038
sahilmgandhi 18:6a4db94011d3 1039 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
sahilmgandhi 18:6a4db94011d3 1040 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
sahilmgandhi 18:6a4db94011d3 1041 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
sahilmgandhi 18:6a4db94011d3 1042 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
sahilmgandhi 18:6a4db94011d3 1043
sahilmgandhi 18:6a4db94011d3 1044 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
sahilmgandhi 18:6a4db94011d3 1045 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
sahilmgandhi 18:6a4db94011d3 1046
sahilmgandhi 18:6a4db94011d3 1047 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
sahilmgandhi 18:6a4db94011d3 1048 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
sahilmgandhi 18:6a4db94011d3 1049 /**
sahilmgandhi 18:6a4db94011d3 1050 * @}
sahilmgandhi 18:6a4db94011d3 1051 */
sahilmgandhi 18:6a4db94011d3 1052
sahilmgandhi 18:6a4db94011d3 1053 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1054 * @{
sahilmgandhi 18:6a4db94011d3 1055 */
sahilmgandhi 18:6a4db94011d3 1056 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
sahilmgandhi 18:6a4db94011d3 1057 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
sahilmgandhi 18:6a4db94011d3 1058 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
sahilmgandhi 18:6a4db94011d3 1059 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
sahilmgandhi 18:6a4db94011d3 1060 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
sahilmgandhi 18:6a4db94011d3 1061 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
sahilmgandhi 18:6a4db94011d3 1062 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
sahilmgandhi 18:6a4db94011d3 1063 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
sahilmgandhi 18:6a4db94011d3 1064 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
sahilmgandhi 18:6a4db94011d3 1065 #if defined(STM32L0)
sahilmgandhi 18:6a4db94011d3 1066 #else
sahilmgandhi 18:6a4db94011d3 1067 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
sahilmgandhi 18:6a4db94011d3 1068 #endif
sahilmgandhi 18:6a4db94011d3 1069 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
sahilmgandhi 18:6a4db94011d3 1070 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
sahilmgandhi 18:6a4db94011d3 1071 /**
sahilmgandhi 18:6a4db94011d3 1072 * @}
sahilmgandhi 18:6a4db94011d3 1073 */
sahilmgandhi 18:6a4db94011d3 1074
sahilmgandhi 18:6a4db94011d3 1075 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1076 * @{
sahilmgandhi 18:6a4db94011d3 1077 */
sahilmgandhi 18:6a4db94011d3 1078 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
sahilmgandhi 18:6a4db94011d3 1079 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
sahilmgandhi 18:6a4db94011d3 1080 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
sahilmgandhi 18:6a4db94011d3 1081 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
sahilmgandhi 18:6a4db94011d3 1082 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
sahilmgandhi 18:6a4db94011d3 1083 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
sahilmgandhi 18:6a4db94011d3 1084 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
sahilmgandhi 18:6a4db94011d3 1085
sahilmgandhi 18:6a4db94011d3 1086 /**
sahilmgandhi 18:6a4db94011d3 1087 * @}
sahilmgandhi 18:6a4db94011d3 1088 */
sahilmgandhi 18:6a4db94011d3 1089
sahilmgandhi 18:6a4db94011d3 1090 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1091 * @{
sahilmgandhi 18:6a4db94011d3 1092 */
sahilmgandhi 18:6a4db94011d3 1093 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
sahilmgandhi 18:6a4db94011d3 1094 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
sahilmgandhi 18:6a4db94011d3 1095 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
sahilmgandhi 18:6a4db94011d3 1096 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
sahilmgandhi 18:6a4db94011d3 1097
sahilmgandhi 18:6a4db94011d3 1098 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
sahilmgandhi 18:6a4db94011d3 1099 /**
sahilmgandhi 18:6a4db94011d3 1100 * @}
sahilmgandhi 18:6a4db94011d3 1101 */
sahilmgandhi 18:6a4db94011d3 1102
sahilmgandhi 18:6a4db94011d3 1103 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1104 * @{
sahilmgandhi 18:6a4db94011d3 1105 */
sahilmgandhi 18:6a4db94011d3 1106 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
sahilmgandhi 18:6a4db94011d3 1107 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
sahilmgandhi 18:6a4db94011d3 1108 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
sahilmgandhi 18:6a4db94011d3 1109 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
sahilmgandhi 18:6a4db94011d3 1110 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
sahilmgandhi 18:6a4db94011d3 1111 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
sahilmgandhi 18:6a4db94011d3 1112 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
sahilmgandhi 18:6a4db94011d3 1113 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
sahilmgandhi 18:6a4db94011d3 1114 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
sahilmgandhi 18:6a4db94011d3 1115 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
sahilmgandhi 18:6a4db94011d3 1116 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
sahilmgandhi 18:6a4db94011d3 1117 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
sahilmgandhi 18:6a4db94011d3 1118 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
sahilmgandhi 18:6a4db94011d3 1119 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
sahilmgandhi 18:6a4db94011d3 1120 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
sahilmgandhi 18:6a4db94011d3 1121 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
sahilmgandhi 18:6a4db94011d3 1122
sahilmgandhi 18:6a4db94011d3 1123 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
sahilmgandhi 18:6a4db94011d3 1124 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
sahilmgandhi 18:6a4db94011d3 1125 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
sahilmgandhi 18:6a4db94011d3 1126 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
sahilmgandhi 18:6a4db94011d3 1127 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
sahilmgandhi 18:6a4db94011d3 1128 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
sahilmgandhi 18:6a4db94011d3 1129 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
sahilmgandhi 18:6a4db94011d3 1130
sahilmgandhi 18:6a4db94011d3 1131 #define CR_OFFSET_BB PWR_CR_OFFSET_BB
sahilmgandhi 18:6a4db94011d3 1132 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
sahilmgandhi 18:6a4db94011d3 1133
sahilmgandhi 18:6a4db94011d3 1134 #define DBP_BitNumber DBP_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 1135 #define PVDE_BitNumber PVDE_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 1136 #define PMODE_BitNumber PMODE_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 1137 #define EWUP_BitNumber EWUP_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 1138 #define FPDS_BitNumber FPDS_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 1139 #define ODEN_BitNumber ODEN_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 1140 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 1141 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 1142 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 1143 #define BRE_BitNumber BRE_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 1144
sahilmgandhi 18:6a4db94011d3 1145 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
sahilmgandhi 18:6a4db94011d3 1146
sahilmgandhi 18:6a4db94011d3 1147 /**
sahilmgandhi 18:6a4db94011d3 1148 * @}
sahilmgandhi 18:6a4db94011d3 1149 */
sahilmgandhi 18:6a4db94011d3 1150
sahilmgandhi 18:6a4db94011d3 1151 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1152 * @{
sahilmgandhi 18:6a4db94011d3 1153 */
sahilmgandhi 18:6a4db94011d3 1154 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
sahilmgandhi 18:6a4db94011d3 1155 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
sahilmgandhi 18:6a4db94011d3 1156 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
sahilmgandhi 18:6a4db94011d3 1157 /**
sahilmgandhi 18:6a4db94011d3 1158 * @}
sahilmgandhi 18:6a4db94011d3 1159 */
sahilmgandhi 18:6a4db94011d3 1160
sahilmgandhi 18:6a4db94011d3 1161 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1162 * @{
sahilmgandhi 18:6a4db94011d3 1163 */
sahilmgandhi 18:6a4db94011d3 1164 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
sahilmgandhi 18:6a4db94011d3 1165 /**
sahilmgandhi 18:6a4db94011d3 1166 * @}
sahilmgandhi 18:6a4db94011d3 1167 */
sahilmgandhi 18:6a4db94011d3 1168
sahilmgandhi 18:6a4db94011d3 1169 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1170 * @{
sahilmgandhi 18:6a4db94011d3 1171 */
sahilmgandhi 18:6a4db94011d3 1172 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
sahilmgandhi 18:6a4db94011d3 1173 #define HAL_TIM_DMAError TIM_DMAError
sahilmgandhi 18:6a4db94011d3 1174 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
sahilmgandhi 18:6a4db94011d3 1175 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
sahilmgandhi 18:6a4db94011d3 1176 /**
sahilmgandhi 18:6a4db94011d3 1177 * @}
sahilmgandhi 18:6a4db94011d3 1178 */
sahilmgandhi 18:6a4db94011d3 1179
sahilmgandhi 18:6a4db94011d3 1180 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1181 * @{
sahilmgandhi 18:6a4db94011d3 1182 */
sahilmgandhi 18:6a4db94011d3 1183 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
sahilmgandhi 18:6a4db94011d3 1184 /**
sahilmgandhi 18:6a4db94011d3 1185 * @}
sahilmgandhi 18:6a4db94011d3 1186 */
sahilmgandhi 18:6a4db94011d3 1187
sahilmgandhi 18:6a4db94011d3 1188 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1189 * @{
sahilmgandhi 18:6a4db94011d3 1190 */
sahilmgandhi 18:6a4db94011d3 1191 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
sahilmgandhi 18:6a4db94011d3 1192 /**
sahilmgandhi 18:6a4db94011d3 1193 * @}
sahilmgandhi 18:6a4db94011d3 1194 */
sahilmgandhi 18:6a4db94011d3 1195
sahilmgandhi 18:6a4db94011d3 1196
sahilmgandhi 18:6a4db94011d3 1197 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1198 * @{
sahilmgandhi 18:6a4db94011d3 1199 */
sahilmgandhi 18:6a4db94011d3 1200
sahilmgandhi 18:6a4db94011d3 1201 /**
sahilmgandhi 18:6a4db94011d3 1202 * @}
sahilmgandhi 18:6a4db94011d3 1203 */
sahilmgandhi 18:6a4db94011d3 1204
sahilmgandhi 18:6a4db94011d3 1205 /* Exported macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1206
sahilmgandhi 18:6a4db94011d3 1207 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1208 * @{
sahilmgandhi 18:6a4db94011d3 1209 */
sahilmgandhi 18:6a4db94011d3 1210 #define AES_IT_CC CRYP_IT_CC
sahilmgandhi 18:6a4db94011d3 1211 #define AES_IT_ERR CRYP_IT_ERR
sahilmgandhi 18:6a4db94011d3 1212 #define AES_FLAG_CCF CRYP_FLAG_CCF
sahilmgandhi 18:6a4db94011d3 1213 /**
sahilmgandhi 18:6a4db94011d3 1214 * @}
sahilmgandhi 18:6a4db94011d3 1215 */
sahilmgandhi 18:6a4db94011d3 1216
sahilmgandhi 18:6a4db94011d3 1217 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1218 * @{
sahilmgandhi 18:6a4db94011d3 1219 */
sahilmgandhi 18:6a4db94011d3 1220 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
sahilmgandhi 18:6a4db94011d3 1221 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
sahilmgandhi 18:6a4db94011d3 1222 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
sahilmgandhi 18:6a4db94011d3 1223 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
sahilmgandhi 18:6a4db94011d3 1224 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
sahilmgandhi 18:6a4db94011d3 1225 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
sahilmgandhi 18:6a4db94011d3 1226 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
sahilmgandhi 18:6a4db94011d3 1227 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
sahilmgandhi 18:6a4db94011d3 1228 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
sahilmgandhi 18:6a4db94011d3 1229 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
sahilmgandhi 18:6a4db94011d3 1230 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
sahilmgandhi 18:6a4db94011d3 1231 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
sahilmgandhi 18:6a4db94011d3 1232 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
sahilmgandhi 18:6a4db94011d3 1233
sahilmgandhi 18:6a4db94011d3 1234 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
sahilmgandhi 18:6a4db94011d3 1235 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
sahilmgandhi 18:6a4db94011d3 1236 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
sahilmgandhi 18:6a4db94011d3 1237 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 1238 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 1239
sahilmgandhi 18:6a4db94011d3 1240 /**
sahilmgandhi 18:6a4db94011d3 1241 * @}
sahilmgandhi 18:6a4db94011d3 1242 */
sahilmgandhi 18:6a4db94011d3 1243
sahilmgandhi 18:6a4db94011d3 1244
sahilmgandhi 18:6a4db94011d3 1245 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1246 * @{
sahilmgandhi 18:6a4db94011d3 1247 */
sahilmgandhi 18:6a4db94011d3 1248 #define __ADC_ENABLE __HAL_ADC_ENABLE
sahilmgandhi 18:6a4db94011d3 1249 #define __ADC_DISABLE __HAL_ADC_DISABLE
sahilmgandhi 18:6a4db94011d3 1250 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
sahilmgandhi 18:6a4db94011d3 1251 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
sahilmgandhi 18:6a4db94011d3 1252 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
sahilmgandhi 18:6a4db94011d3 1253 #define __ADC_IS_ENABLED ADC_IS_ENABLE
sahilmgandhi 18:6a4db94011d3 1254 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
sahilmgandhi 18:6a4db94011d3 1255 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
sahilmgandhi 18:6a4db94011d3 1256 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
sahilmgandhi 18:6a4db94011d3 1257 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
sahilmgandhi 18:6a4db94011d3 1258 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
sahilmgandhi 18:6a4db94011d3 1259 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
sahilmgandhi 18:6a4db94011d3 1260 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
sahilmgandhi 18:6a4db94011d3 1261
sahilmgandhi 18:6a4db94011d3 1262 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
sahilmgandhi 18:6a4db94011d3 1263 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
sahilmgandhi 18:6a4db94011d3 1264 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
sahilmgandhi 18:6a4db94011d3 1265 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
sahilmgandhi 18:6a4db94011d3 1266 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
sahilmgandhi 18:6a4db94011d3 1267 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
sahilmgandhi 18:6a4db94011d3 1268 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
sahilmgandhi 18:6a4db94011d3 1269 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
sahilmgandhi 18:6a4db94011d3 1270 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
sahilmgandhi 18:6a4db94011d3 1271 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
sahilmgandhi 18:6a4db94011d3 1272 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
sahilmgandhi 18:6a4db94011d3 1273 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
sahilmgandhi 18:6a4db94011d3 1274 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
sahilmgandhi 18:6a4db94011d3 1275 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
sahilmgandhi 18:6a4db94011d3 1276 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
sahilmgandhi 18:6a4db94011d3 1277 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
sahilmgandhi 18:6a4db94011d3 1278 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
sahilmgandhi 18:6a4db94011d3 1279 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
sahilmgandhi 18:6a4db94011d3 1280 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
sahilmgandhi 18:6a4db94011d3 1281 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
sahilmgandhi 18:6a4db94011d3 1282
sahilmgandhi 18:6a4db94011d3 1283 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
sahilmgandhi 18:6a4db94011d3 1284 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
sahilmgandhi 18:6a4db94011d3 1285 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
sahilmgandhi 18:6a4db94011d3 1286 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
sahilmgandhi 18:6a4db94011d3 1287 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
sahilmgandhi 18:6a4db94011d3 1288 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
sahilmgandhi 18:6a4db94011d3 1289 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
sahilmgandhi 18:6a4db94011d3 1290 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
sahilmgandhi 18:6a4db94011d3 1291 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
sahilmgandhi 18:6a4db94011d3 1292 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
sahilmgandhi 18:6a4db94011d3 1293
sahilmgandhi 18:6a4db94011d3 1294 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
sahilmgandhi 18:6a4db94011d3 1295 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
sahilmgandhi 18:6a4db94011d3 1296 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
sahilmgandhi 18:6a4db94011d3 1297 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
sahilmgandhi 18:6a4db94011d3 1298 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
sahilmgandhi 18:6a4db94011d3 1299 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
sahilmgandhi 18:6a4db94011d3 1300 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
sahilmgandhi 18:6a4db94011d3 1301 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
sahilmgandhi 18:6a4db94011d3 1302
sahilmgandhi 18:6a4db94011d3 1303 #define __HAL_ADC_SQR1 ADC_SQR1
sahilmgandhi 18:6a4db94011d3 1304 #define __HAL_ADC_SMPR1 ADC_SMPR1
sahilmgandhi 18:6a4db94011d3 1305 #define __HAL_ADC_SMPR2 ADC_SMPR2
sahilmgandhi 18:6a4db94011d3 1306 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
sahilmgandhi 18:6a4db94011d3 1307 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
sahilmgandhi 18:6a4db94011d3 1308 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
sahilmgandhi 18:6a4db94011d3 1309 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
sahilmgandhi 18:6a4db94011d3 1310 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
sahilmgandhi 18:6a4db94011d3 1311 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
sahilmgandhi 18:6a4db94011d3 1312 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
sahilmgandhi 18:6a4db94011d3 1313 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
sahilmgandhi 18:6a4db94011d3 1314 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
sahilmgandhi 18:6a4db94011d3 1315 #define __HAL_ADC_JSQR ADC_JSQR
sahilmgandhi 18:6a4db94011d3 1316
sahilmgandhi 18:6a4db94011d3 1317 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
sahilmgandhi 18:6a4db94011d3 1318 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
sahilmgandhi 18:6a4db94011d3 1319 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
sahilmgandhi 18:6a4db94011d3 1320 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
sahilmgandhi 18:6a4db94011d3 1321 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
sahilmgandhi 18:6a4db94011d3 1322 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
sahilmgandhi 18:6a4db94011d3 1323 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
sahilmgandhi 18:6a4db94011d3 1324 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
sahilmgandhi 18:6a4db94011d3 1325
sahilmgandhi 18:6a4db94011d3 1326 /**
sahilmgandhi 18:6a4db94011d3 1327 * @}
sahilmgandhi 18:6a4db94011d3 1328 */
sahilmgandhi 18:6a4db94011d3 1329
sahilmgandhi 18:6a4db94011d3 1330 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1331 * @{
sahilmgandhi 18:6a4db94011d3 1332 */
sahilmgandhi 18:6a4db94011d3 1333 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
sahilmgandhi 18:6a4db94011d3 1334 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
sahilmgandhi 18:6a4db94011d3 1335 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
sahilmgandhi 18:6a4db94011d3 1336 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
sahilmgandhi 18:6a4db94011d3 1337
sahilmgandhi 18:6a4db94011d3 1338 /**
sahilmgandhi 18:6a4db94011d3 1339 * @}
sahilmgandhi 18:6a4db94011d3 1340 */
sahilmgandhi 18:6a4db94011d3 1341
sahilmgandhi 18:6a4db94011d3 1342 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1343 * @{
sahilmgandhi 18:6a4db94011d3 1344 */
sahilmgandhi 18:6a4db94011d3 1345 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
sahilmgandhi 18:6a4db94011d3 1346 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
sahilmgandhi 18:6a4db94011d3 1347 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
sahilmgandhi 18:6a4db94011d3 1348 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
sahilmgandhi 18:6a4db94011d3 1349 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
sahilmgandhi 18:6a4db94011d3 1350 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
sahilmgandhi 18:6a4db94011d3 1351 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
sahilmgandhi 18:6a4db94011d3 1352 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
sahilmgandhi 18:6a4db94011d3 1353 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
sahilmgandhi 18:6a4db94011d3 1354 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
sahilmgandhi 18:6a4db94011d3 1355 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
sahilmgandhi 18:6a4db94011d3 1356 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
sahilmgandhi 18:6a4db94011d3 1357 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
sahilmgandhi 18:6a4db94011d3 1358 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
sahilmgandhi 18:6a4db94011d3 1359 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
sahilmgandhi 18:6a4db94011d3 1360 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
sahilmgandhi 18:6a4db94011d3 1361
sahilmgandhi 18:6a4db94011d3 1362 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
sahilmgandhi 18:6a4db94011d3 1363 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
sahilmgandhi 18:6a4db94011d3 1364 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
sahilmgandhi 18:6a4db94011d3 1365 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
sahilmgandhi 18:6a4db94011d3 1366 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
sahilmgandhi 18:6a4db94011d3 1367 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
sahilmgandhi 18:6a4db94011d3 1368 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
sahilmgandhi 18:6a4db94011d3 1369 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
sahilmgandhi 18:6a4db94011d3 1370 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
sahilmgandhi 18:6a4db94011d3 1371 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
sahilmgandhi 18:6a4db94011d3 1372 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
sahilmgandhi 18:6a4db94011d3 1373 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
sahilmgandhi 18:6a4db94011d3 1374 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
sahilmgandhi 18:6a4db94011d3 1375 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
sahilmgandhi 18:6a4db94011d3 1376
sahilmgandhi 18:6a4db94011d3 1377
sahilmgandhi 18:6a4db94011d3 1378 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
sahilmgandhi 18:6a4db94011d3 1379 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
sahilmgandhi 18:6a4db94011d3 1380 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
sahilmgandhi 18:6a4db94011d3 1381 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
sahilmgandhi 18:6a4db94011d3 1382 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
sahilmgandhi 18:6a4db94011d3 1383 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
sahilmgandhi 18:6a4db94011d3 1384 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
sahilmgandhi 18:6a4db94011d3 1385 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
sahilmgandhi 18:6a4db94011d3 1386 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
sahilmgandhi 18:6a4db94011d3 1387 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
sahilmgandhi 18:6a4db94011d3 1388 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
sahilmgandhi 18:6a4db94011d3 1389 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
sahilmgandhi 18:6a4db94011d3 1390 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
sahilmgandhi 18:6a4db94011d3 1391 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
sahilmgandhi 18:6a4db94011d3 1392 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
sahilmgandhi 18:6a4db94011d3 1393 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
sahilmgandhi 18:6a4db94011d3 1394 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
sahilmgandhi 18:6a4db94011d3 1395 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
sahilmgandhi 18:6a4db94011d3 1396 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
sahilmgandhi 18:6a4db94011d3 1397 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
sahilmgandhi 18:6a4db94011d3 1398 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
sahilmgandhi 18:6a4db94011d3 1399 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
sahilmgandhi 18:6a4db94011d3 1400 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
sahilmgandhi 18:6a4db94011d3 1401 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
sahilmgandhi 18:6a4db94011d3 1402
sahilmgandhi 18:6a4db94011d3 1403 /**
sahilmgandhi 18:6a4db94011d3 1404 * @}
sahilmgandhi 18:6a4db94011d3 1405 */
sahilmgandhi 18:6a4db94011d3 1406
sahilmgandhi 18:6a4db94011d3 1407 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1408 * @{
sahilmgandhi 18:6a4db94011d3 1409 */
sahilmgandhi 18:6a4db94011d3 1410 #if defined(STM32F3)
sahilmgandhi 18:6a4db94011d3 1411 #define COMP_START __HAL_COMP_ENABLE
sahilmgandhi 18:6a4db94011d3 1412 #define COMP_STOP __HAL_COMP_DISABLE
sahilmgandhi 18:6a4db94011d3 1413 #define COMP_LOCK __HAL_COMP_LOCK
sahilmgandhi 18:6a4db94011d3 1414
sahilmgandhi 18:6a4db94011d3 1415 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
sahilmgandhi 18:6a4db94011d3 1416 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1417 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1418 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
sahilmgandhi 18:6a4db94011d3 1419 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1420 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1421 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
sahilmgandhi 18:6a4db94011d3 1422 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1423 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1424 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
sahilmgandhi 18:6a4db94011d3 1425 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1426 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1427 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
sahilmgandhi 18:6a4db94011d3 1428 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1429 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1430 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
sahilmgandhi 18:6a4db94011d3 1431 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1432 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1433 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
sahilmgandhi 18:6a4db94011d3 1434 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1435 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1436 __HAL_COMP_COMP6_EXTI_GET_FLAG())
sahilmgandhi 18:6a4db94011d3 1437 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1438 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1439 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
sahilmgandhi 18:6a4db94011d3 1440 # endif
sahilmgandhi 18:6a4db94011d3 1441 # if defined(STM32F302xE) || defined(STM32F302xC)
sahilmgandhi 18:6a4db94011d3 1442 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1443 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1444 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1445 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
sahilmgandhi 18:6a4db94011d3 1446 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1447 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1448 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1449 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
sahilmgandhi 18:6a4db94011d3 1450 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1451 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1452 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1453 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
sahilmgandhi 18:6a4db94011d3 1454 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1455 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1456 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1457 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
sahilmgandhi 18:6a4db94011d3 1458 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1459 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1460 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1461 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
sahilmgandhi 18:6a4db94011d3 1462 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1463 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1464 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1465 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
sahilmgandhi 18:6a4db94011d3 1466 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1467 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1468 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1469 __HAL_COMP_COMP6_EXTI_GET_FLAG())
sahilmgandhi 18:6a4db94011d3 1470 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1471 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1472 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1473 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
sahilmgandhi 18:6a4db94011d3 1474 # endif
sahilmgandhi 18:6a4db94011d3 1475 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
sahilmgandhi 18:6a4db94011d3 1476 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1477 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1478 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1479 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1480 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1481 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1482 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
sahilmgandhi 18:6a4db94011d3 1483 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1484 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1485 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1486 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1487 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1488 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1489 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
sahilmgandhi 18:6a4db94011d3 1490 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1491 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1492 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1493 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1494 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1495 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1496 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
sahilmgandhi 18:6a4db94011d3 1497 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1498 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1499 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1500 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1501 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1502 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1503 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
sahilmgandhi 18:6a4db94011d3 1504 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1505 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1506 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1507 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1508 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1509 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1510 __HAL_COMP_COMP7_EXTI_ENABLE_IT())
sahilmgandhi 18:6a4db94011d3 1511 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1512 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1513 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1514 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1515 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1516 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1517 __HAL_COMP_COMP7_EXTI_DISABLE_IT())
sahilmgandhi 18:6a4db94011d3 1518 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1519 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1520 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1521 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1522 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1523 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1524 __HAL_COMP_COMP7_EXTI_GET_FLAG())
sahilmgandhi 18:6a4db94011d3 1525 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1526 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1527 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1528 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1529 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1530 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1531 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
sahilmgandhi 18:6a4db94011d3 1532 # endif
sahilmgandhi 18:6a4db94011d3 1533 # if defined(STM32F373xC) ||defined(STM32F378xx)
sahilmgandhi 18:6a4db94011d3 1534 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1535 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
sahilmgandhi 18:6a4db94011d3 1536 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1537 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
sahilmgandhi 18:6a4db94011d3 1538 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1539 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
sahilmgandhi 18:6a4db94011d3 1540 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1541 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
sahilmgandhi 18:6a4db94011d3 1542 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1543 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
sahilmgandhi 18:6a4db94011d3 1544 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1545 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
sahilmgandhi 18:6a4db94011d3 1546 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1547 __HAL_COMP_COMP2_EXTI_GET_FLAG())
sahilmgandhi 18:6a4db94011d3 1548 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1549 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
sahilmgandhi 18:6a4db94011d3 1550 # endif
sahilmgandhi 18:6a4db94011d3 1551 #else
sahilmgandhi 18:6a4db94011d3 1552 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1553 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
sahilmgandhi 18:6a4db94011d3 1554 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1555 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
sahilmgandhi 18:6a4db94011d3 1556 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1557 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
sahilmgandhi 18:6a4db94011d3 1558 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
sahilmgandhi 18:6a4db94011d3 1559 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
sahilmgandhi 18:6a4db94011d3 1560 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1561 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
sahilmgandhi 18:6a4db94011d3 1562 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 1563 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
sahilmgandhi 18:6a4db94011d3 1564 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1565 __HAL_COMP_COMP2_EXTI_GET_FLAG())
sahilmgandhi 18:6a4db94011d3 1566 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 1567 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
sahilmgandhi 18:6a4db94011d3 1568 #endif
sahilmgandhi 18:6a4db94011d3 1569
sahilmgandhi 18:6a4db94011d3 1570 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
sahilmgandhi 18:6a4db94011d3 1571
sahilmgandhi 18:6a4db94011d3 1572 #if defined(STM32L0) || defined(STM32L4)
sahilmgandhi 18:6a4db94011d3 1573 /* Note: On these STM32 families, the only argument of this macro */
sahilmgandhi 18:6a4db94011d3 1574 /* is COMP_FLAG_LOCK. */
sahilmgandhi 18:6a4db94011d3 1575 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
sahilmgandhi 18:6a4db94011d3 1576 /* argument. */
sahilmgandhi 18:6a4db94011d3 1577 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
sahilmgandhi 18:6a4db94011d3 1578 #endif
sahilmgandhi 18:6a4db94011d3 1579 /**
sahilmgandhi 18:6a4db94011d3 1580 * @}
sahilmgandhi 18:6a4db94011d3 1581 */
sahilmgandhi 18:6a4db94011d3 1582
sahilmgandhi 18:6a4db94011d3 1583 #if defined(STM32L0) || defined(STM32L4)
sahilmgandhi 18:6a4db94011d3 1584 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1585 * @{
sahilmgandhi 18:6a4db94011d3 1586 */
sahilmgandhi 18:6a4db94011d3 1587 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
sahilmgandhi 18:6a4db94011d3 1588 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
sahilmgandhi 18:6a4db94011d3 1589 /**
sahilmgandhi 18:6a4db94011d3 1590 * @}
sahilmgandhi 18:6a4db94011d3 1591 */
sahilmgandhi 18:6a4db94011d3 1592 #endif
sahilmgandhi 18:6a4db94011d3 1593
sahilmgandhi 18:6a4db94011d3 1594 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1595 * @{
sahilmgandhi 18:6a4db94011d3 1596 */
sahilmgandhi 18:6a4db94011d3 1597
sahilmgandhi 18:6a4db94011d3 1598 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
sahilmgandhi 18:6a4db94011d3 1599 ((WAVE) == DAC_WAVE_NOISE)|| \
sahilmgandhi 18:6a4db94011d3 1600 ((WAVE) == DAC_WAVE_TRIANGLE))
sahilmgandhi 18:6a4db94011d3 1601
sahilmgandhi 18:6a4db94011d3 1602 /**
sahilmgandhi 18:6a4db94011d3 1603 * @}
sahilmgandhi 18:6a4db94011d3 1604 */
sahilmgandhi 18:6a4db94011d3 1605
sahilmgandhi 18:6a4db94011d3 1606 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1607 * @{
sahilmgandhi 18:6a4db94011d3 1608 */
sahilmgandhi 18:6a4db94011d3 1609
sahilmgandhi 18:6a4db94011d3 1610 #define IS_WRPAREA IS_OB_WRPAREA
sahilmgandhi 18:6a4db94011d3 1611 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
sahilmgandhi 18:6a4db94011d3 1612 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
sahilmgandhi 18:6a4db94011d3 1613 #define IS_TYPEERASE IS_FLASH_TYPEERASE
sahilmgandhi 18:6a4db94011d3 1614 #define IS_NBSECTORS IS_FLASH_NBSECTORS
sahilmgandhi 18:6a4db94011d3 1615 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
sahilmgandhi 18:6a4db94011d3 1616
sahilmgandhi 18:6a4db94011d3 1617 /**
sahilmgandhi 18:6a4db94011d3 1618 * @}
sahilmgandhi 18:6a4db94011d3 1619 */
sahilmgandhi 18:6a4db94011d3 1620
sahilmgandhi 18:6a4db94011d3 1621 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1622 * @{
sahilmgandhi 18:6a4db94011d3 1623 */
sahilmgandhi 18:6a4db94011d3 1624
sahilmgandhi 18:6a4db94011d3 1625 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
sahilmgandhi 18:6a4db94011d3 1626 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
sahilmgandhi 18:6a4db94011d3 1627 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
sahilmgandhi 18:6a4db94011d3 1628 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
sahilmgandhi 18:6a4db94011d3 1629 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
sahilmgandhi 18:6a4db94011d3 1630 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
sahilmgandhi 18:6a4db94011d3 1631 #define __HAL_I2C_SPEED I2C_SPEED
sahilmgandhi 18:6a4db94011d3 1632 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
sahilmgandhi 18:6a4db94011d3 1633 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
sahilmgandhi 18:6a4db94011d3 1634 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
sahilmgandhi 18:6a4db94011d3 1635 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
sahilmgandhi 18:6a4db94011d3 1636 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
sahilmgandhi 18:6a4db94011d3 1637 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
sahilmgandhi 18:6a4db94011d3 1638 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
sahilmgandhi 18:6a4db94011d3 1639 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
sahilmgandhi 18:6a4db94011d3 1640 /**
sahilmgandhi 18:6a4db94011d3 1641 * @}
sahilmgandhi 18:6a4db94011d3 1642 */
sahilmgandhi 18:6a4db94011d3 1643
sahilmgandhi 18:6a4db94011d3 1644 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1645 * @{
sahilmgandhi 18:6a4db94011d3 1646 */
sahilmgandhi 18:6a4db94011d3 1647
sahilmgandhi 18:6a4db94011d3 1648 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
sahilmgandhi 18:6a4db94011d3 1649 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
sahilmgandhi 18:6a4db94011d3 1650
sahilmgandhi 18:6a4db94011d3 1651 /**
sahilmgandhi 18:6a4db94011d3 1652 * @}
sahilmgandhi 18:6a4db94011d3 1653 */
sahilmgandhi 18:6a4db94011d3 1654
sahilmgandhi 18:6a4db94011d3 1655 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1656 * @{
sahilmgandhi 18:6a4db94011d3 1657 */
sahilmgandhi 18:6a4db94011d3 1658
sahilmgandhi 18:6a4db94011d3 1659 #define __IRDA_DISABLE __HAL_IRDA_DISABLE
sahilmgandhi 18:6a4db94011d3 1660 #define __IRDA_ENABLE __HAL_IRDA_ENABLE
sahilmgandhi 18:6a4db94011d3 1661
sahilmgandhi 18:6a4db94011d3 1662 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
sahilmgandhi 18:6a4db94011d3 1663 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
sahilmgandhi 18:6a4db94011d3 1664 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
sahilmgandhi 18:6a4db94011d3 1665 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
sahilmgandhi 18:6a4db94011d3 1666
sahilmgandhi 18:6a4db94011d3 1667 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
sahilmgandhi 18:6a4db94011d3 1668
sahilmgandhi 18:6a4db94011d3 1669
sahilmgandhi 18:6a4db94011d3 1670 /**
sahilmgandhi 18:6a4db94011d3 1671 * @}
sahilmgandhi 18:6a4db94011d3 1672 */
sahilmgandhi 18:6a4db94011d3 1673
sahilmgandhi 18:6a4db94011d3 1674
sahilmgandhi 18:6a4db94011d3 1675 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1676 * @{
sahilmgandhi 18:6a4db94011d3 1677 */
sahilmgandhi 18:6a4db94011d3 1678 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
sahilmgandhi 18:6a4db94011d3 1679 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
sahilmgandhi 18:6a4db94011d3 1680 /**
sahilmgandhi 18:6a4db94011d3 1681 * @}
sahilmgandhi 18:6a4db94011d3 1682 */
sahilmgandhi 18:6a4db94011d3 1683
sahilmgandhi 18:6a4db94011d3 1684
sahilmgandhi 18:6a4db94011d3 1685 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1686 * @{
sahilmgandhi 18:6a4db94011d3 1687 */
sahilmgandhi 18:6a4db94011d3 1688
sahilmgandhi 18:6a4db94011d3 1689 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
sahilmgandhi 18:6a4db94011d3 1690 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
sahilmgandhi 18:6a4db94011d3 1691 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
sahilmgandhi 18:6a4db94011d3 1692
sahilmgandhi 18:6a4db94011d3 1693 /**
sahilmgandhi 18:6a4db94011d3 1694 * @}
sahilmgandhi 18:6a4db94011d3 1695 */
sahilmgandhi 18:6a4db94011d3 1696
sahilmgandhi 18:6a4db94011d3 1697
sahilmgandhi 18:6a4db94011d3 1698 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1699 * @{
sahilmgandhi 18:6a4db94011d3 1700 */
sahilmgandhi 18:6a4db94011d3 1701 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
sahilmgandhi 18:6a4db94011d3 1702 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
sahilmgandhi 18:6a4db94011d3 1703 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
sahilmgandhi 18:6a4db94011d3 1704 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
sahilmgandhi 18:6a4db94011d3 1705 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
sahilmgandhi 18:6a4db94011d3 1706 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
sahilmgandhi 18:6a4db94011d3 1707 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
sahilmgandhi 18:6a4db94011d3 1708 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
sahilmgandhi 18:6a4db94011d3 1709 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
sahilmgandhi 18:6a4db94011d3 1710 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
sahilmgandhi 18:6a4db94011d3 1711 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
sahilmgandhi 18:6a4db94011d3 1712 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
sahilmgandhi 18:6a4db94011d3 1713 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
sahilmgandhi 18:6a4db94011d3 1714
sahilmgandhi 18:6a4db94011d3 1715 /**
sahilmgandhi 18:6a4db94011d3 1716 * @}
sahilmgandhi 18:6a4db94011d3 1717 */
sahilmgandhi 18:6a4db94011d3 1718
sahilmgandhi 18:6a4db94011d3 1719
sahilmgandhi 18:6a4db94011d3 1720 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1721 * @{
sahilmgandhi 18:6a4db94011d3 1722 */
sahilmgandhi 18:6a4db94011d3 1723 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
sahilmgandhi 18:6a4db94011d3 1724 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
sahilmgandhi 18:6a4db94011d3 1725 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 1726 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 1727 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
sahilmgandhi 18:6a4db94011d3 1728 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
sahilmgandhi 18:6a4db94011d3 1729 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
sahilmgandhi 18:6a4db94011d3 1730 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
sahilmgandhi 18:6a4db94011d3 1731 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
sahilmgandhi 18:6a4db94011d3 1732 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
sahilmgandhi 18:6a4db94011d3 1733 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
sahilmgandhi 18:6a4db94011d3 1734 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
sahilmgandhi 18:6a4db94011d3 1735 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
sahilmgandhi 18:6a4db94011d3 1736 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
sahilmgandhi 18:6a4db94011d3 1737 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
sahilmgandhi 18:6a4db94011d3 1738 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
sahilmgandhi 18:6a4db94011d3 1739 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
sahilmgandhi 18:6a4db94011d3 1740 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
sahilmgandhi 18:6a4db94011d3 1741 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
sahilmgandhi 18:6a4db94011d3 1742 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 1743 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 1744 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
sahilmgandhi 18:6a4db94011d3 1745 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
sahilmgandhi 18:6a4db94011d3 1746 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 1747 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
sahilmgandhi 18:6a4db94011d3 1748 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
sahilmgandhi 18:6a4db94011d3 1749 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
sahilmgandhi 18:6a4db94011d3 1750 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
sahilmgandhi 18:6a4db94011d3 1751 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
sahilmgandhi 18:6a4db94011d3 1752 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
sahilmgandhi 18:6a4db94011d3 1753 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
sahilmgandhi 18:6a4db94011d3 1754 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 1755 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 1756 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
sahilmgandhi 18:6a4db94011d3 1757 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
sahilmgandhi 18:6a4db94011d3 1758
sahilmgandhi 18:6a4db94011d3 1759 #if defined (STM32F4)
sahilmgandhi 18:6a4db94011d3 1760 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
sahilmgandhi 18:6a4db94011d3 1761 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
sahilmgandhi 18:6a4db94011d3 1762 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
sahilmgandhi 18:6a4db94011d3 1763 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
sahilmgandhi 18:6a4db94011d3 1764 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
sahilmgandhi 18:6a4db94011d3 1765 #else
sahilmgandhi 18:6a4db94011d3 1766 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
sahilmgandhi 18:6a4db94011d3 1767 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
sahilmgandhi 18:6a4db94011d3 1768 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
sahilmgandhi 18:6a4db94011d3 1769 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
sahilmgandhi 18:6a4db94011d3 1770 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
sahilmgandhi 18:6a4db94011d3 1771 #endif /* STM32F4 */
sahilmgandhi 18:6a4db94011d3 1772 /**
sahilmgandhi 18:6a4db94011d3 1773 * @}
sahilmgandhi 18:6a4db94011d3 1774 */
sahilmgandhi 18:6a4db94011d3 1775
sahilmgandhi 18:6a4db94011d3 1776
sahilmgandhi 18:6a4db94011d3 1777 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 1778 * @{
sahilmgandhi 18:6a4db94011d3 1779 */
sahilmgandhi 18:6a4db94011d3 1780
sahilmgandhi 18:6a4db94011d3 1781 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
sahilmgandhi 18:6a4db94011d3 1782 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
sahilmgandhi 18:6a4db94011d3 1783
sahilmgandhi 18:6a4db94011d3 1784 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
sahilmgandhi 18:6a4db94011d3 1785 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
sahilmgandhi 18:6a4db94011d3 1786
sahilmgandhi 18:6a4db94011d3 1787 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1788 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1789 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1790 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1791 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1792 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1793 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1794 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1795 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1796 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1797 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1798 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1799 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1800 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1801 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1802 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1803 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1804 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1805 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1806 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1807 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1808 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1809 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1810 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1811 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1812 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1813 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1814 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1815 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1816 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1817 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1818 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1819 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1820 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1821 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1822 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1823 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1824 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1825 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1826 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1827 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1828 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1829 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1830 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1831 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1832 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1833 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1834 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1835 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1836 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1837 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1838 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1839 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1840 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1841 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1842 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1843 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1844 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1845 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1846 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1847 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1848 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1849 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1850 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1851 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1852 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1853 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1854 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1855 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1856 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1857 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1858 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1859 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1860 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1861 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1862 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1863 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1864 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1865 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1866 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1867 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1868 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1869 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1870 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1871 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1872 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1873 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1874 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1875 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1876 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1877 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1878 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1879 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1880 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1881 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1882 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1883 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1884 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1885 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1886 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1887 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1888 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1889 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1890 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1891 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1892 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1893 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1894 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1895 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1896 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1897 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1898 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1899 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1900 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1901 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1902 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1903 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1904 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1905 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1906 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1907 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1908 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1909 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1910 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1911 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1912 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1913 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1914 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1915 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1916 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1917 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1918 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1919 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1920 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1921 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1922 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1923 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1924 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1925 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1926 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1927 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1928 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1929 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1930 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1931 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1932 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1933 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1934 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1935 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1936 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1937 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1938 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1939 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1940 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1941 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1942 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1943 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1944 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1945 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1946 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1947 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1948 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1949 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1950 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1951 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1952 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1953 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1954 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1955 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1956 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1957 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1958 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1959 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1960 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1961 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1962 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1963 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1964 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1965 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1966 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1967 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1968 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1969 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1970 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1971 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1972 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1973 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1974 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1975 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1976 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1977 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1978 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1979 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1980 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1981 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1982 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1983 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1984 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1985 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1986 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1987 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1988 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1989 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1990 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1991 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1992 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1993 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 1994 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 1995 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 1996 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 1997 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 1998 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 1999 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2000 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2001 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2002 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2003 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2004 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2005 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2006 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2007 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2008 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2009 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2010 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2011 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2012 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2013 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2014 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2015 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2016 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2017 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2018 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2019 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2020 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2021 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2022 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2023 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2024 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2025 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2026 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2027 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2028 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2029 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2030 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2031 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2032 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2033 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2034 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2035 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2036 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2037 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2038 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2039 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2040 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2041 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2042 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2043 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2044 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2045 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2046 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2047 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2048 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2049 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2050 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2051 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2052 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2053 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2054 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2055 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2056 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2057 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2058 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2059 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2060 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2061 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2062 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2063 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2064 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2065 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2066 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2067 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2068 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2069 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2070 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2071 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2072 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2073 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2074 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2075 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2076 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2077 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2078 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2079 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2080 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2081 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2082 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2083 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2084 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2085 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2086 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2087 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2088 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2089 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2090 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2091 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2092 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2093 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2094 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2095 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2096 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2097 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2098 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2099 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2100 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2101 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2102 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2103 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2104 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2105 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2106 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2107 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2108 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2109 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2110 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2111 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2112 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2113 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2114 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2115 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2116 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2117 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2118 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2119 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2120 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2121 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2122 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2123 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2124 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2125 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2126 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2127 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2128 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2129 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2130 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2131 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2132 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2133 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2134 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2135 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2136 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2137 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2138 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2139 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2140 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2141 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2142 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2143 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2144 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2145 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2146 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2147 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2148 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2149 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2150 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2151 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2152 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2153 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2154 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2155 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2156 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2157 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2158 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2159 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2160 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2161 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2162 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2163 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2164 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2165 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2166 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2167 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2168 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2169 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2170 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2171 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2172 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2173 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2174 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2175 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2176 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2177 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2178 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2179 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2180 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2181 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2182 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2183 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2184 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2185 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2186 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2187 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2188 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2189 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2190 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2191 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2192 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2193 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2194 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2195 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2196 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2197 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2198 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2199 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2200 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2201 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2202 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2203 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2204 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2205 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2206 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2207 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2208 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2209 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2210 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2211 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2212 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2213 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2214 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2215 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2216 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2217 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2218 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2219 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2220 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2221 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2222 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2223 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2224 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2225 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2226 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2227 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2228 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2229 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2230 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2231 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2232 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2233 #define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2234 #define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2235 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2236 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2237 #define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2238 #define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2239 #define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2240 #define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2241 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2242 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2243 #define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2244 #define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2245 #define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2246 #define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2247 #define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2248 #define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2249 #define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2250 #define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2251 #define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2252 #define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2253 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2254 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2255 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2256 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2257 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2258 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2259 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2260 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2261 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2262 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2263 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2264 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2265 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2266 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2267 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2268 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2269 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2270 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2271 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2272 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2273 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2274 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2275 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2276 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2277 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2278 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2279 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2280 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2281 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2282 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2283 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2284 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2285 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
sahilmgandhi 18:6a4db94011d3 2286 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
sahilmgandhi 18:6a4db94011d3 2287
sahilmgandhi 18:6a4db94011d3 2288 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2289 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2290 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2291 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2292 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2293 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2294 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2295 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2296 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2297 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2298 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2299 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2300 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2301 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2302 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2303 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2304 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2305 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2306 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2307 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2308 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2309 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2310 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2311 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2312 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2313 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2314 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2315 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2316 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2317 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2318 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2319 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2320 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2321 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2322 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2323 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2324 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2325 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2326 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2327 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2328 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2329 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2330 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2331 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2332 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2333 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2334 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2335 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2336 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2337 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2338 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2339 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2340 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2341 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2342 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2343 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2344 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2345 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2346 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2347 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2348 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2349 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2350 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2351 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2352 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2353 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2354 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2355 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2356 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2357 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2358 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2359 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2360 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2361 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2362 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2363 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2364 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2365 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2366 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2367 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2368 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2369 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2370 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2371 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2372 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2373 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2374 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2375 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2376 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2377 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2378 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2379 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2380 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2381 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2382 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2383 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2384 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2385 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2386 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2387 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2388 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2389 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2390 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2391 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2392 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2393 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2394 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2395 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2396 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2397 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2398 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2399 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2400 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2401 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2402 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2403 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2404 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
sahilmgandhi 18:6a4db94011d3 2405 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
sahilmgandhi 18:6a4db94011d3 2406 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2407 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2408 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2409 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2410 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
sahilmgandhi 18:6a4db94011d3 2411 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
sahilmgandhi 18:6a4db94011d3 2412 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2413 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2414 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2415 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2416 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2417 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2418 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2419 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2420 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2421 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2422 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2423 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2424 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2425 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2426 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2427 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2428 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2429 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2430 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2431 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2432 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2433 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2434 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2435 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2436
sahilmgandhi 18:6a4db94011d3 2437 /* alias define maintained for legacy */
sahilmgandhi 18:6a4db94011d3 2438 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2439 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2440
sahilmgandhi 18:6a4db94011d3 2441 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2442 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2443 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2444 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2445 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2446 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2447 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2448 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2449 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2450 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2451 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2452 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2453 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2454 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2455 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2456 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2457 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2458 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2459 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2460 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2461 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2462 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2463
sahilmgandhi 18:6a4db94011d3 2464 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2465 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2466 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2467 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2468 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2469 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2470 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2471 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2472 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2473 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2474 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2475 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2476 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2477 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2478 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2479 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2480 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2481 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2482 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2483 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2484 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2485 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2486
sahilmgandhi 18:6a4db94011d3 2487 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2488 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2489 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2490 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2491 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2492 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2493 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2494 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2495 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2496 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2497 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2498 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2499 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2500 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2501 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2502 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2503 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2504 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2505 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2506 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2507 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2508 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2509 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2510 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2511 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2512 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2513 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2514 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2515 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2516 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2517 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2518 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2519 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2520 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2521 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2522 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2523 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2524 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2525 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2526 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2527 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2528 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2529 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2530 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2531 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2532 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2533 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2534 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2535 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2536 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2537 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2538 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2539 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2540 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2541 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2542 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2543 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2544 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2545 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2546 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2547 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2548 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2549 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2550 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2551 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2552 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2553 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2554 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2555 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2556 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2557 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2558 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2559 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2560 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2561 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2562 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2563 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2564 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2565 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2566 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2567 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2568 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2569 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2570 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2571 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2572 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2573 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2574 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2575 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2576 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2577 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2578 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2579 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2580 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2581 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2582 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2583 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2584 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2585 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2586 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2587 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2588 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2589 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2590 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2591 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2592 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2593 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2594 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2595 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2596 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2597 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2598 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2599 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2600 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2601 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2602 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2603
sahilmgandhi 18:6a4db94011d3 2604 #if defined(STM32F4)
sahilmgandhi 18:6a4db94011d3 2605 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2606 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2607 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2608 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2609 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2610 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2611 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2612 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2613 #define Sdmmc1ClockSelection SdioClockSelection
sahilmgandhi 18:6a4db94011d3 2614 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
sahilmgandhi 18:6a4db94011d3 2615 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
sahilmgandhi 18:6a4db94011d3 2616 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
sahilmgandhi 18:6a4db94011d3 2617 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
sahilmgandhi 18:6a4db94011d3 2618 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
sahilmgandhi 18:6a4db94011d3 2619 #endif
sahilmgandhi 18:6a4db94011d3 2620
sahilmgandhi 18:6a4db94011d3 2621 #if defined(STM32F7) || defined(STM32L4)
sahilmgandhi 18:6a4db94011d3 2622 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2623 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2624 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2625 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2626 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2627 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2628 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2629 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2630 #define SdioClockSelection Sdmmc1ClockSelection
sahilmgandhi 18:6a4db94011d3 2631 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
sahilmgandhi 18:6a4db94011d3 2632 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
sahilmgandhi 18:6a4db94011d3 2633 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
sahilmgandhi 18:6a4db94011d3 2634 #endif
sahilmgandhi 18:6a4db94011d3 2635
sahilmgandhi 18:6a4db94011d3 2636 #if defined(STM32F7)
sahilmgandhi 18:6a4db94011d3 2637 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
sahilmgandhi 18:6a4db94011d3 2638 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
sahilmgandhi 18:6a4db94011d3 2639 #endif
sahilmgandhi 18:6a4db94011d3 2640
sahilmgandhi 18:6a4db94011d3 2641 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
sahilmgandhi 18:6a4db94011d3 2642 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
sahilmgandhi 18:6a4db94011d3 2643
sahilmgandhi 18:6a4db94011d3 2644 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
sahilmgandhi 18:6a4db94011d3 2645
sahilmgandhi 18:6a4db94011d3 2646 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
sahilmgandhi 18:6a4db94011d3 2647 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
sahilmgandhi 18:6a4db94011d3 2648 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
sahilmgandhi 18:6a4db94011d3 2649 #define IS_RCC_HCLK_DIV IS_RCC_PCLK
sahilmgandhi 18:6a4db94011d3 2650 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
sahilmgandhi 18:6a4db94011d3 2651
sahilmgandhi 18:6a4db94011d3 2652 #define RCC_IT_HSI14 RCC_IT_HSI14RDY
sahilmgandhi 18:6a4db94011d3 2653
sahilmgandhi 18:6a4db94011d3 2654 #if defined(STM32L0)
sahilmgandhi 18:6a4db94011d3 2655 #define RCC_IT_LSECSS RCC_IT_CSSLSE
sahilmgandhi 18:6a4db94011d3 2656 #define RCC_IT_CSS RCC_IT_CSSHSE
sahilmgandhi 18:6a4db94011d3 2657 #endif
sahilmgandhi 18:6a4db94011d3 2658
sahilmgandhi 18:6a4db94011d3 2659 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
sahilmgandhi 18:6a4db94011d3 2660 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
sahilmgandhi 18:6a4db94011d3 2661 #define RCC_MCO_NODIV RCC_MCODIV_1
sahilmgandhi 18:6a4db94011d3 2662 #define RCC_MCO_DIV1 RCC_MCODIV_1
sahilmgandhi 18:6a4db94011d3 2663 #define RCC_MCO_DIV2 RCC_MCODIV_2
sahilmgandhi 18:6a4db94011d3 2664 #define RCC_MCO_DIV4 RCC_MCODIV_4
sahilmgandhi 18:6a4db94011d3 2665 #define RCC_MCO_DIV8 RCC_MCODIV_8
sahilmgandhi 18:6a4db94011d3 2666 #define RCC_MCO_DIV16 RCC_MCODIV_16
sahilmgandhi 18:6a4db94011d3 2667 #define RCC_MCO_DIV32 RCC_MCODIV_32
sahilmgandhi 18:6a4db94011d3 2668 #define RCC_MCO_DIV64 RCC_MCODIV_64
sahilmgandhi 18:6a4db94011d3 2669 #define RCC_MCO_DIV128 RCC_MCODIV_128
sahilmgandhi 18:6a4db94011d3 2670 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
sahilmgandhi 18:6a4db94011d3 2671 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
sahilmgandhi 18:6a4db94011d3 2672 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
sahilmgandhi 18:6a4db94011d3 2673 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
sahilmgandhi 18:6a4db94011d3 2674 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
sahilmgandhi 18:6a4db94011d3 2675 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
sahilmgandhi 18:6a4db94011d3 2676 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
sahilmgandhi 18:6a4db94011d3 2677 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
sahilmgandhi 18:6a4db94011d3 2678 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
sahilmgandhi 18:6a4db94011d3 2679 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
sahilmgandhi 18:6a4db94011d3 2680 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
sahilmgandhi 18:6a4db94011d3 2681
sahilmgandhi 18:6a4db94011d3 2682 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
sahilmgandhi 18:6a4db94011d3 2683
sahilmgandhi 18:6a4db94011d3 2684 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
sahilmgandhi 18:6a4db94011d3 2685 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
sahilmgandhi 18:6a4db94011d3 2686 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
sahilmgandhi 18:6a4db94011d3 2687 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
sahilmgandhi 18:6a4db94011d3 2688 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
sahilmgandhi 18:6a4db94011d3 2689 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
sahilmgandhi 18:6a4db94011d3 2690 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
sahilmgandhi 18:6a4db94011d3 2691 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
sahilmgandhi 18:6a4db94011d3 2692
sahilmgandhi 18:6a4db94011d3 2693 #define HSION_BitNumber RCC_HSION_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2694 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2695 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2696 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2697 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2698 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2699 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2700 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2701 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2702 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2703 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2704 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2705 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2706 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2707 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2708 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2709 #define LSION_BitNumber RCC_LSION_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2710 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2711 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2712 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2713 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2714 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2715 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2716 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2717 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2718 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
sahilmgandhi 18:6a4db94011d3 2719 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
sahilmgandhi 18:6a4db94011d3 2720 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
sahilmgandhi 18:6a4db94011d3 2721 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
sahilmgandhi 18:6a4db94011d3 2722 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
sahilmgandhi 18:6a4db94011d3 2723 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
sahilmgandhi 18:6a4db94011d3 2724 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
sahilmgandhi 18:6a4db94011d3 2725
sahilmgandhi 18:6a4db94011d3 2726 #define CR_HSION_BB RCC_CR_HSION_BB
sahilmgandhi 18:6a4db94011d3 2727 #define CR_CSSON_BB RCC_CR_CSSON_BB
sahilmgandhi 18:6a4db94011d3 2728 #define CR_PLLON_BB RCC_CR_PLLON_BB
sahilmgandhi 18:6a4db94011d3 2729 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
sahilmgandhi 18:6a4db94011d3 2730 #define CR_MSION_BB RCC_CR_MSION_BB
sahilmgandhi 18:6a4db94011d3 2731 #define CSR_LSION_BB RCC_CSR_LSION_BB
sahilmgandhi 18:6a4db94011d3 2732 #define CSR_LSEON_BB RCC_CSR_LSEON_BB
sahilmgandhi 18:6a4db94011d3 2733 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
sahilmgandhi 18:6a4db94011d3 2734 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
sahilmgandhi 18:6a4db94011d3 2735 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
sahilmgandhi 18:6a4db94011d3 2736 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
sahilmgandhi 18:6a4db94011d3 2737 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
sahilmgandhi 18:6a4db94011d3 2738 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
sahilmgandhi 18:6a4db94011d3 2739 #define CR_HSEON_BB RCC_CR_HSEON_BB
sahilmgandhi 18:6a4db94011d3 2740 #define CSR_RMVF_BB RCC_CSR_RMVF_BB
sahilmgandhi 18:6a4db94011d3 2741 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
sahilmgandhi 18:6a4db94011d3 2742 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
sahilmgandhi 18:6a4db94011d3 2743
sahilmgandhi 18:6a4db94011d3 2744 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
sahilmgandhi 18:6a4db94011d3 2745 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
sahilmgandhi 18:6a4db94011d3 2746 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
sahilmgandhi 18:6a4db94011d3 2747 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
sahilmgandhi 18:6a4db94011d3 2748 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
sahilmgandhi 18:6a4db94011d3 2749
sahilmgandhi 18:6a4db94011d3 2750 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
sahilmgandhi 18:6a4db94011d3 2751
sahilmgandhi 18:6a4db94011d3 2752 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
sahilmgandhi 18:6a4db94011d3 2753 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
sahilmgandhi 18:6a4db94011d3 2754
sahilmgandhi 18:6a4db94011d3 2755 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
sahilmgandhi 18:6a4db94011d3 2756 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
sahilmgandhi 18:6a4db94011d3 2757 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
sahilmgandhi 18:6a4db94011d3 2758 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
sahilmgandhi 18:6a4db94011d3 2759 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
sahilmgandhi 18:6a4db94011d3 2760 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
sahilmgandhi 18:6a4db94011d3 2761
sahilmgandhi 18:6a4db94011d3 2762 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
sahilmgandhi 18:6a4db94011d3 2763 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
sahilmgandhi 18:6a4db94011d3 2764 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
sahilmgandhi 18:6a4db94011d3 2765 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
sahilmgandhi 18:6a4db94011d3 2766 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
sahilmgandhi 18:6a4db94011d3 2767 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
sahilmgandhi 18:6a4db94011d3 2768 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
sahilmgandhi 18:6a4db94011d3 2769 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
sahilmgandhi 18:6a4db94011d3 2770 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
sahilmgandhi 18:6a4db94011d3 2771 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
sahilmgandhi 18:6a4db94011d3 2772 #define DfsdmClockSelection Dfsdm1ClockSelection
sahilmgandhi 18:6a4db94011d3 2773 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
sahilmgandhi 18:6a4db94011d3 2774 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
sahilmgandhi 18:6a4db94011d3 2775 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
sahilmgandhi 18:6a4db94011d3 2776 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
sahilmgandhi 18:6a4db94011d3 2777 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
sahilmgandhi 18:6a4db94011d3 2778
sahilmgandhi 18:6a4db94011d3 2779 /**
sahilmgandhi 18:6a4db94011d3 2780 * @}
sahilmgandhi 18:6a4db94011d3 2781 */
sahilmgandhi 18:6a4db94011d3 2782
sahilmgandhi 18:6a4db94011d3 2783 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 2784 * @{
sahilmgandhi 18:6a4db94011d3 2785 */
sahilmgandhi 18:6a4db94011d3 2786 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
sahilmgandhi 18:6a4db94011d3 2787
sahilmgandhi 18:6a4db94011d3 2788 /**
sahilmgandhi 18:6a4db94011d3 2789 * @}
sahilmgandhi 18:6a4db94011d3 2790 */
sahilmgandhi 18:6a4db94011d3 2791
sahilmgandhi 18:6a4db94011d3 2792 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 2793 * @{
sahilmgandhi 18:6a4db94011d3 2794 */
sahilmgandhi 18:6a4db94011d3 2795
sahilmgandhi 18:6a4db94011d3 2796 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
sahilmgandhi 18:6a4db94011d3 2797 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
sahilmgandhi 18:6a4db94011d3 2798 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
sahilmgandhi 18:6a4db94011d3 2799
sahilmgandhi 18:6a4db94011d3 2800 #if defined (STM32F1)
sahilmgandhi 18:6a4db94011d3 2801 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
sahilmgandhi 18:6a4db94011d3 2802
sahilmgandhi 18:6a4db94011d3 2803 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
sahilmgandhi 18:6a4db94011d3 2804
sahilmgandhi 18:6a4db94011d3 2805 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
sahilmgandhi 18:6a4db94011d3 2806
sahilmgandhi 18:6a4db94011d3 2807 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
sahilmgandhi 18:6a4db94011d3 2808
sahilmgandhi 18:6a4db94011d3 2809 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
sahilmgandhi 18:6a4db94011d3 2810 #else
sahilmgandhi 18:6a4db94011d3 2811 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 2812 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
sahilmgandhi 18:6a4db94011d3 2813 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
sahilmgandhi 18:6a4db94011d3 2814 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 2815 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 2816 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
sahilmgandhi 18:6a4db94011d3 2817 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 2818 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
sahilmgandhi 18:6a4db94011d3 2819 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
sahilmgandhi 18:6a4db94011d3 2820 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 2821 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
sahilmgandhi 18:6a4db94011d3 2822 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
sahilmgandhi 18:6a4db94011d3 2823 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
sahilmgandhi 18:6a4db94011d3 2824 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
sahilmgandhi 18:6a4db94011d3 2825 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
sahilmgandhi 18:6a4db94011d3 2826 #endif /* STM32F1 */
sahilmgandhi 18:6a4db94011d3 2827
sahilmgandhi 18:6a4db94011d3 2828 #define IS_ALARM IS_RTC_ALARM
sahilmgandhi 18:6a4db94011d3 2829 #define IS_ALARM_MASK IS_RTC_ALARM_MASK
sahilmgandhi 18:6a4db94011d3 2830 #define IS_TAMPER IS_RTC_TAMPER
sahilmgandhi 18:6a4db94011d3 2831 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
sahilmgandhi 18:6a4db94011d3 2832 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
sahilmgandhi 18:6a4db94011d3 2833 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
sahilmgandhi 18:6a4db94011d3 2834 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
sahilmgandhi 18:6a4db94011d3 2835 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
sahilmgandhi 18:6a4db94011d3 2836 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
sahilmgandhi 18:6a4db94011d3 2837 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
sahilmgandhi 18:6a4db94011d3 2838 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
sahilmgandhi 18:6a4db94011d3 2839 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
sahilmgandhi 18:6a4db94011d3 2840 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
sahilmgandhi 18:6a4db94011d3 2841 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
sahilmgandhi 18:6a4db94011d3 2842
sahilmgandhi 18:6a4db94011d3 2843 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
sahilmgandhi 18:6a4db94011d3 2844 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
sahilmgandhi 18:6a4db94011d3 2845
sahilmgandhi 18:6a4db94011d3 2846 /**
sahilmgandhi 18:6a4db94011d3 2847 * @}
sahilmgandhi 18:6a4db94011d3 2848 */
sahilmgandhi 18:6a4db94011d3 2849
sahilmgandhi 18:6a4db94011d3 2850 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 2851 * @{
sahilmgandhi 18:6a4db94011d3 2852 */
sahilmgandhi 18:6a4db94011d3 2853
sahilmgandhi 18:6a4db94011d3 2854 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
sahilmgandhi 18:6a4db94011d3 2855 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
sahilmgandhi 18:6a4db94011d3 2856
sahilmgandhi 18:6a4db94011d3 2857 #if defined(STM32F4)
sahilmgandhi 18:6a4db94011d3 2858 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
sahilmgandhi 18:6a4db94011d3 2859 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
sahilmgandhi 18:6a4db94011d3 2860 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
sahilmgandhi 18:6a4db94011d3 2861 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
sahilmgandhi 18:6a4db94011d3 2862 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
sahilmgandhi 18:6a4db94011d3 2863 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
sahilmgandhi 18:6a4db94011d3 2864 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
sahilmgandhi 18:6a4db94011d3 2865 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
sahilmgandhi 18:6a4db94011d3 2866 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
sahilmgandhi 18:6a4db94011d3 2867 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
sahilmgandhi 18:6a4db94011d3 2868 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
sahilmgandhi 18:6a4db94011d3 2869 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
sahilmgandhi 18:6a4db94011d3 2870 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
sahilmgandhi 18:6a4db94011d3 2871 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
sahilmgandhi 18:6a4db94011d3 2872 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
sahilmgandhi 18:6a4db94011d3 2873 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
sahilmgandhi 18:6a4db94011d3 2874 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
sahilmgandhi 18:6a4db94011d3 2875 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
sahilmgandhi 18:6a4db94011d3 2876 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
sahilmgandhi 18:6a4db94011d3 2877 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
sahilmgandhi 18:6a4db94011d3 2878 /* alias CMSIS */
sahilmgandhi 18:6a4db94011d3 2879 #define SDMMC1_IRQn SDIO_IRQn
sahilmgandhi 18:6a4db94011d3 2880 #define SDMMC1_IRQHandler SDIO_IRQHandler
sahilmgandhi 18:6a4db94011d3 2881 #endif
sahilmgandhi 18:6a4db94011d3 2882
sahilmgandhi 18:6a4db94011d3 2883 #if defined(STM32F7) || defined(STM32L4)
sahilmgandhi 18:6a4db94011d3 2884 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED
sahilmgandhi 18:6a4db94011d3 2885 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
sahilmgandhi 18:6a4db94011d3 2886 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
sahilmgandhi 18:6a4db94011d3 2887 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
sahilmgandhi 18:6a4db94011d3 2888 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
sahilmgandhi 18:6a4db94011d3 2889 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
sahilmgandhi 18:6a4db94011d3 2890 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
sahilmgandhi 18:6a4db94011d3 2891 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
sahilmgandhi 18:6a4db94011d3 2892 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
sahilmgandhi 18:6a4db94011d3 2893 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
sahilmgandhi 18:6a4db94011d3 2894 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
sahilmgandhi 18:6a4db94011d3 2895 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
sahilmgandhi 18:6a4db94011d3 2896 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
sahilmgandhi 18:6a4db94011d3 2897 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
sahilmgandhi 18:6a4db94011d3 2898 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
sahilmgandhi 18:6a4db94011d3 2899 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
sahilmgandhi 18:6a4db94011d3 2900 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
sahilmgandhi 18:6a4db94011d3 2901 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
sahilmgandhi 18:6a4db94011d3 2902 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
sahilmgandhi 18:6a4db94011d3 2903 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
sahilmgandhi 18:6a4db94011d3 2904 /* alias CMSIS for compatibilities */
sahilmgandhi 18:6a4db94011d3 2905 #define SDIO_IRQn SDMMC1_IRQn
sahilmgandhi 18:6a4db94011d3 2906 #define SDIO_IRQHandler SDMMC1_IRQHandler
sahilmgandhi 18:6a4db94011d3 2907 #endif
sahilmgandhi 18:6a4db94011d3 2908 /**
sahilmgandhi 18:6a4db94011d3 2909 * @}
sahilmgandhi 18:6a4db94011d3 2910 */
sahilmgandhi 18:6a4db94011d3 2911
sahilmgandhi 18:6a4db94011d3 2912 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 2913 * @{
sahilmgandhi 18:6a4db94011d3 2914 */
sahilmgandhi 18:6a4db94011d3 2915
sahilmgandhi 18:6a4db94011d3 2916 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
sahilmgandhi 18:6a4db94011d3 2917 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
sahilmgandhi 18:6a4db94011d3 2918 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
sahilmgandhi 18:6a4db94011d3 2919 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
sahilmgandhi 18:6a4db94011d3 2920 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
sahilmgandhi 18:6a4db94011d3 2921 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
sahilmgandhi 18:6a4db94011d3 2922
sahilmgandhi 18:6a4db94011d3 2923 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
sahilmgandhi 18:6a4db94011d3 2924 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
sahilmgandhi 18:6a4db94011d3 2925
sahilmgandhi 18:6a4db94011d3 2926 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
sahilmgandhi 18:6a4db94011d3 2927
sahilmgandhi 18:6a4db94011d3 2928 /**
sahilmgandhi 18:6a4db94011d3 2929 * @}
sahilmgandhi 18:6a4db94011d3 2930 */
sahilmgandhi 18:6a4db94011d3 2931
sahilmgandhi 18:6a4db94011d3 2932 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 2933 * @{
sahilmgandhi 18:6a4db94011d3 2934 */
sahilmgandhi 18:6a4db94011d3 2935 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
sahilmgandhi 18:6a4db94011d3 2936 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
sahilmgandhi 18:6a4db94011d3 2937 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
sahilmgandhi 18:6a4db94011d3 2938 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
sahilmgandhi 18:6a4db94011d3 2939 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
sahilmgandhi 18:6a4db94011d3 2940 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
sahilmgandhi 18:6a4db94011d3 2941 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
sahilmgandhi 18:6a4db94011d3 2942 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
sahilmgandhi 18:6a4db94011d3 2943 /**
sahilmgandhi 18:6a4db94011d3 2944 * @}
sahilmgandhi 18:6a4db94011d3 2945 */
sahilmgandhi 18:6a4db94011d3 2946
sahilmgandhi 18:6a4db94011d3 2947 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 2948 * @{
sahilmgandhi 18:6a4db94011d3 2949 */
sahilmgandhi 18:6a4db94011d3 2950
sahilmgandhi 18:6a4db94011d3 2951 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
sahilmgandhi 18:6a4db94011d3 2952 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
sahilmgandhi 18:6a4db94011d3 2953 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
sahilmgandhi 18:6a4db94011d3 2954
sahilmgandhi 18:6a4db94011d3 2955 /**
sahilmgandhi 18:6a4db94011d3 2956 * @}
sahilmgandhi 18:6a4db94011d3 2957 */
sahilmgandhi 18:6a4db94011d3 2958
sahilmgandhi 18:6a4db94011d3 2959 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 2960 * @{
sahilmgandhi 18:6a4db94011d3 2961 */
sahilmgandhi 18:6a4db94011d3 2962
sahilmgandhi 18:6a4db94011d3 2963 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
sahilmgandhi 18:6a4db94011d3 2964 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
sahilmgandhi 18:6a4db94011d3 2965 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
sahilmgandhi 18:6a4db94011d3 2966 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
sahilmgandhi 18:6a4db94011d3 2967
sahilmgandhi 18:6a4db94011d3 2968 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
sahilmgandhi 18:6a4db94011d3 2969
sahilmgandhi 18:6a4db94011d3 2970 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
sahilmgandhi 18:6a4db94011d3 2971 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
sahilmgandhi 18:6a4db94011d3 2972
sahilmgandhi 18:6a4db94011d3 2973 /**
sahilmgandhi 18:6a4db94011d3 2974 * @}
sahilmgandhi 18:6a4db94011d3 2975 */
sahilmgandhi 18:6a4db94011d3 2976
sahilmgandhi 18:6a4db94011d3 2977
sahilmgandhi 18:6a4db94011d3 2978 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 2979 * @{
sahilmgandhi 18:6a4db94011d3 2980 */
sahilmgandhi 18:6a4db94011d3 2981
sahilmgandhi 18:6a4db94011d3 2982 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
sahilmgandhi 18:6a4db94011d3 2983 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
sahilmgandhi 18:6a4db94011d3 2984 #define __USART_ENABLE __HAL_USART_ENABLE
sahilmgandhi 18:6a4db94011d3 2985 #define __USART_DISABLE __HAL_USART_DISABLE
sahilmgandhi 18:6a4db94011d3 2986
sahilmgandhi 18:6a4db94011d3 2987 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
sahilmgandhi 18:6a4db94011d3 2988 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
sahilmgandhi 18:6a4db94011d3 2989
sahilmgandhi 18:6a4db94011d3 2990 /**
sahilmgandhi 18:6a4db94011d3 2991 * @}
sahilmgandhi 18:6a4db94011d3 2992 */
sahilmgandhi 18:6a4db94011d3 2993
sahilmgandhi 18:6a4db94011d3 2994 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 2995 * @{
sahilmgandhi 18:6a4db94011d3 2996 */
sahilmgandhi 18:6a4db94011d3 2997 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
sahilmgandhi 18:6a4db94011d3 2998
sahilmgandhi 18:6a4db94011d3 2999 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
sahilmgandhi 18:6a4db94011d3 3000 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 3001 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 3002 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
sahilmgandhi 18:6a4db94011d3 3003
sahilmgandhi 18:6a4db94011d3 3004 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
sahilmgandhi 18:6a4db94011d3 3005 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 3006 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 3007 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
sahilmgandhi 18:6a4db94011d3 3008
sahilmgandhi 18:6a4db94011d3 3009 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
sahilmgandhi 18:6a4db94011d3 3010 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
sahilmgandhi 18:6a4db94011d3 3011 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
sahilmgandhi 18:6a4db94011d3 3012 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
sahilmgandhi 18:6a4db94011d3 3013 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
sahilmgandhi 18:6a4db94011d3 3014 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 3015 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 3016
sahilmgandhi 18:6a4db94011d3 3017 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
sahilmgandhi 18:6a4db94011d3 3018 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
sahilmgandhi 18:6a4db94011d3 3019 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
sahilmgandhi 18:6a4db94011d3 3020 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
sahilmgandhi 18:6a4db94011d3 3021 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
sahilmgandhi 18:6a4db94011d3 3022 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 3023 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 3024 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
sahilmgandhi 18:6a4db94011d3 3025
sahilmgandhi 18:6a4db94011d3 3026 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
sahilmgandhi 18:6a4db94011d3 3027 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
sahilmgandhi 18:6a4db94011d3 3028 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
sahilmgandhi 18:6a4db94011d3 3029 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
sahilmgandhi 18:6a4db94011d3 3030 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
sahilmgandhi 18:6a4db94011d3 3031 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 3032 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
sahilmgandhi 18:6a4db94011d3 3033 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
sahilmgandhi 18:6a4db94011d3 3034
sahilmgandhi 18:6a4db94011d3 3035 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
sahilmgandhi 18:6a4db94011d3 3036 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
sahilmgandhi 18:6a4db94011d3 3037
sahilmgandhi 18:6a4db94011d3 3038 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
sahilmgandhi 18:6a4db94011d3 3039 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
sahilmgandhi 18:6a4db94011d3 3040 /**
sahilmgandhi 18:6a4db94011d3 3041 * @}
sahilmgandhi 18:6a4db94011d3 3042 */
sahilmgandhi 18:6a4db94011d3 3043
sahilmgandhi 18:6a4db94011d3 3044 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 3045 * @{
sahilmgandhi 18:6a4db94011d3 3046 */
sahilmgandhi 18:6a4db94011d3 3047 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
sahilmgandhi 18:6a4db94011d3 3048 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
sahilmgandhi 18:6a4db94011d3 3049
sahilmgandhi 18:6a4db94011d3 3050 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
sahilmgandhi 18:6a4db94011d3 3051 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
sahilmgandhi 18:6a4db94011d3 3052
sahilmgandhi 18:6a4db94011d3 3053 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
sahilmgandhi 18:6a4db94011d3 3054
sahilmgandhi 18:6a4db94011d3 3055 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
sahilmgandhi 18:6a4db94011d3 3056 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
sahilmgandhi 18:6a4db94011d3 3057 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
sahilmgandhi 18:6a4db94011d3 3058 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
sahilmgandhi 18:6a4db94011d3 3059 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
sahilmgandhi 18:6a4db94011d3 3060 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
sahilmgandhi 18:6a4db94011d3 3061 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
sahilmgandhi 18:6a4db94011d3 3062 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
sahilmgandhi 18:6a4db94011d3 3063 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
sahilmgandhi 18:6a4db94011d3 3064 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
sahilmgandhi 18:6a4db94011d3 3065 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
sahilmgandhi 18:6a4db94011d3 3066 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
sahilmgandhi 18:6a4db94011d3 3067
sahilmgandhi 18:6a4db94011d3 3068 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
sahilmgandhi 18:6a4db94011d3 3069 /**
sahilmgandhi 18:6a4db94011d3 3070 * @}
sahilmgandhi 18:6a4db94011d3 3071 */
sahilmgandhi 18:6a4db94011d3 3072
sahilmgandhi 18:6a4db94011d3 3073 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 3074 * @{
sahilmgandhi 18:6a4db94011d3 3075 */
sahilmgandhi 18:6a4db94011d3 3076
sahilmgandhi 18:6a4db94011d3 3077 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
sahilmgandhi 18:6a4db94011d3 3078 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
sahilmgandhi 18:6a4db94011d3 3079 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
sahilmgandhi 18:6a4db94011d3 3080 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
sahilmgandhi 18:6a4db94011d3 3081 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
sahilmgandhi 18:6a4db94011d3 3082 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
sahilmgandhi 18:6a4db94011d3 3083 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
sahilmgandhi 18:6a4db94011d3 3084
sahilmgandhi 18:6a4db94011d3 3085 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
sahilmgandhi 18:6a4db94011d3 3086 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
sahilmgandhi 18:6a4db94011d3 3087 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
sahilmgandhi 18:6a4db94011d3 3088 /**
sahilmgandhi 18:6a4db94011d3 3089 * @}
sahilmgandhi 18:6a4db94011d3 3090 */
sahilmgandhi 18:6a4db94011d3 3091
sahilmgandhi 18:6a4db94011d3 3092 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 3093 * @{
sahilmgandhi 18:6a4db94011d3 3094 */
sahilmgandhi 18:6a4db94011d3 3095 #define __HAL_LTDC_LAYER LTDC_LAYER
sahilmgandhi 18:6a4db94011d3 3096 /**
sahilmgandhi 18:6a4db94011d3 3097 * @}
sahilmgandhi 18:6a4db94011d3 3098 */
sahilmgandhi 18:6a4db94011d3 3099
sahilmgandhi 18:6a4db94011d3 3100 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 3101 * @{
sahilmgandhi 18:6a4db94011d3 3102 */
sahilmgandhi 18:6a4db94011d3 3103 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
sahilmgandhi 18:6a4db94011d3 3104 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
sahilmgandhi 18:6a4db94011d3 3105 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
sahilmgandhi 18:6a4db94011d3 3106 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
sahilmgandhi 18:6a4db94011d3 3107 #define SAI_STREOMODE SAI_STEREOMODE
sahilmgandhi 18:6a4db94011d3 3108 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
sahilmgandhi 18:6a4db94011d3 3109 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
sahilmgandhi 18:6a4db94011d3 3110 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
sahilmgandhi 18:6a4db94011d3 3111 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
sahilmgandhi 18:6a4db94011d3 3112 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
sahilmgandhi 18:6a4db94011d3 3113 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
sahilmgandhi 18:6a4db94011d3 3114 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
sahilmgandhi 18:6a4db94011d3 3115 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
sahilmgandhi 18:6a4db94011d3 3116 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
sahilmgandhi 18:6a4db94011d3 3117 /**
sahilmgandhi 18:6a4db94011d3 3118 * @}
sahilmgandhi 18:6a4db94011d3 3119 */
sahilmgandhi 18:6a4db94011d3 3120
sahilmgandhi 18:6a4db94011d3 3121
sahilmgandhi 18:6a4db94011d3 3122 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
sahilmgandhi 18:6a4db94011d3 3123 * @{
sahilmgandhi 18:6a4db94011d3 3124 */
sahilmgandhi 18:6a4db94011d3 3125
sahilmgandhi 18:6a4db94011d3 3126 /**
sahilmgandhi 18:6a4db94011d3 3127 * @}
sahilmgandhi 18:6a4db94011d3 3128 */
sahilmgandhi 18:6a4db94011d3 3129
sahilmgandhi 18:6a4db94011d3 3130 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 3131 }
sahilmgandhi 18:6a4db94011d3 3132 #endif
sahilmgandhi 18:6a4db94011d3 3133
sahilmgandhi 18:6a4db94011d3 3134 #endif /* ___STM32_HAL_LEGACY */
sahilmgandhi 18:6a4db94011d3 3135
sahilmgandhi 18:6a4db94011d3 3136 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
sahilmgandhi 18:6a4db94011d3 3137