MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file Objects.h
sahilmgandhi 18:6a4db94011d3 4 * @brief Implements an assertion.
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 0.1 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2015-11-06 $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup debug
sahilmgandhi 18:6a4db94011d3 28 */
sahilmgandhi 18:6a4db94011d3 29 #ifndef OBJECTS_H_
sahilmgandhi 18:6a4db94011d3 30 #define OBJECTS_H_
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 34 extern "C" {
sahilmgandhi 18:6a4db94011d3 35 #endif
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 #include "gpio_map.h"
sahilmgandhi 18:6a4db94011d3 38 #include "uart_16c550_map.h"
sahilmgandhi 18:6a4db94011d3 39 #include "PinNames.h"
sahilmgandhi 18:6a4db94011d3 40 #include "PortNames.h"
sahilmgandhi 18:6a4db94011d3 41 #include "PeripheralNames.h"
sahilmgandhi 18:6a4db94011d3 42 #include "target_config.h"
sahilmgandhi 18:6a4db94011d3 43 #include "spi.h"
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 typedef enum {
sahilmgandhi 18:6a4db94011d3 46 FlowControlNone_1,
sahilmgandhi 18:6a4db94011d3 47 FlowControlRTS_1,
sahilmgandhi 18:6a4db94011d3 48 FlowControlCTS_1,
sahilmgandhi 18:6a4db94011d3 49 FlowControlRTSCTS_1
sahilmgandhi 18:6a4db94011d3 50 } FlowControl_1;
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 struct serial_s {
sahilmgandhi 18:6a4db94011d3 53 Uart16C550Reg_pt UARTREG;
sahilmgandhi 18:6a4db94011d3 54 FlowControl_1 FlowCtrl;
sahilmgandhi 18:6a4db94011d3 55 IRQn_Type IRQType;
sahilmgandhi 18:6a4db94011d3 56 int index;
sahilmgandhi 18:6a4db94011d3 57 };
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 typedef struct _gpio_t {
sahilmgandhi 18:6a4db94011d3 60 GpioReg_pt GPIOMEMBASE;
sahilmgandhi 18:6a4db94011d3 61 PinName gpioPin;
sahilmgandhi 18:6a4db94011d3 62 uint32_t gpioMask;
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 } gpio_t;
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 /* TODO: This is currently a dummy structure; implementation will be done along
sahilmgandhi 18:6a4db94011d3 68 * with the sleep API implementation
sahilmgandhi 18:6a4db94011d3 69 */
sahilmgandhi 18:6a4db94011d3 70 typedef struct sleep_s {
sahilmgandhi 18:6a4db94011d3 71 uint32_t timeToSleep; /* 0: Use sleep type variable to select low power mode; Noz-zero: Selects sleep type based on timeToSleep duration using table 1. sleep below */
sahilmgandhi 18:6a4db94011d3 72 uint8_t SleepType; /* 0: Sleep; 1: DeepSleep; 2: Coma */
sahilmgandhi 18:6a4db94011d3 73 } sleep_t;
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 /* Table 1. Sleep
sahilmgandhi 18:6a4db94011d3 76 ___________________________________________________________________________________
sahilmgandhi 18:6a4db94011d3 77 | Sleep duration | Sleep Type |
sahilmgandhi 18:6a4db94011d3 78 |-------------------------------------------------------------------|---------------|
sahilmgandhi 18:6a4db94011d3 79 | > Zero AND <= SLEEP_DURATION_SLEEP_MAX | sleep |
sahilmgandhi 18:6a4db94011d3 80 | > SLEEP_DURATION_SLEEP_MAX AND <= SLEEP_DURATION_DEEPSLEEP_MAX | deepsleep |
sahilmgandhi 18:6a4db94011d3 81 | > SLEEP_DURATION_DEEPSLEEP_MAX | coma |
sahilmgandhi 18:6a4db94011d3 82 |___________________________________________________________________|_______________|
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 */
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 struct gpio_irq_s {
sahilmgandhi 18:6a4db94011d3 87 uint32_t pin;
sahilmgandhi 18:6a4db94011d3 88 uint32_t pinMask;
sahilmgandhi 18:6a4db94011d3 89 GpioReg_pt GPIOMEMBASE;
sahilmgandhi 18:6a4db94011d3 90 };
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 typedef struct {
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 /* options to configure the ADC */
sahilmgandhi 18:6a4db94011d3 95 uint8_t interruptConfig; /**< 1= interrupt Enable 0=Interrupt Disable */
sahilmgandhi 18:6a4db94011d3 96 uint8_t PrescaleVal; /**< Prescaler: Sets the converter clock frequency. Fclk = 32 MHz/(prescaler + 1) where prescaler is the value of this register segment. The minimum tested value is 07 (4 MHz clock) */
sahilmgandhi 18:6a4db94011d3 97 uint8_t measurementType; /**< 1= Absolute 0= Differential */
sahilmgandhi 18:6a4db94011d3 98 uint8_t mode; /**< 1= Continuous Conversion 0= Single Shot */
sahilmgandhi 18:6a4db94011d3 99 uint8_t referenceCh; /**< Selects 1 to 8 channels for reference channel */
sahilmgandhi 18:6a4db94011d3 100 uint8_t convCh; /**< Selects 1 or 8 channels to do a conversion on.*/
sahilmgandhi 18:6a4db94011d3 101 uint8_t inputScale; /**< Sets the input scale, 000 ? 1.0, 001 ? 0.6923, 010 ? 0.5294, 011 ? 0.4286, 100 ? 0.3600, 101 ? 0.3103, 110 ? 0.2728, 111 ? 0.2432 */
sahilmgandhi 18:6a4db94011d3 102 uint8_t samplingTime; /**< Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
sahilmgandhi 18:6a4db94011d3 103 uint8_t WarmUpTime; /**< The number of converter clock cycles that the state machine dwells in the warm or warm_meas state */
sahilmgandhi 18:6a4db94011d3 104 uint16_t samplingRate; /**< Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 } analog_config_s;
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 struct analogin_s {
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 analog_config_s *adcConf;
sahilmgandhi 18:6a4db94011d3 111 AdcReg_pt adcReg;
sahilmgandhi 18:6a4db94011d3 112 PinName pin;
sahilmgandhi 18:6a4db94011d3 113 uint8_t pinFlag;
sahilmgandhi 18:6a4db94011d3 114 uint32_t ADC_Offset_Value;
sahilmgandhi 18:6a4db94011d3 115 };
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 struct pwmout_s {
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 PwmReg_pt pwmReg;
sahilmgandhi 18:6a4db94011d3 120 };
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 struct port_s {
sahilmgandhi 18:6a4db94011d3 123 GpioReg_pt GPIOMEMBASE;
sahilmgandhi 18:6a4db94011d3 124 PortName port;
sahilmgandhi 18:6a4db94011d3 125 uint32_t mask;
sahilmgandhi 18:6a4db94011d3 126 };
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 typedef enum {
sahilmgandhi 18:6a4db94011d3 129 littleEndian = 0,
sahilmgandhi 18:6a4db94011d3 130 bigEndian
sahilmgandhi 18:6a4db94011d3 131 } spi_ipc7207_endian_t, *spi_ipc7207_endian_pt;
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 /** Type for the clock polarity. */
sahilmgandhi 18:6a4db94011d3 134 typedef enum {
sahilmgandhi 18:6a4db94011d3 135 activeLow = 0,
sahilmgandhi 18:6a4db94011d3 136 activeHigh
sahilmgandhi 18:6a4db94011d3 137 } spi_clockPolarity_t, *spi_clockPolarity_pt;
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /** Type for the clock phase. */
sahilmgandhi 18:6a4db94011d3 140 typedef enum {
sahilmgandhi 18:6a4db94011d3 141 risingEdge = 0,
sahilmgandhi 18:6a4db94011d3 142 fallingEdge
sahilmgandhi 18:6a4db94011d3 143 } spi_clockPhase_t, *spi_clockPhase_pt;
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 struct spi_s {
sahilmgandhi 18:6a4db94011d3 146 SpiIpc7207Reg_pt membase; /* Register address */
sahilmgandhi 18:6a4db94011d3 147 IRQn_Type irq; /* IRQ number of the IRQ associated to the device. */
sahilmgandhi 18:6a4db94011d3 148 uint8_t irqEnable; /* IRQ enables for 8 IRQ sources:
sahilmgandhi 18:6a4db94011d3 149 * - bit 7 = Receive FIFO Full
sahilmgandhi 18:6a4db94011d3 150 * - bit 6 = Receive FIFO 'Half' Full (watermark level)
sahilmgandhi 18:6a4db94011d3 151 * - bit 5 = Receive FIFO Not Empty
sahilmgandhi 18:6a4db94011d3 152 * - bit 4 = Transmit FIFO Not Full
sahilmgandhi 18:6a4db94011d3 153 * - bit 3 = Transmit FIFO 'Half' Empty (watermark level)
sahilmgandhi 18:6a4db94011d3 154 * - bit 2 = Transmit FIFO Empty
sahilmgandhi 18:6a4db94011d3 155 * - bit 1 = Transfer Error
sahilmgandhi 18:6a4db94011d3 156 * - bit 0 = ssIn (conditionally inverted and synchronized to PCLK)
sahilmgandhi 18:6a4db94011d3 157 * (unused option in current implementation / irq 6 and 7 used) */
sahilmgandhi 18:6a4db94011d3 158 uint8_t slaveSelectEnable; /* Slave Select enables (x4):
sahilmgandhi 18:6a4db94011d3 159 * - 0 (x4) = Slave select enable
sahilmgandhi 18:6a4db94011d3 160 * - 1 (x4) = Slave select disable */
sahilmgandhi 18:6a4db94011d3 161 uint8_t slaveSelectBurst; /* Slave Select burst mode:
sahilmgandhi 18:6a4db94011d3 162 * - NO_BURST_MODE = Burst mode disable
sahilmgandhi 18:6a4db94011d3 163 * - BURST_MODE = Burst mode enable */
sahilmgandhi 18:6a4db94011d3 164 uint8_t slaveSelectPolarity; /* Slave Select polarity (x4) for up to 4 slaves:
sahilmgandhi 18:6a4db94011d3 165 * - 0 (x4) = Slave select is active low
sahilmgandhi 18:6a4db94011d3 166 * - 1 (x4) = Slave select is active high */
sahilmgandhi 18:6a4db94011d3 167 uint8_t txWatermark; /* Transmit FIFO Watermark: Defines level of RX Half Full Flag
sahilmgandhi 18:6a4db94011d3 168 * - Value between 1 and 15
sahilmgandhi 18:6a4db94011d3 169 * (unused option in current implementation / not txWatermark irq used) */
sahilmgandhi 18:6a4db94011d3 170 uint8_t rxWatermark; /* Receive FIFO Watermark: Defines level of TX Half Full Flag:
sahilmgandhi 18:6a4db94011d3 171 * - Value between 1 and 15
sahilmgandhi 18:6a4db94011d3 172 * * (unused option in current implementation / rxWatermark fixed to 1) */
sahilmgandhi 18:6a4db94011d3 173 spi_ipc7207_endian_t endian; /* Bits endianness:
sahilmgandhi 18:6a4db94011d3 174 * - LITTLE_ENDIAN = LSB first
sahilmgandhi 18:6a4db94011d3 175 * - BIG_ENDIAN = MSB first */
sahilmgandhi 18:6a4db94011d3 176 uint8_t samplingEdge; /* SDI sampling edge (relative to SDO sampling edge):
sahilmgandhi 18:6a4db94011d3 177 * - 0 = opposite to SDO sampling edge
sahilmgandhi 18:6a4db94011d3 178 * - 1 = same as SDO sampling edge */
sahilmgandhi 18:6a4db94011d3 179 uint32_t baudrate; /* The expected baud rate. */
sahilmgandhi 18:6a4db94011d3 180 spi_clockPolarity_t clockPolarity; /* The clock polarity (active high or low). */
sahilmgandhi 18:6a4db94011d3 181 spi_clockPhase_t clockPhase; /* The clock phase (sample on rising or falling edge). */
sahilmgandhi 18:6a4db94011d3 182 uint8_t wordSize; /* The size word size in number of bits. */
sahilmgandhi 18:6a4db94011d3 183 uint8_t Mode;
sahilmgandhi 18:6a4db94011d3 184 uint32_t event;
sahilmgandhi 18:6a4db94011d3 185 };
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 struct i2c_s {
sahilmgandhi 18:6a4db94011d3 188 uint32_t baudrate; /**< The expected baud rate. */
sahilmgandhi 18:6a4db94011d3 189 uint32_t I2cStatusFromInt;
sahilmgandhi 18:6a4db94011d3 190 uint8_t ClockSource; /**< I2C clock source, 0 – clkI2C pin, 1 – PCLK */
sahilmgandhi 18:6a4db94011d3 191 uint8_t irqEnable; /**< IRQs to be enabled */
sahilmgandhi 18:6a4db94011d3 192 I2cIpc7208Reg_pt membase; /**< The memory base for the device's registers. */
sahilmgandhi 18:6a4db94011d3 193 IRQn_Type irq; /**< The IRQ number of the IRQ associated to the device. */
sahilmgandhi 18:6a4db94011d3 194 //queue_pt rxQueue; /**< The receive queue for the device instance. */
sahilmgandhi 18:6a4db94011d3 195 };
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 struct trng_s {
sahilmgandhi 18:6a4db94011d3 198 RandReg_pt membase; /**< The memory base for the device's registers. */
sahilmgandhi 18:6a4db94011d3 199 };
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 202 }
sahilmgandhi 18:6a4db94011d3 203 #endif
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 #endif //OBJECTS_H_