MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ***************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file ncs36510_init.c
sahilmgandhi 18:6a4db94011d3 4 * @brief Initialization of Orion SoC
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev:
sahilmgandhi 18:6a4db94011d3 8 * $Date: $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup main
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 /*************************************************************************************************
sahilmgandhi 18:6a4db94011d3 33 * *
sahilmgandhi 18:6a4db94011d3 34 * Header files *
sahilmgandhi 18:6a4db94011d3 35 * *
sahilmgandhi 18:6a4db94011d3 36 *************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 37 #include "ncs36510Init.h"
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 void fPmuInit(void);
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 /**
sahilmgandhi 18:6a4db94011d3 42 * @brief
sahilmgandhi 18:6a4db94011d3 43 * Hardware trimming function
sahilmgandhi 18:6a4db94011d3 44 * This function copies trim codes from specific flash location
sahilmgandhi 18:6a4db94011d3 45 * where they are stored to proper hw registers.
sahilmgandhi 18:6a4db94011d3 46 */
sahilmgandhi 18:6a4db94011d3 47 boolean fTrim()
sahilmgandhi 18:6a4db94011d3 48 {
sahilmgandhi 18:6a4db94011d3 49 boolean status = False;
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /**- Check if trim values are present */
sahilmgandhi 18:6a4db94011d3 52 /**- If Trim data is present. Only trim if valid trim values are present. */
sahilmgandhi 18:6a4db94011d3 53 /**- Copy trims in registers */
sahilmgandhi 18:6a4db94011d3 54 if (TRIMREG->REVISION_CODE != 0xFFFFFFFF) {
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 if ( TRIMREG->MAC_ADDR_LOW != 0xFFFFFFFF ) {
sahilmgandhi 18:6a4db94011d3 57 MACHWREG->LONG_ADDRESS_LOW = TRIMREG->MAC_ADDR_LOW;
sahilmgandhi 18:6a4db94011d3 58 }
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 if ( TRIMREG->MAC_ADDR_HIGH != 0xFFFFFFFF ) {
sahilmgandhi 18:6a4db94011d3 61 MACHWREG->LONG_ADDRESS_HIGH = TRIMREG->MAC_ADDR_HIGH;
sahilmgandhi 18:6a4db94011d3 62 }
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /**- board specific clock trims may only be done when present, writing all 1's is not good */
sahilmgandhi 18:6a4db94011d3 65 if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
sahilmgandhi 18:6a4db94011d3 66 CLOCKREG->TRIM_32K_EXT.WORD = TRIMREG->TRIM_32K_EXT;
sahilmgandhi 18:6a4db94011d3 67 }
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
sahilmgandhi 18:6a4db94011d3 70 CLOCKREG->TRIM_32M_EXT.WORD = TRIMREG->TRIM_32M_EXT;
sahilmgandhi 18:6a4db94011d3 71 }
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 MACHWREG->TX_LENGTH.BITS.TX_PRE_CHIPS = TRIMREG->TX_PRE_CHIPS;
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 if ((TRIMREG->TX_TRIM & 0xFFFF0000) != 0xFFFF0000) {
sahilmgandhi 18:6a4db94011d3 76 RFANATRIMREG->TX_TRIM.WORD = TRIMREG->TX_TRIM;
sahilmgandhi 18:6a4db94011d3 77 }
sahilmgandhi 18:6a4db94011d3 78 RFANATRIMREG->PLL_VCO_TAP_LOCATION = TRIMREG->PLL_VCO_TAP_LOCATION;
sahilmgandhi 18:6a4db94011d3 79 RFANATRIMREG->PLL_TRIM.WORD = TRIMREG->PLL_TRIM;
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 /**- board specific RSSI trims may only be done when present, writing all 1's is not good */
sahilmgandhi 18:6a4db94011d3 82 if ((TRIMREG->RSSI_OFFSET & 0xFFFF0000) != 0xFFFF0000) {
sahilmgandhi 18:6a4db94011d3 83 DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = TRIMREG->RSSI_OFFSET;
sahilmgandhi 18:6a4db94011d3 84 }
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 RFANATRIMREG->RX_CHAIN_TRIM = TRIMREG->RX_CHAIN_TRIM;
sahilmgandhi 18:6a4db94011d3 87 RFANATRIMREG->PMU_TRIM = TRIMREG->PMU_TRIM;
sahilmgandhi 18:6a4db94011d3 88 RANDREG->WR_SEED_RD_RAND = TRIMREG->WR_SEED_RD_RAND;
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 /* High side injection settings */
sahilmgandhi 18:6a4db94011d3 91 RFANATRIMREG->RX_VCO_TRIM_LUT1 = TRIMREG->RX_VCO_LUT1.WORD;;
sahilmgandhi 18:6a4db94011d3 92 RFANATRIMREG->RX_VCO_TRIM_LUT2 = TRIMREG->RX_VCO_LUT2.WORD;;
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 RFANATRIMREG->TX_VCO_TRIM_LUT1 = TRIMREG->TX_VCO_LUT1.WORD;;
sahilmgandhi 18:6a4db94011d3 95 RFANATRIMREG->TX_VCO_TRIM_LUT2 = TRIMREG->TX_VCO_LUT2.WORD;;
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 status = True;
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 } else {
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 return(False);
sahilmgandhi 18:6a4db94011d3 102 }
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 /** Read in user trim values programmed in the flash memory
sahilmgandhi 18:6a4db94011d3 105 The user trim values take precedence over factory trim for MAC address
sahilmgandhi 18:6a4db94011d3 106 */
sahilmgandhi 18:6a4db94011d3 107 if (( USERTRIMREG->MAC_ADDRESS_LOW != 0xFFFFFFFF ) &&
sahilmgandhi 18:6a4db94011d3 108 (USERTRIMREG->MAC_ADDRESS_HIGH != 0xFFFFFFFF)) {
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 MACHWREG->LONG_ADDRESS_LOW = USERTRIMREG->MAC_ADDRESS_LOW;
sahilmgandhi 18:6a4db94011d3 111 MACHWREG->LONG_ADDRESS_HIGH = USERTRIMREG->MAC_ADDRESS_HIGH;
sahilmgandhi 18:6a4db94011d3 112 }
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 if (USERTRIMREG->TRIM_32K_EXT != 0xFFFFFFFF) {
sahilmgandhi 18:6a4db94011d3 115 CLOCKREG->TRIM_32K_EXT.WORD = (USERTRIMREG->TRIM_32K_EXT & 0x00000FFF);
sahilmgandhi 18:6a4db94011d3 116 }
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 if (USERTRIMREG->TRIM_32K_EXT != 0xFFFFFFFF) {
sahilmgandhi 18:6a4db94011d3 119 CLOCKREG->TRIM_32K_EXT.WORD = (USERTRIMREG->TRIM_32K_EXT & 0x00000FFF);
sahilmgandhi 18:6a4db94011d3 120 }
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 if (USERTRIMREG->RSSI_OFFSET != 0xFFFFFFFF) {
sahilmgandhi 18:6a4db94011d3 123 DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = (USERTRIMREG->RSSI_OFFSET & 0x0000003F);
sahilmgandhi 18:6a4db94011d3 124 }
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 if (USERTRIMREG->TX_TRIM != 0xFFFFFFFF) {
sahilmgandhi 18:6a4db94011d3 127 RFANATRIMREG->TX_TRIM.BITS.TX_TUNE = (USERTRIMREG->TX_TRIM & 0x0000000F);
sahilmgandhi 18:6a4db94011d3 128 }
sahilmgandhi 18:6a4db94011d3 129 return(status);
sahilmgandhi 18:6a4db94011d3 130 }
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 /* See clock.h for documentation. */
sahilmgandhi 18:6a4db94011d3 133 void fClockInit()
sahilmgandhi 18:6a4db94011d3 134 {
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 /** Enable external 32MHz oscillator */
sahilmgandhi 18:6a4db94011d3 137 CLOCKREG->CCR.BITS.OSC_SEL = 1;
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /** - Wait external 32MHz oscillator to be ready */
sahilmgandhi 18:6a4db94011d3 140 while(CLOCKREG->CSR.BITS.XTAL32M != 1) {} /* If you get stuck here, something is wrong with board or trim values */
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 /** Internal 32MHz calibration \n *//** - Enable internal 32MHz clock */
sahilmgandhi 18:6a4db94011d3 143 PMUREG->CONTROL.BITS.INT32M = 0;
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 /** - Wait 5 uSec for clock to stabilize */
sahilmgandhi 18:6a4db94011d3 146 volatile uint8_t Timer;
sahilmgandhi 18:6a4db94011d3 147 for(Timer = 0; Timer < 10; Timer++);
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 /** - Enable calibration */
sahilmgandhi 18:6a4db94011d3 150 CLOCKREG->CCR.BITS.CAL32M = True;
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 /** - Wait calibration to be completed */
sahilmgandhi 18:6a4db94011d3 153 while(CLOCKREG->CSR.BITS.CAL32MDONE == False); /* If you stuck here, issue with internal 32M calibration */
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 /** - Check calibration status */
sahilmgandhi 18:6a4db94011d3 156 while(CLOCKREG->CSR.BITS.CAL32MFAIL == True); /* If you stuck here, issue with internal 32M calibration */
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 /** - Power down internal 32MHz osc */
sahilmgandhi 18:6a4db94011d3 159 PMUREG->CONTROL.BITS.INT32M = 1;
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 /** Internal 32KHz calibration \n */ /** - Enable internal 32KHz clock */
sahilmgandhi 18:6a4db94011d3 162 PMUREG->CONTROL.BITS.INT32K = 0;
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 /** - Wait 5 uSec for clock to stabilize */
sahilmgandhi 18:6a4db94011d3 165 for(Timer = 0; Timer < 10; Timer++);
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 /** - Enable calibration */
sahilmgandhi 18:6a4db94011d3 168 CLOCKREG->CCR.BITS.CAL32K = True;
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 /** - Wait calibration to be completed */
sahilmgandhi 18:6a4db94011d3 171 while(CLOCKREG->CSR.BITS.DONE32K == False); /* If you stuck here, issue with internal 32K calibration */
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 /** - Check calibration status */
sahilmgandhi 18:6a4db94011d3 174 while(CLOCKREG->CSR.BITS.CAL32K == True); /* If you stuck here, issue with internal 32M calibration */
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 /** - Power down external 32KHz osc */
sahilmgandhi 18:6a4db94011d3 177 PMUREG->CONTROL.BITS.EXT32K = 1;
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 /** Disable all peripheral clocks by default */
sahilmgandhi 18:6a4db94011d3 180 CLOCKREG->PDIS.WORD = 0xFFFFFFFF;
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 /** Set core frequency */
sahilmgandhi 18:6a4db94011d3 183 CLOCKREG->FDIV = CPU_CLOCK_DIV - 1;
sahilmgandhi 18:6a4db94011d3 184 }
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 /* Initializes PMU module */
sahilmgandhi 18:6a4db94011d3 187 void fPmuInit()
sahilmgandhi 18:6a4db94011d3 188 {
sahilmgandhi 18:6a4db94011d3 189 /** Enable the clock for PMU peripheral device */
sahilmgandhi 18:6a4db94011d3 190 CLOCK_ENABLE(CLOCK_PMU);
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 /** Unset wakeup on pending (only enabled irq can wakeup) */
sahilmgandhi 18:6a4db94011d3 193 SCB->SCR &= ~SCB_SCR_SEVONPEND_Msk;
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 /** Unset auto sleep when returning from wakeup irq */
sahilmgandhi 18:6a4db94011d3 196 SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 /** Set regulator timings */
sahilmgandhi 18:6a4db94011d3 199 PMUREG->FVDD_TSETTLE = 160;
sahilmgandhi 18:6a4db94011d3 200 PMUREG->FVDD_TSTARTUP = 400;
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 /** Keep SRAMA & SRAMB powered in coma mode */
sahilmgandhi 18:6a4db94011d3 204 PMUREG->CONTROL.BITS.SRAMA = False;
sahilmgandhi 18:6a4db94011d3 205 PMUREG->CONTROL.BITS.SRAMB = False;
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 PMUREG->CONTROL.BITS.N1V1 = True; /* Enable ACTIVE mode switching regulator */
sahilmgandhi 18:6a4db94011d3 208 PMUREG->CONTROL.BITS.C1V1 = True; /* Enable COMA mode switching regulator */
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 /** Disable the clock for PMU peripheral device, all settings are done */
sahilmgandhi 18:6a4db94011d3 211 CLOCK_DISABLE(CLOCK_PMU);
sahilmgandhi 18:6a4db94011d3 212 }
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 /* See clock.h for documentation. */
sahilmgandhi 18:6a4db94011d3 215 uint32_t fClockGetPeriphClockfrequency()
sahilmgandhi 18:6a4db94011d3 216 {
sahilmgandhi 18:6a4db94011d3 217 return (CPU_CLOCK_ROOT_HZ / CPU_CLOCK_DIV);
sahilmgandhi 18:6a4db94011d3 218 }
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 /**
sahilmgandhi 18:6a4db94011d3 222 * @brief
sahilmgandhi 18:6a4db94011d3 223 * Hardware initialization function
sahilmgandhi 18:6a4db94011d3 224 * This function initializes hardware at application start up prior
sahilmgandhi 18:6a4db94011d3 225 * to other initializations or OS operations.
sahilmgandhi 18:6a4db94011d3 226 */
sahilmgandhi 18:6a4db94011d3 227 static void fHwInit(void)
sahilmgandhi 18:6a4db94011d3 228 {
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 /* Trim register settings */
sahilmgandhi 18:6a4db94011d3 231 fTrim();
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 /* Clock setting */
sahilmgandhi 18:6a4db94011d3 234 /** - Initialize clock */
sahilmgandhi 18:6a4db94011d3 235 fClockInit();
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 /** - Initialize pmu */
sahilmgandhi 18:6a4db94011d3 238 fPmuInit();
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 /** Orion has 4 interrupt bits in interrupt priority register
sahilmgandhi 18:6a4db94011d3 241 * The lowest 4 bits are not used.
sahilmgandhi 18:6a4db94011d3 242 *
sahilmgandhi 18:6a4db94011d3 243 @verbatim
sahilmgandhi 18:6a4db94011d3 244 +-----+-----+-----+-----+-----+-----+-----+-----+
sahilmgandhi 18:6a4db94011d3 245 |bit 7|bit 6|bit 5|bit 4|bit 3|bit 2|bit 1|bit 0|
sahilmgandhi 18:6a4db94011d3 246 | | | | | 0 | 0 | 0 | 0 |
sahilmgandhi 18:6a4db94011d3 247 +-----+-----+-----+-----+-----+-----+-----+-----+
sahilmgandhi 18:6a4db94011d3 248 |
sahilmgandhi 18:6a4db94011d3 249 INTERRUPT PRIORITY | NOT IMPLEMENTED,
sahilmgandhi 18:6a4db94011d3 250 | read as 0
sahilmgandhi 18:6a4db94011d3 251 Valid priorities are 0x00, 0x10, 0x20, 0x30
sahilmgandhi 18:6a4db94011d3 252 0x40, 0x50, 0x60, 0x70
sahilmgandhi 18:6a4db94011d3 253 0x80, 0x90, 0xA0, 0xB0
sahilmgandhi 18:6a4db94011d3 254 0xC0, 0xD0, 0xE0, 0xF0
sahilmgandhi 18:6a4db94011d3 255 @endverbatim
sahilmgandhi 18:6a4db94011d3 256 * Lowest number is highest priority
sahilmgandhi 18:6a4db94011d3 257 *
sahilmgandhi 18:6a4db94011d3 258 *
sahilmgandhi 18:6a4db94011d3 259 * This range is defined by
sahilmgandhi 18:6a4db94011d3 260 * configKERNEL_INTERRUPT_PRIORITY (lowest)
sahilmgandhi 18:6a4db94011d3 261 * and configMAX_SYSCALL_INTERRUPT_PRIORITY (highest). All interrupt
sahilmgandhi 18:6a4db94011d3 262 * priorities need to fall in that range.
sahilmgandhi 18:6a4db94011d3 263 *
sahilmgandhi 18:6a4db94011d3 264 * To be future safe, the LSbits of the priority are set to 0xF.
sahilmgandhi 18:6a4db94011d3 265 * This wil lmake sure that if more interrupt bits are used, the
sahilmgandhi 18:6a4db94011d3 266 * priority is maintained.
sahilmgandhi 18:6a4db94011d3 267 */
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 /** - Set IRQs priorities */
sahilmgandhi 18:6a4db94011d3 270 NVIC_SetPriority(Tim0_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 271 NVIC_SetPriority(Tim1_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 272 NVIC_SetPriority(Tim2_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 273 NVIC_SetPriority(Uart1_IRQn,14);
sahilmgandhi 18:6a4db94011d3 274 NVIC_SetPriority(Spi_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 275 NVIC_SetPriority(I2C_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 276 NVIC_SetPriority(Gpio_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 277 NVIC_SetPriority(Rtc_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 278 NVIC_SetPriority(MacHw_IRQn, 13);
sahilmgandhi 18:6a4db94011d3 279 NVIC_SetPriority(Aes_IRQn, 13);
sahilmgandhi 18:6a4db94011d3 280 NVIC_SetPriority(Adc_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 281 NVIC_SetPriority(ClockCal_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 282 NVIC_SetPriority(Uart2_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 283 NVIC_SetPriority(Dma_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 284 NVIC_SetPriority(Uvi_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 285 NVIC_SetPriority(DbgPwrUp_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 286 NVIC_SetPriority(Spi2_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 287 NVIC_SetPriority(I2C2_IRQn, 14);
sahilmgandhi 18:6a4db94011d3 288 }
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 extern void __Vectors;
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292 void fNcs36510Init(void)
sahilmgandhi 18:6a4db94011d3 293 {
sahilmgandhi 18:6a4db94011d3 294 /** Setting this register is helping to debug imprecise bus access faults
sahilmgandhi 18:6a4db94011d3 295 * making them precise bus access faults. It has an impact on application
sahilmgandhi 18:6a4db94011d3 296 * performance. */
sahilmgandhi 18:6a4db94011d3 297 // SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk;
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 /** This main function implements: */
sahilmgandhi 18:6a4db94011d3 300 /**- Disable all interrupts */
sahilmgandhi 18:6a4db94011d3 301 NVIC->ICER[0] = 0x1F;
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 /**- Clear all Pending interrupts */
sahilmgandhi 18:6a4db94011d3 304 NVIC->ICPR[0] = 0x1F;
sahilmgandhi 18:6a4db94011d3 305
sahilmgandhi 18:6a4db94011d3 306 /**- Clear all pending SV and systick */
sahilmgandhi 18:6a4db94011d3 307 SCB->ICSR = (uint32_t)0x0A000000;
sahilmgandhi 18:6a4db94011d3 308 SCB->VTOR = (uint32_t) (&__Vectors);
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 /**- Initialize hardware */
sahilmgandhi 18:6a4db94011d3 311 fHwInit();
sahilmgandhi 18:6a4db94011d3 312 }