MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file memory_map.h
sahilmgandhi 18:6a4db94011d3 4 * @brief Defines the silicon memory map. All peripheral devices shall be mapped in structures.
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 3525 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup bsp
sahilmgandhi 18:6a4db94011d3 28 @verbatim
sahilmgandhi 18:6a4db94011d3 29 +-----------------+
sahilmgandhi 18:6a4db94011d3 30 | | ,_________________________
sahilmgandhi 18:6a4db94011d3 31 | Private Per. | |PMUREG 0x4001D000|
sahilmgandhi 18:6a4db94011d3 32 0xE0000000 +-----------------+ |PADREG 0x4001C000|
sahilmgandhi 18:6a4db94011d3 33 | |_____________|CLOCKREG 0x4001B000|
sahilmgandhi 18:6a4db94011d3 34 | PERIPHERALS | |RFANAREG 0x40019000|
sahilmgandhi 18:6a4db94011d3 35 +-----------------+ |RESETREG 0x40018000|
sahilmgandhi 18:6a4db94011d3 36 | | |FLASHREG 0x40017000|
sahilmgandhi 18:6a4db94011d3 37 0x3FFF8000 |SRAM A 32K | |AESREG 0x40016000|
sahilmgandhi 18:6a4db94011d3 38 +-----------------+ |ADCREG 0x40015000|
sahilmgandhi 18:6a4db94011d3 39 | | |MACHWREG 0x40014000|
sahilmgandhi 18:6a4db94011d3 40 |SRAM B 16K | |RANDREG 0x40011000|
sahilmgandhi 18:6a4db94011d3 41 0x3FFF4000 +-----------------+ |CROSSBREG 0x40010000|
sahilmgandhi 18:6a4db94011d3 42 | | |RTCREG 0x4000F000|
sahilmgandhi 18:6a4db94011d3 43 0x24000100 |SRAM DMA 7B | |GPIOREG 0x4000C000|
sahilmgandhi 18:6a4db94011d3 44 +-----------------+ |PWMREG 0x4000B000|
sahilmgandhi 18:6a4db94011d3 45 0x24000000 |SRAM MAC 256B | |WDTREG 0x4000A000|
sahilmgandhi 18:6a4db94011d3 46 +-----------------+ |UARTREG 0x40008000|
sahilmgandhi 18:6a4db94011d3 47 | 320K | |I2CREG 0x40007000|
sahilmgandhi 18:6a4db94011d3 48 0x00102000 |FLASHB | |SPIREG 0x40006000|
sahilmgandhi 18:6a4db94011d3 49 0x00100000 |FLASHB Inf Block | |UARTREG 0x40005000|
sahilmgandhi 18:6a4db94011d3 50 +-----------------+ |TIM2REG 0x40002000|
sahilmgandhi 18:6a4db94011d3 51 | 320K | |TIM1REG 0x40001000|
sahilmgandhi 18:6a4db94011d3 52 0x00002000 |FLASHA | |TIM0REG 0x40000000|
sahilmgandhi 18:6a4db94011d3 53 0x00000000 |FLASHA Inf Block | '`''''''''''''''''''''''''
sahilmgandhi 18:6a4db94011d3 54 '`'''''''''''''''''
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 @endverbatim
sahilmgandhi 18:6a4db94011d3 57 */
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 #ifndef _MEMORY_MAP_H_
sahilmgandhi 18:6a4db94011d3 60 #define _MEMORY_MAP_H_
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 /*************************************************************************************************
sahilmgandhi 18:6a4db94011d3 63 * *
sahilmgandhi 18:6a4db94011d3 64 * Header files *
sahilmgandhi 18:6a4db94011d3 65 * *
sahilmgandhi 18:6a4db94011d3 66 *************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 #include "architecture.h"
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 // Register maps of HW modules controlled with device drivers
sahilmgandhi 18:6a4db94011d3 73 #include "adc_sar_map.h"
sahilmgandhi 18:6a4db94011d3 74 #include "aes_map.h"
sahilmgandhi 18:6a4db94011d3 75 #include "flash_map.h"
sahilmgandhi 18:6a4db94011d3 76 #include "gpio_map.h"
sahilmgandhi 18:6a4db94011d3 77 #include "i2c_ipc7208_map.h"
sahilmgandhi 18:6a4db94011d3 78 #include "pwm_map.h"
sahilmgandhi 18:6a4db94011d3 79 #include "rtc_map.h"
sahilmgandhi 18:6a4db94011d3 80 #include "spi_ipc7207_map.h"
sahilmgandhi 18:6a4db94011d3 81 #include "timer_map.h"
sahilmgandhi 18:6a4db94011d3 82 #include "uart_16c550_map.h"
sahilmgandhi 18:6a4db94011d3 83 #include "wdt_map.h"
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 // Register maps of HW modules controlled with specific functions
sahilmgandhi 18:6a4db94011d3 86 #include "clock_map.h"
sahilmgandhi 18:6a4db94011d3 87 #include "crossbar_map.h"
sahilmgandhi 18:6a4db94011d3 88 #include "dma_map.h"
sahilmgandhi 18:6a4db94011d3 89 #include "macHw_map.h"
sahilmgandhi 18:6a4db94011d3 90 #include "pad_map.h"
sahilmgandhi 18:6a4db94011d3 91 #include "pmu_map.h"
sahilmgandhi 18:6a4db94011d3 92 #include "random_map.h"
sahilmgandhi 18:6a4db94011d3 93 #include "reset_map.h"
sahilmgandhi 18:6a4db94011d3 94 #include "rfAna_map.h"
sahilmgandhi 18:6a4db94011d3 95 #include "test_map.h"
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 // Trim structure map
sahilmgandhi 18:6a4db94011d3 98 #include "trim_map.h"
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 /*************************************************************************************************
sahilmgandhi 18:6a4db94011d3 101 * *
sahilmgandhi 18:6a4db94011d3 102 * Symbolic Constants *
sahilmgandhi 18:6a4db94011d3 103 * *
sahilmgandhi 18:6a4db94011d3 104 *************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 /** Trim structure mapping
sahilmgandhi 18:6a4db94011d3 107 *
sahilmgandhi 18:6a4db94011d3 108 */
sahilmgandhi 18:6a4db94011d3 109 #define TRIMREG_BASE ((uint32_t)0x1FA0)
sahilmgandhi 18:6a4db94011d3 110 #define TRIMREG ((TrimReg_t *)TRIMREG_BASE)
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 /** User trim structure mapping
sahilmgandhi 18:6a4db94011d3 113 *
sahilmgandhi 18:6a4db94011d3 114 */
sahilmgandhi 18:6a4db94011d3 115 #define USRETRIMREG_BASE ((uint32_t)0x2800)
sahilmgandhi 18:6a4db94011d3 116 #define USERTRIMREG ((UserTrimReg_t *)USRETRIMREG_BASE)
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 /** DMA HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 119 #define DMAREG_BASE ((uint32_t)0x24000400)
sahilmgandhi 18:6a4db94011d3 120 /** DMA HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 121 #define DMAREG ((DmaReg_pt)DMAREG_BASE)
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 /** MAC MATCH HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 124 #define MACMATCHREG_BASE ((uint32_t)0x24000100)
sahilmgandhi 18:6a4db94011d3 125 /** MAC MATCH HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 126 #define MACMATCHREG ((volatile uint8_t *)MACMATCHREG_BASE)
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /** MAC RX HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 129 #define MACRXREG_BASE ((uint32_t)0x24000080)
sahilmgandhi 18:6a4db94011d3 130 /** MAC RX HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 131 #define MACRXREG ((volatile uint8_t *)MACRXREG_BASE)
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 /** MAC TX HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 134 #define MACTXREG_BASE ((uint32_t)0x24000000)
sahilmgandhi 18:6a4db94011d3 135 /** MAC TX HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 136 #define MACTXREG ((volatile uint8_t *)MACTXREG_BASE)
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 /** TEST Interface for flash HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 139 #define TESTNVMREG_BASE ((uint32_t)0x4001F140)
sahilmgandhi 18:6a4db94011d3 140 /** TEST Interface for flash HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 141 #define TESTNVMREG ((TestNvmReg_pt)TESTNVMREG_BASE)
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 /** Test Interface for digital HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 144 #define TESTDIGREG_BASE ((uint32_t)0x4001F100)
sahilmgandhi 18:6a4db94011d3 145 /** Test Interface for digital HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 146 #define TESTDIGREG ((TestDigReg_pt)TESTDIGREG_BASE)
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 /** Test Interface HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 149 #define TESTREG_BASE ((uint32_t)0x4001F000)
sahilmgandhi 18:6a4db94011d3 150 /** Test Interface HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 151 #define TESTREG ((TestReg_pt)TESTREG_BASE)
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 /** Device option HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 154 #define DEVOPTREG_BASE ((uint32_t)0x4001E000)
sahilmgandhi 18:6a4db94011d3 155 /** MAC TX HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 156 #define DEVOPTREG ((volatile uint32_t *)DEVOPTREG_BASE)
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 /** PMU HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 159 #define PMUREG_BASE ((uint32_t)0x4001D000)
sahilmgandhi 18:6a4db94011d3 160 /** PMU HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 161 #define PMUREG ((PmuReg_pt)PMUREG_BASE)
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 /** PAD Control HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 164 #define PADREG_BASE ((uint32_t)0x4001C000)
sahilmgandhi 18:6a4db94011d3 165 /** PAD Control HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 166 #define PADREG ((PadReg_pt)PADREG_BASE)
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 /** Clock Control HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 169 #define CLOCKREG_BASE ((uint32_t)0x4001B000)
sahilmgandhi 18:6a4db94011d3 170 /** Clock Control HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 171 #define CLOCKREG ((ClockReg_pt)CLOCKREG_BASE)
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 /** Analogue Trim HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 174 #define RFANATRIMREG_BASE ((uint32_t)0x40019080)
sahilmgandhi 18:6a4db94011d3 175 /** Analogue Trim HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 176 #define RFANATRIMREG ((RfAnaTrimReg_pt)RFANATRIMREG_BASE)
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 /** Analogue RF HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 179 #define RFANAREG_BASE ((uint32_t)0x40019000)
sahilmgandhi 18:6a4db94011d3 180 /** Analogue RF HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 181 #define RFANAREG ((RfAnaReg_pt)RFANAREG_BASE)
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 /** Reset Cause HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 184 #define RESETREG_BASE ((uint32_t)0x40018000)
sahilmgandhi 18:6a4db94011d3 185 /** Reset Cause HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 186 #define RESETREG ((ResetReg_pt)RESETREG_BASE)
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 /** FLASH Control HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 189 #define FLASHREG_BASE ((uint32_t)0x40017000)
sahilmgandhi 18:6a4db94011d3 190 /** FLASH Control HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 191 #define FLASHREG ((FlashReg_pt)FLASHREG_BASE)
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 /** AES Encryption HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 194 #define AESREG_BASE ((uint32_t)0x40016000)
sahilmgandhi 18:6a4db94011d3 195 /** AES Encryption HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 196 #define AESREG ((AesReg_pt)AESREG_BASE)
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 /** SAR ADC HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 199 #define ADCREG_BASE ((uint32_t)0x40015000)
sahilmgandhi 18:6a4db94011d3 200 /** SAR ADC HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 201 #define ADCREG ((AdcReg_pt)ADCREG_BASE)
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 /** Demodulator HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 204 #define DMDREG_BASE ((uint32_t)0x40014100)
sahilmgandhi 18:6a4db94011d3 205 /** Demodulator HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 206 #define DMDREG ((DmdReg_pt)DMDREG_BASE)
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 /** MAC Control HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 209 #define MACHWREG_BASE ((uint32_t)0x40014000)
sahilmgandhi 18:6a4db94011d3 210 /** MAC Control HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 211 #define MACHWREG ((MacHwReg_pt)MACHWREG_BASE)
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 /** Random Generator HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 214 #define RANDREG_BASE ((uint32_t)0x40011000)
sahilmgandhi 18:6a4db94011d3 215 /** Random Generator HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 216 #define RANDREG ((RandReg_pt)RANDREG_BASE)
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 /** Cross Bar HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 219 #define CROSSBREG_BASE ((uint32_t)0x40010000)
sahilmgandhi 18:6a4db94011d3 220 /** Cross Bar HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 221 #define CROSSBREG ((CrossbReg_pt)CROSSBREG_BASE)
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 /** Real Time Clock HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 224 #define RTCREG_BASE ((uint32_t)0x4000F000)
sahilmgandhi 18:6a4db94011d3 225 /** Real Time Clock HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 226 #define RTCREG ((RtcReg_pt)RTCREG_BASE)
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 /** GPIO HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 229 #define GPIOREG_BASE ((uint32_t)0x4000C000)
sahilmgandhi 18:6a4db94011d3 230 /** GPIO HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 231 #define GPIOREG ((GpioReg_pt)GPIOREG_BASE)
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 /** PWM HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 234 #define PWMREG_BASE ((uint32_t)0x4000B000)
sahilmgandhi 18:6a4db94011d3 235 /** PWM HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 236 #define PWMREG ((PwmReg_pt)PWMREG_BASE)
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /** Watchdog Timer HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 239 #define WDTREG_BASE ((uint32_t)0x4000A000)
sahilmgandhi 18:6a4db94011d3 240 /** Watchdog Timer HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 241 #define WDTREG ((WdtReg_pt)WDTREG_BASE)
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 /** UART 2 HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 244 #define UART2REG_BASE ((uint32_t)0x40008000)
sahilmgandhi 18:6a4db94011d3 245 /** UART 2 HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 246 #define UART2REG ((Uart16C550Reg_pt)UART2REG_BASE)
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /** I2C HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 249 #define I2C1REG_BASE ((uint32_t)0x40007000)
sahilmgandhi 18:6a4db94011d3 250 /** I2C HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 251 #define I2C1REG ((I2cIpc7208Reg_pt)I2C1REG_BASE)
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 /** SPI HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 254 #define SPI1REG_BASE ((uint32_t)0x40006000)
sahilmgandhi 18:6a4db94011d3 255 /** SPI HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 256 #define SPI1REG ((SpiIpc7207Reg_pt)SPI1REG_BASE)
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 /** UART1 HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 259 #define UART1REG_BASE ((uint32_t)0x40005000)
sahilmgandhi 18:6a4db94011d3 260 /** UART1 HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 261 #define UART1REG ((Uart16C550Reg_pt)UART1REG_BASE)
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 #define UARTREG_BASES { UART1REG_BASE, UART2REG_BASE}
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /** Timer 2 HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 266 #define TIM2REG_BASE ((uint32_t)0x40002000)
sahilmgandhi 18:6a4db94011d3 267 /** Timer 2 HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 268 #define TIM2REG ((TimerReg_pt)TIM2REG_BASE)
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 /** Timer 1 HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 271 #define TIM1REG_BASE ((uint32_t)0x40001000)
sahilmgandhi 18:6a4db94011d3 272 /** Timer 1 HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 273 #define TIM1REG ((TimerReg_pt)TIM1REG_BASE)
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 /** Timer 0 HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 276 #define TIM0REG_BASE ((uint32_t)0x40000000)
sahilmgandhi 18:6a4db94011d3 277 /** Timer 0 HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 278 #define TIM0REG ((TimerReg_pt)TIM0REG_BASE)
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 /** I2C2 HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 281 #define I2C2REG_BASE ((uint32_t)0x4000D000)
sahilmgandhi 18:6a4db94011d3 282 /** I2C2 HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 283 #define I2C2REG ((I2cIpc7208Reg_pt)I2C2REG_BASE)
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 /** SPI2 HW Registers Offset */
sahilmgandhi 18:6a4db94011d3 286 #define SPI2REG_BASE ((uint32_t)0x40009000)
sahilmgandhi 18:6a4db94011d3 287 /** SPI2 HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 288 #define SPI2REG ((SpiIpc7207Reg_pt)SPI2REG_BASE)
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 #endif /*_MEMORY_MAP_H_*/