MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file macHw_map.h
sahilmgandhi 18:6a4db94011d3 4 * @brief MACHW hw module register map
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 3390 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2015-05-13 17:21:05 +0530 (Wed, 13 May 2015) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup macHw
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 #ifndef MACHW_MAP_H_
sahilmgandhi 18:6a4db94011d3 33 #define MACHW_MAP_H_
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 /*************************************************************************************************
sahilmgandhi 18:6a4db94011d3 36 * *
sahilmgandhi 18:6a4db94011d3 37 * Header files *
sahilmgandhi 18:6a4db94011d3 38 * *
sahilmgandhi 18:6a4db94011d3 39 *************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 #include "architecture.h"
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 /**************************************************************************************************
sahilmgandhi 18:6a4db94011d3 44 * *
sahilmgandhi 18:6a4db94011d3 45 * Type definitions *
sahilmgandhi 18:6a4db94011d3 46 * *
sahilmgandhi 18:6a4db94011d3 47 **************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** macHw register map (phy, mac and agc parts) */
sahilmgandhi 18:6a4db94011d3 50 typedef struct {
sahilmgandhi 18:6a4db94011d3 51 __O uint32_t SEQUENCER; /**< 0x40014000 */
sahilmgandhi 18:6a4db94011d3 52 union {
sahilmgandhi 18:6a4db94011d3 53 struct {
sahilmgandhi 18:6a4db94011d3 54 __IO uint32_t MODE:2;
sahilmgandhi 18:6a4db94011d3 55 __IO uint32_t NOACK:1;
sahilmgandhi 18:6a4db94011d3 56 __IO uint32_t FT:1;
sahilmgandhi 18:6a4db94011d3 57 __IO uint32_t PAD0:3;
sahilmgandhi 18:6a4db94011d3 58 __IO uint32_t AUTO:1;
sahilmgandhi 18:6a4db94011d3 59 __IO uint32_t PAD1:1;
sahilmgandhi 18:6a4db94011d3 60 __IO uint32_t NOW:1;
sahilmgandhi 18:6a4db94011d3 61 __IO uint32_t PAD2:1;
sahilmgandhi 18:6a4db94011d3 62 __IO uint32_t PRM:1;
sahilmgandhi 18:6a4db94011d3 63 __IO uint32_t NFCS:1;
sahilmgandhi 18:6a4db94011d3 64 __IO uint32_t PAN:1;
sahilmgandhi 18:6a4db94011d3 65 __IO uint32_t RSTT:1;
sahilmgandhi 18:6a4db94011d3 66 __IO uint32_t RSTR:1;
sahilmgandhi 18:6a4db94011d3 67 __IO uint32_t ACK_ENABLE:1;
sahilmgandhi 18:6a4db94011d3 68 __IO uint32_t BEA_ENABLE:1;
sahilmgandhi 18:6a4db94011d3 69 __IO uint32_t CMD_ENABLE:1;
sahilmgandhi 18:6a4db94011d3 70 __IO uint32_t DATA_ENABLE:1;
sahilmgandhi 18:6a4db94011d3 71 __IO uint32_t RES_ENABLE:1;
sahilmgandhi 18:6a4db94011d3 72 } BITS;
sahilmgandhi 18:6a4db94011d3 73 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 74 } SEQ_OPTIONS; /**< 0x40014004 */
sahilmgandhi 18:6a4db94011d3 75 union {
sahilmgandhi 18:6a4db94011d3 76 struct {
sahilmgandhi 18:6a4db94011d3 77 __IO uint32_t SRST:1;
sahilmgandhi 18:6a4db94011d3 78 __IO uint32_t ON:1;
sahilmgandhi 18:6a4db94011d3 79 __IO uint32_t CLKDIV:1;
sahilmgandhi 18:6a4db94011d3 80 } BITS;
sahilmgandhi 18:6a4db94011d3 81 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 82 } CONTROL; /**< 0x40014008 */
sahilmgandhi 18:6a4db94011d3 83 __O uint32_t PAD0; /**< 0x4001400C */
sahilmgandhi 18:6a4db94011d3 84 union {
sahilmgandhi 18:6a4db94011d3 85 struct {
sahilmgandhi 18:6a4db94011d3 86 __I uint32_t CODE:4;
sahilmgandhi 18:6a4db94011d3 87 __I uint32_t PAD0:8;
sahilmgandhi 18:6a4db94011d3 88 __I uint32_t MSO:1;
sahilmgandhi 18:6a4db94011d3 89 __I uint32_t CB:1;
sahilmgandhi 18:6a4db94011d3 90 __I uint32_t PAD1:1;
sahilmgandhi 18:6a4db94011d3 91 __I uint32_t MST:1;
sahilmgandhi 18:6a4db94011d3 92 } BITS;
sahilmgandhi 18:6a4db94011d3 93 __I uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 94 } STATUS; /**< 0x40014010 */
sahilmgandhi 18:6a4db94011d3 95 union {
sahilmgandhi 18:6a4db94011d3 96 struct {
sahilmgandhi 18:6a4db94011d3 97 __IO uint32_t TFP:1;
sahilmgandhi 18:6a4db94011d3 98 __IO uint32_t SDC:1;
sahilmgandhi 18:6a4db94011d3 99 __IO uint32_t IC:1;
sahilmgandhi 18:6a4db94011d3 100 __IO uint32_t SDB:1;
sahilmgandhi 18:6a4db94011d3 101 __IO uint32_t SSP:1;
sahilmgandhi 18:6a4db94011d3 102 __IO uint32_t TFPO:1;
sahilmgandhi 18:6a4db94011d3 103 } BITS;
sahilmgandhi 18:6a4db94011d3 104 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 105 } OPTIONS; /**< 0x40014014 */
sahilmgandhi 18:6a4db94011d3 106 __IO uint32_t PANID; /**< 0x40014018 */
sahilmgandhi 18:6a4db94011d3 107 __IO uint32_t SHORT_ADDRESS; /**< 0x4001401C */
sahilmgandhi 18:6a4db94011d3 108 __IO uint32_t LONG_ADDRESS_HIGH; /**< 0x40014020 */
sahilmgandhi 18:6a4db94011d3 109 __IO uint32_t LONG_ADDRESS_LOW; /**< 0x40014024 */
sahilmgandhi 18:6a4db94011d3 110 union {
sahilmgandhi 18:6a4db94011d3 111 struct {
sahilmgandhi 18:6a4db94011d3 112 __IO uint32_t BIT_CLOCK_DIVIDER:8;
sahilmgandhi 18:6a4db94011d3 113 __IO uint32_t SYSTEM_CLOCK_DIVIDER:8;
sahilmgandhi 18:6a4db94011d3 114 __IO uint32_t CHIP_CLOCK_DIVIDER:8;
sahilmgandhi 18:6a4db94011d3 115 } BITS;
sahilmgandhi 18:6a4db94011d3 116 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 117 } DIVIDER; /**< 0x40014028 */
sahilmgandhi 18:6a4db94011d3 118 union {
sahilmgandhi 18:6a4db94011d3 119 struct {
sahilmgandhi 18:6a4db94011d3 120 __IO uint32_t RECEIVE_WARMPUP:12;
sahilmgandhi 18:6a4db94011d3 121 __IO uint32_t PAD0:4;
sahilmgandhi 18:6a4db94011d3 122 __IO uint32_t TRANSMIT_WARMPUP:12;
sahilmgandhi 18:6a4db94011d3 123 } BITS;
sahilmgandhi 18:6a4db94011d3 124 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 125 } RX_TX_WARMPUPS; /**< 0x4001402c */
sahilmgandhi 18:6a4db94011d3 126 union {
sahilmgandhi 18:6a4db94011d3 127 struct {
sahilmgandhi 18:6a4db94011d3 128 __O uint32_t EC:1;
sahilmgandhi 18:6a4db94011d3 129 __O uint32_t ES:1;
sahilmgandhi 18:6a4db94011d3 130 __O uint32_t DATA:1;
sahilmgandhi 18:6a4db94011d3 131 __O uint32_t FS:1;
sahilmgandhi 18:6a4db94011d3 132 __O uint32_t FP:1;
sahilmgandhi 18:6a4db94011d3 133 __O uint32_t FMD:1;
sahilmgandhi 18:6a4db94011d3 134 __I uint32_t PC:1;
sahilmgandhi 18:6a4db94011d3 135 } BITS;
sahilmgandhi 18:6a4db94011d3 136 __O uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 137 } CLEAR_IRQ; /**< 0x40014030 */
sahilmgandhi 18:6a4db94011d3 138 union {
sahilmgandhi 18:6a4db94011d3 139 struct {
sahilmgandhi 18:6a4db94011d3 140 __IO uint32_t EC:1;
sahilmgandhi 18:6a4db94011d3 141 __IO uint32_t ES:1;
sahilmgandhi 18:6a4db94011d3 142 __IO uint32_t DATA:1;
sahilmgandhi 18:6a4db94011d3 143 __IO uint32_t FS:1;
sahilmgandhi 18:6a4db94011d3 144 __IO uint32_t FP:1;
sahilmgandhi 18:6a4db94011d3 145 __IO uint32_t FM:1;
sahilmgandhi 18:6a4db94011d3 146 __I uint32_t PC:1;
sahilmgandhi 18:6a4db94011d3 147 } BITS;
sahilmgandhi 18:6a4db94011d3 148 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 149 } MASK_IRQ; /**< 0x40014034 */
sahilmgandhi 18:6a4db94011d3 150 union {
sahilmgandhi 18:6a4db94011d3 151 struct {
sahilmgandhi 18:6a4db94011d3 152 __I uint32_t EC:1;
sahilmgandhi 18:6a4db94011d3 153 __I uint32_t ES:1;
sahilmgandhi 18:6a4db94011d3 154 __I uint32_t DATA:1;
sahilmgandhi 18:6a4db94011d3 155 __I uint32_t FS:1;
sahilmgandhi 18:6a4db94011d3 156 __I uint32_t FP:1;
sahilmgandhi 18:6a4db94011d3 157 __I uint32_t FM:1;
sahilmgandhi 18:6a4db94011d3 158 __I uint32_t PC:1;
sahilmgandhi 18:6a4db94011d3 159 } BITS;
sahilmgandhi 18:6a4db94011d3 160 __I uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 161 } IRQ_STATUS; /**< 0x40014038 */
sahilmgandhi 18:6a4db94011d3 162 __O uint32_t PAD1; /**< 0x4001403C */
sahilmgandhi 18:6a4db94011d3 163 union {
sahilmgandhi 18:6a4db94011d3 164 struct {
sahilmgandhi 18:6a4db94011d3 165 __IO uint32_t START:1;
sahilmgandhi 18:6a4db94011d3 166 __IO uint32_t STOP:1;
sahilmgandhi 18:6a4db94011d3 167 } BITS;
sahilmgandhi 18:6a4db94011d3 168 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 169 } TIMER_ENABLE; /**< 0x40014040 */
sahilmgandhi 18:6a4db94011d3 170 union {
sahilmgandhi 18:6a4db94011d3 171 struct {
sahilmgandhi 18:6a4db94011d3 172 __IO uint32_t START:1;
sahilmgandhi 18:6a4db94011d3 173 __IO uint32_t STOP:1;
sahilmgandhi 18:6a4db94011d3 174 } BITS;
sahilmgandhi 18:6a4db94011d3 175 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 176 } TIMER_DISABLE; /**< 0x40014044 */
sahilmgandhi 18:6a4db94011d3 177 __IO uint32_t TIMER; /**< 0x40014048 */
sahilmgandhi 18:6a4db94011d3 178 __IO uint32_t START_TIME; /**< 0x4001404C */
sahilmgandhi 18:6a4db94011d3 179 __IO uint32_t STOP_TIME; /**< 0x40014050 */
sahilmgandhi 18:6a4db94011d3 180 union {
sahilmgandhi 18:6a4db94011d3 181 struct {
sahilmgandhi 18:6a4db94011d3 182 __I uint32_t START:1;
sahilmgandhi 18:6a4db94011d3 183 __I uint32_t STOP:1;
sahilmgandhi 18:6a4db94011d3 184 } BITS;
sahilmgandhi 18:6a4db94011d3 185 __I uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 186 } TIMER_STATUS; /**< 0x40014054 */
sahilmgandhi 18:6a4db94011d3 187 __I uint32_t PROTOCOL_TIMER; /**< 0x40014058 */
sahilmgandhi 18:6a4db94011d3 188 __O uint32_t PAD4; /**< 0x4001405C */
sahilmgandhi 18:6a4db94011d3 189 __I uint32_t FINISH_TIME; /**< 0x40014060 */
sahilmgandhi 18:6a4db94011d3 190 union {
sahilmgandhi 18:6a4db94011d3 191 struct {
sahilmgandhi 18:6a4db94011d3 192 __IO uint32_t TX_SLOT_OFFSET:12;
sahilmgandhi 18:6a4db94011d3 193 __IO uint32_t PAD0:4;
sahilmgandhi 18:6a4db94011d3 194 __IO uint32_t RX_SLOT_OFFSET:12;
sahilmgandhi 18:6a4db94011d3 195 } BITS;
sahilmgandhi 18:6a4db94011d3 196 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 197 } SLOT_OFFSET; /**< 0x40014064 */
sahilmgandhi 18:6a4db94011d3 198 __I uint32_t TIME_STAMP; /**< 0x40014068 */
sahilmgandhi 18:6a4db94011d3 199 union {
sahilmgandhi 18:6a4db94011d3 200 struct {
sahilmgandhi 18:6a4db94011d3 201 __IO uint32_t CRD_SHORT_ADDRESS:16;
sahilmgandhi 18:6a4db94011d3 202 __IO uint32_t PAD0:13;
sahilmgandhi 18:6a4db94011d3 203 __IO uint32_t ASSOC_PAN_COORD:1;
sahilmgandhi 18:6a4db94011d3 204 __IO uint32_t PAN_COORD_ADDR_L:1;
sahilmgandhi 18:6a4db94011d3 205 __IO uint32_t PAN_COORD_ADDR_S:1;
sahilmgandhi 18:6a4db94011d3 206 } BITS;
sahilmgandhi 18:6a4db94011d3 207 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 208 } CRD_SHORT_ADDR; /**< 0x4001406C */
sahilmgandhi 18:6a4db94011d3 209 __IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014070 */
sahilmgandhi 18:6a4db94011d3 210 __IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014074 */
sahilmgandhi 18:6a4db94011d3 211 __O uint32_t PAD5; /**< 0x40014078 */
sahilmgandhi 18:6a4db94011d3 212 __O uint32_t PAD9; /**< 0x4001407C */
sahilmgandhi 18:6a4db94011d3 213 __O uint32_t PAD10; /**< 0x40014080 */
sahilmgandhi 18:6a4db94011d3 214 __O uint32_t PAD11; /**< 0x40014084 */
sahilmgandhi 18:6a4db94011d3 215 __IO uint32_t RX_LENGTH; /**< 0x40014088 */
sahilmgandhi 18:6a4db94011d3 216 union {
sahilmgandhi 18:6a4db94011d3 217 struct {
sahilmgandhi 18:6a4db94011d3 218 __IO uint32_t TXLENGTH:7;
sahilmgandhi 18:6a4db94011d3 219 __O uint32_t PAD0:1;
sahilmgandhi 18:6a4db94011d3 220 __IO uint32_t TX_PRE_CHIPS:4;
sahilmgandhi 18:6a4db94011d3 221 } BITS;
sahilmgandhi 18:6a4db94011d3 222 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 223 } TX_LENGTH; /**< 0x4001408C */
sahilmgandhi 18:6a4db94011d3 224 __IO uint32_t TX_SEQ_NUMBER; /**< 0x40014090 */
sahilmgandhi 18:6a4db94011d3 225 __IO uint32_t TX_ACK_DELAY; /**< 0x40014094 */
sahilmgandhi 18:6a4db94011d3 226 union {
sahilmgandhi 18:6a4db94011d3 227 struct {
sahilmgandhi 18:6a4db94011d3 228 __IO uint32_t RXACKDELAY:12;
sahilmgandhi 18:6a4db94011d3 229 __IO uint32_t PAD0:4;
sahilmgandhi 18:6a4db94011d3 230 __IO uint32_t RXAUTODELAY:12;
sahilmgandhi 18:6a4db94011d3 231 } BITS;
sahilmgandhi 18:6a4db94011d3 232 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 233 } RX_ACK_DELAY; /**< 0x40014098 */
sahilmgandhi 18:6a4db94011d3 234 __IO uint32_t TX_FLUSH; /**< 0x4001409C */
sahilmgandhi 18:6a4db94011d3 235 union {
sahilmgandhi 18:6a4db94011d3 236 struct {
sahilmgandhi 18:6a4db94011d3 237 __IO uint32_t CCA_DELAY:12;
sahilmgandhi 18:6a4db94011d3 238 __IO uint32_t PAD0:4;
sahilmgandhi 18:6a4db94011d3 239 __IO uint32_t CCA_LENGTH:12;
sahilmgandhi 18:6a4db94011d3 240 } BITS;
sahilmgandhi 18:6a4db94011d3 241 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 242 } CCA; /**< 0x400140A0 */
sahilmgandhi 18:6a4db94011d3 243 union {
sahilmgandhi 18:6a4db94011d3 244 struct {
sahilmgandhi 18:6a4db94011d3 245 __IO uint32_t RXACK_END:12;
sahilmgandhi 18:6a4db94011d3 246 __IO uint32_t PAD0:4;
sahilmgandhi 18:6a4db94011d3 247 __IO uint32_t RXSLOTTED_END:12;
sahilmgandhi 18:6a4db94011d3 248 } BITS;
sahilmgandhi 18:6a4db94011d3 249 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 250 } ACK_STOP; /**< 0x400140A4 */
sahilmgandhi 18:6a4db94011d3 251 __IO uint32_t TXCCA; /**< 0x400140A8 */
sahilmgandhi 18:6a4db94011d3 252 __IO uint32_t ADDR_L_LOC; /**< 0x400140AC */
sahilmgandhi 18:6a4db94011d3 253 __IO uint32_t ADDR_S_LOC; /**< 0x400140B0 */
sahilmgandhi 18:6a4db94011d3 254 __IO uint32_t FRAME_MATCH_RESULT; /**< 0x400140B4 */
sahilmgandhi 18:6a4db94011d3 255 __IO uint32_t FRAME_MATCH_ADDR_L; /**< 0x400140B8 */
sahilmgandhi 18:6a4db94011d3 256 __IO uint32_t FRAME_MATCH_ADDR_S; /**< 0x400140BC */
sahilmgandhi 18:6a4db94011d3 257 union {
sahilmgandhi 18:6a4db94011d3 258 struct {
sahilmgandhi 18:6a4db94011d3 259 __IO uint32_t AA:1;
sahilmgandhi 18:6a4db94011d3 260 __IO uint32_t AFA:1;
sahilmgandhi 18:6a4db94011d3 261 __IO uint32_t PRE:1;
sahilmgandhi 18:6a4db94011d3 262 __IO uint32_t PAD0:25;
sahilmgandhi 18:6a4db94011d3 263 __IO uint32_t GAIN_START:4;
sahilmgandhi 18:6a4db94011d3 264 } BITS;
sahilmgandhi 18:6a4db94011d3 265 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 266 } AGC_CONTROL; /**< 0x400140C0 */
sahilmgandhi 18:6a4db94011d3 267 union {
sahilmgandhi 18:6a4db94011d3 268 struct {
sahilmgandhi 18:6a4db94011d3 269 __IO uint32_t SETTLE_DELAY:8;
sahilmgandhi 18:6a4db94011d3 270 __IO uint32_t MEASURE_DELAY:8;
sahilmgandhi 18:6a4db94011d3 271 __IO uint32_t DIVIDER:8;
sahilmgandhi 18:6a4db94011d3 272 __IO uint32_t HIGH_THRESHOLD:4;
sahilmgandhi 18:6a4db94011d3 273 __IO uint32_t LOW_THRESHOLD:4;
sahilmgandhi 18:6a4db94011d3 274 } BITS;
sahilmgandhi 18:6a4db94011d3 275 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 276 } AGC_SETTINGS; /**< 0x400140C4 */
sahilmgandhi 18:6a4db94011d3 277 union {
sahilmgandhi 18:6a4db94011d3 278 struct {
sahilmgandhi 18:6a4db94011d3 279 __IO uint32_t GC1:3;
sahilmgandhi 18:6a4db94011d3 280 __IO uint32_t GC2:3;
sahilmgandhi 18:6a4db94011d3 281 __IO uint32_t GC3:1;
sahilmgandhi 18:6a4db94011d3 282 __IO uint32_t PAD:1;
sahilmgandhi 18:6a4db94011d3 283 __IO uint32_t AGC_STATE:4;
sahilmgandhi 18:6a4db94011d3 284 } BITS;
sahilmgandhi 18:6a4db94011d3 285 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 286 } AGC_STATUS; /**< 0x400140C8 */
sahilmgandhi 18:6a4db94011d3 287 union {
sahilmgandhi 18:6a4db94011d3 288 struct {
sahilmgandhi 18:6a4db94011d3 289 __IO uint32_t GAIN3:7;
sahilmgandhi 18:6a4db94011d3 290 __IO uint32_t PAD0:1;
sahilmgandhi 18:6a4db94011d3 291 __IO uint32_t GAIN2:7;
sahilmgandhi 18:6a4db94011d3 292 __IO uint32_t PAD1:1;
sahilmgandhi 18:6a4db94011d3 293 __IO uint32_t GAIN1:7;
sahilmgandhi 18:6a4db94011d3 294 __IO uint32_t PAD2:1;
sahilmgandhi 18:6a4db94011d3 295 __IO uint32_t GAIN0:7;
sahilmgandhi 18:6a4db94011d3 296 __IO uint32_t PAD3:1;
sahilmgandhi 18:6a4db94011d3 297 } BITS;
sahilmgandhi 18:6a4db94011d3 298 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 299 } AGC_GAIN_TABLE0; /**< 0x400140CC */
sahilmgandhi 18:6a4db94011d3 300 union {
sahilmgandhi 18:6a4db94011d3 301 struct {
sahilmgandhi 18:6a4db94011d3 302 __IO uint32_t GAIN7:7;
sahilmgandhi 18:6a4db94011d3 303 __IO uint32_t PAD0:1;
sahilmgandhi 18:6a4db94011d3 304 __IO uint32_t GAIN6:7;
sahilmgandhi 18:6a4db94011d3 305 __IO uint32_t PAD1:1;
sahilmgandhi 18:6a4db94011d3 306 __IO uint32_t GAIN5:7;
sahilmgandhi 18:6a4db94011d3 307 __IO uint32_t PAD2:1;
sahilmgandhi 18:6a4db94011d3 308 __IO uint32_t GAIN4:7;
sahilmgandhi 18:6a4db94011d3 309 __IO uint32_t PAD3:1;
sahilmgandhi 18:6a4db94011d3 310 } BITS;
sahilmgandhi 18:6a4db94011d3 311 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 312 } AGC_GAIN_TABLE1; /**< 0x400140D0 */
sahilmgandhi 18:6a4db94011d3 313 union {
sahilmgandhi 18:6a4db94011d3 314 struct {
sahilmgandhi 18:6a4db94011d3 315 __IO uint32_t GAIN11:7;
sahilmgandhi 18:6a4db94011d3 316 __IO uint32_t PAD0:1;
sahilmgandhi 18:6a4db94011d3 317 __IO uint32_t GAIN10:7;
sahilmgandhi 18:6a4db94011d3 318 __IO uint32_t PAD1:1;
sahilmgandhi 18:6a4db94011d3 319 __IO uint32_t GAIN9:7;
sahilmgandhi 18:6a4db94011d3 320 __IO uint32_t PAD2:1;
sahilmgandhi 18:6a4db94011d3 321 __IO uint32_t GAIN8:7;
sahilmgandhi 18:6a4db94011d3 322 __IO uint32_t PAD3:1;
sahilmgandhi 18:6a4db94011d3 323 } BITS;
sahilmgandhi 18:6a4db94011d3 324 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 325 } AGC_GAIN_TABLE2; /**< 0x400140D4 */
sahilmgandhi 18:6a4db94011d3 326 union {
sahilmgandhi 18:6a4db94011d3 327 struct {
sahilmgandhi 18:6a4db94011d3 328 __IO uint32_t GAIN15:7;
sahilmgandhi 18:6a4db94011d3 329 __IO uint32_t PAD0:1;
sahilmgandhi 18:6a4db94011d3 330 __IO uint32_t GAIN14:7;
sahilmgandhi 18:6a4db94011d3 331 __IO uint32_t PAD1:1;
sahilmgandhi 18:6a4db94011d3 332 __IO uint32_t GAIN13:7;
sahilmgandhi 18:6a4db94011d3 333 __IO uint32_t PAD2:1;
sahilmgandhi 18:6a4db94011d3 334 __IO uint32_t GAIN12:7;
sahilmgandhi 18:6a4db94011d3 335 __IO uint32_t PAD3:1;
sahilmgandhi 18:6a4db94011d3 336 } BITS;
sahilmgandhi 18:6a4db94011d3 337 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 338 } AGC_GAIN_TABLE3; /**< 0x400140D8 */
sahilmgandhi 18:6a4db94011d3 339 } MacHwReg_t, *MacHwReg_pt;
sahilmgandhi 18:6a4db94011d3 340
sahilmgandhi 18:6a4db94011d3 341 /** macHw register map (demodulator part) */
sahilmgandhi 18:6a4db94011d3 342 typedef struct {
sahilmgandhi 18:6a4db94011d3 343 union {
sahilmgandhi 18:6a4db94011d3 344 struct {
sahilmgandhi 18:6a4db94011d3 345 __IO uint32_t DRC:1; /**< Reserved */
sahilmgandhi 18:6a4db94011d3 346 __IO uint32_t SWIQ:1; /**< Compensation for quadrature polarity. (set to 1 for RevB) */
sahilmgandhi 18:6a4db94011d3 347 __IO uint32_t LIF:1; /**< Allows the receiver to use a low-IF frequency of +1.23 MHz (0) or -1.23 MHz (1). */
sahilmgandhi 18:6a4db94011d3 348 __IO uint32_t PM:1; /**< Preamble Mode: Mode 0 (high sensitivity) – Preamble detection is based on observation of a regular pattern of correlation peaks over a span of 5 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If 4 out of 5 symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode improves preamble detection rate by tolerating one corrupt correlation result in the span of 5 symbols. However, the relaxed detection rule allows a higher rate of false preamble detection when no signal is present. Mode 1 (low false detection) – Preamble detection is based on a span of 4 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If all four symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode enforces a more strict detection rule and therefore offers lower rate of false preamble detection at the expense of higher missed detection. */
sahilmgandhi 18:6a4db94011d3 349 __IO uint32_t ASM:1; /**< This bit determines whether antenna selection is automatic (1) or manual (0). For applications that do not use antenna diversity, this bit should be set to 0. */
sahilmgandhi 18:6a4db94011d3 350 __IO uint32_t AS:1; /**< If automatic antenna selection mode is used, this bit determines the initial antenna selection. If manual antenna selection mode is used, this bit determines the antenna selection, 0 or 1. */
sahilmgandhi 18:6a4db94011d3 351 __IO uint32_t DTC:1; /**< Sets the decay time constant used in the RSSI calculation and Digital Gain Control functions. 0: Time constant set to 1 symbol period. This produces a slower response time but more stable RSSI values. Not recommended for use with antenna diversity. 1: Time constant set to 1/4th of a symbol period. This produces a faster response with slightly more variance in the RSSI calculation. Recommended for most cases. */
sahilmgandhi 18:6a4db94011d3 352 __IO uint32_t PAD1:9;
sahilmgandhi 18:6a4db94011d3 353 __IO uint32_t DFR:16; /**<Selectively enables individual frequency offsets used during preamble search. Each of the 15 bits in this field corresponds to one of 15 different frequency offsets. A bit value of 0 removes a specific frequency offset from the search, while a bit value of 1 includes the frequency offset in the search. */
sahilmgandhi 18:6a4db94011d3 354 } BITS;
sahilmgandhi 18:6a4db94011d3 355 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 356 } DMD_CONTROL0; /**< 0x40014100 */
sahilmgandhi 18:6a4db94011d3 357 union {
sahilmgandhi 18:6a4db94011d3 358 struct {
sahilmgandhi 18:6a4db94011d3 359 __IO uint32_t DST:4; /**< This value specifies the SFD search period in symbols. After preamble detection, the demodulator begins symbol recovery and searches for the start-of-frame delimiter (SFD). If the SFD is not found within the number of symbols specified, the preamble detection flag is cleared and a new preamble search is initiated. The default value of 8 symbols should be sufficient for 802.15.4 compliant applications. Default 8 */
sahilmgandhi 18:6a4db94011d3 360 __IO uint32_t PAD0:4;
sahilmgandhi 18:6a4db94011d3 361 __IO uint32_t DPT:6; /**< The similarity criteria used for preamble detection includes a rule that all time index values must occupy a span equal to or less than this value. The default span of 0011 means that the correlation peaks must span a range of 3Ts, where Ts is the sample period = 0.25 µs. This value is recommended for typical multipath conditions. Very long-range applications may benefit from a higher value. Default 3 */
sahilmgandhi 18:6a4db94011d3 362 __IO uint32_t PAD1:2;
sahilmgandhi 18:6a4db94011d3 363 __IO uint32_t DPF:4; /**< The similarity criteria used for preamble detection includes a rule that all frequency index values must occupy a span equal to or less than this value. The default span of 0001 means that the difference between largest frequency index and smallest frequency index must be less than or equal to 1. Default 1 */
sahilmgandhi 18:6a4db94011d3 364 __IO uint32_t PAD2:4;
sahilmgandhi 18:6a4db94011d3 365 __IO uint32_t DCT:4; /**< In order for preamble detection to be declared, the correlation peaks must exceed a threshold. The threshold is computed dynamically and includes a programmable scale factor: 1 + bit[27]/2 + bit[26]/4 + bit[25]/8 + bit[24]/16 The default value of 1.5 is recommended for manual-antenna selection, while a value of 1.75 is recommended for automatic antenna selection. */
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 } BITS;
sahilmgandhi 18:6a4db94011d3 368 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 369 } DMD_CONTROL1; /**< 0x40014104 */
sahilmgandhi 18:6a4db94011d3 370 union {
sahilmgandhi 18:6a4db94011d3 371 struct {
sahilmgandhi 18:6a4db94011d3 372 __IO uint32_t RSSI_THRESHOLD:8; /**< Threshold value used to determine clear channel assessment (CCA) result. The channel is declared busy if RSSI > threshold. Default 0xFF */
sahilmgandhi 18:6a4db94011d3 373 __IO uint32_t RSSI_OFFSET:6; /**< Calibration constant added to the RSSI calculation. The 6-bit field is treated as a signed value in two’s complement format with values from -32 to +31 dB. */
sahilmgandhi 18:6a4db94011d3 374 } BITS;
sahilmgandhi 18:6a4db94011d3 375 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 376 } DMD_CONTROL2; /**< 0x40014108 */
sahilmgandhi 18:6a4db94011d3 377 union {
sahilmgandhi 18:6a4db94011d3 378 struct {
sahilmgandhi 18:6a4db94011d3 379 __I uint32_t RSSI_VALUE:8; /**< The value is captured at the end of packet reception or at the end of ED/CCA measurements and is interpreted in dBm as follows: 00000000 -> 0127dBm (or below) ... 01111111 -> 0dBm (or above) */
sahilmgandhi 18:6a4db94011d3 380 __I uint32_t FREQUENCY_OFFSET:4; /**< Frequency correction applied to the received packet. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
sahilmgandhi 18:6a4db94011d3 381 __I uint32_t ANT:1; /**< Antenna used for reception. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
sahilmgandhi 18:6a4db94011d3 382 __I uint32_t PAD0:3;
sahilmgandhi 18:6a4db94011d3 383 __I uint32_t RSSI_COMPONENT:4; /**< Magnitude of the baseband digital signal (units are dB relative to A/D saturation). The value is updated until AGC is frozen. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
sahilmgandhi 18:6a4db94011d3 384 } BITS;
sahilmgandhi 18:6a4db94011d3 385 __I uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 386 } DMD_STATUS; /**< 0x4001410C */
sahilmgandhi 18:6a4db94011d3 387 } DmdReg_t, *DmdReg_pt;
sahilmgandhi 18:6a4db94011d3 388
sahilmgandhi 18:6a4db94011d3 389 #endif /* MACHW_MAP_H_ */