MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralNames.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file peripheralnames.h
sahilmgandhi 18:6a4db94011d3 4 * @brief Implements an assertion.
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 0.1 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2015-11-07 $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup debug
sahilmgandhi 18:6a4db94011d3 28 */
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 #ifndef MBED_PERIPHERALNAMES_H
sahilmgandhi 18:6a4db94011d3 31 #define MBED_PERIPHERALNAMES_H
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 #include "memory_map.h" /* This is needed because enums use base adresses */
sahilmgandhi 18:6a4db94011d3 36 #include "PinNames.h"
sahilmgandhi 18:6a4db94011d3 37 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 38 extern "C" {
sahilmgandhi 18:6a4db94011d3 39 #endif
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 typedef enum {
sahilmgandhi 18:6a4db94011d3 42 ADC_0 = (int)ADCREG_BASE
sahilmgandhi 18:6a4db94011d3 43 } ADCName;
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 typedef enum {
sahilmgandhi 18:6a4db94011d3 46 UART_0 = (int)UART1REG_BASE,
sahilmgandhi 18:6a4db94011d3 47 UART_1 = (int)UART2REG_BASE,
sahilmgandhi 18:6a4db94011d3 48 } UARTName;
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 #define STDIO_UART_TX USBTX
sahilmgandhi 18:6a4db94011d3 51 #define STDIO_UART_RX USBRX
sahilmgandhi 18:6a4db94011d3 52 #define STDIO_UART UART_0
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 typedef enum {
sahilmgandhi 18:6a4db94011d3 55 SPI_0 = (int)SPI1REG_BASE,
sahilmgandhi 18:6a4db94011d3 56 SPI_1 = (int)SPI2REG_BASE
sahilmgandhi 18:6a4db94011d3 57 } SPIName;
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 typedef enum {
sahilmgandhi 18:6a4db94011d3 60 I2C_0 = (int)I2C1REG_BASE,
sahilmgandhi 18:6a4db94011d3 61 I2C_1 = (int)I2C2REG_BASE
sahilmgandhi 18:6a4db94011d3 62 } I2CName;
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 typedef enum {
sahilmgandhi 18:6a4db94011d3 65 PWM_0 = (int)PWMREG_BASE,
sahilmgandhi 18:6a4db94011d3 66 } PWMName;
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 69 }
sahilmgandhi 18:6a4db94011d3 70 #endif
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 #endif