MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <stdlib.h>
sahilmgandhi 18:6a4db94011d3 17 #include <string.h>
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "i2c_api.h"
sahilmgandhi 18:6a4db94011d3 20 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 21 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 #define LPC824_I2C0_FMPLUS 1
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 #if DEVICE_I2C
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 static const SWM_Map SWM_I2C_SDA[] = {
sahilmgandhi 18:6a4db94011d3 28 //PINASSIGN Register ID, Pinselect bitfield position
sahilmgandhi 18:6a4db94011d3 29 { 9, 8},
sahilmgandhi 18:6a4db94011d3 30 { 9, 24},
sahilmgandhi 18:6a4db94011d3 31 {10, 8},
sahilmgandhi 18:6a4db94011d3 32 };
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 static const SWM_Map SWM_I2C_SCL[] = {
sahilmgandhi 18:6a4db94011d3 35 //PINASSIGN Register ID, Pinselect bitfield position
sahilmgandhi 18:6a4db94011d3 36 { 9, 16},
sahilmgandhi 18:6a4db94011d3 37 {10, 0},
sahilmgandhi 18:6a4db94011d3 38 {10, 16},
sahilmgandhi 18:6a4db94011d3 39 };
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 static int i2c_used = 0;
sahilmgandhi 18:6a4db94011d3 43 static uint8_t repeated_start = 0;
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 #define I2C_DAT(x) (x->i2c->MSTDAT)
sahilmgandhi 18:6a4db94011d3 46 #define I2C_STAT(x) ((x->i2c->STAT >> 1) & (0x07))
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 static inline void i2c_power_enable(int ch)
sahilmgandhi 18:6a4db94011d3 49 {
sahilmgandhi 18:6a4db94011d3 50 switch(ch) {
sahilmgandhi 18:6a4db94011d3 51 case 0:
sahilmgandhi 18:6a4db94011d3 52 // I2C0, Same as for LPC812
sahilmgandhi 18:6a4db94011d3 53 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5);
sahilmgandhi 18:6a4db94011d3 54 LPC_SYSCON->PRESETCTRL &= ~(1 << 6);
sahilmgandhi 18:6a4db94011d3 55 LPC_SYSCON->PRESETCTRL |= (1 << 6);
sahilmgandhi 18:6a4db94011d3 56 break;
sahilmgandhi 18:6a4db94011d3 57 case 1:
sahilmgandhi 18:6a4db94011d3 58 case 2:
sahilmgandhi 18:6a4db94011d3 59 case 3:
sahilmgandhi 18:6a4db94011d3 60 // I2C1,I2C2 or I2C3. Not available for LPC812
sahilmgandhi 18:6a4db94011d3 61 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (20 + ch));
sahilmgandhi 18:6a4db94011d3 62 LPC_SYSCON->PRESETCTRL &= ~(1 << (13 + ch));
sahilmgandhi 18:6a4db94011d3 63 LPC_SYSCON->PRESETCTRL |= (1 << (13 + ch));
sahilmgandhi 18:6a4db94011d3 64 break;
sahilmgandhi 18:6a4db94011d3 65 default:
sahilmgandhi 18:6a4db94011d3 66 break;
sahilmgandhi 18:6a4db94011d3 67 }
sahilmgandhi 18:6a4db94011d3 68 }
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 static inline void i2c_interface_enable(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 72 obj->i2c->CFG |= (1 << 0); // Enable Master mode
sahilmgandhi 18:6a4db94011d3 73 // obj->i2c->CFG &= ~(1 << 1); // Disable Slave mode
sahilmgandhi 18:6a4db94011d3 74 }
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 static int get_available_i2c(void) {
sahilmgandhi 18:6a4db94011d3 78 int i;
sahilmgandhi 18:6a4db94011d3 79 for (i=0; i<3; i++) {
sahilmgandhi 18:6a4db94011d3 80 if ((i2c_used & (1 << i)) == 0)
sahilmgandhi 18:6a4db94011d3 81 return i+1;
sahilmgandhi 18:6a4db94011d3 82 }
sahilmgandhi 18:6a4db94011d3 83 return -1;
sahilmgandhi 18:6a4db94011d3 84 }
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
sahilmgandhi 18:6a4db94011d3 87 {
sahilmgandhi 18:6a4db94011d3 88 const SWM_Map *swm;
sahilmgandhi 18:6a4db94011d3 89 uint32_t regVal;
sahilmgandhi 18:6a4db94011d3 90 int i2c_ch = 0;
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 //LPC824
sahilmgandhi 18:6a4db94011d3 93 //I2C0 can support FM+ but only on P0_11 and P0_10
sahilmgandhi 18:6a4db94011d3 94 if (sda == I2C_SDA && scl == I2C_SCL) {
sahilmgandhi 18:6a4db94011d3 95 //Select I2C mode for P0_11 and P0_10
sahilmgandhi 18:6a4db94011d3 96 LPC_SWM->PINENABLE0 &= ~(0x3 << 11);
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 #if(LPC824_I2C0_FMPLUS == 1)
sahilmgandhi 18:6a4db94011d3 99 // Enable FM+ mode on P0_11, P0_10
sahilmgandhi 18:6a4db94011d3 100 LPC_IOCON->PIO0_10 &= ~(0x3 << 8);
sahilmgandhi 18:6a4db94011d3 101 LPC_IOCON->PIO0_10 |= (0x2 << 8); //FM+ mode
sahilmgandhi 18:6a4db94011d3 102 LPC_IOCON->PIO0_11 &= ~(0x3 << 8);
sahilmgandhi 18:6a4db94011d3 103 LPC_IOCON->PIO0_11 |= (0x2 << 8); //FM+ mode
sahilmgandhi 18:6a4db94011d3 104 #endif
sahilmgandhi 18:6a4db94011d3 105 }
sahilmgandhi 18:6a4db94011d3 106 else {
sahilmgandhi 18:6a4db94011d3 107 //Select any other pin for I2C1, I2C2 or I2C3
sahilmgandhi 18:6a4db94011d3 108 i2c_ch = get_available_i2c();
sahilmgandhi 18:6a4db94011d3 109 if (i2c_ch == -1)
sahilmgandhi 18:6a4db94011d3 110 return;
sahilmgandhi 18:6a4db94011d3 111 i2c_used |= (1 << (i2c_ch - 1));
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 swm = &SWM_I2C_SDA[i2c_ch - 1];
sahilmgandhi 18:6a4db94011d3 114 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 115 LPC_SWM->PINASSIGN[swm->n] = regVal | ((sda >> PIN_SHIFT) << swm->offset);
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 swm = &SWM_I2C_SCL[i2c_ch - 1];
sahilmgandhi 18:6a4db94011d3 118 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 119 LPC_SWM->PINASSIGN[swm->n] = regVal | ((scl >> PIN_SHIFT) << swm->offset);
sahilmgandhi 18:6a4db94011d3 120 }
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 switch(i2c_ch) {
sahilmgandhi 18:6a4db94011d3 123 case 0:
sahilmgandhi 18:6a4db94011d3 124 obj->i2c = (LPC_I2C0_Type *)LPC_I2C0;
sahilmgandhi 18:6a4db94011d3 125 break;
sahilmgandhi 18:6a4db94011d3 126 case 1:
sahilmgandhi 18:6a4db94011d3 127 obj->i2c = (LPC_I2C0_Type *)LPC_I2C1;
sahilmgandhi 18:6a4db94011d3 128 break;
sahilmgandhi 18:6a4db94011d3 129 case 2:
sahilmgandhi 18:6a4db94011d3 130 obj->i2c = (LPC_I2C0_Type *)LPC_I2C2;
sahilmgandhi 18:6a4db94011d3 131 break;
sahilmgandhi 18:6a4db94011d3 132 case 3:
sahilmgandhi 18:6a4db94011d3 133 obj->i2c = (LPC_I2C0_Type *)LPC_I2C3;
sahilmgandhi 18:6a4db94011d3 134 break;
sahilmgandhi 18:6a4db94011d3 135 default:
sahilmgandhi 18:6a4db94011d3 136 break;
sahilmgandhi 18:6a4db94011d3 137 }
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 // enable power
sahilmgandhi 18:6a4db94011d3 140 i2c_power_enable(i2c_ch);
sahilmgandhi 18:6a4db94011d3 141 // set default frequency at 100k
sahilmgandhi 18:6a4db94011d3 142 i2c_frequency(obj, 100000);
sahilmgandhi 18:6a4db94011d3 143 i2c_interface_enable(obj);
sahilmgandhi 18:6a4db94011d3 144 }
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 static inline int i2c_status(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 148 return I2C_STAT(obj);
sahilmgandhi 18:6a4db94011d3 149 }
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 // Wait until the Master Serial Interrupt (SI) is set
sahilmgandhi 18:6a4db94011d3 152 // Timeout when it takes too long.
sahilmgandhi 18:6a4db94011d3 153 static int i2c_wait_SI(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 154 int timeout = 0;
sahilmgandhi 18:6a4db94011d3 155 while (!(obj->i2c->STAT & (1 << 0))) {
sahilmgandhi 18:6a4db94011d3 156 timeout++;
sahilmgandhi 18:6a4db94011d3 157 if (timeout > 100000) return -1;
sahilmgandhi 18:6a4db94011d3 158 }
sahilmgandhi 18:6a4db94011d3 159 return 0;
sahilmgandhi 18:6a4db94011d3 160 }
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 //Attention. Spec says: First store Address in DAT before setting STA !
sahilmgandhi 18:6a4db94011d3 164 //Undefined state when using single byte I2C operations and too much delay
sahilmgandhi 18:6a4db94011d3 165 //between i2c_start and do_i2c_write(Address).
sahilmgandhi 18:6a4db94011d3 166 //Also note that lpc812/824 will immediately continue reading a byte when Address b0 == 1
sahilmgandhi 18:6a4db94011d3 167 inline int i2c_start(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 168 int status = 0;
sahilmgandhi 18:6a4db94011d3 169 if (repeated_start) {
sahilmgandhi 18:6a4db94011d3 170 obj->i2c->MSTCTL = (1 << 1) | (1 << 0); // STA bit and Continue bit to complete previous RD or WR
sahilmgandhi 18:6a4db94011d3 171 repeated_start = 0;
sahilmgandhi 18:6a4db94011d3 172 } else {
sahilmgandhi 18:6a4db94011d3 173 obj->i2c->MSTCTL = (1 << 1); // STA bit
sahilmgandhi 18:6a4db94011d3 174 }
sahilmgandhi 18:6a4db94011d3 175 return status;
sahilmgandhi 18:6a4db94011d3 176 }
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 //Generate Stop condition and wait until bus is Idle
sahilmgandhi 18:6a4db94011d3 179 //Will also send NAK for previous RD
sahilmgandhi 18:6a4db94011d3 180 inline int i2c_stop(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 181 int timeout = 0;
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 // STP bit and Continue bit. Sends NAK to complete previous RD
sahilmgandhi 18:6a4db94011d3 184 obj->i2c->MSTCTL = (1 << 2) | (1 << 0);
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 //Spin until Ready (b0 == 1)and Status is Idle (b3..b1 == 000)
sahilmgandhi 18:6a4db94011d3 187 while ((obj->i2c->STAT & ((7 << 1) | (1 << 0))) != ((0 << 1) | (1 << 0))) {
sahilmgandhi 18:6a4db94011d3 188 timeout ++;
sahilmgandhi 18:6a4db94011d3 189 if (timeout > 100000) return 1;
sahilmgandhi 18:6a4db94011d3 190 }
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 // repeated_start = 0; // bus free
sahilmgandhi 18:6a4db94011d3 193 return 0;
sahilmgandhi 18:6a4db94011d3 194 }
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 //Spec says: first check Idle and status is Ok
sahilmgandhi 18:6a4db94011d3 197 static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
sahilmgandhi 18:6a4db94011d3 198 // write the data
sahilmgandhi 18:6a4db94011d3 199 I2C_DAT(obj) = value;
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 if (!addr)
sahilmgandhi 18:6a4db94011d3 202 obj->i2c->MSTCTL = (1 << 0); //Set continue for data. Should not be set for addr since that uses STA
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204 // wait and return status
sahilmgandhi 18:6a4db94011d3 205 i2c_wait_SI(obj);
sahilmgandhi 18:6a4db94011d3 206 return i2c_status(obj);
sahilmgandhi 18:6a4db94011d3 207 }
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 //Attention, correct Order: wait for data ready, read data, read status, continue, return
sahilmgandhi 18:6a4db94011d3 211 //Dont read DAT or STAT when not ready, so dont read after setting continue.
sahilmgandhi 18:6a4db94011d3 212 //Results may be invalid when next read is underway.
sahilmgandhi 18:6a4db94011d3 213 static inline int i2c_do_read(i2c_t *obj, int last) {
sahilmgandhi 18:6a4db94011d3 214 // wait for it to arrive
sahilmgandhi 18:6a4db94011d3 215 i2c_wait_SI(obj);
sahilmgandhi 18:6a4db94011d3 216 if (!last)
sahilmgandhi 18:6a4db94011d3 217 obj->i2c->MSTCTL = (1 << 0); //ACK and Continue
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 // return the data
sahilmgandhi 18:6a4db94011d3 220 return (I2C_DAT(obj) & 0xFF);
sahilmgandhi 18:6a4db94011d3 221 }
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223
sahilmgandhi 18:6a4db94011d3 224 void i2c_frequency(i2c_t *obj, int hz) {
sahilmgandhi 18:6a4db94011d3 225 // No peripheral clock divider on the M0
sahilmgandhi 18:6a4db94011d3 226 uint32_t PCLK = SystemCoreClock;
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 uint32_t clkdiv = PCLK / (hz * 4) - 1;
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 obj->i2c->CLKDIV = clkdiv;
sahilmgandhi 18:6a4db94011d3 231 obj->i2c->MSTTIME = 0;
sahilmgandhi 18:6a4db94011d3 232 }
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 // The I2C does a read or a write as a whole operation
sahilmgandhi 18:6a4db94011d3 235 // There are two types of error conditions it can encounter
sahilmgandhi 18:6a4db94011d3 236 // 1) it can not obtain the bus
sahilmgandhi 18:6a4db94011d3 237 // 2) it gets error responses at part of the transmission
sahilmgandhi 18:6a4db94011d3 238 //
sahilmgandhi 18:6a4db94011d3 239 // We tackle them as follows:
sahilmgandhi 18:6a4db94011d3 240 // 1) we retry until we get the bus. we could have a "timeout" if we can not get it
sahilmgandhi 18:6a4db94011d3 241 // which basically turns it in to a 2)
sahilmgandhi 18:6a4db94011d3 242 // 2) on error, we use the standard error mechanisms to report/debug
sahilmgandhi 18:6a4db94011d3 243 //
sahilmgandhi 18:6a4db94011d3 244 // Therefore an I2C transaction should always complete. If it doesn't it is usually
sahilmgandhi 18:6a4db94011d3 245 // because something is setup wrong (e.g. wiring), and we don't need to programatically
sahilmgandhi 18:6a4db94011d3 246 // check for that
sahilmgandhi 18:6a4db94011d3 247 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
sahilmgandhi 18:6a4db94011d3 248 int count, status;
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 //Store the address+RD and then generate STA
sahilmgandhi 18:6a4db94011d3 251 I2C_DAT(obj) = address | 0x01;
sahilmgandhi 18:6a4db94011d3 252 i2c_start(obj);
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 // Wait for completion of STA and Sending of SlaveAddress+RD and first Read byte
sahilmgandhi 18:6a4db94011d3 255 i2c_wait_SI(obj);
sahilmgandhi 18:6a4db94011d3 256 status = i2c_status(obj);
sahilmgandhi 18:6a4db94011d3 257 if (status == 0x03) { // NAK on SlaveAddress
sahilmgandhi 18:6a4db94011d3 258 i2c_stop(obj);
sahilmgandhi 18:6a4db94011d3 259 return I2C_ERROR_NO_SLAVE;
sahilmgandhi 18:6a4db94011d3 260 }
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 // Read in all except last byte
sahilmgandhi 18:6a4db94011d3 263 for (count = 0; count < (length-1); count++) {
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 // Wait for it to arrive, note that first byte read after address+RD is already waiting
sahilmgandhi 18:6a4db94011d3 266 i2c_wait_SI(obj);
sahilmgandhi 18:6a4db94011d3 267 status = i2c_status(obj);
sahilmgandhi 18:6a4db94011d3 268 if (status != 0x01) { // RX RDY
sahilmgandhi 18:6a4db94011d3 269 i2c_stop(obj);
sahilmgandhi 18:6a4db94011d3 270 return count;
sahilmgandhi 18:6a4db94011d3 271 }
sahilmgandhi 18:6a4db94011d3 272 data[count] = I2C_DAT(obj) & 0xFF; // Store read byte
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 obj->i2c->MSTCTL = (1 << 0); // Send ACK and Continue to read
sahilmgandhi 18:6a4db94011d3 275 }
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 // Read final byte
sahilmgandhi 18:6a4db94011d3 278 // Wait for it to arrive
sahilmgandhi 18:6a4db94011d3 279 i2c_wait_SI(obj);
sahilmgandhi 18:6a4db94011d3 280
sahilmgandhi 18:6a4db94011d3 281 status = i2c_status(obj);
sahilmgandhi 18:6a4db94011d3 282 if (status != 0x01) { // RX RDY
sahilmgandhi 18:6a4db94011d3 283 i2c_stop(obj);
sahilmgandhi 18:6a4db94011d3 284 return count;
sahilmgandhi 18:6a4db94011d3 285 }
sahilmgandhi 18:6a4db94011d3 286 data[count] = I2C_DAT(obj) & 0xFF; // Store final read byte
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 // If not repeated start, send stop.
sahilmgandhi 18:6a4db94011d3 289 if (stop) {
sahilmgandhi 18:6a4db94011d3 290 i2c_stop(obj); // Also sends NAK for last read byte
sahilmgandhi 18:6a4db94011d3 291 } else {
sahilmgandhi 18:6a4db94011d3 292 repeated_start = 1;
sahilmgandhi 18:6a4db94011d3 293 }
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 return length;
sahilmgandhi 18:6a4db94011d3 296 }
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
sahilmgandhi 18:6a4db94011d3 300 int i, status;
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 //Store the address+/WR and then generate STA
sahilmgandhi 18:6a4db94011d3 303 I2C_DAT(obj) = address & 0xFE;
sahilmgandhi 18:6a4db94011d3 304 i2c_start(obj);
sahilmgandhi 18:6a4db94011d3 305
sahilmgandhi 18:6a4db94011d3 306 // Wait for completion of STA and Sending of SlaveAddress+/WR
sahilmgandhi 18:6a4db94011d3 307 i2c_wait_SI(obj);
sahilmgandhi 18:6a4db94011d3 308 status = i2c_status(obj);
sahilmgandhi 18:6a4db94011d3 309 if (status == 0x03) { // NAK SlaveAddress
sahilmgandhi 18:6a4db94011d3 310 i2c_stop(obj);
sahilmgandhi 18:6a4db94011d3 311 return I2C_ERROR_NO_SLAVE;
sahilmgandhi 18:6a4db94011d3 312 }
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 //Write all bytes
sahilmgandhi 18:6a4db94011d3 315 for (i=0; i<length; i++) {
sahilmgandhi 18:6a4db94011d3 316 status = i2c_do_write(obj, data[i], 0);
sahilmgandhi 18:6a4db94011d3 317 if (status != 0x02) { // TX RDY. Handles a Slave NAK on datawrite
sahilmgandhi 18:6a4db94011d3 318 i2c_stop(obj);
sahilmgandhi 18:6a4db94011d3 319 return i;
sahilmgandhi 18:6a4db94011d3 320 }
sahilmgandhi 18:6a4db94011d3 321 }
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 // If not repeated start, send stop.
sahilmgandhi 18:6a4db94011d3 324 if (stop) {
sahilmgandhi 18:6a4db94011d3 325 i2c_stop(obj);
sahilmgandhi 18:6a4db94011d3 326 } else {
sahilmgandhi 18:6a4db94011d3 327 repeated_start = 1;
sahilmgandhi 18:6a4db94011d3 328 }
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 return length;
sahilmgandhi 18:6a4db94011d3 331 }
sahilmgandhi 18:6a4db94011d3 332
sahilmgandhi 18:6a4db94011d3 333 void i2c_reset(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 334 i2c_stop(obj);
sahilmgandhi 18:6a4db94011d3 335 }
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 int i2c_byte_read(i2c_t *obj, int last) {
sahilmgandhi 18:6a4db94011d3 338 return (i2c_do_read(obj, last) & 0xFF);
sahilmgandhi 18:6a4db94011d3 339 // return (i2c_do_read(obj, last, 0) & 0xFF);
sahilmgandhi 18:6a4db94011d3 340 }
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 int i2c_byte_write(i2c_t *obj, int data) {
sahilmgandhi 18:6a4db94011d3 343 int ack;
sahilmgandhi 18:6a4db94011d3 344 int status = i2c_do_write(obj, (data & 0xFF), 0);
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 switch(status) {
sahilmgandhi 18:6a4db94011d3 347 case 2: // TX RDY. Handles a Slave NAK on datawrite
sahilmgandhi 18:6a4db94011d3 348 ack = 1;
sahilmgandhi 18:6a4db94011d3 349 break;
sahilmgandhi 18:6a4db94011d3 350 default:
sahilmgandhi 18:6a4db94011d3 351 ack = 0;
sahilmgandhi 18:6a4db94011d3 352 break;
sahilmgandhi 18:6a4db94011d3 353 }
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 return ack;
sahilmgandhi 18:6a4db94011d3 356 }
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358
sahilmgandhi 18:6a4db94011d3 359 #if DEVICE_I2CSLAVE
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 #define I2C_SLVDAT(x) (x->i2c->SLVDAT)
sahilmgandhi 18:6a4db94011d3 362 #define I2C_SLVSTAT(x) ((x->i2c->STAT >> 9) & (0x03))
sahilmgandhi 18:6a4db94011d3 363 #define I2C_SLVSI(x) ((x->i2c->STAT >> 8) & (0x01))
sahilmgandhi 18:6a4db94011d3 364 //#define I2C_SLVCNT(x) (x->i2c->SLVCTL = (1 << 0))
sahilmgandhi 18:6a4db94011d3 365 //#define I2C_SLVNAK(x) (x->i2c->SLVCTL = (1 << 1))
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 #if(0)
sahilmgandhi 18:6a4db94011d3 368 // Wait until the Slave Serial Interrupt (SI) is set
sahilmgandhi 18:6a4db94011d3 369 // Timeout when it takes too long.
sahilmgandhi 18:6a4db94011d3 370 static int i2c_wait_slave_SI(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 371 int timeout = 0;
sahilmgandhi 18:6a4db94011d3 372 while (!(obj->i2c->STAT & (1 << 8))) {
sahilmgandhi 18:6a4db94011d3 373 timeout++;
sahilmgandhi 18:6a4db94011d3 374 if (timeout > 100000) return -1;
sahilmgandhi 18:6a4db94011d3 375 }
sahilmgandhi 18:6a4db94011d3 376 return 0;
sahilmgandhi 18:6a4db94011d3 377 }
sahilmgandhi 18:6a4db94011d3 378 #endif
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 if (enable_slave) {
sahilmgandhi 18:6a4db94011d3 383 // obj->i2c->CFG &= ~(1 << 0); //Disable Master mode
sahilmgandhi 18:6a4db94011d3 384 obj->i2c->CFG |= (1 << 1); //Enable Slave mode
sahilmgandhi 18:6a4db94011d3 385 }
sahilmgandhi 18:6a4db94011d3 386 else {
sahilmgandhi 18:6a4db94011d3 387 // obj->i2c->CFG |= (1 << 0); //Enable Master mode
sahilmgandhi 18:6a4db94011d3 388 obj->i2c->CFG &= ~(1 << 1); //Disable Slave mode
sahilmgandhi 18:6a4db94011d3 389 }
sahilmgandhi 18:6a4db94011d3 390 }
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 // Wait for next I2C event and find out what is going on
sahilmgandhi 18:6a4db94011d3 393 //
sahilmgandhi 18:6a4db94011d3 394 int i2c_slave_receive(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 395 int addr;
sahilmgandhi 18:6a4db94011d3 396
sahilmgandhi 18:6a4db94011d3 397 // Check if there is any data pending
sahilmgandhi 18:6a4db94011d3 398 if (! I2C_SLVSI(obj)) {
sahilmgandhi 18:6a4db94011d3 399 return 0; //NoData
sahilmgandhi 18:6a4db94011d3 400 };
sahilmgandhi 18:6a4db94011d3 401
sahilmgandhi 18:6a4db94011d3 402 // Check State
sahilmgandhi 18:6a4db94011d3 403 switch(I2C_SLVSTAT(obj)) {
sahilmgandhi 18:6a4db94011d3 404 case 0x0: // Slave address plus R/W received
sahilmgandhi 18:6a4db94011d3 405 // At least one of the four slave addresses has been matched by hardware.
sahilmgandhi 18:6a4db94011d3 406 // You can figure out which address by checking Slave address match Index in STAT register.
sahilmgandhi 18:6a4db94011d3 407
sahilmgandhi 18:6a4db94011d3 408 // Get the received address
sahilmgandhi 18:6a4db94011d3 409 addr = I2C_SLVDAT(obj) & 0xFF;
sahilmgandhi 18:6a4db94011d3 410 // Send ACK on address and Continue
sahilmgandhi 18:6a4db94011d3 411 obj->i2c->SLVCTL = (1 << 0);
sahilmgandhi 18:6a4db94011d3 412
sahilmgandhi 18:6a4db94011d3 413 if (addr == 0x00) {
sahilmgandhi 18:6a4db94011d3 414 return 2; //WriteGeneral
sahilmgandhi 18:6a4db94011d3 415 }
sahilmgandhi 18:6a4db94011d3 416 //check the RW bit
sahilmgandhi 18:6a4db94011d3 417 if ((addr & 0x01) == 0x01) {
sahilmgandhi 18:6a4db94011d3 418 return 1; //ReadAddressed
sahilmgandhi 18:6a4db94011d3 419 }
sahilmgandhi 18:6a4db94011d3 420 else {
sahilmgandhi 18:6a4db94011d3 421 return 3; //WriteAddressed
sahilmgandhi 18:6a4db94011d3 422 }
sahilmgandhi 18:6a4db94011d3 423 //break;
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
sahilmgandhi 18:6a4db94011d3 426 // Oops, should never get here...
sahilmgandhi 18:6a4db94011d3 427 obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data, try to recover...
sahilmgandhi 18:6a4db94011d3 428 return 0; //NoData
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
sahilmgandhi 18:6a4db94011d3 431 // Oops, should never get here...
sahilmgandhi 18:6a4db94011d3 432 I2C_SLVDAT(obj) = 0xFF; // Send dummy data for transmission
sahilmgandhi 18:6a4db94011d3 433 obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover...
sahilmgandhi 18:6a4db94011d3 434 return 0; //NoData
sahilmgandhi 18:6a4db94011d3 435
sahilmgandhi 18:6a4db94011d3 436 case 0x3: // Reserved.
sahilmgandhi 18:6a4db94011d3 437 default: // Oops, should never get here...
sahilmgandhi 18:6a4db94011d3 438 obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover...
sahilmgandhi 18:6a4db94011d3 439 return 0; //NoData
sahilmgandhi 18:6a4db94011d3 440 //break;
sahilmgandhi 18:6a4db94011d3 441 } //switch status
sahilmgandhi 18:6a4db94011d3 442 }
sahilmgandhi 18:6a4db94011d3 443
sahilmgandhi 18:6a4db94011d3 444 // The dedicated I2C Slave byte read and byte write functions need to be called
sahilmgandhi 18:6a4db94011d3 445 // from 'common' mbed I2CSlave API for devices that have separate Master and
sahilmgandhi 18:6a4db94011d3 446 // Slave engines such as the lpc812 and lpc1549.
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 //Called when Slave is addressed for Write, Slave will receive Data in polling mode
sahilmgandhi 18:6a4db94011d3 449 //Parameter last=1 means received byte will be NACKed.
sahilmgandhi 18:6a4db94011d3 450 int i2c_slave_byte_read(i2c_t *obj, int last) {
sahilmgandhi 18:6a4db94011d3 451 int data;
sahilmgandhi 18:6a4db94011d3 452
sahilmgandhi 18:6a4db94011d3 453 // Wait for data
sahilmgandhi 18:6a4db94011d3 454 while (!I2C_SLVSI(obj)); // Wait forever
sahilmgandhi 18:6a4db94011d3 455 //if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 // Dont bother to check State, were not returning it anyhow..
sahilmgandhi 18:6a4db94011d3 458 //if (I2C_SLVSTAT(obj)) == 0x01) {
sahilmgandhi 18:6a4db94011d3 459 // Slave receive. Received data is available (Slave Receiver mode).
sahilmgandhi 18:6a4db94011d3 460 //};
sahilmgandhi 18:6a4db94011d3 461
sahilmgandhi 18:6a4db94011d3 462 data = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data
sahilmgandhi 18:6a4db94011d3 463 if (last) {
sahilmgandhi 18:6a4db94011d3 464 obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data and Continue
sahilmgandhi 18:6a4db94011d3 465 }
sahilmgandhi 18:6a4db94011d3 466 else {
sahilmgandhi 18:6a4db94011d3 467 obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read
sahilmgandhi 18:6a4db94011d3 468 }
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 return data;
sahilmgandhi 18:6a4db94011d3 471 }
sahilmgandhi 18:6a4db94011d3 472
sahilmgandhi 18:6a4db94011d3 473
sahilmgandhi 18:6a4db94011d3 474 //Called when Slave is addressed for Read, Slave will send Data in polling mode
sahilmgandhi 18:6a4db94011d3 475 //
sahilmgandhi 18:6a4db94011d3 476 int i2c_slave_byte_write(i2c_t *obj, int data) {
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 // Wait until Ready
sahilmgandhi 18:6a4db94011d3 479 while (!I2C_SLVSI(obj)); // Wait forever
sahilmgandhi 18:6a4db94011d3 480 // if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
sahilmgandhi 18:6a4db94011d3 481
sahilmgandhi 18:6a4db94011d3 482 // Check State
sahilmgandhi 18:6a4db94011d3 483 switch(I2C_SLVSTAT(obj)) {
sahilmgandhi 18:6a4db94011d3 484 case 0x0: // Slave address plus R/W received
sahilmgandhi 18:6a4db94011d3 485 // At least one of the four slave addresses has been matched by hardware.
sahilmgandhi 18:6a4db94011d3 486 // You can figure out which address by checking Slave address match Index in STAT register.
sahilmgandhi 18:6a4db94011d3 487 // I2C Restart occurred
sahilmgandhi 18:6a4db94011d3 488 return -1;
sahilmgandhi 18:6a4db94011d3 489 //break;
sahilmgandhi 18:6a4db94011d3 490 case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
sahilmgandhi 18:6a4db94011d3 491 // Should not get here...
sahilmgandhi 18:6a4db94011d3 492 return -2;
sahilmgandhi 18:6a4db94011d3 493 //break;
sahilmgandhi 18:6a4db94011d3 494 case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
sahilmgandhi 18:6a4db94011d3 495 I2C_SLVDAT(obj) = data & 0xFF; // Store the data for transmission
sahilmgandhi 18:6a4db94011d3 496 obj->i2c->SLVCTL = (1 << 0); // Continue to send
sahilmgandhi 18:6a4db94011d3 497
sahilmgandhi 18:6a4db94011d3 498 return 1;
sahilmgandhi 18:6a4db94011d3 499 //break;
sahilmgandhi 18:6a4db94011d3 500 case 0x3: // Reserved.
sahilmgandhi 18:6a4db94011d3 501 default:
sahilmgandhi 18:6a4db94011d3 502 // Should not get here...
sahilmgandhi 18:6a4db94011d3 503 return -3;
sahilmgandhi 18:6a4db94011d3 504 //break;
sahilmgandhi 18:6a4db94011d3 505 } // switch status
sahilmgandhi 18:6a4db94011d3 506 }
sahilmgandhi 18:6a4db94011d3 507
sahilmgandhi 18:6a4db94011d3 508
sahilmgandhi 18:6a4db94011d3 509 //Called when Slave is addressed for Write, Slave will receive Data in polling mode
sahilmgandhi 18:6a4db94011d3 510 //Parameter length (>=1) is the maximum allowable number of bytes. All bytes will be ACKed.
sahilmgandhi 18:6a4db94011d3 511 int i2c_slave_read(i2c_t *obj, char *data, int length) {
sahilmgandhi 18:6a4db94011d3 512 int count=0;
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514 // Read and ACK all expected bytes
sahilmgandhi 18:6a4db94011d3 515 while (count < length) {
sahilmgandhi 18:6a4db94011d3 516 // Wait for data
sahilmgandhi 18:6a4db94011d3 517 while (!I2C_SLVSI(obj)); // Wait forever
sahilmgandhi 18:6a4db94011d3 518 // if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
sahilmgandhi 18:6a4db94011d3 519
sahilmgandhi 18:6a4db94011d3 520 // Check State
sahilmgandhi 18:6a4db94011d3 521 switch(I2C_SLVSTAT(obj)) {
sahilmgandhi 18:6a4db94011d3 522 case 0x0: // Slave address plus R/W received
sahilmgandhi 18:6a4db94011d3 523 // At least one of the four slave addresses has been matched by hardware.
sahilmgandhi 18:6a4db94011d3 524 // You can figure out which address by checking Slave address match Index in STAT register.
sahilmgandhi 18:6a4db94011d3 525 // I2C Restart occurred
sahilmgandhi 18:6a4db94011d3 526 return -1;
sahilmgandhi 18:6a4db94011d3 527 //break;
sahilmgandhi 18:6a4db94011d3 528
sahilmgandhi 18:6a4db94011d3 529 case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
sahilmgandhi 18:6a4db94011d3 530 data[count] = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data
sahilmgandhi 18:6a4db94011d3 531 obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read
sahilmgandhi 18:6a4db94011d3 532 break;
sahilmgandhi 18:6a4db94011d3 533
sahilmgandhi 18:6a4db94011d3 534 case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
sahilmgandhi 18:6a4db94011d3 535 case 0x3: // Reserved.
sahilmgandhi 18:6a4db94011d3 536 default: // Should never get here...
sahilmgandhi 18:6a4db94011d3 537 return -2;
sahilmgandhi 18:6a4db94011d3 538 //break;
sahilmgandhi 18:6a4db94011d3 539 } // switch status
sahilmgandhi 18:6a4db94011d3 540
sahilmgandhi 18:6a4db94011d3 541 count++;
sahilmgandhi 18:6a4db94011d3 542 } // for all bytes
sahilmgandhi 18:6a4db94011d3 543
sahilmgandhi 18:6a4db94011d3 544 return count; // Received the expected number of bytes
sahilmgandhi 18:6a4db94011d3 545 }
sahilmgandhi 18:6a4db94011d3 546
sahilmgandhi 18:6a4db94011d3 547
sahilmgandhi 18:6a4db94011d3 548 //Called when Slave is addressed for Read, Slave will send Data in polling mode
sahilmgandhi 18:6a4db94011d3 549 //Parameter length (>=1) is the maximum number of bytes. Exit when Slave byte is NACKed.
sahilmgandhi 18:6a4db94011d3 550 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
sahilmgandhi 18:6a4db94011d3 551 int count;
sahilmgandhi 18:6a4db94011d3 552
sahilmgandhi 18:6a4db94011d3 553 // Send and all bytes or Exit on NAK
sahilmgandhi 18:6a4db94011d3 554 for (count=0; count < length; count++) {
sahilmgandhi 18:6a4db94011d3 555 // Wait until Ready for data
sahilmgandhi 18:6a4db94011d3 556 while (!I2C_SLVSI(obj)); // Wait forever
sahilmgandhi 18:6a4db94011d3 557 // if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559 // Check State
sahilmgandhi 18:6a4db94011d3 560 switch(I2C_SLVSTAT(obj)) {
sahilmgandhi 18:6a4db94011d3 561 case 0x0: // Slave address plus R/W received
sahilmgandhi 18:6a4db94011d3 562 // At least one of the four slave addresses has been matched by hardware.
sahilmgandhi 18:6a4db94011d3 563 // You can figure out which address by checking Slave address match Index in STAT register.
sahilmgandhi 18:6a4db94011d3 564 // I2C Restart occurred
sahilmgandhi 18:6a4db94011d3 565 return -1;
sahilmgandhi 18:6a4db94011d3 566 //break;
sahilmgandhi 18:6a4db94011d3 567 case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
sahilmgandhi 18:6a4db94011d3 568 // Should not get here...
sahilmgandhi 18:6a4db94011d3 569 return -2;
sahilmgandhi 18:6a4db94011d3 570 //break;
sahilmgandhi 18:6a4db94011d3 571 case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
sahilmgandhi 18:6a4db94011d3 572 I2C_SLVDAT(obj) = data[count] & 0xFF; // Store the data for transmission
sahilmgandhi 18:6a4db94011d3 573 obj->i2c->SLVCTL = (1 << 0); // Continue to send
sahilmgandhi 18:6a4db94011d3 574 break;
sahilmgandhi 18:6a4db94011d3 575 case 0x3: // Reserved.
sahilmgandhi 18:6a4db94011d3 576 default:
sahilmgandhi 18:6a4db94011d3 577 // Should not get here...
sahilmgandhi 18:6a4db94011d3 578 return -3;
sahilmgandhi 18:6a4db94011d3 579 //break;
sahilmgandhi 18:6a4db94011d3 580 } // switch status
sahilmgandhi 18:6a4db94011d3 581 } // for all bytes
sahilmgandhi 18:6a4db94011d3 582
sahilmgandhi 18:6a4db94011d3 583 return length; // Transmitted the max number of bytes
sahilmgandhi 18:6a4db94011d3 584 }
sahilmgandhi 18:6a4db94011d3 585
sahilmgandhi 18:6a4db94011d3 586
sahilmgandhi 18:6a4db94011d3 587 // Set the four slave addresses.
sahilmgandhi 18:6a4db94011d3 588 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
sahilmgandhi 18:6a4db94011d3 589 obj->i2c->SLVADR0 = (address & 0xFE); // Store address in address 0 register
sahilmgandhi 18:6a4db94011d3 590 obj->i2c->SLVADR1 = (0x00 & 0xFE); // Store general call write address in address 1 register
sahilmgandhi 18:6a4db94011d3 591 obj->i2c->SLVADR2 = (0x01); // Disable address 2 register
sahilmgandhi 18:6a4db94011d3 592 obj->i2c->SLVADR3 = (0x01); // Disable address 3 register
sahilmgandhi 18:6a4db94011d3 593 obj->i2c->SLVQUAL0 = (mask & 0xFE); // Qualifier mask for address 0 register. Any maskbit that is 1 will always be a match
sahilmgandhi 18:6a4db94011d3 594 }
sahilmgandhi 18:6a4db94011d3 595
sahilmgandhi 18:6a4db94011d3 596 #endif
sahilmgandhi 18:6a4db94011d3 597
sahilmgandhi 18:6a4db94011d3 598 #endif