Mouse code for the MacroRat
mbed-dev/targets/TARGET_NXP/TARGET_LPC82X/device/LPC82x.h@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | |
sahilmgandhi | 18:6a4db94011d3 | 2 | /****************************************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @file LPC82x.h |
sahilmgandhi | 18:6a4db94011d3 | 4 | * |
sahilmgandhi | 18:6a4db94011d3 | 5 | * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for |
sahilmgandhi | 18:6a4db94011d3 | 6 | * LPC82x from . |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * @version V0.4 |
sahilmgandhi | 18:6a4db94011d3 | 9 | * @date 17. June 2014 |
sahilmgandhi | 18:6a4db94011d3 | 10 | * |
sahilmgandhi | 18:6a4db94011d3 | 11 | * @note Generated with SVDConv V2.80 |
sahilmgandhi | 18:6a4db94011d3 | 12 | * from CMSIS SVD File 'LPC82x.svd' Version 0.4, |
sahilmgandhi | 18:6a4db94011d3 | 13 | *******************************************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 14 | |
sahilmgandhi | 18:6a4db94011d3 | 15 | |
sahilmgandhi | 18:6a4db94011d3 | 16 | |
sahilmgandhi | 18:6a4db94011d3 | 17 | /** @addtogroup (null) |
sahilmgandhi | 18:6a4db94011d3 | 18 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 19 | */ |
sahilmgandhi | 18:6a4db94011d3 | 20 | |
sahilmgandhi | 18:6a4db94011d3 | 21 | /** @addtogroup LPC82x |
sahilmgandhi | 18:6a4db94011d3 | 22 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 23 | */ |
sahilmgandhi | 18:6a4db94011d3 | 24 | |
sahilmgandhi | 18:6a4db94011d3 | 25 | #ifndef LPC82X_H |
sahilmgandhi | 18:6a4db94011d3 | 26 | #define LPC82X_H |
sahilmgandhi | 18:6a4db94011d3 | 27 | |
sahilmgandhi | 18:6a4db94011d3 | 28 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 29 | extern "C" { |
sahilmgandhi | 18:6a4db94011d3 | 30 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 31 | |
sahilmgandhi | 18:6a4db94011d3 | 32 | |
sahilmgandhi | 18:6a4db94011d3 | 33 | /* ------------------------- Interrupt Number Definition ------------------------ */ |
sahilmgandhi | 18:6a4db94011d3 | 34 | |
sahilmgandhi | 18:6a4db94011d3 | 35 | typedef enum { |
sahilmgandhi | 18:6a4db94011d3 | 36 | /* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */ |
sahilmgandhi | 18:6a4db94011d3 | 37 | Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ |
sahilmgandhi | 18:6a4db94011d3 | 38 | NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ |
sahilmgandhi | 18:6a4db94011d3 | 39 | HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ |
sahilmgandhi | 18:6a4db94011d3 | 40 | SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ |
sahilmgandhi | 18:6a4db94011d3 | 41 | DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ |
sahilmgandhi | 18:6a4db94011d3 | 42 | PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ |
sahilmgandhi | 18:6a4db94011d3 | 43 | SysTick_IRQn = -1, /*!< 15 System Tick Timer */ |
sahilmgandhi | 18:6a4db94011d3 | 44 | /* ---------------------- LPC82x Specific Interrupt Numbers --------------------- */ |
sahilmgandhi | 18:6a4db94011d3 | 45 | SPI0_IRQn = 0, /*!< 0 SPI0 */ |
sahilmgandhi | 18:6a4db94011d3 | 46 | SPI1_IRQn = 1, /*!< 1 SPI1 */ |
sahilmgandhi | 18:6a4db94011d3 | 47 | UART0_IRQn = 3, /*!< 3 UART0 */ |
sahilmgandhi | 18:6a4db94011d3 | 48 | UART1_IRQn = 4, /*!< 4 UART1 */ |
sahilmgandhi | 18:6a4db94011d3 | 49 | UART2_IRQn = 5, /*!< 5 UART2 */ |
sahilmgandhi | 18:6a4db94011d3 | 50 | I2C1_IRQn = 7, /*!< 7 I2C1 */ |
sahilmgandhi | 18:6a4db94011d3 | 51 | I2C0_IRQn = 8, /*!< 8 I2C0 */ |
sahilmgandhi | 18:6a4db94011d3 | 52 | SCT_IRQn = 9, /*!< 9 SCT */ |
sahilmgandhi | 18:6a4db94011d3 | 53 | MRT_IRQn = 10, /*!< 10 MRT */ |
sahilmgandhi | 18:6a4db94011d3 | 54 | CMP_IRQn = 11, /*!< 11 CMP */ |
sahilmgandhi | 18:6a4db94011d3 | 55 | WDT_IRQn = 12, /*!< 12 WDT */ |
sahilmgandhi | 18:6a4db94011d3 | 56 | BOD_IRQn = 13, /*!< 13 BOD */ |
sahilmgandhi | 18:6a4db94011d3 | 57 | FLASH_IRQn = 14, /*!< 14 FLASH */ |
sahilmgandhi | 18:6a4db94011d3 | 58 | WKT_IRQn = 15, /*!< 15 WKT */ |
sahilmgandhi | 18:6a4db94011d3 | 59 | ADC_SEQA_IRQn = 16, /*!< 16 ADC_SEQA */ |
sahilmgandhi | 18:6a4db94011d3 | 60 | ADC_SEQB_IRQn = 17, /*!< 17 ADC_SEQB */ |
sahilmgandhi | 18:6a4db94011d3 | 61 | ADC_THCMP_IRQn = 18, /*!< 18 ADC_THCMP */ |
sahilmgandhi | 18:6a4db94011d3 | 62 | ADC_OVR_IRQn = 19, /*!< 19 ADC_OVR */ |
sahilmgandhi | 18:6a4db94011d3 | 63 | DMA_IRQn = 20, /*!< 20 DMA */ |
sahilmgandhi | 18:6a4db94011d3 | 64 | I2C2_IRQn = 21, /*!< 21 I2C2 */ |
sahilmgandhi | 18:6a4db94011d3 | 65 | I2C3_IRQn = 22, /*!< 22 I2C3 */ |
sahilmgandhi | 18:6a4db94011d3 | 66 | PIN_INT0_IRQn = 24, /*!< 24 PIN_INT0 */ |
sahilmgandhi | 18:6a4db94011d3 | 67 | PIN_INT1_IRQn = 25, /*!< 25 PIN_INT1 */ |
sahilmgandhi | 18:6a4db94011d3 | 68 | PIN_INT2_IRQn = 26, /*!< 26 PIN_INT2 */ |
sahilmgandhi | 18:6a4db94011d3 | 69 | PIN_INT3_IRQn = 27, /*!< 27 PIN_INT3 */ |
sahilmgandhi | 18:6a4db94011d3 | 70 | PIN_INT4_IRQn = 28, /*!< 28 PIN_INT4 */ |
sahilmgandhi | 18:6a4db94011d3 | 71 | PIN_INT5_IRQn = 29, /*!< 29 PIN_INT5 */ |
sahilmgandhi | 18:6a4db94011d3 | 72 | PIN_INT6_IRQn = 30, /*!< 30 PIN_INT6 */ |
sahilmgandhi | 18:6a4db94011d3 | 73 | PIN_INT7_IRQn = 31 /*!< 31 PIN_INT7 */ |
sahilmgandhi | 18:6a4db94011d3 | 74 | } IRQn_Type; |
sahilmgandhi | 18:6a4db94011d3 | 75 | |
sahilmgandhi | 18:6a4db94011d3 | 76 | |
sahilmgandhi | 18:6a4db94011d3 | 77 | /** @addtogroup Configuration_of_CMSIS |
sahilmgandhi | 18:6a4db94011d3 | 78 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 79 | */ |
sahilmgandhi | 18:6a4db94011d3 | 80 | |
sahilmgandhi | 18:6a4db94011d3 | 81 | |
sahilmgandhi | 18:6a4db94011d3 | 82 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 83 | /* ================ Processor and Core Peripheral Section ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 84 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 85 | |
sahilmgandhi | 18:6a4db94011d3 | 86 | /* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */ |
sahilmgandhi | 18:6a4db94011d3 | 87 | #define __CM0PLUS_REV 0x0001 /*!< Cortex-M0PLUS Core Revision */ |
sahilmgandhi | 18:6a4db94011d3 | 88 | #define __MPU_PRESENT 0 /*!< MPU present or not */ |
sahilmgandhi | 18:6a4db94011d3 | 89 | #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ |
sahilmgandhi | 18:6a4db94011d3 | 90 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
sahilmgandhi | 18:6a4db94011d3 | 91 | #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ |
sahilmgandhi | 18:6a4db94011d3 | 92 | /** @} */ /* End of group Configuration_of_CMSIS */ |
sahilmgandhi | 18:6a4db94011d3 | 93 | |
sahilmgandhi | 18:6a4db94011d3 | 94 | #include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */ |
sahilmgandhi | 18:6a4db94011d3 | 95 | #include "system_LPC82x.h" /*!< LPC82x System */ |
sahilmgandhi | 18:6a4db94011d3 | 96 | |
sahilmgandhi | 18:6a4db94011d3 | 97 | |
sahilmgandhi | 18:6a4db94011d3 | 98 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 99 | /* ================ Device Specific Peripheral Section ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 100 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 101 | |
sahilmgandhi | 18:6a4db94011d3 | 102 | |
sahilmgandhi | 18:6a4db94011d3 | 103 | /** @addtogroup Device_Peripheral_Registers |
sahilmgandhi | 18:6a4db94011d3 | 104 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 105 | */ |
sahilmgandhi | 18:6a4db94011d3 | 106 | |
sahilmgandhi | 18:6a4db94011d3 | 107 | |
sahilmgandhi | 18:6a4db94011d3 | 108 | /* ------------------- Start of section using anonymous unions ------------------ */ |
sahilmgandhi | 18:6a4db94011d3 | 109 | #if defined(__CC_ARM) |
sahilmgandhi | 18:6a4db94011d3 | 110 | #pragma push |
sahilmgandhi | 18:6a4db94011d3 | 111 | #pragma anon_unions |
sahilmgandhi | 18:6a4db94011d3 | 112 | #elif defined(__ICCARM__) |
sahilmgandhi | 18:6a4db94011d3 | 113 | #pragma language=extended |
sahilmgandhi | 18:6a4db94011d3 | 114 | #elif defined(__GNUC__) |
sahilmgandhi | 18:6a4db94011d3 | 115 | /* anonymous unions are enabled by default */ |
sahilmgandhi | 18:6a4db94011d3 | 116 | #elif defined(__TMS470__) |
sahilmgandhi | 18:6a4db94011d3 | 117 | /* anonymous unions are enabled by default */ |
sahilmgandhi | 18:6a4db94011d3 | 118 | #elif defined(__TASKING__) |
sahilmgandhi | 18:6a4db94011d3 | 119 | #pragma warning 586 |
sahilmgandhi | 18:6a4db94011d3 | 120 | #else |
sahilmgandhi | 18:6a4db94011d3 | 121 | #warning Not supported compiler type |
sahilmgandhi | 18:6a4db94011d3 | 122 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 123 | |
sahilmgandhi | 18:6a4db94011d3 | 124 | |
sahilmgandhi | 18:6a4db94011d3 | 125 | |
sahilmgandhi | 18:6a4db94011d3 | 126 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 127 | /* ================ WWDT ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 128 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 129 | |
sahilmgandhi | 18:6a4db94011d3 | 130 | |
sahilmgandhi | 18:6a4db94011d3 | 131 | /** |
sahilmgandhi | 18:6a4db94011d3 | 132 | * @brief Windowed Watchdog Timer (WWDT) (WWDT) |
sahilmgandhi | 18:6a4db94011d3 | 133 | */ |
sahilmgandhi | 18:6a4db94011d3 | 134 | |
sahilmgandhi | 18:6a4db94011d3 | 135 | typedef struct { /*!< (@ 0x40000000) WWDT Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 136 | __IO uint32_t MOD; /*!< (@ 0x40000000) Watchdog mode register. This register contains |
sahilmgandhi | 18:6a4db94011d3 | 137 | the basic mode and status of the Watchdog Timer. */ |
sahilmgandhi | 18:6a4db94011d3 | 138 | __IO uint32_t TC; /*!< (@ 0x40000004) Watchdog timer constant register. This 24-bit |
sahilmgandhi | 18:6a4db94011d3 | 139 | register determines the time-out value. */ |
sahilmgandhi | 18:6a4db94011d3 | 140 | __O uint32_t FEED; /*!< (@ 0x40000008) Watchdog feed sequence register. Writing 0xAA |
sahilmgandhi | 18:6a4db94011d3 | 141 | followed by 0x55 to this register reloads the Watchdog timer |
sahilmgandhi | 18:6a4db94011d3 | 142 | with the value contained in WDTC. */ |
sahilmgandhi | 18:6a4db94011d3 | 143 | __I uint32_t TV; /*!< (@ 0x4000000C) Watchdog timer value register. This 24-bit register |
sahilmgandhi | 18:6a4db94011d3 | 144 | reads out the current value of the Watchdog timer. */ |
sahilmgandhi | 18:6a4db94011d3 | 145 | __I uint32_t RESERVED0; |
sahilmgandhi | 18:6a4db94011d3 | 146 | __IO uint32_t WARNINT; /*!< (@ 0x40000014) Watchdog Warning Interrupt compare value. */ |
sahilmgandhi | 18:6a4db94011d3 | 147 | __IO uint32_t WINDOW; /*!< (@ 0x40000018) Watchdog Window compare value. */ |
sahilmgandhi | 18:6a4db94011d3 | 148 | } LPC_WWDT_Type; |
sahilmgandhi | 18:6a4db94011d3 | 149 | |
sahilmgandhi | 18:6a4db94011d3 | 150 | |
sahilmgandhi | 18:6a4db94011d3 | 151 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 152 | /* ================ MRT ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 153 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 154 | |
sahilmgandhi | 18:6a4db94011d3 | 155 | |
sahilmgandhi | 18:6a4db94011d3 | 156 | /** |
sahilmgandhi | 18:6a4db94011d3 | 157 | * @brief Multi-Rate Timer (MRT) (MRT) |
sahilmgandhi | 18:6a4db94011d3 | 158 | */ |
sahilmgandhi | 18:6a4db94011d3 | 159 | |
sahilmgandhi | 18:6a4db94011d3 | 160 | typedef struct { /*!< (@ 0x40004000) MRT Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 161 | __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value |
sahilmgandhi | 18:6a4db94011d3 | 162 | is loaded into the TIMER0 register. */ |
sahilmgandhi | 18:6a4db94011d3 | 163 | __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the |
sahilmgandhi | 18:6a4db94011d3 | 164 | value of the down-counter. */ |
sahilmgandhi | 18:6a4db94011d3 | 165 | __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls |
sahilmgandhi | 18:6a4db94011d3 | 166 | the MRT0 modes. */ |
sahilmgandhi | 18:6a4db94011d3 | 167 | __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */ |
sahilmgandhi | 18:6a4db94011d3 | 168 | __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value |
sahilmgandhi | 18:6a4db94011d3 | 169 | is loaded into the TIMER0 register. */ |
sahilmgandhi | 18:6a4db94011d3 | 170 | __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the |
sahilmgandhi | 18:6a4db94011d3 | 171 | value of the down-counter. */ |
sahilmgandhi | 18:6a4db94011d3 | 172 | __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls |
sahilmgandhi | 18:6a4db94011d3 | 173 | the MRT0 modes. */ |
sahilmgandhi | 18:6a4db94011d3 | 174 | __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */ |
sahilmgandhi | 18:6a4db94011d3 | 175 | __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value |
sahilmgandhi | 18:6a4db94011d3 | 176 | is loaded into the TIMER0 register. */ |
sahilmgandhi | 18:6a4db94011d3 | 177 | __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the |
sahilmgandhi | 18:6a4db94011d3 | 178 | value of the down-counter. */ |
sahilmgandhi | 18:6a4db94011d3 | 179 | __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls |
sahilmgandhi | 18:6a4db94011d3 | 180 | the MRT0 modes. */ |
sahilmgandhi | 18:6a4db94011d3 | 181 | __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */ |
sahilmgandhi | 18:6a4db94011d3 | 182 | __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value |
sahilmgandhi | 18:6a4db94011d3 | 183 | is loaded into the TIMER0 register. */ |
sahilmgandhi | 18:6a4db94011d3 | 184 | __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the |
sahilmgandhi | 18:6a4db94011d3 | 185 | value of the down-counter. */ |
sahilmgandhi | 18:6a4db94011d3 | 186 | __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls |
sahilmgandhi | 18:6a4db94011d3 | 187 | the MRT0 modes. */ |
sahilmgandhi | 18:6a4db94011d3 | 188 | __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */ |
sahilmgandhi | 18:6a4db94011d3 | 189 | __I uint32_t RESERVED0[45]; |
sahilmgandhi | 18:6a4db94011d3 | 190 | __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns |
sahilmgandhi | 18:6a4db94011d3 | 191 | the number of the first idle channel. */ |
sahilmgandhi | 18:6a4db94011d3 | 192 | __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */ |
sahilmgandhi | 18:6a4db94011d3 | 193 | } LPC_MRT_Type; |
sahilmgandhi | 18:6a4db94011d3 | 194 | |
sahilmgandhi | 18:6a4db94011d3 | 195 | |
sahilmgandhi | 18:6a4db94011d3 | 196 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 197 | /* ================ WKT ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 198 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 199 | |
sahilmgandhi | 18:6a4db94011d3 | 200 | |
sahilmgandhi | 18:6a4db94011d3 | 201 | /** |
sahilmgandhi | 18:6a4db94011d3 | 202 | * @brief Self wake-up timer (WKT) (WKT) |
sahilmgandhi | 18:6a4db94011d3 | 203 | */ |
sahilmgandhi | 18:6a4db94011d3 | 204 | |
sahilmgandhi | 18:6a4db94011d3 | 205 | typedef struct { /*!< (@ 0x40008000) WKT Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 206 | __IO uint32_t CTRL; /*!< (@ 0x40008000) Self wake-up timer control register. */ |
sahilmgandhi | 18:6a4db94011d3 | 207 | __I uint32_t RESERVED0[2]; |
sahilmgandhi | 18:6a4db94011d3 | 208 | __IO uint32_t COUNT; /*!< (@ 0x4000800C) Counter register. */ |
sahilmgandhi | 18:6a4db94011d3 | 209 | } LPC_WKT_Type; |
sahilmgandhi | 18:6a4db94011d3 | 210 | |
sahilmgandhi | 18:6a4db94011d3 | 211 | |
sahilmgandhi | 18:6a4db94011d3 | 212 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 213 | /* ================ SWM ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 214 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 215 | |
sahilmgandhi | 18:6a4db94011d3 | 216 | |
sahilmgandhi | 18:6a4db94011d3 | 217 | /** |
sahilmgandhi | 18:6a4db94011d3 | 218 | * @brief Switch matrix (SWM) (SWM) |
sahilmgandhi | 18:6a4db94011d3 | 219 | */ |
sahilmgandhi | 18:6a4db94011d3 | 220 | |
sahilmgandhi | 18:6a4db94011d3 | 221 | typedef struct { /*!< (@ 0x4000C000) SWM Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 222 | union { |
sahilmgandhi | 18:6a4db94011d3 | 223 | __IO uint32_t PINASSIGN[12]; |
sahilmgandhi | 18:6a4db94011d3 | 224 | struct { |
sahilmgandhi | 18:6a4db94011d3 | 225 | __IO uint32_t PINASSIGN0; /*!< (@ 0x4000C000) Pin assign register 0. Assign movable functions |
sahilmgandhi | 18:6a4db94011d3 | 226 | U0_TXD, U0_RXD, U0_RTS, U0_CTS. */ |
sahilmgandhi | 18:6a4db94011d3 | 227 | __IO uint32_t PINASSIGN1; /*!< (@ 0x4000C004) Pin assign register 1. Assign movable functions |
sahilmgandhi | 18:6a4db94011d3 | 228 | U0_SCLK, U1_TXD, U1_RXD, U1_RTS. */ |
sahilmgandhi | 18:6a4db94011d3 | 229 | __IO uint32_t PINASSIGN2; /*!< (@ 0x4000C008) Pin assign register 2. Assign movable functions |
sahilmgandhi | 18:6a4db94011d3 | 230 | U1_CTS, U1_SCLK, U2_TXD, U2_RXD. */ |
sahilmgandhi | 18:6a4db94011d3 | 231 | __IO uint32_t PINASSIGN3; /*!< (@ 0x4000C00C) Pin assign register 3. Assign movable function |
sahilmgandhi | 18:6a4db94011d3 | 232 | U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK. */ |
sahilmgandhi | 18:6a4db94011d3 | 233 | __IO uint32_t PINASSIGN4; /*!< (@ 0x4000C010) Pin assign register 4. Assign movable functions |
sahilmgandhi | 18:6a4db94011d3 | 234 | SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1. */ |
sahilmgandhi | 18:6a4db94011d3 | 235 | __IO uint32_t PINASSIGN5; /*!< (@ 0x4000C014) Pin assign register 5. Assign movable functions |
sahilmgandhi | 18:6a4db94011d3 | 236 | SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI */ |
sahilmgandhi | 18:6a4db94011d3 | 237 | __IO uint32_t PINASSIGN6; /*!< (@ 0x4000C018) Pin assign register 6. Assign movable functions |
sahilmgandhi | 18:6a4db94011d3 | 238 | SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0. */ |
sahilmgandhi | 18:6a4db94011d3 | 239 | __IO uint32_t PINASSIGN7; /*!< (@ 0x4000C01C) Pin assign register 7. Assign movable functions |
sahilmgandhi | 18:6a4db94011d3 | 240 | SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0. */ |
sahilmgandhi | 18:6a4db94011d3 | 241 | __IO uint32_t PINASSIGN8; /*!< (@ 0x4000C020) Pin assign register 8. Assign movable functions |
sahilmgandhi | 18:6a4db94011d3 | 242 | SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4. */ |
sahilmgandhi | 18:6a4db94011d3 | 243 | __IO uint32_t PINASSIGN9; /*!< (@ 0x4000C024) Pin assign register 9. Assign movable functions |
sahilmgandhi | 18:6a4db94011d3 | 244 | SCT_OUT5, I2C1_SDA, I2C1_SCL, I2C2_SDA. */ |
sahilmgandhi | 18:6a4db94011d3 | 245 | __IO uint32_t PINASSIGN10; /*!< (@ 0x4000C028) Pin assign register 10. Assign movable functions |
sahilmgandhi | 18:6a4db94011d3 | 246 | I2C2_SCL, I2C3_SDA, I2C3_SCL, ADC_PINTRIG0. */ |
sahilmgandhi | 18:6a4db94011d3 | 247 | __IO uint32_t PINASSIGN11; /*!< (@ 0x4000C02C) Pin assign register 11. Assign movable functions |
sahilmgandhi | 18:6a4db94011d3 | 248 | ADC_PINTRIG1, ACMP_O, CLKOUT, GPIO_INT_BMAT */ |
sahilmgandhi | 18:6a4db94011d3 | 249 | }; |
sahilmgandhi | 18:6a4db94011d3 | 250 | }; |
sahilmgandhi | 18:6a4db94011d3 | 251 | __I uint32_t RESERVED0[100]; |
sahilmgandhi | 18:6a4db94011d3 | 252 | __IO uint32_t PINENABLE0; /*!< (@ 0x4000C1C0) Pin enable register 0. Enables fixed-pin functions |
sahilmgandhi | 18:6a4db94011d3 | 253 | ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, |
sahilmgandhi | 18:6a4db94011d3 | 254 | VDDCMP. */ |
sahilmgandhi | 18:6a4db94011d3 | 255 | } LPC_SWM_Type; |
sahilmgandhi | 18:6a4db94011d3 | 256 | |
sahilmgandhi | 18:6a4db94011d3 | 257 | |
sahilmgandhi | 18:6a4db94011d3 | 258 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 259 | /* ================ ADC ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 260 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 261 | |
sahilmgandhi | 18:6a4db94011d3 | 262 | |
sahilmgandhi | 18:6a4db94011d3 | 263 | /** |
sahilmgandhi | 18:6a4db94011d3 | 264 | * @brief 12-bit Analog-to-Digital Converter (ADC) (ADC) |
sahilmgandhi | 18:6a4db94011d3 | 265 | */ |
sahilmgandhi | 18:6a4db94011d3 | 266 | |
sahilmgandhi | 18:6a4db94011d3 | 267 | typedef struct { /*!< (@ 0x4001C000) ADC Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 268 | __IO uint32_t CTRL; /*!< (@ 0x4001C000) A/D Control Register. Contains the clock divide |
sahilmgandhi | 18:6a4db94011d3 | 269 | value, enable bits for each sequence and the A/D power-down |
sahilmgandhi | 18:6a4db94011d3 | 270 | bit. */ |
sahilmgandhi | 18:6a4db94011d3 | 271 | __I uint32_t RESERVED0; |
sahilmgandhi | 18:6a4db94011d3 | 272 | __IO uint32_t SEQA_CTRL; /*!< (@ 0x4001C008) A/D Conversion Sequence-A control Register: Controls |
sahilmgandhi | 18:6a4db94011d3 | 273 | triggering and channel selection for conversion sequence-A. |
sahilmgandhi | 18:6a4db94011d3 | 274 | Also specifies interrupt mode for sequence-A. */ |
sahilmgandhi | 18:6a4db94011d3 | 275 | __IO uint32_t SEQB_CTRL; /*!< (@ 0x4001C00C) A/D Conversion Sequence-B Control Register: Controls |
sahilmgandhi | 18:6a4db94011d3 | 276 | triggering and channel selection for conversion sequence-B. |
sahilmgandhi | 18:6a4db94011d3 | 277 | Also specifies interrupt mode for sequence-B. */ |
sahilmgandhi | 18:6a4db94011d3 | 278 | __IO uint32_t SEQA_GDAT; /*!< (@ 0x4001C010) A/D Sequence-A Global Data Register. This register |
sahilmgandhi | 18:6a4db94011d3 | 279 | contains the result of the most recent A/D conversion performed |
sahilmgandhi | 18:6a4db94011d3 | 280 | under sequence-A */ |
sahilmgandhi | 18:6a4db94011d3 | 281 | __IO uint32_t SEQB_GDAT; /*!< (@ 0x4001C014) A/D Sequence-B Global Data Register. This register |
sahilmgandhi | 18:6a4db94011d3 | 282 | contains the result of the most recent A/D conversion performed |
sahilmgandhi | 18:6a4db94011d3 | 283 | under sequence-B */ |
sahilmgandhi | 18:6a4db94011d3 | 284 | __I uint32_t RESERVED1[2]; |
sahilmgandhi | 18:6a4db94011d3 | 285 | __I uint32_t DAT0; /*!< (@ 0x4001C020) A/D Channel 0 Data Register. This register contains |
sahilmgandhi | 18:6a4db94011d3 | 286 | the result of the most recent conversion completed on channel |
sahilmgandhi | 18:6a4db94011d3 | 287 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 288 | __I uint32_t DAT1; /*!< (@ 0x4001C024) A/D Channel 0 Data Register. This register contains |
sahilmgandhi | 18:6a4db94011d3 | 289 | the result of the most recent conversion completed on channel |
sahilmgandhi | 18:6a4db94011d3 | 290 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 291 | __I uint32_t DAT2; /*!< (@ 0x4001C028) A/D Channel 0 Data Register. This register contains |
sahilmgandhi | 18:6a4db94011d3 | 292 | the result of the most recent conversion completed on channel |
sahilmgandhi | 18:6a4db94011d3 | 293 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 294 | __I uint32_t DAT3; /*!< (@ 0x4001C02C) A/D Channel 0 Data Register. This register contains |
sahilmgandhi | 18:6a4db94011d3 | 295 | the result of the most recent conversion completed on channel |
sahilmgandhi | 18:6a4db94011d3 | 296 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 297 | __I uint32_t DAT4; /*!< (@ 0x4001C030) A/D Channel 0 Data Register. This register contains |
sahilmgandhi | 18:6a4db94011d3 | 298 | the result of the most recent conversion completed on channel |
sahilmgandhi | 18:6a4db94011d3 | 299 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 300 | __I uint32_t DAT5; /*!< (@ 0x4001C034) A/D Channel 0 Data Register. This register contains |
sahilmgandhi | 18:6a4db94011d3 | 301 | the result of the most recent conversion completed on channel |
sahilmgandhi | 18:6a4db94011d3 | 302 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 303 | __I uint32_t DAT6; /*!< (@ 0x4001C038) A/D Channel 0 Data Register. This register contains |
sahilmgandhi | 18:6a4db94011d3 | 304 | the result of the most recent conversion completed on channel |
sahilmgandhi | 18:6a4db94011d3 | 305 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 306 | __I uint32_t DAT7; /*!< (@ 0x4001C03C) A/D Channel 0 Data Register. This register contains |
sahilmgandhi | 18:6a4db94011d3 | 307 | the result of the most recent conversion completed on channel |
sahilmgandhi | 18:6a4db94011d3 | 308 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 309 | __I uint32_t DAT8; /*!< (@ 0x4001C040) A/D Channel 0 Data Register. This register contains |
sahilmgandhi | 18:6a4db94011d3 | 310 | the result of the most recent conversion completed on channel |
sahilmgandhi | 18:6a4db94011d3 | 311 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 312 | __I uint32_t DAT9; /*!< (@ 0x4001C044) A/D Channel 0 Data Register. This register contains |
sahilmgandhi | 18:6a4db94011d3 | 313 | the result of the most recent conversion completed on channel |
sahilmgandhi | 18:6a4db94011d3 | 314 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 315 | __I uint32_t DAT10; /*!< (@ 0x4001C048) A/D Channel 0 Data Register. This register contains |
sahilmgandhi | 18:6a4db94011d3 | 316 | the result of the most recent conversion completed on channel |
sahilmgandhi | 18:6a4db94011d3 | 317 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 318 | __I uint32_t DAT11; /*!< (@ 0x4001C04C) A/D Channel 0 Data Register. This register contains |
sahilmgandhi | 18:6a4db94011d3 | 319 | the result of the most recent conversion completed on channel |
sahilmgandhi | 18:6a4db94011d3 | 320 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 321 | __IO uint32_t THR0_LOW; /*!< (@ 0x4001C050) A/D Low Compare Threshold Register 0 : Contains |
sahilmgandhi | 18:6a4db94011d3 | 322 | the lower threshold level for automatic threshold comparison |
sahilmgandhi | 18:6a4db94011d3 | 323 | for any channels linked to threshold pair 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 324 | __IO uint32_t THR1_LOW; /*!< (@ 0x4001C054) A/D Low Compare Threshold Register 1: Contains |
sahilmgandhi | 18:6a4db94011d3 | 325 | the lower threshold level for automatic threshold comparison |
sahilmgandhi | 18:6a4db94011d3 | 326 | for any channels linked to threshold pair 1. */ |
sahilmgandhi | 18:6a4db94011d3 | 327 | __IO uint32_t THR0_HIGH; /*!< (@ 0x4001C058) A/D High Compare Threshold Register 0: Contains |
sahilmgandhi | 18:6a4db94011d3 | 328 | the upper threshold level for automatic threshold comparison |
sahilmgandhi | 18:6a4db94011d3 | 329 | for any channels linked to threshold pair 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 330 | __IO uint32_t THR1_HIGH; /*!< (@ 0x4001C05C) A/D High Compare Threshold Register 1: Contains |
sahilmgandhi | 18:6a4db94011d3 | 331 | the upper threshold level for automatic threshold comparison |
sahilmgandhi | 18:6a4db94011d3 | 332 | for any channels linked to threshold pair 1. */ |
sahilmgandhi | 18:6a4db94011d3 | 333 | __IO uint32_t CHAN_THRSEL; /*!< (@ 0x4001C060) A/D Channel-Threshold Select Register. Specifies |
sahilmgandhi | 18:6a4db94011d3 | 334 | which set of threshold compare registers are to be used for |
sahilmgandhi | 18:6a4db94011d3 | 335 | each channel */ |
sahilmgandhi | 18:6a4db94011d3 | 336 | __IO uint32_t INTEN; /*!< (@ 0x4001C064) A/D Interrupt Enable Register. This register |
sahilmgandhi | 18:6a4db94011d3 | 337 | contains enable bits that enable the sequence-A, sequence-B, |
sahilmgandhi | 18:6a4db94011d3 | 338 | threshold compare and data overrun interrupts to be generated. */ |
sahilmgandhi | 18:6a4db94011d3 | 339 | __IO uint32_t FLAGS; /*!< (@ 0x4001C068) A/D Flags Register. Contains the four interrupt |
sahilmgandhi | 18:6a4db94011d3 | 340 | request flags and the individual component overrun and threshold-compare |
sahilmgandhi | 18:6a4db94011d3 | 341 | flags. (The overrun bits replicate information stored in the |
sahilmgandhi | 18:6a4db94011d3 | 342 | result registers). */ |
sahilmgandhi | 18:6a4db94011d3 | 343 | __IO uint32_t TRM; /*!< (@ 0x4001C06C) ADC trim register. */ |
sahilmgandhi | 18:6a4db94011d3 | 344 | } LPC_ADC_Type; |
sahilmgandhi | 18:6a4db94011d3 | 345 | |
sahilmgandhi | 18:6a4db94011d3 | 346 | |
sahilmgandhi | 18:6a4db94011d3 | 347 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 348 | /* ================ PMU ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 349 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 350 | |
sahilmgandhi | 18:6a4db94011d3 | 351 | |
sahilmgandhi | 18:6a4db94011d3 | 352 | /** |
sahilmgandhi | 18:6a4db94011d3 | 353 | * @brief Power Management Unit (PMU) (PMU) |
sahilmgandhi | 18:6a4db94011d3 | 354 | */ |
sahilmgandhi | 18:6a4db94011d3 | 355 | |
sahilmgandhi | 18:6a4db94011d3 | 356 | typedef struct { /*!< (@ 0x40020000) PMU Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 357 | __IO uint32_t PCON; /*!< (@ 0x40020000) Power control register */ |
sahilmgandhi | 18:6a4db94011d3 | 358 | __IO uint32_t GPREG0; /*!< (@ 0x40020004) General purpose register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 359 | __IO uint32_t GPREG1; /*!< (@ 0x40020008) General purpose register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 360 | __IO uint32_t GPREG2; /*!< (@ 0x4002000C) General purpose register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 361 | __IO uint32_t GPREG3; /*!< (@ 0x40020010) General purpose register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 362 | __IO uint32_t DPDCTRL; /*!< (@ 0x40020014) Deep power-down control register. Also includes |
sahilmgandhi | 18:6a4db94011d3 | 363 | bits for general purpose storage. */ |
sahilmgandhi | 18:6a4db94011d3 | 364 | } LPC_PMU_Type; |
sahilmgandhi | 18:6a4db94011d3 | 365 | |
sahilmgandhi | 18:6a4db94011d3 | 366 | |
sahilmgandhi | 18:6a4db94011d3 | 367 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 368 | /* ================ CMP ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 369 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 370 | |
sahilmgandhi | 18:6a4db94011d3 | 371 | |
sahilmgandhi | 18:6a4db94011d3 | 372 | /** |
sahilmgandhi | 18:6a4db94011d3 | 373 | * @brief Analog comparator (CMP) |
sahilmgandhi | 18:6a4db94011d3 | 374 | */ |
sahilmgandhi | 18:6a4db94011d3 | 375 | |
sahilmgandhi | 18:6a4db94011d3 | 376 | typedef struct { /*!< (@ 0x40024000) CMP Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 377 | __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */ |
sahilmgandhi | 18:6a4db94011d3 | 378 | __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */ |
sahilmgandhi | 18:6a4db94011d3 | 379 | } LPC_CMP_Type; |
sahilmgandhi | 18:6a4db94011d3 | 380 | |
sahilmgandhi | 18:6a4db94011d3 | 381 | |
sahilmgandhi | 18:6a4db94011d3 | 382 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 383 | /* ================ DMATRIGMUX ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 384 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 385 | |
sahilmgandhi | 18:6a4db94011d3 | 386 | |
sahilmgandhi | 18:6a4db94011d3 | 387 | /** |
sahilmgandhi | 18:6a4db94011d3 | 388 | * @brief DMA trigger mux (DMATRIGMUX) |
sahilmgandhi | 18:6a4db94011d3 | 389 | */ |
sahilmgandhi | 18:6a4db94011d3 | 390 | |
sahilmgandhi | 18:6a4db94011d3 | 391 | typedef struct { /*!< (@ 0x40028000) DMATRIGMUX Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 392 | __IO uint32_t DMA_ITRIG_INMUX0; /*!< (@ 0x40028000) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 393 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 394 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 395 | __IO uint32_t DMA_ITRIG_INMUX1; /*!< (@ 0x40028004) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 396 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 397 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 398 | __IO uint32_t DMA_ITRIG_INMUX2; /*!< (@ 0x40028008) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 399 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 400 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 401 | __IO uint32_t DMA_ITRIG_INMUX3; /*!< (@ 0x4002800C) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 402 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 403 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 404 | __IO uint32_t DMA_ITRIG_INMUX4; /*!< (@ 0x40028010) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 405 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 406 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 407 | __IO uint32_t DMA_ITRIG_INMUX5; /*!< (@ 0x40028014) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 408 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 409 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 410 | __IO uint32_t DMA_ITRIG_INMUX6; /*!< (@ 0x40028018) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 411 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 412 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 413 | __IO uint32_t DMA_ITRIG_INMUX7; /*!< (@ 0x4002801C) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 414 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 415 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 416 | __IO uint32_t DMA_ITRIG_INMUX8; /*!< (@ 0x40028020) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 417 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 418 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 419 | __IO uint32_t DMA_ITRIG_INMUX9; /*!< (@ 0x40028024) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 420 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 421 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 422 | __IO uint32_t DMA_ITRIG_INMUX10; /*!< (@ 0x40028028) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 423 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 424 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 425 | __IO uint32_t DMA_ITRIG_INMUX11; /*!< (@ 0x4002802C) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 426 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 427 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 428 | __IO uint32_t DMA_ITRIG_INMUX12; /*!< (@ 0x40028030) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 429 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 430 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 431 | __IO uint32_t DMA_ITRIG_INMUX13; /*!< (@ 0x40028034) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 432 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 433 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 434 | __IO uint32_t DMA_ITRIG_INMUX14; /*!< (@ 0x40028038) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 435 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 436 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 437 | __IO uint32_t DMA_ITRIG_INMUX15; /*!< (@ 0x4002803C) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 438 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 439 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 440 | __IO uint32_t DMA_ITRIG_INMUX16; /*!< (@ 0x40028040) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 441 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 442 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 443 | __IO uint32_t DMA_ITRIG_INMUX17; /*!< (@ 0x40028044) Input mux register for trigger inputs 0 to 23 |
sahilmgandhi | 18:6a4db94011d3 | 444 | connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin |
sahilmgandhi | 18:6a4db94011d3 | 445 | interrupts, and DMA requests. */ |
sahilmgandhi | 18:6a4db94011d3 | 446 | } LPC_DMATRIGMUX_Type; |
sahilmgandhi | 18:6a4db94011d3 | 447 | |
sahilmgandhi | 18:6a4db94011d3 | 448 | |
sahilmgandhi | 18:6a4db94011d3 | 449 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 450 | /* ================ INPUTMUX ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 451 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 452 | |
sahilmgandhi | 18:6a4db94011d3 | 453 | |
sahilmgandhi | 18:6a4db94011d3 | 454 | /** |
sahilmgandhi | 18:6a4db94011d3 | 455 | * @brief Input multiplexing (INPUTMUX) |
sahilmgandhi | 18:6a4db94011d3 | 456 | */ |
sahilmgandhi | 18:6a4db94011d3 | 457 | |
sahilmgandhi | 18:6a4db94011d3 | 458 | typedef struct { /*!< (@ 0x4002C000) INPUTMUX Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 459 | __IO uint32_t DMA_INMUX_INMUX0; /*!< (@ 0x4002C000) Input mux register for DMA trigger input 20. |
sahilmgandhi | 18:6a4db94011d3 | 460 | Selects from 18 DMA trigger outputs. */ |
sahilmgandhi | 18:6a4db94011d3 | 461 | __IO uint32_t DMA_INMUX_INMUX1; /*!< (@ 0x4002C004) Input mux register for DMA trigger input 20. |
sahilmgandhi | 18:6a4db94011d3 | 462 | Selects from 18 DMA trigger outputs. */ |
sahilmgandhi | 18:6a4db94011d3 | 463 | __I uint32_t RESERVED0[6]; |
sahilmgandhi | 18:6a4db94011d3 | 464 | __IO uint32_t SCT0_INMUX0; /*!< (@ 0x4002C020) Input mux register for SCT input 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 465 | __IO uint32_t SCT0_INMUX1; /*!< (@ 0x4002C024) Input mux register for SCT input 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 466 | __IO uint32_t SCT0_INMUX2; /*!< (@ 0x4002C028) Input mux register for SCT input 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 467 | __IO uint32_t SCT0_INMUX3; /*!< (@ 0x4002C02C) Input mux register for SCT input 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 468 | } LPC_INPUTMUX_Type; |
sahilmgandhi | 18:6a4db94011d3 | 469 | |
sahilmgandhi | 18:6a4db94011d3 | 470 | |
sahilmgandhi | 18:6a4db94011d3 | 471 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 472 | /* ================ FLASHCTRL ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 473 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 474 | |
sahilmgandhi | 18:6a4db94011d3 | 475 | |
sahilmgandhi | 18:6a4db94011d3 | 476 | /** |
sahilmgandhi | 18:6a4db94011d3 | 477 | * @brief Flash controller (FLASHCTRL) |
sahilmgandhi | 18:6a4db94011d3 | 478 | */ |
sahilmgandhi | 18:6a4db94011d3 | 479 | |
sahilmgandhi | 18:6a4db94011d3 | 480 | typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 481 | __I uint32_t RESERVED0[4]; |
sahilmgandhi | 18:6a4db94011d3 | 482 | __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */ |
sahilmgandhi | 18:6a4db94011d3 | 483 | __I uint32_t RESERVED1[3]; |
sahilmgandhi | 18:6a4db94011d3 | 484 | __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */ |
sahilmgandhi | 18:6a4db94011d3 | 485 | __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */ |
sahilmgandhi | 18:6a4db94011d3 | 486 | __I uint32_t RESERVED2; |
sahilmgandhi | 18:6a4db94011d3 | 487 | __I uint32_t FMSW0; /*!< (@ 0x4004002C) Signature Word */ |
sahilmgandhi | 18:6a4db94011d3 | 488 | } LPC_FLASHCTRL_Type; |
sahilmgandhi | 18:6a4db94011d3 | 489 | |
sahilmgandhi | 18:6a4db94011d3 | 490 | |
sahilmgandhi | 18:6a4db94011d3 | 491 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 492 | /* ================ IOCON ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 493 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 494 | |
sahilmgandhi | 18:6a4db94011d3 | 495 | |
sahilmgandhi | 18:6a4db94011d3 | 496 | /** |
sahilmgandhi | 18:6a4db94011d3 | 497 | * @brief I/O configuration (IOCON) (IOCON) |
sahilmgandhi | 18:6a4db94011d3 | 498 | */ |
sahilmgandhi | 18:6a4db94011d3 | 499 | |
sahilmgandhi | 18:6a4db94011d3 | 500 | typedef struct { /*!< (@ 0x40044000) IOCON Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 501 | __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */ |
sahilmgandhi | 18:6a4db94011d3 | 502 | __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */ |
sahilmgandhi | 18:6a4db94011d3 | 503 | __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */ |
sahilmgandhi | 18:6a4db94011d3 | 504 | __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5/RESET */ |
sahilmgandhi | 18:6a4db94011d3 | 505 | __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */ |
sahilmgandhi | 18:6a4db94011d3 | 506 | __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3/SWCLK */ |
sahilmgandhi | 18:6a4db94011d3 | 507 | __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2/SWDIO */ |
sahilmgandhi | 18:6a4db94011d3 | 508 | __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11. This is the |
sahilmgandhi | 18:6a4db94011d3 | 509 | pin configuration for the true open-drain pin. */ |
sahilmgandhi | 18:6a4db94011d3 | 510 | __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10. This is the |
sahilmgandhi | 18:6a4db94011d3 | 511 | pin configuration for the true open-drain pin. */ |
sahilmgandhi | 18:6a4db94011d3 | 512 | __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */ |
sahilmgandhi | 18:6a4db94011d3 | 513 | __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */ |
sahilmgandhi | 18:6a4db94011d3 | 514 | __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_17 */ |
sahilmgandhi | 18:6a4db94011d3 | 515 | __I uint32_t RESERVED0; |
sahilmgandhi | 18:6a4db94011d3 | 516 | __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9/XTALOUT */ |
sahilmgandhi | 18:6a4db94011d3 | 517 | __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8/XTALIN */ |
sahilmgandhi | 18:6a4db94011d3 | 518 | __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */ |
sahilmgandhi | 18:6a4db94011d3 | 519 | __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6/VDDCMP */ |
sahilmgandhi | 18:6a4db94011d3 | 520 | __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0/ACMP_I0 */ |
sahilmgandhi | 18:6a4db94011d3 | 521 | __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */ |
sahilmgandhi | 18:6a4db94011d3 | 522 | __I uint32_t RESERVED1; |
sahilmgandhi | 18:6a4db94011d3 | 523 | __IO uint32_t PIO0_28; /*!< (@ 0x40044050) I/O configuration for pin PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 524 | __IO uint32_t PIO0_27; /*!< (@ 0x40044054) I/O configuration for pin PIO0_27 */ |
sahilmgandhi | 18:6a4db94011d3 | 525 | __IO uint32_t PIO0_26; /*!< (@ 0x40044058) I/O configuration for pin PIO0_26 */ |
sahilmgandhi | 18:6a4db94011d3 | 526 | __IO uint32_t PIO0_25; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_25 */ |
sahilmgandhi | 18:6a4db94011d3 | 527 | __IO uint32_t PIO0_24; /*!< (@ 0x40044060) I/O configuration for pin PIO0_24 */ |
sahilmgandhi | 18:6a4db94011d3 | 528 | __IO uint32_t PIO0_23; /*!< (@ 0x40044064) I/O configuration for pin PIO0_23/ADC_3 */ |
sahilmgandhi | 18:6a4db94011d3 | 529 | __IO uint32_t PIO0_22; /*!< (@ 0x40044068) I/O configuration for pin PIO0_22/ADC_4 */ |
sahilmgandhi | 18:6a4db94011d3 | 530 | __IO uint32_t PIO0_21; /*!< (@ 0x4004406C) I/O configuration for pin PIO0_21/ACMP_I4/ADC_5 */ |
sahilmgandhi | 18:6a4db94011d3 | 531 | __IO uint32_t PIO0_20; /*!< (@ 0x40044070) I/O configuration for pin PIO0_20/ADC_6 */ |
sahilmgandhi | 18:6a4db94011d3 | 532 | __IO uint32_t PIO0_19; /*!< (@ 0x40044074) I/O configuration for pin PIO0_19/ADC_7 */ |
sahilmgandhi | 18:6a4db94011d3 | 533 | __IO uint32_t PIO0_18; /*!< (@ 0x40044078) I/O configuration for pin PIO0_18/ADC_8 */ |
sahilmgandhi | 18:6a4db94011d3 | 534 | } LPC_IOCON_Type; |
sahilmgandhi | 18:6a4db94011d3 | 535 | |
sahilmgandhi | 18:6a4db94011d3 | 536 | |
sahilmgandhi | 18:6a4db94011d3 | 537 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 538 | /* ================ SYSCON ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 539 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 540 | |
sahilmgandhi | 18:6a4db94011d3 | 541 | |
sahilmgandhi | 18:6a4db94011d3 | 542 | /** |
sahilmgandhi | 18:6a4db94011d3 | 543 | * @brief System configuration (SYSCON) (SYSCON) |
sahilmgandhi | 18:6a4db94011d3 | 544 | */ |
sahilmgandhi | 18:6a4db94011d3 | 545 | |
sahilmgandhi | 18:6a4db94011d3 | 546 | typedef struct { /*!< (@ 0x40048000) SYSCON Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 547 | __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */ |
sahilmgandhi | 18:6a4db94011d3 | 548 | __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */ |
sahilmgandhi | 18:6a4db94011d3 | 549 | __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */ |
sahilmgandhi | 18:6a4db94011d3 | 550 | __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */ |
sahilmgandhi | 18:6a4db94011d3 | 551 | __I uint32_t RESERVED0[4]; |
sahilmgandhi | 18:6a4db94011d3 | 552 | __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */ |
sahilmgandhi | 18:6a4db94011d3 | 553 | __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */ |
sahilmgandhi | 18:6a4db94011d3 | 554 | __IO uint32_t IRCCTRL; /*!< (@ 0x40048028) IRC control */ |
sahilmgandhi | 18:6a4db94011d3 | 555 | __I uint32_t RESERVED1; |
sahilmgandhi | 18:6a4db94011d3 | 556 | __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */ |
sahilmgandhi | 18:6a4db94011d3 | 557 | __I uint32_t RESERVED2[3]; |
sahilmgandhi | 18:6a4db94011d3 | 558 | __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */ |
sahilmgandhi | 18:6a4db94011d3 | 559 | __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */ |
sahilmgandhi | 18:6a4db94011d3 | 560 | __I uint32_t RESERVED3[10]; |
sahilmgandhi | 18:6a4db94011d3 | 561 | __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */ |
sahilmgandhi | 18:6a4db94011d3 | 562 | __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */ |
sahilmgandhi | 18:6a4db94011d3 | 563 | __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */ |
sahilmgandhi | 18:6a4db94011d3 | 564 | __I uint32_t RESERVED4; |
sahilmgandhi | 18:6a4db94011d3 | 565 | __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */ |
sahilmgandhi | 18:6a4db94011d3 | 566 | __I uint32_t RESERVED5[4]; |
sahilmgandhi | 18:6a4db94011d3 | 567 | __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048094) USART clock divider */ |
sahilmgandhi | 18:6a4db94011d3 | 568 | __I uint32_t RESERVED6[18]; |
sahilmgandhi | 18:6a4db94011d3 | 569 | __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */ |
sahilmgandhi | 18:6a4db94011d3 | 570 | __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */ |
sahilmgandhi | 18:6a4db94011d3 | 571 | __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */ |
sahilmgandhi | 18:6a4db94011d3 | 572 | __I uint32_t RESERVED7; |
sahilmgandhi | 18:6a4db94011d3 | 573 | __IO uint32_t UARTFRGDIV; /*!< (@ 0x400480F0) USART1 to USART4 common fractional generator |
sahilmgandhi | 18:6a4db94011d3 | 574 | divider value */ |
sahilmgandhi | 18:6a4db94011d3 | 575 | __IO uint32_t UARTFRGMULT; /*!< (@ 0x400480F4) USART1 to USART4 common fractional generator |
sahilmgandhi | 18:6a4db94011d3 | 576 | multiplier value */ |
sahilmgandhi | 18:6a4db94011d3 | 577 | __I uint32_t RESERVED8; |
sahilmgandhi | 18:6a4db94011d3 | 578 | __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */ |
sahilmgandhi | 18:6a4db94011d3 | 579 | __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 580 | __I uint32_t RESERVED9[12]; |
sahilmgandhi | 18:6a4db94011d3 | 581 | __IO uint32_t IOCONCLKDIV6; /*!< (@ 0x40048134) Peripheral clock 6 to the IOCON block for programmable |
sahilmgandhi | 18:6a4db94011d3 | 582 | glitch filter */ |
sahilmgandhi | 18:6a4db94011d3 | 583 | __I uint32_t RESERVED10[6]; |
sahilmgandhi | 18:6a4db94011d3 | 584 | __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */ |
sahilmgandhi | 18:6a4db94011d3 | 585 | __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */ |
sahilmgandhi | 18:6a4db94011d3 | 586 | __I uint32_t RESERVED11[6]; |
sahilmgandhi | 18:6a4db94011d3 | 587 | __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt |
sahilmgandhi | 18:6a4db94011d3 | 588 | latency and determinism. */ |
sahilmgandhi | 18:6a4db94011d3 | 589 | __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ |
sahilmgandhi | 18:6a4db94011d3 | 590 | union { |
sahilmgandhi | 18:6a4db94011d3 | 591 | __IO uint32_t PINTSEL[8]; |
sahilmgandhi | 18:6a4db94011d3 | 592 | struct { |
sahilmgandhi | 18:6a4db94011d3 | 593 | __IO uint32_t PINTSEL0; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 594 | __IO uint32_t PINTSEL1; /*!< (@ 0x4004817C) GPIO Pin Interrupt Select register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 595 | __IO uint32_t PINTSEL2; /*!< (@ 0x40048180) GPIO Pin Interrupt Select register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 596 | __IO uint32_t PINTSEL3; /*!< (@ 0x40048184) GPIO Pin Interrupt Select register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 597 | __IO uint32_t PINTSEL4; /*!< (@ 0x40048188) GPIO Pin Interrupt Select register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 598 | __IO uint32_t PINTSEL5; /*!< (@ 0x4004818C) GPIO Pin Interrupt Select register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 599 | __IO uint32_t PINTSEL6; /*!< (@ 0x40048190) GPIO Pin Interrupt Select register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 600 | __IO uint32_t PINTSEL7; /*!< (@ 0x40048194) GPIO Pin Interrupt Select register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 601 | }; |
sahilmgandhi | 18:6a4db94011d3 | 602 | }; |
sahilmgandhi | 18:6a4db94011d3 | 603 | __I uint32_t RESERVED12[27]; |
sahilmgandhi | 18:6a4db94011d3 | 604 | __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 pin wake-up enable register */ |
sahilmgandhi | 18:6a4db94011d3 | 605 | __I uint32_t RESERVED13[3]; |
sahilmgandhi | 18:6a4db94011d3 | 606 | __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register */ |
sahilmgandhi | 18:6a4db94011d3 | 607 | __I uint32_t RESERVED14[6]; |
sahilmgandhi | 18:6a4db94011d3 | 608 | __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */ |
sahilmgandhi | 18:6a4db94011d3 | 609 | __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */ |
sahilmgandhi | 18:6a4db94011d3 | 610 | __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */ |
sahilmgandhi | 18:6a4db94011d3 | 611 | __I uint32_t RESERVED15[111]; |
sahilmgandhi | 18:6a4db94011d3 | 612 | __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */ |
sahilmgandhi | 18:6a4db94011d3 | 613 | } LPC_SYSCON_Type; |
sahilmgandhi | 18:6a4db94011d3 | 614 | |
sahilmgandhi | 18:6a4db94011d3 | 615 | |
sahilmgandhi | 18:6a4db94011d3 | 616 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 617 | /* ================ I2C0 ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 618 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 619 | |
sahilmgandhi | 18:6a4db94011d3 | 620 | |
sahilmgandhi | 18:6a4db94011d3 | 621 | /** |
sahilmgandhi | 18:6a4db94011d3 | 622 | * @brief I2C0-bus interface (I2C0) |
sahilmgandhi | 18:6a4db94011d3 | 623 | */ |
sahilmgandhi | 18:6a4db94011d3 | 624 | |
sahilmgandhi | 18:6a4db94011d3 | 625 | typedef struct { /*!< (@ 0x40050000) I2C0 Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 626 | __IO uint32_t CFG; /*!< (@ 0x40050000) Configuration for shared functions. */ |
sahilmgandhi | 18:6a4db94011d3 | 627 | __IO uint32_t STAT; /*!< (@ 0x40050004) Status register for Master, Slave, and Monitor |
sahilmgandhi | 18:6a4db94011d3 | 628 | functions. */ |
sahilmgandhi | 18:6a4db94011d3 | 629 | __IO uint32_t INTENSET; /*!< (@ 0x40050008) Interrupt Enable Set and read register. */ |
sahilmgandhi | 18:6a4db94011d3 | 630 | __O uint32_t INTENCLR; /*!< (@ 0x4005000C) Interrupt Enable Clear register. */ |
sahilmgandhi | 18:6a4db94011d3 | 631 | __IO uint32_t TIMEOUT; /*!< (@ 0x40050010) Time-out value register. */ |
sahilmgandhi | 18:6a4db94011d3 | 632 | __IO uint32_t CLKDIV; /*!< (@ 0x40050014) Clock pre-divider for the entire I2C block. This |
sahilmgandhi | 18:6a4db94011d3 | 633 | determines what time increments are used for the MSTTIME and |
sahilmgandhi | 18:6a4db94011d3 | 634 | SLVTIME registers. */ |
sahilmgandhi | 18:6a4db94011d3 | 635 | __I uint32_t INTSTAT; /*!< (@ 0x40050018) Interrupt Status register for Master, Slave, |
sahilmgandhi | 18:6a4db94011d3 | 636 | and Monitor functions. */ |
sahilmgandhi | 18:6a4db94011d3 | 637 | __I uint32_t RESERVED0; |
sahilmgandhi | 18:6a4db94011d3 | 638 | __IO uint32_t MSTCTL; /*!< (@ 0x40050020) Master control register. */ |
sahilmgandhi | 18:6a4db94011d3 | 639 | __IO uint32_t MSTTIME; /*!< (@ 0x40050024) Master timing configuration. */ |
sahilmgandhi | 18:6a4db94011d3 | 640 | __IO uint32_t MSTDAT; /*!< (@ 0x40050028) Combined Master receiver and transmitter data |
sahilmgandhi | 18:6a4db94011d3 | 641 | register. */ |
sahilmgandhi | 18:6a4db94011d3 | 642 | __I uint32_t RESERVED1[5]; |
sahilmgandhi | 18:6a4db94011d3 | 643 | __IO uint32_t SLVCTL; /*!< (@ 0x40050040) Slave control register. */ |
sahilmgandhi | 18:6a4db94011d3 | 644 | __IO uint32_t SLVDAT; /*!< (@ 0x40050044) Combined Slave receiver and transmitter data |
sahilmgandhi | 18:6a4db94011d3 | 645 | register. */ |
sahilmgandhi | 18:6a4db94011d3 | 646 | union { |
sahilmgandhi | 18:6a4db94011d3 | 647 | __IO uint32_t SLVADR[4]; |
sahilmgandhi | 18:6a4db94011d3 | 648 | struct { |
sahilmgandhi | 18:6a4db94011d3 | 649 | __IO uint32_t SLVADR0; /*!< (@ 0x40050048) Slave address 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 650 | __IO uint32_t SLVADR1; /*!< (@ 0x4005004C) Slave address 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 651 | __IO uint32_t SLVADR2; /*!< (@ 0x40050050) Slave address 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 652 | __IO uint32_t SLVADR3; /*!< (@ 0x40050054) Slave address 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 653 | }; |
sahilmgandhi | 18:6a4db94011d3 | 654 | }; |
sahilmgandhi | 18:6a4db94011d3 | 655 | __IO uint32_t SLVQUAL0; /*!< (@ 0x40050058) Slave Qualification for address 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 656 | __I uint32_t RESERVED2[9]; |
sahilmgandhi | 18:6a4db94011d3 | 657 | __I uint32_t MONRXDAT; /*!< (@ 0x40050080) Monitor receiver data register. */ |
sahilmgandhi | 18:6a4db94011d3 | 658 | } LPC_I2C0_Type; |
sahilmgandhi | 18:6a4db94011d3 | 659 | |
sahilmgandhi | 18:6a4db94011d3 | 660 | |
sahilmgandhi | 18:6a4db94011d3 | 661 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 662 | /* ================ SPI0 ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 663 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 664 | |
sahilmgandhi | 18:6a4db94011d3 | 665 | |
sahilmgandhi | 18:6a4db94011d3 | 666 | /** |
sahilmgandhi | 18:6a4db94011d3 | 667 | * @brief SPI0 (SPI0) |
sahilmgandhi | 18:6a4db94011d3 | 668 | */ |
sahilmgandhi | 18:6a4db94011d3 | 669 | |
sahilmgandhi | 18:6a4db94011d3 | 670 | typedef struct { /*!< (@ 0x40058000) SPI0 Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 671 | __IO uint32_t CFG; /*!< (@ 0x40058000) SPI Configuration register */ |
sahilmgandhi | 18:6a4db94011d3 | 672 | __IO uint32_t DLY; /*!< (@ 0x40058004) SPI Delay register */ |
sahilmgandhi | 18:6a4db94011d3 | 673 | __IO uint32_t STAT; /*!< (@ 0x40058008) SPI Status. Some status flags can be cleared |
sahilmgandhi | 18:6a4db94011d3 | 674 | by writing a 1 to that bit position */ |
sahilmgandhi | 18:6a4db94011d3 | 675 | __IO uint32_t INTENSET; /*!< (@ 0x4005800C) SPI Interrupt Enable read and Set. A complete |
sahilmgandhi | 18:6a4db94011d3 | 676 | value may be read from this register. Writing a 1 to any implemented |
sahilmgandhi | 18:6a4db94011d3 | 677 | bit position causes that bit to be set. */ |
sahilmgandhi | 18:6a4db94011d3 | 678 | __O uint32_t INTENCLR; /*!< (@ 0x40058010) SPI Interrupt Enable Clear. Writing a 1 to any |
sahilmgandhi | 18:6a4db94011d3 | 679 | implemented bit position causes the corresponding bit in INTENSET |
sahilmgandhi | 18:6a4db94011d3 | 680 | to be cleared. */ |
sahilmgandhi | 18:6a4db94011d3 | 681 | __I uint32_t RXDAT; /*!< (@ 0x40058014) SPI Receive Data */ |
sahilmgandhi | 18:6a4db94011d3 | 682 | __IO uint32_t TXDATCTL; /*!< (@ 0x40058018) SPI Transmit Data with Control */ |
sahilmgandhi | 18:6a4db94011d3 | 683 | __IO uint32_t TXDAT; /*!< (@ 0x4005801C) SPI Transmit Data */ |
sahilmgandhi | 18:6a4db94011d3 | 684 | __IO uint32_t TXCTL; /*!< (@ 0x40058020) SPI Transmit Control */ |
sahilmgandhi | 18:6a4db94011d3 | 685 | __IO uint32_t DIV; /*!< (@ 0x40058024) SPI clock Divider */ |
sahilmgandhi | 18:6a4db94011d3 | 686 | __I uint32_t INTSTAT; /*!< (@ 0x40058028) SPI Interrupt Status */ |
sahilmgandhi | 18:6a4db94011d3 | 687 | } LPC_SPI0_Type; |
sahilmgandhi | 18:6a4db94011d3 | 688 | |
sahilmgandhi | 18:6a4db94011d3 | 689 | |
sahilmgandhi | 18:6a4db94011d3 | 690 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 691 | /* ================ USART0 ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 692 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 693 | |
sahilmgandhi | 18:6a4db94011d3 | 694 | |
sahilmgandhi | 18:6a4db94011d3 | 695 | /** |
sahilmgandhi | 18:6a4db94011d3 | 696 | * @brief USART0 (USART0) |
sahilmgandhi | 18:6a4db94011d3 | 697 | */ |
sahilmgandhi | 18:6a4db94011d3 | 698 | |
sahilmgandhi | 18:6a4db94011d3 | 699 | typedef struct { /*!< (@ 0x40064000) USART0 Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 700 | __IO uint32_t CFG; /*!< (@ 0x40064000) USART Configuration register. Basic USART configuration |
sahilmgandhi | 18:6a4db94011d3 | 701 | settings that typically are not changed during operation. */ |
sahilmgandhi | 18:6a4db94011d3 | 702 | __IO uint32_t CTL; /*!< (@ 0x40064004) USART Control register. USART control settings |
sahilmgandhi | 18:6a4db94011d3 | 703 | that are more likely to change during operation. */ |
sahilmgandhi | 18:6a4db94011d3 | 704 | __IO uint32_t STAT; /*!< (@ 0x40064008) USART Status register. The complete status value |
sahilmgandhi | 18:6a4db94011d3 | 705 | can be read here. Writing ones clears some bits in the register. |
sahilmgandhi | 18:6a4db94011d3 | 706 | Some bits can be cleared by writing a 1 to them. */ |
sahilmgandhi | 18:6a4db94011d3 | 707 | __IO uint32_t INTENSET; /*!< (@ 0x4006400C) Interrupt Enable read and Set register. Contains |
sahilmgandhi | 18:6a4db94011d3 | 708 | an individual interrupt enable bit for each potential USART |
sahilmgandhi | 18:6a4db94011d3 | 709 | interrupt. A complete value may be read from this register. |
sahilmgandhi | 18:6a4db94011d3 | 710 | Writing a 1 to any implemented bit position causes that bit |
sahilmgandhi | 18:6a4db94011d3 | 711 | to be set. */ |
sahilmgandhi | 18:6a4db94011d3 | 712 | __O uint32_t INTENCLR; /*!< (@ 0x40064010) Interrupt Enable Clear register. Allows clearing |
sahilmgandhi | 18:6a4db94011d3 | 713 | any combination of bits in the INTENSET register. Writing a |
sahilmgandhi | 18:6a4db94011d3 | 714 | 1 to any implemented bit position causes the corresponding bit |
sahilmgandhi | 18:6a4db94011d3 | 715 | to be cleared. */ |
sahilmgandhi | 18:6a4db94011d3 | 716 | __I uint32_t RXDAT; /*!< (@ 0x40064014) Receiver Data register. Contains the last character |
sahilmgandhi | 18:6a4db94011d3 | 717 | received. */ |
sahilmgandhi | 18:6a4db94011d3 | 718 | __I uint32_t RXDATSTAT; /*!< (@ 0x40064018) Receiver Data with Status register. Combines |
sahilmgandhi | 18:6a4db94011d3 | 719 | the last character received with the current USART receive status. |
sahilmgandhi | 18:6a4db94011d3 | 720 | Allows DMA or software to recover incoming data and status together. */ |
sahilmgandhi | 18:6a4db94011d3 | 721 | __IO uint32_t TXDAT; /*!< (@ 0x4006401C) Transmit Data register. Data to be transmitted |
sahilmgandhi | 18:6a4db94011d3 | 722 | is written here. */ |
sahilmgandhi | 18:6a4db94011d3 | 723 | __IO uint32_t BRG; /*!< (@ 0x40064020) Baud Rate Generator register. 16-bit integer |
sahilmgandhi | 18:6a4db94011d3 | 724 | baud rate divisor value. */ |
sahilmgandhi | 18:6a4db94011d3 | 725 | __I uint32_t INTSTAT; /*!< (@ 0x40064024) Interrupt status register. Reflects interrupts |
sahilmgandhi | 18:6a4db94011d3 | 726 | that are currently enabled. */ |
sahilmgandhi | 18:6a4db94011d3 | 727 | __IO uint32_t OSR; /*!< (@ 0x40064028) Oversample selection register for asynchronous |
sahilmgandhi | 18:6a4db94011d3 | 728 | communication. */ |
sahilmgandhi | 18:6a4db94011d3 | 729 | __IO uint32_t ADDR; /*!< (@ 0x4006402C) Address register for automatic address matching. */ |
sahilmgandhi | 18:6a4db94011d3 | 730 | } LPC_USART0_Type; |
sahilmgandhi | 18:6a4db94011d3 | 731 | |
sahilmgandhi | 18:6a4db94011d3 | 732 | |
sahilmgandhi | 18:6a4db94011d3 | 733 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 734 | /* ================ CRC ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 735 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 736 | |
sahilmgandhi | 18:6a4db94011d3 | 737 | |
sahilmgandhi | 18:6a4db94011d3 | 738 | /** |
sahilmgandhi | 18:6a4db94011d3 | 739 | * @brief Cyclic Redundancy Check (CRC) engine (CRC) |
sahilmgandhi | 18:6a4db94011d3 | 740 | */ |
sahilmgandhi | 18:6a4db94011d3 | 741 | |
sahilmgandhi | 18:6a4db94011d3 | 742 | typedef struct { /*!< (@ 0x50000000) CRC Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 743 | __IO uint32_t MODE; /*!< (@ 0x50000000) CRC mode register */ |
sahilmgandhi | 18:6a4db94011d3 | 744 | __IO uint32_t SEED; /*!< (@ 0x50000004) CRC seed register */ |
sahilmgandhi | 18:6a4db94011d3 | 745 | |
sahilmgandhi | 18:6a4db94011d3 | 746 | union { |
sahilmgandhi | 18:6a4db94011d3 | 747 | __O uint32_t WR_DATA; /*!< (@ 0x50000008) CRC data register */ |
sahilmgandhi | 18:6a4db94011d3 | 748 | __I uint32_t SUM; /*!< (@ 0x50000008) CRC checksum register */ |
sahilmgandhi | 18:6a4db94011d3 | 749 | }; |
sahilmgandhi | 18:6a4db94011d3 | 750 | } LPC_CRC_Type; |
sahilmgandhi | 18:6a4db94011d3 | 751 | |
sahilmgandhi | 18:6a4db94011d3 | 752 | |
sahilmgandhi | 18:6a4db94011d3 | 753 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 754 | /* ================ SCT ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 755 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 756 | |
sahilmgandhi | 18:6a4db94011d3 | 757 | |
sahilmgandhi | 18:6a4db94011d3 | 758 | /** |
sahilmgandhi | 18:6a4db94011d3 | 759 | * @brief State Configurable Timer (SCT) (SCT) |
sahilmgandhi | 18:6a4db94011d3 | 760 | */ |
sahilmgandhi | 18:6a4db94011d3 | 761 | |
sahilmgandhi | 18:6a4db94011d3 | 762 | typedef struct { /*!< (@ 0x50004000) SCT Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 763 | __IO uint32_t CONFIG; /*!< (@ 0x50004000) SCT configuration register */ |
sahilmgandhi | 18:6a4db94011d3 | 764 | __IO uint32_t CTRL; /*!< (@ 0x50004004) SCT control register */ |
sahilmgandhi | 18:6a4db94011d3 | 765 | __IO uint32_t LIMIT; /*!< (@ 0x50004008) SCT limit register */ |
sahilmgandhi | 18:6a4db94011d3 | 766 | __IO uint32_t HALT; /*!< (@ 0x5000400C) SCT halt condition register */ |
sahilmgandhi | 18:6a4db94011d3 | 767 | __IO uint32_t STOP; /*!< (@ 0x50004010) SCT stop condition register */ |
sahilmgandhi | 18:6a4db94011d3 | 768 | __IO uint32_t START; /*!< (@ 0x50004014) SCT start condition register */ |
sahilmgandhi | 18:6a4db94011d3 | 769 | __I uint32_t RESERVED0[10]; |
sahilmgandhi | 18:6a4db94011d3 | 770 | __IO uint32_t COUNT; /*!< (@ 0x50004040) SCT counter register */ |
sahilmgandhi | 18:6a4db94011d3 | 771 | __IO uint32_t STATE; /*!< (@ 0x50004044) SCT state register */ |
sahilmgandhi | 18:6a4db94011d3 | 772 | __I uint32_t INPUT; /*!< (@ 0x50004048) SCT input register */ |
sahilmgandhi | 18:6a4db94011d3 | 773 | __IO uint32_t REGMODE; /*!< (@ 0x5000404C) SCT match/capture registers mode register */ |
sahilmgandhi | 18:6a4db94011d3 | 774 | __IO uint32_t OUTPUT; /*!< (@ 0x50004050) SCT output register */ |
sahilmgandhi | 18:6a4db94011d3 | 775 | __IO uint32_t OUTPUTDIRCTRL; /*!< (@ 0x50004054) SCT output counter direction control register */ |
sahilmgandhi | 18:6a4db94011d3 | 776 | __IO uint32_t RES; /*!< (@ 0x50004058) SCT conflict resolution register */ |
sahilmgandhi | 18:6a4db94011d3 | 777 | __IO uint32_t DMAREQ0; /*!< (@ 0x5000405C) SCT DMA request 0 register */ |
sahilmgandhi | 18:6a4db94011d3 | 778 | __IO uint32_t DMAREQ1; /*!< (@ 0x50004060) SCT DMA request 1 register */ |
sahilmgandhi | 18:6a4db94011d3 | 779 | __I uint32_t RESERVED1[35]; |
sahilmgandhi | 18:6a4db94011d3 | 780 | __IO uint32_t EVEN; /*!< (@ 0x500040F0) SCT event enable register */ |
sahilmgandhi | 18:6a4db94011d3 | 781 | __IO uint32_t EVFLAG; /*!< (@ 0x500040F4) SCT event flag register */ |
sahilmgandhi | 18:6a4db94011d3 | 782 | __IO uint32_t CONEN; /*!< (@ 0x500040F8) SCT conflict enable register */ |
sahilmgandhi | 18:6a4db94011d3 | 783 | __IO uint32_t CONFLAG; /*!< (@ 0x500040FC) SCT conflict flag register */ |
sahilmgandhi | 18:6a4db94011d3 | 784 | |
sahilmgandhi | 18:6a4db94011d3 | 785 | union { |
sahilmgandhi | 18:6a4db94011d3 | 786 | union { |
sahilmgandhi | 18:6a4db94011d3 | 787 | __IO uint32_t CAP0; /*!< (@ 0x50004100) SCT capture register of capture channel 0 to |
sahilmgandhi | 18:6a4db94011d3 | 788 | 7; REGMOD0 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 789 | __IO uint32_t MATCH0; /*!< (@ 0x50004100) SCT match value register of match channels 0 |
sahilmgandhi | 18:6a4db94011d3 | 790 | to 7; REGMOD0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 791 | }; |
sahilmgandhi | 18:6a4db94011d3 | 792 | |
sahilmgandhi | 18:6a4db94011d3 | 793 | union { |
sahilmgandhi | 18:6a4db94011d3 | 794 | __IO uint32_t CAP1; /*!< (@ 0x50004104) SCT capture register of capture channel 0 to |
sahilmgandhi | 18:6a4db94011d3 | 795 | 7; REGMOD0 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 796 | __IO uint32_t MATCH1; /*!< (@ 0x50004104) SCT match value register of match channels 0 |
sahilmgandhi | 18:6a4db94011d3 | 797 | to 7; REGMOD0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 798 | }; |
sahilmgandhi | 18:6a4db94011d3 | 799 | |
sahilmgandhi | 18:6a4db94011d3 | 800 | union { |
sahilmgandhi | 18:6a4db94011d3 | 801 | __IO uint32_t CAP2; /*!< (@ 0x50004108) SCT capture register of capture channel 0 to |
sahilmgandhi | 18:6a4db94011d3 | 802 | 7; REGMOD0 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 803 | __IO uint32_t MATCH2; /*!< (@ 0x50004108) SCT match value register of match channels 0 |
sahilmgandhi | 18:6a4db94011d3 | 804 | to 7; REGMOD0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 805 | }; |
sahilmgandhi | 18:6a4db94011d3 | 806 | |
sahilmgandhi | 18:6a4db94011d3 | 807 | union { |
sahilmgandhi | 18:6a4db94011d3 | 808 | __IO uint32_t MATCH3; /*!< (@ 0x5000410C) SCT match value register of match channels 0 |
sahilmgandhi | 18:6a4db94011d3 | 809 | to 7; REGMOD0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 810 | __IO uint32_t CAP3; /*!< (@ 0x5000410C) SCT capture register of capture channel 0 to |
sahilmgandhi | 18:6a4db94011d3 | 811 | 7; REGMOD0 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 812 | }; |
sahilmgandhi | 18:6a4db94011d3 | 813 | |
sahilmgandhi | 18:6a4db94011d3 | 814 | union { |
sahilmgandhi | 18:6a4db94011d3 | 815 | __IO uint32_t CAP4; /*!< (@ 0x50004110) SCT capture register of capture channel 0 to |
sahilmgandhi | 18:6a4db94011d3 | 816 | 7; REGMOD0 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 817 | __IO uint32_t MATCH4; /*!< (@ 0x50004110) SCT match value register of match channels 0 |
sahilmgandhi | 18:6a4db94011d3 | 818 | to 7; REGMOD0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 819 | }; |
sahilmgandhi | 18:6a4db94011d3 | 820 | |
sahilmgandhi | 18:6a4db94011d3 | 821 | union { |
sahilmgandhi | 18:6a4db94011d3 | 822 | __IO uint32_t MATCH5; /*!< (@ 0x50004114) SCT match value register of match channels 0 |
sahilmgandhi | 18:6a4db94011d3 | 823 | to 7; REGMOD0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 824 | __IO uint32_t CAP5; /*!< (@ 0x50004114) SCT capture register of capture channel 0 to |
sahilmgandhi | 18:6a4db94011d3 | 825 | 7; REGMOD0 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 826 | }; |
sahilmgandhi | 18:6a4db94011d3 | 827 | |
sahilmgandhi | 18:6a4db94011d3 | 828 | union { |
sahilmgandhi | 18:6a4db94011d3 | 829 | __IO uint32_t CAP6; /*!< (@ 0x50004118) SCT capture register of capture channel 0 to |
sahilmgandhi | 18:6a4db94011d3 | 830 | 7; REGMOD0 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 831 | __IO uint32_t MATCH6; /*!< (@ 0x50004118) SCT match value register of match channels 0 |
sahilmgandhi | 18:6a4db94011d3 | 832 | to 7; REGMOD0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 833 | }; |
sahilmgandhi | 18:6a4db94011d3 | 834 | |
sahilmgandhi | 18:6a4db94011d3 | 835 | union { |
sahilmgandhi | 18:6a4db94011d3 | 836 | __IO uint32_t CAP7; /*!< (@ 0x5000411C) SCT capture register of capture channel 0 to |
sahilmgandhi | 18:6a4db94011d3 | 837 | 7; REGMOD0 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 838 | __IO uint32_t MATCH7; /*!< (@ 0x5000411C) SCT match value register of match channels 0 |
sahilmgandhi | 18:6a4db94011d3 | 839 | to 7; REGMOD0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 840 | }; |
sahilmgandhi | 18:6a4db94011d3 | 841 | __IO uint32_t CAP[8]; |
sahilmgandhi | 18:6a4db94011d3 | 842 | __IO uint32_t MATCH[8]; |
sahilmgandhi | 18:6a4db94011d3 | 843 | }; |
sahilmgandhi | 18:6a4db94011d3 | 844 | __I uint32_t RESERVED2[56]; |
sahilmgandhi | 18:6a4db94011d3 | 845 | |
sahilmgandhi | 18:6a4db94011d3 | 846 | union { |
sahilmgandhi | 18:6a4db94011d3 | 847 | struct { |
sahilmgandhi | 18:6a4db94011d3 | 848 | union { |
sahilmgandhi | 18:6a4db94011d3 | 849 | __IO uint32_t CAPCTRL0; /*!< (@ 0x50004200) SCT capture control register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 850 | = 1 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 851 | __IO uint32_t MATCHREL0; /*!< (@ 0x50004200) SCT match reload value register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 852 | = 0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 853 | }; |
sahilmgandhi | 18:6a4db94011d3 | 854 | |
sahilmgandhi | 18:6a4db94011d3 | 855 | union { |
sahilmgandhi | 18:6a4db94011d3 | 856 | __IO uint32_t CAPCTRL1; /*!< (@ 0x50004204) SCT capture control register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 857 | = 1 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 858 | __IO uint32_t MATCHREL1; /*!< (@ 0x50004204) SCT match reload value register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 859 | = 0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 860 | }; |
sahilmgandhi | 18:6a4db94011d3 | 861 | |
sahilmgandhi | 18:6a4db94011d3 | 862 | union { |
sahilmgandhi | 18:6a4db94011d3 | 863 | __IO uint32_t CAPCTRL2; /*!< (@ 0x50004208) SCT capture control register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 864 | = 1 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 865 | __IO uint32_t MATCHREL2; /*!< (@ 0x50004208) SCT match reload value register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 866 | = 0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 867 | }; |
sahilmgandhi | 18:6a4db94011d3 | 868 | |
sahilmgandhi | 18:6a4db94011d3 | 869 | union { |
sahilmgandhi | 18:6a4db94011d3 | 870 | __IO uint32_t MATCHREL3; /*!< (@ 0x5000420C) SCT match reload value register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 871 | = 0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 872 | __IO uint32_t CAPCTRL3; /*!< (@ 0x5000420C) SCT capture control register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 873 | = 1 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 874 | }; |
sahilmgandhi | 18:6a4db94011d3 | 875 | |
sahilmgandhi | 18:6a4db94011d3 | 876 | union { |
sahilmgandhi | 18:6a4db94011d3 | 877 | __IO uint32_t CAPCTRL4; /*!< (@ 0x50004210) SCT capture control register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 878 | = 1 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 879 | __IO uint32_t MATCHREL4; /*!< (@ 0x50004210) SCT match reload value register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 880 | = 0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 881 | }; |
sahilmgandhi | 18:6a4db94011d3 | 882 | |
sahilmgandhi | 18:6a4db94011d3 | 883 | union { |
sahilmgandhi | 18:6a4db94011d3 | 884 | __IO uint32_t CAPCTRL5; /*!< (@ 0x50004214) SCT capture control register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 885 | = 1 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 886 | __IO uint32_t MATCHREL5; /*!< (@ 0x50004214) SCT match reload value register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 887 | = 0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 888 | }; |
sahilmgandhi | 18:6a4db94011d3 | 889 | |
sahilmgandhi | 18:6a4db94011d3 | 890 | union { |
sahilmgandhi | 18:6a4db94011d3 | 891 | __IO uint32_t CAPCTRL6; /*!< (@ 0x50004218) SCT capture control register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 892 | = 1 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 893 | __IO uint32_t MATCHREL6; /*!< (@ 0x50004218) SCT match reload value register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 894 | = 0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 895 | }; |
sahilmgandhi | 18:6a4db94011d3 | 896 | |
sahilmgandhi | 18:6a4db94011d3 | 897 | union { |
sahilmgandhi | 18:6a4db94011d3 | 898 | __IO uint32_t CAPCTRL7; /*!< (@ 0x5000421C) SCT capture control register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 899 | = 1 to REGMODE7 = 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 900 | __IO uint32_t MATCHREL7; /*!< (@ 0x5000421C) SCT match reload value register 0 to 7; REGMOD0 |
sahilmgandhi | 18:6a4db94011d3 | 901 | = 0 to REGMODE7 = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 902 | }; |
sahilmgandhi | 18:6a4db94011d3 | 903 | }; |
sahilmgandhi | 18:6a4db94011d3 | 904 | __IO uint32_t MATCHREL[8]; |
sahilmgandhi | 18:6a4db94011d3 | 905 | }; |
sahilmgandhi | 18:6a4db94011d3 | 906 | __I uint32_t RESERVED3[56]; |
sahilmgandhi | 18:6a4db94011d3 | 907 | |
sahilmgandhi | 18:6a4db94011d3 | 908 | union { |
sahilmgandhi | 18:6a4db94011d3 | 909 | struct { |
sahilmgandhi | 18:6a4db94011d3 | 910 | __IO uint32_t EV0_STATE; /*!< (@ 0x50004300) SCT event state register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 911 | __IO uint32_t EV0_CTRL; /*!< (@ 0x50004304) SCT event control register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 912 | __IO uint32_t EV1_STATE; /*!< (@ 0x50004308) SCT event state register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 913 | __IO uint32_t EV1_CTRL; /*!< (@ 0x5000430C) SCT event control register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 914 | __IO uint32_t EV2_STATE; /*!< (@ 0x50004310) SCT event state register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 915 | __IO uint32_t EV2_CTRL; /*!< (@ 0x50004314) SCT event control register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 916 | __IO uint32_t EV3_STATE; /*!< (@ 0x50004318) SCT event state register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 917 | __IO uint32_t EV3_CTRL; /*!< (@ 0x5000431C) SCT event control register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 918 | __IO uint32_t EV4_STATE; /*!< (@ 0x50004320) SCT event state register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 919 | __IO uint32_t EV4_CTRL; /*!< (@ 0x50004324) SCT event control register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 920 | __IO uint32_t EV5_STATE; /*!< (@ 0x50004328) SCT event state register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 921 | __IO uint32_t EV5_CTRL; /*!< (@ 0x5000432C) SCT event control register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 922 | __IO uint32_t EV6_STATE; /*!< (@ 0x50004330) SCT event state register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 923 | __IO uint32_t EV6_CTRL; /*!< (@ 0x50004334) SCT event control register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 924 | __IO uint32_t EV7_STATE; /*!< (@ 0x50004338) SCT event state register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 925 | __IO uint32_t EV7_CTRL; /*!< (@ 0x5000433C) SCT event control register 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 926 | }; |
sahilmgandhi | 18:6a4db94011d3 | 927 | __IO struct { |
sahilmgandhi | 18:6a4db94011d3 | 928 | uint32_t STATE; |
sahilmgandhi | 18:6a4db94011d3 | 929 | uint32_t CTRL; |
sahilmgandhi | 18:6a4db94011d3 | 930 | } EVENT[8]; |
sahilmgandhi | 18:6a4db94011d3 | 931 | }; |
sahilmgandhi | 18:6a4db94011d3 | 932 | |
sahilmgandhi | 18:6a4db94011d3 | 933 | __I uint32_t RESERVED4[112]; |
sahilmgandhi | 18:6a4db94011d3 | 934 | |
sahilmgandhi | 18:6a4db94011d3 | 935 | union { |
sahilmgandhi | 18:6a4db94011d3 | 936 | struct { |
sahilmgandhi | 18:6a4db94011d3 | 937 | __IO uint32_t OUT0_SET; /*!< (@ 0x50004500) SCT output 0 set register */ |
sahilmgandhi | 18:6a4db94011d3 | 938 | __IO uint32_t OUT0_CLR; /*!< (@ 0x50004504) SCT output 0 clear register */ |
sahilmgandhi | 18:6a4db94011d3 | 939 | __IO uint32_t OUT1_SET; /*!< (@ 0x50004508) SCT output 0 set register */ |
sahilmgandhi | 18:6a4db94011d3 | 940 | __IO uint32_t OUT1_CLR; /*!< (@ 0x5000450C) SCT output 0 clear register */ |
sahilmgandhi | 18:6a4db94011d3 | 941 | __IO uint32_t OUT2_SET; /*!< (@ 0x50004510) SCT output 0 set register */ |
sahilmgandhi | 18:6a4db94011d3 | 942 | __IO uint32_t OUT2_CLR; /*!< (@ 0x50004514) SCT output 0 clear register */ |
sahilmgandhi | 18:6a4db94011d3 | 943 | __IO uint32_t OUT3_SET; /*!< (@ 0x50004518) SCT output 0 set register */ |
sahilmgandhi | 18:6a4db94011d3 | 944 | __IO uint32_t OUT3_CLR; /*!< (@ 0x5000451C) SCT output 0 clear register */ |
sahilmgandhi | 18:6a4db94011d3 | 945 | __IO uint32_t OUT4_SET; /*!< (@ 0x50004520) SCT output 0 set register */ |
sahilmgandhi | 18:6a4db94011d3 | 946 | __IO uint32_t OUT4_CLR; /*!< (@ 0x50004524) SCT output 0 clear register */ |
sahilmgandhi | 18:6a4db94011d3 | 947 | __IO uint32_t OUT5_SET; /*!< (@ 0x50004528) SCT output 0 set register */ |
sahilmgandhi | 18:6a4db94011d3 | 948 | __IO uint32_t OUT5_CLR; /*!< (@ 0x5000452C) SCT output 0 clear register */ |
sahilmgandhi | 18:6a4db94011d3 | 949 | }; |
sahilmgandhi | 18:6a4db94011d3 | 950 | __IO struct { |
sahilmgandhi | 18:6a4db94011d3 | 951 | uint32_t SET; |
sahilmgandhi | 18:6a4db94011d3 | 952 | uint32_t CLR; |
sahilmgandhi | 18:6a4db94011d3 | 953 | } OUT[6]; |
sahilmgandhi | 18:6a4db94011d3 | 954 | }; |
sahilmgandhi | 18:6a4db94011d3 | 955 | |
sahilmgandhi | 18:6a4db94011d3 | 956 | } LPC_SCT_Type; |
sahilmgandhi | 18:6a4db94011d3 | 957 | |
sahilmgandhi | 18:6a4db94011d3 | 958 | |
sahilmgandhi | 18:6a4db94011d3 | 959 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 960 | /* ================ DMA ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 961 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 962 | |
sahilmgandhi | 18:6a4db94011d3 | 963 | |
sahilmgandhi | 18:6a4db94011d3 | 964 | /** |
sahilmgandhi | 18:6a4db94011d3 | 965 | * @brief DMA controller (DMA) |
sahilmgandhi | 18:6a4db94011d3 | 966 | */ |
sahilmgandhi | 18:6a4db94011d3 | 967 | |
sahilmgandhi | 18:6a4db94011d3 | 968 | typedef struct { /*!< (@ 0x50008000) DMA Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 969 | __IO uint32_t CTRL; /*!< (@ 0x50008000) DMA control. */ |
sahilmgandhi | 18:6a4db94011d3 | 970 | __I uint32_t INTSTAT; /*!< (@ 0x50008004) Interrupt status. */ |
sahilmgandhi | 18:6a4db94011d3 | 971 | __IO uint32_t SRAMBASE; /*!< (@ 0x50008008) SRAM address of the channel configuration table. */ |
sahilmgandhi | 18:6a4db94011d3 | 972 | __I uint32_t RESERVED0[5]; |
sahilmgandhi | 18:6a4db94011d3 | 973 | __IO uint32_t ENABLESET0; /*!< (@ 0x50008020) Channel Enable read and Set for all DMA channels. */ |
sahilmgandhi | 18:6a4db94011d3 | 974 | __I uint32_t RESERVED1; |
sahilmgandhi | 18:6a4db94011d3 | 975 | __O uint32_t ENABLECLR0; /*!< (@ 0x50008028) Channel Enable Clear for all DMA channels. */ |
sahilmgandhi | 18:6a4db94011d3 | 976 | __I uint32_t RESERVED2; |
sahilmgandhi | 18:6a4db94011d3 | 977 | __I uint32_t ACTIVE0; /*!< (@ 0x50008030) Channel Active status for all DMA channels. */ |
sahilmgandhi | 18:6a4db94011d3 | 978 | __I uint32_t RESERVED3; |
sahilmgandhi | 18:6a4db94011d3 | 979 | __I uint32_t BUSY0; /*!< (@ 0x50008038) Channel Busy status for all DMA channels. */ |
sahilmgandhi | 18:6a4db94011d3 | 980 | __I uint32_t RESERVED4; |
sahilmgandhi | 18:6a4db94011d3 | 981 | __IO uint32_t ERRINT0; /*!< (@ 0x50008040) Error Interrupt status for all DMA channels. */ |
sahilmgandhi | 18:6a4db94011d3 | 982 | __I uint32_t RESERVED5; |
sahilmgandhi | 18:6a4db94011d3 | 983 | __IO uint32_t INTENSET0; /*!< (@ 0x50008048) Interrupt Enable read and Set for all DMA channels. */ |
sahilmgandhi | 18:6a4db94011d3 | 984 | __I uint32_t RESERVED6; |
sahilmgandhi | 18:6a4db94011d3 | 985 | __O uint32_t INTENCLR0; /*!< (@ 0x50008050) Interrupt Enable Clear for all DMA channels. */ |
sahilmgandhi | 18:6a4db94011d3 | 986 | __I uint32_t RESERVED7; |
sahilmgandhi | 18:6a4db94011d3 | 987 | __IO uint32_t INTA0; /*!< (@ 0x50008058) Interrupt A status for all DMA channels. */ |
sahilmgandhi | 18:6a4db94011d3 | 988 | __I uint32_t RESERVED8; |
sahilmgandhi | 18:6a4db94011d3 | 989 | __IO uint32_t INTB0; /*!< (@ 0x50008060) Interrupt B status for all DMA channels. */ |
sahilmgandhi | 18:6a4db94011d3 | 990 | __I uint32_t RESERVED9; |
sahilmgandhi | 18:6a4db94011d3 | 991 | __O uint32_t SETVALID0; /*!< (@ 0x50008068) Set ValidPending control bits for all DMA channels. */ |
sahilmgandhi | 18:6a4db94011d3 | 992 | __I uint32_t RESERVED10; |
sahilmgandhi | 18:6a4db94011d3 | 993 | __O uint32_t SETTRIG0; /*!< (@ 0x50008070) Set Trigger control bits for all DMA channels. */ |
sahilmgandhi | 18:6a4db94011d3 | 994 | __I uint32_t RESERVED11; |
sahilmgandhi | 18:6a4db94011d3 | 995 | __O uint32_t ABORT0; /*!< (@ 0x50008078) Channel Abort control for all DMA channels. */ |
sahilmgandhi | 18:6a4db94011d3 | 996 | __I uint32_t RESERVED12[225]; |
sahilmgandhi | 18:6a4db94011d3 | 997 | __IO uint32_t CFG0; /*!< (@ 0x50008400) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 998 | __I uint32_t CTLSTAT0; /*!< (@ 0x50008404) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 999 | __IO uint32_t XFERCFG0; /*!< (@ 0x50008408) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1000 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1001 | __I uint32_t RESERVED13; |
sahilmgandhi | 18:6a4db94011d3 | 1002 | __IO uint32_t CFG1; /*!< (@ 0x50008410) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1003 | __I uint32_t CTLSTAT1; /*!< (@ 0x50008414) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1004 | __IO uint32_t XFERCFG1; /*!< (@ 0x50008418) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1005 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1006 | __I uint32_t RESERVED14; |
sahilmgandhi | 18:6a4db94011d3 | 1007 | __IO uint32_t CFG2; /*!< (@ 0x50008420) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1008 | __I uint32_t CTLSTAT2; /*!< (@ 0x50008424) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1009 | __IO uint32_t XFERCFG2; /*!< (@ 0x50008428) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1010 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1011 | __I uint32_t RESERVED15; |
sahilmgandhi | 18:6a4db94011d3 | 1012 | __IO uint32_t CFG3; /*!< (@ 0x50008430) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1013 | __I uint32_t CTLSTAT3; /*!< (@ 0x50008434) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1014 | __IO uint32_t XFERCFG3; /*!< (@ 0x50008438) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1015 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1016 | __I uint32_t RESERVED16; |
sahilmgandhi | 18:6a4db94011d3 | 1017 | __IO uint32_t CFG4; /*!< (@ 0x50008440) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1018 | __I uint32_t CTLSTAT4; /*!< (@ 0x50008444) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1019 | __IO uint32_t XFERCFG4; /*!< (@ 0x50008448) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1020 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1021 | __I uint32_t RESERVED17; |
sahilmgandhi | 18:6a4db94011d3 | 1022 | __IO uint32_t CFG5; /*!< (@ 0x50008450) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1023 | __I uint32_t CTLSTAT5; /*!< (@ 0x50008454) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1024 | __IO uint32_t XFERCFG5; /*!< (@ 0x50008458) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1025 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1026 | __I uint32_t RESERVED18; |
sahilmgandhi | 18:6a4db94011d3 | 1027 | __IO uint32_t CFG6; /*!< (@ 0x50008460) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1028 | __I uint32_t CTLSTAT6; /*!< (@ 0x50008464) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1029 | __IO uint32_t XFERCFG6; /*!< (@ 0x50008468) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1030 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1031 | __I uint32_t RESERVED19; |
sahilmgandhi | 18:6a4db94011d3 | 1032 | __IO uint32_t CFG7; /*!< (@ 0x50008470) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1033 | __I uint32_t CTLSTAT7; /*!< (@ 0x50008474) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1034 | __IO uint32_t XFERCFG7; /*!< (@ 0x50008478) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1035 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1036 | __I uint32_t RESERVED20; |
sahilmgandhi | 18:6a4db94011d3 | 1037 | __IO uint32_t CFG8; /*!< (@ 0x50008480) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1038 | __I uint32_t CTLSTAT8; /*!< (@ 0x50008484) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1039 | __IO uint32_t XFERCFG8; /*!< (@ 0x50008488) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1040 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1041 | __I uint32_t RESERVED21; |
sahilmgandhi | 18:6a4db94011d3 | 1042 | __IO uint32_t CFG9; /*!< (@ 0x50008490) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1043 | __I uint32_t CTLSTAT9; /*!< (@ 0x50008494) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1044 | __IO uint32_t XFERCFG9; /*!< (@ 0x50008498) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1045 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1046 | __I uint32_t RESERVED22; |
sahilmgandhi | 18:6a4db94011d3 | 1047 | __IO uint32_t CFG10; /*!< (@ 0x500084A0) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1048 | __I uint32_t CTLSTAT10; /*!< (@ 0x500084A4) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1049 | __IO uint32_t XFERCFG10; /*!< (@ 0x500084A8) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1050 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1051 | __I uint32_t RESERVED23; |
sahilmgandhi | 18:6a4db94011d3 | 1052 | __IO uint32_t CFG11; /*!< (@ 0x500084B0) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1053 | __I uint32_t CTLSTAT11; /*!< (@ 0x500084B4) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1054 | __IO uint32_t XFERCFG11; /*!< (@ 0x500084B8) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1055 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1056 | __I uint32_t RESERVED24; |
sahilmgandhi | 18:6a4db94011d3 | 1057 | __IO uint32_t CFG12; /*!< (@ 0x500084C0) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1058 | __I uint32_t CTLSTAT12; /*!< (@ 0x500084C4) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1059 | __IO uint32_t XFERCFG12; /*!< (@ 0x500084C8) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1060 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1061 | __I uint32_t RESERVED25; |
sahilmgandhi | 18:6a4db94011d3 | 1062 | __IO uint32_t CFG13; /*!< (@ 0x500084D0) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1063 | __I uint32_t CTLSTAT13; /*!< (@ 0x500084D4) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1064 | __IO uint32_t XFERCFG13; /*!< (@ 0x500084D8) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1065 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1066 | __I uint32_t RESERVED26; |
sahilmgandhi | 18:6a4db94011d3 | 1067 | __IO uint32_t CFG14; /*!< (@ 0x500084E0) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1068 | __I uint32_t CTLSTAT14; /*!< (@ 0x500084E4) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1069 | __IO uint32_t XFERCFG14; /*!< (@ 0x500084E8) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1070 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1071 | __I uint32_t RESERVED27; |
sahilmgandhi | 18:6a4db94011d3 | 1072 | __IO uint32_t CFG15; /*!< (@ 0x500084F0) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1073 | __I uint32_t CTLSTAT15; /*!< (@ 0x500084F4) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1074 | __IO uint32_t XFERCFG15; /*!< (@ 0x500084F8) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1075 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1076 | __I uint32_t RESERVED28; |
sahilmgandhi | 18:6a4db94011d3 | 1077 | __IO uint32_t CFG16; /*!< (@ 0x50008500) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1078 | __I uint32_t CTLSTAT16; /*!< (@ 0x50008504) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1079 | __IO uint32_t XFERCFG16; /*!< (@ 0x50008508) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1080 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1081 | __I uint32_t RESERVED29; |
sahilmgandhi | 18:6a4db94011d3 | 1082 | __IO uint32_t CFG17; /*!< (@ 0x50008510) Configuration register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1083 | __I uint32_t CTLSTAT17; /*!< (@ 0x50008514) Control and status register for DMA channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1084 | __IO uint32_t XFERCFG17; /*!< (@ 0x50008518) Transfer configuration register for DMA channel |
sahilmgandhi | 18:6a4db94011d3 | 1085 | 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1086 | } LPC_DMA_Type; |
sahilmgandhi | 18:6a4db94011d3 | 1087 | |
sahilmgandhi | 18:6a4db94011d3 | 1088 | |
sahilmgandhi | 18:6a4db94011d3 | 1089 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 1090 | /* ================ GPIO_PORT ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 1091 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 1092 | |
sahilmgandhi | 18:6a4db94011d3 | 1093 | |
sahilmgandhi | 18:6a4db94011d3 | 1094 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1095 | * @brief General Purpose I/O port (GPIO) (GPIO_PORT) |
sahilmgandhi | 18:6a4db94011d3 | 1096 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1097 | |
sahilmgandhi | 18:6a4db94011d3 | 1098 | typedef struct { /*!< (@ 0xA0000000) GPIO_PORT Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 1099 | __IO uint8_t B0; /*!< (@ 0xA0000000) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1100 | __IO uint8_t B1; /*!< (@ 0xA0000001) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1101 | __IO uint8_t B2; /*!< (@ 0xA0000002) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1102 | __IO uint8_t B3; /*!< (@ 0xA0000003) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1103 | __IO uint8_t B4; /*!< (@ 0xA0000004) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1104 | __IO uint8_t B5; /*!< (@ 0xA0000005) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1105 | __IO uint8_t B6; /*!< (@ 0xA0000006) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1106 | __IO uint8_t B7; /*!< (@ 0xA0000007) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1107 | __IO uint8_t B8; /*!< (@ 0xA0000008) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1108 | __IO uint8_t B9; /*!< (@ 0xA0000009) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1109 | __IO uint8_t B10; /*!< (@ 0xA000000A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1110 | __IO uint8_t B11; /*!< (@ 0xA000000B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1111 | __IO uint8_t B12; /*!< (@ 0xA000000C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1112 | __IO uint8_t B13; /*!< (@ 0xA000000D) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1113 | __IO uint8_t B14; /*!< (@ 0xA000000E) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1114 | __IO uint8_t B15; /*!< (@ 0xA000000F) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1115 | __IO uint8_t B16; /*!< (@ 0xA0000010) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1116 | __IO uint8_t B17; /*!< (@ 0xA0000011) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1117 | __IO uint8_t B18; /*!< (@ 0xA0000012) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1118 | __IO uint8_t B19; /*!< (@ 0xA0000013) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1119 | __IO uint8_t B20; /*!< (@ 0xA0000014) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1120 | __IO uint8_t B21; /*!< (@ 0xA0000015) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1121 | __IO uint8_t B22; /*!< (@ 0xA0000016) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1122 | __IO uint8_t B23; /*!< (@ 0xA0000017) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1123 | __IO uint8_t B24; /*!< (@ 0xA0000018) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1124 | __IO uint8_t B25; /*!< (@ 0xA0000019) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1125 | __IO uint8_t B26; /*!< (@ 0xA000001A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1126 | __IO uint8_t B27; /*!< (@ 0xA000001B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1127 | __IO uint8_t B28; /*!< (@ 0xA000001C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ |
sahilmgandhi | 18:6a4db94011d3 | 1128 | __I uint8_t RESERVED0[4067]; |
sahilmgandhi | 18:6a4db94011d3 | 1129 | __IO uint32_t W0; /*!< (@ 0xA0001000) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1130 | __IO uint32_t W1; /*!< (@ 0xA0001004) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1131 | __IO uint32_t W2; /*!< (@ 0xA0001008) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1132 | __IO uint32_t W3; /*!< (@ 0xA000100C) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1133 | __IO uint32_t W4; /*!< (@ 0xA0001010) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1134 | __IO uint32_t W5; /*!< (@ 0xA0001014) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1135 | __IO uint32_t W6; /*!< (@ 0xA0001018) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1136 | __IO uint32_t W7; /*!< (@ 0xA000101C) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1137 | __IO uint32_t W8; /*!< (@ 0xA0001020) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1138 | __IO uint32_t W9; /*!< (@ 0xA0001024) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1139 | __IO uint32_t W10; /*!< (@ 0xA0001028) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1140 | __IO uint32_t W11; /*!< (@ 0xA000102C) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1141 | __IO uint32_t W12; /*!< (@ 0xA0001030) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1142 | __IO uint32_t W13; /*!< (@ 0xA0001034) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1143 | __IO uint32_t W14; /*!< (@ 0xA0001038) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1144 | __IO uint32_t W15; /*!< (@ 0xA000103C) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1145 | __IO uint32_t W16; /*!< (@ 0xA0001040) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1146 | __IO uint32_t W17; /*!< (@ 0xA0001044) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1147 | __IO uint32_t W18; /*!< (@ 0xA0001048) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1148 | __IO uint32_t W19; /*!< (@ 0xA000104C) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1149 | __IO uint32_t W20; /*!< (@ 0xA0001050) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1150 | __IO uint32_t W21; /*!< (@ 0xA0001054) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1151 | __IO uint32_t W22; /*!< (@ 0xA0001058) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1152 | __IO uint32_t W23; /*!< (@ 0xA000105C) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1153 | __IO uint32_t W24; /*!< (@ 0xA0001060) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1154 | __IO uint32_t W25; /*!< (@ 0xA0001064) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1155 | __IO uint32_t W26; /*!< (@ 0xA0001068) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1156 | __IO uint32_t W27; /*!< (@ 0xA000106C) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1157 | __IO uint32_t W28; /*!< (@ 0xA0001070) Word pin registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1158 | __I uint32_t RESERVED1[995]; |
sahilmgandhi | 18:6a4db94011d3 | 1159 | __IO uint32_t DIR0; /*!< (@ 0xA0002000) Direction registers port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1160 | __I uint32_t RESERVED2[31]; |
sahilmgandhi | 18:6a4db94011d3 | 1161 | __IO uint32_t MASK0; /*!< (@ 0xA0002080) Mask register port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1162 | __I uint32_t RESERVED3[31]; |
sahilmgandhi | 18:6a4db94011d3 | 1163 | __IO uint32_t PIN0; /*!< (@ 0xA0002100) Port pin register port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1164 | __I uint32_t RESERVED4[31]; |
sahilmgandhi | 18:6a4db94011d3 | 1165 | __IO uint32_t MPIN0; /*!< (@ 0xA0002180) Masked port register port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1166 | __I uint32_t RESERVED5[31]; |
sahilmgandhi | 18:6a4db94011d3 | 1167 | __IO uint32_t SET0; /*!< (@ 0xA0002200) Write: Set register for port 0 Read: output bits |
sahilmgandhi | 18:6a4db94011d3 | 1168 | for port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1169 | __I uint32_t RESERVED6[31]; |
sahilmgandhi | 18:6a4db94011d3 | 1170 | __O uint32_t CLR0; /*!< (@ 0xA0002280) Clear port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1171 | __I uint32_t RESERVED7[31]; |
sahilmgandhi | 18:6a4db94011d3 | 1172 | __O uint32_t NOT0; /*!< (@ 0xA0002300) Toggle port 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1173 | __I uint32_t RESERVED8[31]; |
sahilmgandhi | 18:6a4db94011d3 | 1174 | __O uint32_t DIRSET0; /*!< (@ 0xA0002380) Set pin direction bits for port 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1175 | __I uint32_t RESERVED9[31]; |
sahilmgandhi | 18:6a4db94011d3 | 1176 | __O uint32_t DIRCLR0; /*!< (@ 0xA0002400) Clear pin direction bits for port 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1177 | __I uint32_t RESERVED10[31]; |
sahilmgandhi | 18:6a4db94011d3 | 1178 | __O uint32_t DIRNOT0; /*!< (@ 0xA0002480) Toggle pin direction bits for port 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 1179 | } LPC_GPIO_PORT_Type; |
sahilmgandhi | 18:6a4db94011d3 | 1180 | |
sahilmgandhi | 18:6a4db94011d3 | 1181 | |
sahilmgandhi | 18:6a4db94011d3 | 1182 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 1183 | /* ================ PIN_INT ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 1184 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 1185 | |
sahilmgandhi | 18:6a4db94011d3 | 1186 | |
sahilmgandhi | 18:6a4db94011d3 | 1187 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1188 | * @brief Pin interrupt and pattern match engine (PIN_INT) |
sahilmgandhi | 18:6a4db94011d3 | 1189 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1190 | |
sahilmgandhi | 18:6a4db94011d3 | 1191 | typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */ |
sahilmgandhi | 18:6a4db94011d3 | 1192 | __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */ |
sahilmgandhi | 18:6a4db94011d3 | 1193 | __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin interrupt level or rising edge interrupt |
sahilmgandhi | 18:6a4db94011d3 | 1194 | enable register */ |
sahilmgandhi | 18:6a4db94011d3 | 1195 | __O uint32_t SIENR; /*!< (@ 0xA0004008) Pin interrupt level (rising edge) interrupt set |
sahilmgandhi | 18:6a4db94011d3 | 1196 | register */ |
sahilmgandhi | 18:6a4db94011d3 | 1197 | __O uint32_t CIENR; /*!< (@ 0xA000400C) Pin interrupt level or rising edge interrupt |
sahilmgandhi | 18:6a4db94011d3 | 1198 | clear register */ |
sahilmgandhi | 18:6a4db94011d3 | 1199 | __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin interrupt active level or falling edge interrupt |
sahilmgandhi | 18:6a4db94011d3 | 1200 | enable register */ |
sahilmgandhi | 18:6a4db94011d3 | 1201 | __O uint32_t SIENF; /*!< (@ 0xA0004014) Pin interrupt active level or falling edge interrupt |
sahilmgandhi | 18:6a4db94011d3 | 1202 | set register */ |
sahilmgandhi | 18:6a4db94011d3 | 1203 | __O uint32_t CIENF; /*!< (@ 0xA0004018) Pin interrupt active level (falling edge) interrupt |
sahilmgandhi | 18:6a4db94011d3 | 1204 | clear register */ |
sahilmgandhi | 18:6a4db94011d3 | 1205 | __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin interrupt rising edge register */ |
sahilmgandhi | 18:6a4db94011d3 | 1206 | __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin interrupt falling edge register */ |
sahilmgandhi | 18:6a4db94011d3 | 1207 | __IO uint32_t IST; /*!< (@ 0xA0004024) Pin interrupt status register */ |
sahilmgandhi | 18:6a4db94011d3 | 1208 | __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */ |
sahilmgandhi | 18:6a4db94011d3 | 1209 | __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source |
sahilmgandhi | 18:6a4db94011d3 | 1210 | register */ |
sahilmgandhi | 18:6a4db94011d3 | 1211 | __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration |
sahilmgandhi | 18:6a4db94011d3 | 1212 | register */ |
sahilmgandhi | 18:6a4db94011d3 | 1213 | } LPC_PIN_INT_Type; |
sahilmgandhi | 18:6a4db94011d3 | 1214 | |
sahilmgandhi | 18:6a4db94011d3 | 1215 | |
sahilmgandhi | 18:6a4db94011d3 | 1216 | /* -------------------- End of section using anonymous unions ------------------- */ |
sahilmgandhi | 18:6a4db94011d3 | 1217 | #if defined(__CC_ARM) |
sahilmgandhi | 18:6a4db94011d3 | 1218 | #pragma pop |
sahilmgandhi | 18:6a4db94011d3 | 1219 | #elif defined(__ICCARM__) |
sahilmgandhi | 18:6a4db94011d3 | 1220 | /* leave anonymous unions enabled */ |
sahilmgandhi | 18:6a4db94011d3 | 1221 | #elif defined(__GNUC__) |
sahilmgandhi | 18:6a4db94011d3 | 1222 | /* anonymous unions are enabled by default */ |
sahilmgandhi | 18:6a4db94011d3 | 1223 | #elif defined(__TMS470__) |
sahilmgandhi | 18:6a4db94011d3 | 1224 | /* anonymous unions are enabled by default */ |
sahilmgandhi | 18:6a4db94011d3 | 1225 | #elif defined(__TASKING__) |
sahilmgandhi | 18:6a4db94011d3 | 1226 | #pragma warning restore |
sahilmgandhi | 18:6a4db94011d3 | 1227 | #else |
sahilmgandhi | 18:6a4db94011d3 | 1228 | #warning Not supported compiler type |
sahilmgandhi | 18:6a4db94011d3 | 1229 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1230 | |
sahilmgandhi | 18:6a4db94011d3 | 1231 | |
sahilmgandhi | 18:6a4db94011d3 | 1232 | |
sahilmgandhi | 18:6a4db94011d3 | 1233 | |
sahilmgandhi | 18:6a4db94011d3 | 1234 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 1235 | /* ================ Peripheral memory map ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 1236 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 1237 | |
sahilmgandhi | 18:6a4db94011d3 | 1238 | #define LPC_WWDT_BASE 0x40000000UL |
sahilmgandhi | 18:6a4db94011d3 | 1239 | #define LPC_MRT_BASE 0x40004000UL |
sahilmgandhi | 18:6a4db94011d3 | 1240 | #define LPC_WKT_BASE 0x40008000UL |
sahilmgandhi | 18:6a4db94011d3 | 1241 | #define LPC_SWM_BASE 0x4000C000UL |
sahilmgandhi | 18:6a4db94011d3 | 1242 | #define LPC_ADC_BASE 0x4001C000UL |
sahilmgandhi | 18:6a4db94011d3 | 1243 | #define LPC_PMU_BASE 0x40020000UL |
sahilmgandhi | 18:6a4db94011d3 | 1244 | #define LPC_CMP_BASE 0x40024000UL |
sahilmgandhi | 18:6a4db94011d3 | 1245 | #define LPC_DMATRIGMUX_BASE 0x40028000UL |
sahilmgandhi | 18:6a4db94011d3 | 1246 | #define LPC_INPUTMUX_BASE 0x4002C000UL |
sahilmgandhi | 18:6a4db94011d3 | 1247 | #define LPC_FLASHCTRL_BASE 0x40040000UL |
sahilmgandhi | 18:6a4db94011d3 | 1248 | #define LPC_IOCON_BASE 0x40044000UL |
sahilmgandhi | 18:6a4db94011d3 | 1249 | #define LPC_SYSCON_BASE 0x40048000UL |
sahilmgandhi | 18:6a4db94011d3 | 1250 | #define LPC_I2C0_BASE 0x40050000UL |
sahilmgandhi | 18:6a4db94011d3 | 1251 | #define LPC_I2C1_BASE 0x40054000UL |
sahilmgandhi | 18:6a4db94011d3 | 1252 | #define LPC_SPI0_BASE 0x40058000UL |
sahilmgandhi | 18:6a4db94011d3 | 1253 | #define LPC_SPI1_BASE 0x4005C000UL |
sahilmgandhi | 18:6a4db94011d3 | 1254 | #define LPC_USART0_BASE 0x40064000UL |
sahilmgandhi | 18:6a4db94011d3 | 1255 | #define LPC_USART1_BASE 0x40068000UL |
sahilmgandhi | 18:6a4db94011d3 | 1256 | #define LPC_USART2_BASE 0x4006C000UL |
sahilmgandhi | 18:6a4db94011d3 | 1257 | #define LPC_I2C2_BASE 0x40070000UL |
sahilmgandhi | 18:6a4db94011d3 | 1258 | #define LPC_I2C3_BASE 0x40074000UL |
sahilmgandhi | 18:6a4db94011d3 | 1259 | #define LPC_CRC_BASE 0x50000000UL |
sahilmgandhi | 18:6a4db94011d3 | 1260 | #define LPC_SCT_BASE 0x50004000UL |
sahilmgandhi | 18:6a4db94011d3 | 1261 | #define LPC_DMA_BASE 0x50008000UL |
sahilmgandhi | 18:6a4db94011d3 | 1262 | #define LPC_GPIO_PORT_BASE 0xA0000000UL |
sahilmgandhi | 18:6a4db94011d3 | 1263 | #define LPC_PIN_INT_BASE 0xA0004000UL |
sahilmgandhi | 18:6a4db94011d3 | 1264 | |
sahilmgandhi | 18:6a4db94011d3 | 1265 | |
sahilmgandhi | 18:6a4db94011d3 | 1266 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 1267 | /* ================ Peripheral declaration ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 1268 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 1269 | |
sahilmgandhi | 18:6a4db94011d3 | 1270 | #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1271 | #define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1272 | #define LPC_WKT ((LPC_WKT_Type *) LPC_WKT_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1273 | #define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1274 | #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1275 | #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1276 | #define LPC_CMP ((LPC_CMP_Type *) LPC_CMP_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1277 | #define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1278 | #define LPC_INPUTMUX ((LPC_INPUTMUX_Type *) LPC_INPUTMUX_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1279 | #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1280 | #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1281 | #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1282 | #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1283 | #define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1284 | #define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1285 | #define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1286 | #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1287 | #define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1288 | #define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1289 | #define LPC_I2C2 ((LPC_I2C0_Type *) LPC_I2C2_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1290 | #define LPC_I2C3 ((LPC_I2C0_Type *) LPC_I2C3_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1291 | #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1292 | #define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1293 | #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1294 | #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1295 | #define LPC_PIN_INT ((LPC_PIN_INT_Type *) LPC_PIN_INT_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1296 | |
sahilmgandhi | 18:6a4db94011d3 | 1297 | |
sahilmgandhi | 18:6a4db94011d3 | 1298 | /** @} */ /* End of group Device_Peripheral_Registers */ |
sahilmgandhi | 18:6a4db94011d3 | 1299 | /** @} */ /* End of group LPC82x */ |
sahilmgandhi | 18:6a4db94011d3 | 1300 | /** @} */ /* End of group (null) */ |
sahilmgandhi | 18:6a4db94011d3 | 1301 | |
sahilmgandhi | 18:6a4db94011d3 | 1302 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 1303 | } |
sahilmgandhi | 18:6a4db94011d3 | 1304 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1305 | |
sahilmgandhi | 18:6a4db94011d3 | 1306 | |
sahilmgandhi | 18:6a4db94011d3 | 1307 | #endif /* LPC82x_H */ |
sahilmgandhi | 18:6a4db94011d3 | 1308 |