MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC408X/device/system_LPC407x_8x_177x_8x.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**********************************************************************
sahilmgandhi 18:6a4db94011d3 2 * $Id$ system_LPC407x_8x_177x_8x.c 2012-01-16
sahilmgandhi 18:6a4db94011d3 3 *//**
sahilmgandhi 18:6a4db94011d3 4 * @file system_LPC407x_8x_177x_8x.c
sahilmgandhi 18:6a4db94011d3 5 * @brief CMSIS Cortex-M3, M4 Device Peripheral Access Layer Source File
sahilmgandhi 18:6a4db94011d3 6 * for the NXP LPC407x_8x_177x_8x Device Series
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * ARM Limited (ARM) is supplying this software for use with
sahilmgandhi 18:6a4db94011d3 9 * Cortex-M processor based microcontrollers. This file can be
sahilmgandhi 18:6a4db94011d3 10 * freely distributed within development tools that are supporting
sahilmgandhi 18:6a4db94011d3 11 * such ARM based processors.
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * @version 1.2
sahilmgandhi 18:6a4db94011d3 14 * @date 20. June. 2012
sahilmgandhi 18:6a4db94011d3 15 * @author NXP MCU SW Application Team
sahilmgandhi 18:6a4db94011d3 16 *
sahilmgandhi 18:6a4db94011d3 17 * Copyright(C) 2012, NXP Semiconductor
sahilmgandhi 18:6a4db94011d3 18 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 ***********************************************************************
sahilmgandhi 18:6a4db94011d3 21 * Software that is described herein is for illustrative purposes only
sahilmgandhi 18:6a4db94011d3 22 * which provides customers with programming information regarding the
sahilmgandhi 18:6a4db94011d3 23 * products. This software is supplied "AS IS" without any warranties.
sahilmgandhi 18:6a4db94011d3 24 * NXP Semiconductors assumes no responsibility or liability for the
sahilmgandhi 18:6a4db94011d3 25 * use of the software, conveys no license or title under any patent,
sahilmgandhi 18:6a4db94011d3 26 * copyright, or mask work right to the product. NXP Semiconductors
sahilmgandhi 18:6a4db94011d3 27 * reserves the right to make changes in the software without
sahilmgandhi 18:6a4db94011d3 28 * notification. NXP Semiconductors also make no representation or
sahilmgandhi 18:6a4db94011d3 29 * warranty that such application will be suitable for the specified
sahilmgandhi 18:6a4db94011d3 30 * use without further testing or modification.
sahilmgandhi 18:6a4db94011d3 31 **********************************************************************/
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 34 #include "LPC407x_8x_177x_8x.h"
sahilmgandhi 18:6a4db94011d3 35 #include "system_LPC407x_8x_177x_8x.h"
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 #define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y))
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 /*
sahilmgandhi 18:6a4db94011d3 40 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
sahilmgandhi 18:6a4db94011d3 41 */
sahilmgandhi 18:6a4db94011d3 42 /*--------------------- Clock Configuration ----------------------------------
sahilmgandhi 18:6a4db94011d3 43 //
sahilmgandhi 18:6a4db94011d3 44 // <e> Clock Configuration
sahilmgandhi 18:6a4db94011d3 45 // <h> System Controls and Status Register (SCS - address 0x400F C1A0)
sahilmgandhi 18:6a4db94011d3 46 // <o1.0> EMC Shift Control Bit
sahilmgandhi 18:6a4db94011d3 47 // <i> Controls how addresses are output on the EMC address pins for static memories
sahilmgandhi 18:6a4db94011d3 48 // <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0)
sahilmgandhi 18:6a4db94011d3 49 // <1=> Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1)
sahilmgandhi 18:6a4db94011d3 50 //
sahilmgandhi 18:6a4db94011d3 51 // <o1.1> EMC Reset Disable Bit
sahilmgandhi 18:6a4db94011d3 52 // <i> If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition
sahilmgandhi 18:6a4db94011d3 53 // <i> If 1, EMC is still retained its state through a warm reset
sahilmgandhi 18:6a4db94011d3 54 // <0=> Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0)
sahilmgandhi 18:6a4db94011d3 55 // <1=> Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1)
sahilmgandhi 18:6a4db94011d3 56 //
sahilmgandhi 18:6a4db94011d3 57 // <o1.2> EMC Burst Control
sahilmgandhi 18:6a4db94011d3 58 // <i> Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects
sahilmgandhi 18:6a4db94011d3 59 // <0=> Burst enabled (Bit 2 is 0)
sahilmgandhi 18:6a4db94011d3 60 // <1=> Bust disbled (Bit 2 is 1)
sahilmgandhi 18:6a4db94011d3 61 //
sahilmgandhi 18:6a4db94011d3 62 // <o1.3> MCIPWR Active Level
sahilmgandhi 18:6a4db94011d3 63 // <i> Selects the active level for the SD card interface signal SD_PWR
sahilmgandhi 18:6a4db94011d3 64 // <0=> SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0)
sahilmgandhi 18:6a4db94011d3 65 // <1=> SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1)
sahilmgandhi 18:6a4db94011d3 66 //
sahilmgandhi 18:6a4db94011d3 67 // <o1.4> Main Oscillator Range Select
sahilmgandhi 18:6a4db94011d3 68 // <0=> In Range 1 MHz to 20 MHz (Bit 4 is 0)
sahilmgandhi 18:6a4db94011d3 69 // <1=> In Range 15 MHz to 25 MHz (Bit 4 is 1)
sahilmgandhi 18:6a4db94011d3 70 //
sahilmgandhi 18:6a4db94011d3 71 // <o1.5> Main Oscillator enable
sahilmgandhi 18:6a4db94011d3 72 // <i> 0 (zero) means disabled, 1 means enable
sahilmgandhi 18:6a4db94011d3 73 //
sahilmgandhi 18:6a4db94011d3 74 // <o1.6> Main Oscillator status (Read-Only)
sahilmgandhi 18:6a4db94011d3 75 // </h>
sahilmgandhi 18:6a4db94011d3 76 //
sahilmgandhi 18:6a4db94011d3 77 // <h> Clock Source Select Register (CLKSRCSEL - address 0x400F C10C)
sahilmgandhi 18:6a4db94011d3 78 // <o2.0> CLKSRC: Select the clock source for sysclk to PLL0 clock
sahilmgandhi 18:6a4db94011d3 79 // <0=> Internal RC oscillator (Bit 0 is 0)
sahilmgandhi 18:6a4db94011d3 80 // <1=> Main oscillator (Bit 0 is 1)
sahilmgandhi 18:6a4db94011d3 81 // </h>
sahilmgandhi 18:6a4db94011d3 82 //
sahilmgandhi 18:6a4db94011d3 83 // <e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084)
sahilmgandhi 18:6a4db94011d3 84 // <i> F_in is in the range of 1 MHz to 25 MHz
sahilmgandhi 18:6a4db94011d3 85 // <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
sahilmgandhi 18:6a4db94011d3 86 // <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
sahilmgandhi 18:6a4db94011d3 87 //
sahilmgandhi 18:6a4db94011d3 88 // <o4.0..4> MSEL: PLL Multiplier Value
sahilmgandhi 18:6a4db94011d3 89 // <i> M Value
sahilmgandhi 18:6a4db94011d3 90 // <1-32><#-1>
sahilmgandhi 18:6a4db94011d3 91 //
sahilmgandhi 18:6a4db94011d3 92 // <o4.5..6> PSEL: PLL Divider Value
sahilmgandhi 18:6a4db94011d3 93 // <i> P Value
sahilmgandhi 18:6a4db94011d3 94 // <0=> 1
sahilmgandhi 18:6a4db94011d3 95 // <1=> 2
sahilmgandhi 18:6a4db94011d3 96 // <2=> 4
sahilmgandhi 18:6a4db94011d3 97 // <3=> 8
sahilmgandhi 18:6a4db94011d3 98 // </e>
sahilmgandhi 18:6a4db94011d3 99 //
sahilmgandhi 18:6a4db94011d3 100 // <e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4)
sahilmgandhi 18:6a4db94011d3 101 // <i> F_in is in the range of 1 MHz to 25 MHz
sahilmgandhi 18:6a4db94011d3 102 // <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
sahilmgandhi 18:6a4db94011d3 103 // <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
sahilmgandhi 18:6a4db94011d3 104 //
sahilmgandhi 18:6a4db94011d3 105 // <o6.0..4> MSEL: PLL Multiplier Value
sahilmgandhi 18:6a4db94011d3 106 // <i> M Value
sahilmgandhi 18:6a4db94011d3 107 // <1-32><#-1>
sahilmgandhi 18:6a4db94011d3 108 //
sahilmgandhi 18:6a4db94011d3 109 // <o6.5..6> PSEL: PLL Divider Value
sahilmgandhi 18:6a4db94011d3 110 // <i> P Value
sahilmgandhi 18:6a4db94011d3 111 // <0=> 1
sahilmgandhi 18:6a4db94011d3 112 // <1=> 2
sahilmgandhi 18:6a4db94011d3 113 // <2=> 4
sahilmgandhi 18:6a4db94011d3 114 // <3=> 8
sahilmgandhi 18:6a4db94011d3 115 // </e>
sahilmgandhi 18:6a4db94011d3 116 //
sahilmgandhi 18:6a4db94011d3 117 // <h> CPU Clock Selection Register (CCLKSEL - address 0x400F C104)
sahilmgandhi 18:6a4db94011d3 118 // <o7.0..4> CCLKDIV: Select the value for divider of CPU clock (CCLK)
sahilmgandhi 18:6a4db94011d3 119 // <i> 0: The divider is turned off. No clock will be provided to the CPU
sahilmgandhi 18:6a4db94011d3 120 // <i> n: The input clock is divided by n to produce the CPU clock
sahilmgandhi 18:6a4db94011d3 121 // <0-31>
sahilmgandhi 18:6a4db94011d3 122 //
sahilmgandhi 18:6a4db94011d3 123 // <o7.8> CCLKSEL: Select the input to the divider of CPU clock
sahilmgandhi 18:6a4db94011d3 124 // <0=> sysclk clock is used
sahilmgandhi 18:6a4db94011d3 125 // <1=> Main PLL0 clock is used
sahilmgandhi 18:6a4db94011d3 126 // </h>
sahilmgandhi 18:6a4db94011d3 127 //
sahilmgandhi 18:6a4db94011d3 128 // <h> USB Clock Selection Register (USBCLKSEL - 0x400F C108)
sahilmgandhi 18:6a4db94011d3 129 // <o8.0..4> USBDIV: USB clock (source PLL0) divider selection
sahilmgandhi 18:6a4db94011d3 130 // <0=> Divider is off and no clock provides to USB subsystem
sahilmgandhi 18:6a4db94011d3 131 // <4=> Divider value is 4 (The source clock is divided by 4)
sahilmgandhi 18:6a4db94011d3 132 // <6=> Divider value is 6 (The source clock is divided by 6)
sahilmgandhi 18:6a4db94011d3 133 //
sahilmgandhi 18:6a4db94011d3 134 // <o8.8..9> USBSEL: Select the source for USB clock divider
sahilmgandhi 18:6a4db94011d3 135 // <i> When CPU clock is selected, the USB can be accessed
sahilmgandhi 18:6a4db94011d3 136 // <i> by software but cannot perform USB functions
sahilmgandhi 18:6a4db94011d3 137 // <0=> sysclk clock (the clock input to PLL0)
sahilmgandhi 18:6a4db94011d3 138 // <1=> The clock output from PLL0
sahilmgandhi 18:6a4db94011d3 139 // <2=> The clock output from PLL1
sahilmgandhi 18:6a4db94011d3 140 // </h>
sahilmgandhi 18:6a4db94011d3 141 //
sahilmgandhi 18:6a4db94011d3 142 // <h> EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100)
sahilmgandhi 18:6a4db94011d3 143 // <o9.0> EMCDIV: Set the divider for EMC clock
sahilmgandhi 18:6a4db94011d3 144 // <0=> Divider value is 1
sahilmgandhi 18:6a4db94011d3 145 // <1=> Divider value is 2 (EMC clock is equal a half of input clock)
sahilmgandhi 18:6a4db94011d3 146 // </h>
sahilmgandhi 18:6a4db94011d3 147 //
sahilmgandhi 18:6a4db94011d3 148 // <h> Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8)
sahilmgandhi 18:6a4db94011d3 149 // <o10.0..4> PCLKDIV: APB Peripheral clock divider
sahilmgandhi 18:6a4db94011d3 150 // <i> 0: The divider is turned off. No clock will be provided to APB peripherals
sahilmgandhi 18:6a4db94011d3 151 // <i> n: The input clock is divided by n to produce the APB peripheral clock
sahilmgandhi 18:6a4db94011d3 152 // <0-31>
sahilmgandhi 18:6a4db94011d3 153 // </h>
sahilmgandhi 18:6a4db94011d3 154 //
sahilmgandhi 18:6a4db94011d3 155 // <h> SPIFI Clock Selection Register (SPIFICLKSEL - address 0x400F C1B4)
sahilmgandhi 18:6a4db94011d3 156 // <o11.0..4> SPIFIDIV: Set the divider for SPIFI clock
sahilmgandhi 18:6a4db94011d3 157 // <i> 0: The divider is turned off. No clock will be provided to the SPIFI
sahilmgandhi 18:6a4db94011d3 158 // <i> n: The input clock is divided by n to produce the SPIFI clock
sahilmgandhi 18:6a4db94011d3 159 // <0-31>
sahilmgandhi 18:6a4db94011d3 160 //
sahilmgandhi 18:6a4db94011d3 161 // <o11.8..9> SPIFISEL: Select the input clock for SPIFI clock divider
sahilmgandhi 18:6a4db94011d3 162 // <0=> sysclk clock (the clock input to PLL0)
sahilmgandhi 18:6a4db94011d3 163 // <1=> The clock output from PLL0
sahilmgandhi 18:6a4db94011d3 164 // <2=> The clock output from PLL1
sahilmgandhi 18:6a4db94011d3 165 // </h>
sahilmgandhi 18:6a4db94011d3 166 //
sahilmgandhi 18:6a4db94011d3 167 // <h> Power Control for Peripherals Register (PCONP - address 0x400F C1C8)
sahilmgandhi 18:6a4db94011d3 168 // <o12.0> PCLCD: LCD controller power/clock enable (bit 0)
sahilmgandhi 18:6a4db94011d3 169 // <o12.1> PCTIM0: Timer/Counter 0 power/clock enable (bit 1)
sahilmgandhi 18:6a4db94011d3 170 // <o12.2> PCTIM1: Timer/Counter 1 power/clock enable (bit 2)
sahilmgandhi 18:6a4db94011d3 171 // <o12.3> PCUART0: UART 0 power/clock enable (bit 3)
sahilmgandhi 18:6a4db94011d3 172 // <o12.4> PCUART1: UART 1 power/clock enable (bit 4)
sahilmgandhi 18:6a4db94011d3 173 // <o12.5> PCPWM0: PWM0 power/clock enable (bit 5)
sahilmgandhi 18:6a4db94011d3 174 // <o12.6> PCPWM1: PWM1 power/clock enable (bit 6)
sahilmgandhi 18:6a4db94011d3 175 // <o12.7> PCI2C0: I2C 0 interface power/clock enable (bit 7)
sahilmgandhi 18:6a4db94011d3 176 // <o12.8> PCUART4: UART 4 power/clock enable (bit 8)
sahilmgandhi 18:6a4db94011d3 177 // <o12.9> PCRTC: RTC and Event Recorder power/clock enable (bit 9)
sahilmgandhi 18:6a4db94011d3 178 // <o12.10> PCSSP1: SSP 1 interface power/clock enable (bit 10)
sahilmgandhi 18:6a4db94011d3 179 // <o12.11> PCEMC: External Memory Controller power/clock enable (bit 11)
sahilmgandhi 18:6a4db94011d3 180 // <o12.12> PCADC: A/D converter power/clock enable (bit 12)
sahilmgandhi 18:6a4db94011d3 181 // <o12.13> PCCAN1: CAN controller 1 power/clock enable (bit 13)
sahilmgandhi 18:6a4db94011d3 182 // <o12.14> PCCAN2: CAN controller 2 power/clock enable (bit 14)
sahilmgandhi 18:6a4db94011d3 183 // <o12.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15)
sahilmgandhi 18:6a4db94011d3 184 // <o12.17> PCMCPWM: Motor Control PWM power/clock enable (bit 17)
sahilmgandhi 18:6a4db94011d3 185 // <o12.18> PCQEI: Quadrature encoder interface power/clock enable (bit 18)
sahilmgandhi 18:6a4db94011d3 186 // <o12.19> PCI2C1: I2C 1 interface power/clock enable (bit 19)
sahilmgandhi 18:6a4db94011d3 187 // <o12.20> PCSSP2: SSP 2 interface power/clock enable (bit 20)
sahilmgandhi 18:6a4db94011d3 188 // <o12.21> PCSSP0: SSP 0 interface power/clock enable (bit 21)
sahilmgandhi 18:6a4db94011d3 189 // <o12.22> PCTIM2: Timer 2 power/clock enable (bit 22)
sahilmgandhi 18:6a4db94011d3 190 // <o12.23> PCTIM3: Timer 3 power/clock enable (bit 23)
sahilmgandhi 18:6a4db94011d3 191 // <o12.24> PCUART2: UART 2 power/clock enable (bit 24)
sahilmgandhi 18:6a4db94011d3 192 // <o12.25> PCUART3: UART 3 power/clock enable (bit 25)
sahilmgandhi 18:6a4db94011d3 193 // <o12.26> PCI2C2: I2C 2 interface power/clock enable (bit 26)
sahilmgandhi 18:6a4db94011d3 194 // <o12.27> PCI2S: I2S interface power/clock enable (bit 27)
sahilmgandhi 18:6a4db94011d3 195 // <o12.28> PCSDC: SD Card interface power/clock enable (bit 28)
sahilmgandhi 18:6a4db94011d3 196 // <o12.29> PCGPDMA: GPDMA function power/clock enable (bit 29)
sahilmgandhi 18:6a4db94011d3 197 // <o12.30> PCENET: Ethernet block power/clock enable (bit 30)
sahilmgandhi 18:6a4db94011d3 198 // <o12.31> PCUSB: USB interface power/clock enable (bit 31)
sahilmgandhi 18:6a4db94011d3 199 // </h>
sahilmgandhi 18:6a4db94011d3 200 //
sahilmgandhi 18:6a4db94011d3 201 // <h> Clock Output Configuration Register (CLKOUTCFG)
sahilmgandhi 18:6a4db94011d3 202 // <o13.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection
sahilmgandhi 18:6a4db94011d3 203 // <0=> CPU clock
sahilmgandhi 18:6a4db94011d3 204 // <1=> Main Oscillator
sahilmgandhi 18:6a4db94011d3 205 // <2=> Internal RC Oscillator
sahilmgandhi 18:6a4db94011d3 206 // <3=> USB clock
sahilmgandhi 18:6a4db94011d3 207 // <4=> RTC Oscillator
sahilmgandhi 18:6a4db94011d3 208 // <5=> unused
sahilmgandhi 18:6a4db94011d3 209 // <6=> Watchdog Oscillator
sahilmgandhi 18:6a4db94011d3 210 //
sahilmgandhi 18:6a4db94011d3 211 // <o13.4..7> CLKOUTDIV: Output Clock Divider
sahilmgandhi 18:6a4db94011d3 212 // <1-16><#-1>
sahilmgandhi 18:6a4db94011d3 213 //
sahilmgandhi 18:6a4db94011d3 214 // <o13.8> CLKOUT_EN: CLKOUT enable
sahilmgandhi 18:6a4db94011d3 215 // </h>
sahilmgandhi 18:6a4db94011d3 216 //
sahilmgandhi 18:6a4db94011d3 217 // </e>
sahilmgandhi 18:6a4db94011d3 218 */
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 #define CLOCK_SETUP 1
sahilmgandhi 18:6a4db94011d3 221 #define SCS_Val 0x00000020
sahilmgandhi 18:6a4db94011d3 222 #define CLKSRCSEL_Val 0x00000001
sahilmgandhi 18:6a4db94011d3 223 #define PLL0_SETUP 1
sahilmgandhi 18:6a4db94011d3 224 #define PLL0CFG_Val 0x00000009
sahilmgandhi 18:6a4db94011d3 225 #define PLL1_SETUP 1
sahilmgandhi 18:6a4db94011d3 226 #define PLL1CFG_Val 0x00000023
sahilmgandhi 18:6a4db94011d3 227 #define CCLKSEL_Val 0x00000101
sahilmgandhi 18:6a4db94011d3 228 #define USBCLKSEL_Val 0x00000201
sahilmgandhi 18:6a4db94011d3 229 #define EMCCLKSEL_Val 0x00000001
sahilmgandhi 18:6a4db94011d3 230 #define PCLKSEL_Val 0x00000002
sahilmgandhi 18:6a4db94011d3 231 #define SPIFICLKSEL_Val 0x00000002
sahilmgandhi 18:6a4db94011d3 232 #define PCONP_Val 0x042887DE
sahilmgandhi 18:6a4db94011d3 233 #define CLKOUTCFG_Val 0x00000100
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 #ifdef CORE_M4
sahilmgandhi 18:6a4db94011d3 236 #define LPC_CPACR 0xE000ED88
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 #define SCB_MVFR0 0xE000EF40
sahilmgandhi 18:6a4db94011d3 239 #define SCB_MVFR0_RESET 0x10110021
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 #define SCB_MVFR1 0xE000EF44
sahilmgandhi 18:6a4db94011d3 242 #define SCB_MVFR1_RESET 0x11000011
sahilmgandhi 18:6a4db94011d3 243 #endif
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245
sahilmgandhi 18:6a4db94011d3 246 /*--------------------- Flash Accelerator Configuration ----------------------
sahilmgandhi 18:6a4db94011d3 247 //
sahilmgandhi 18:6a4db94011d3 248 // <e> Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000)
sahilmgandhi 18:6a4db94011d3 249 // <o1.12..15> FLASHTIM: Flash Access Time
sahilmgandhi 18:6a4db94011d3 250 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
sahilmgandhi 18:6a4db94011d3 251 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
sahilmgandhi 18:6a4db94011d3 252 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
sahilmgandhi 18:6a4db94011d3 253 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
sahilmgandhi 18:6a4db94011d3 254 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
sahilmgandhi 18:6a4db94011d3 255 // <5=> 6 CPU clocks (for any CPU clock)
sahilmgandhi 18:6a4db94011d3 256 // </e>
sahilmgandhi 18:6a4db94011d3 257 */
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 #define FLASH_SETUP 1
sahilmgandhi 18:6a4db94011d3 260 #define FLASHCFG_Val 0x00005000
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 263 Check the register settings
sahilmgandhi 18:6a4db94011d3 264 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 265 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
sahilmgandhi 18:6a4db94011d3 266 #define CHECK_RSVD(val, mask) (val & mask)
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 /* Clock Configuration -------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 269 #if (CHECK_RSVD((SCS_Val), ~0x0000003F))
sahilmgandhi 18:6a4db94011d3 270 #error "SCS: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 271 #endif
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
sahilmgandhi 18:6a4db94011d3 274 #error "CLKSRCSEL: Value out of range!"
sahilmgandhi 18:6a4db94011d3 275 #endif
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 #if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F))
sahilmgandhi 18:6a4db94011d3 278 #error "PLL0CFG: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 279 #endif
sahilmgandhi 18:6a4db94011d3 280
sahilmgandhi 18:6a4db94011d3 281 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
sahilmgandhi 18:6a4db94011d3 282 #error "PLL1CFG: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 283 #endif
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 #if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F))
sahilmgandhi 18:6a4db94011d3 286 #error "CCLKSEL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 287 #endif
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 #if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
sahilmgandhi 18:6a4db94011d3 290 #error "USBCLKSEL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 291 #endif
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 #if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
sahilmgandhi 18:6a4db94011d3 294 #error "EMCCLKSEL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 295 #endif
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 #if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
sahilmgandhi 18:6a4db94011d3 298 #error "PCLKSEL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 299 #endif
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 #if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
sahilmgandhi 18:6a4db94011d3 302 #error "PCONP: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 303 #endif
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
sahilmgandhi 18:6a4db94011d3 306 #error "CLKOUTCFG: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 307 #endif
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 /* Flash Accelerator Configuration -------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 310 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
sahilmgandhi 18:6a4db94011d3 311 #warning "FLASHCFG: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 312 #endif
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 316 DEFINES
sahilmgandhi 18:6a4db94011d3 317 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 318 /* pll_out_clk = F_cco / (2 � P)
sahilmgandhi 18:6a4db94011d3 319 F_cco = pll_in_clk � M � 2 � P */
sahilmgandhi 18:6a4db94011d3 320 #define __M ((PLL0CFG_Val & 0x1F) + 1)
sahilmgandhi 18:6a4db94011d3 321 #define __PLL0_CLK(__F_IN) (__F_IN * __M)
sahilmgandhi 18:6a4db94011d3 322 #define __CCLK_DIV (CCLKSEL_Val & 0x1F)
sahilmgandhi 18:6a4db94011d3 323 #define __PCLK_DIV (PCLKSEL_Val & 0x1F)
sahilmgandhi 18:6a4db94011d3 324 #define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1)
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326 /* Determine core clock frequency according to settings */
sahilmgandhi 18:6a4db94011d3 327 #if (CLOCK_SETUP) /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 328
sahilmgandhi 18:6a4db94011d3 329 #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
sahilmgandhi 18:6a4db94011d3 330 #error "Main Oscillator is selected as clock source but is not enabled!"
sahilmgandhi 18:6a4db94011d3 331 #endif
sahilmgandhi 18:6a4db94011d3 332
sahilmgandhi 18:6a4db94011d3 333 #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
sahilmgandhi 18:6a4db94011d3 334 #error "Main PLL is selected as clock source but is not enabled!"
sahilmgandhi 18:6a4db94011d3 335 #endif
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */
sahilmgandhi 18:6a4db94011d3 338 #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
sahilmgandhi 18:6a4db94011d3 339 #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
sahilmgandhi 18:6a4db94011d3 340 #define __PER_CLK (IRC_OSC/ __PCLK_DIV)
sahilmgandhi 18:6a4db94011d3 341 #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
sahilmgandhi 18:6a4db94011d3 342 #else /* sysclk = osc_clk */
sahilmgandhi 18:6a4db94011d3 343 #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
sahilmgandhi 18:6a4db94011d3 344 #define __PER_CLK (OSC_CLK/ __PCLK_DIV)
sahilmgandhi 18:6a4db94011d3 345 #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
sahilmgandhi 18:6a4db94011d3 346 #endif
sahilmgandhi 18:6a4db94011d3 347 #else /* cclk = pll_clk */
sahilmgandhi 18:6a4db94011d3 348 #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
sahilmgandhi 18:6a4db94011d3 349 #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
sahilmgandhi 18:6a4db94011d3 350 #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
sahilmgandhi 18:6a4db94011d3 351 #define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
sahilmgandhi 18:6a4db94011d3 352 #else /* sysclk = osc_clk */
sahilmgandhi 18:6a4db94011d3 353 #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
sahilmgandhi 18:6a4db94011d3 354 #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
sahilmgandhi 18:6a4db94011d3 355 #define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
sahilmgandhi 18:6a4db94011d3 356 #endif
sahilmgandhi 18:6a4db94011d3 357 #endif
sahilmgandhi 18:6a4db94011d3 358
sahilmgandhi 18:6a4db94011d3 359 #else
sahilmgandhi 18:6a4db94011d3 360 #define __CORE_CLK (IRC_OSC)
sahilmgandhi 18:6a4db94011d3 361 #define __PER_CLK (IRC_OSC)
sahilmgandhi 18:6a4db94011d3 362 #define __EMC_CLK (__CORE_CLK)
sahilmgandhi 18:6a4db94011d3 363 #endif
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 366 Clock Variable definitions
sahilmgandhi 18:6a4db94011d3 367 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 368 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
sahilmgandhi 18:6a4db94011d3 369 uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */
sahilmgandhi 18:6a4db94011d3 370 uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */
sahilmgandhi 18:6a4db94011d3 371 uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will
sahilmgandhi 18:6a4db94011d3 372 be updated after call SystemCoreClockUpdate, should be 48MHz*/
sahilmgandhi 18:6a4db94011d3 373
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 376 Clock functions
sahilmgandhi 18:6a4db94011d3 377 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 378 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
sahilmgandhi 18:6a4db94011d3 379 {
sahilmgandhi 18:6a4db94011d3 380 /* Determine clock frequency according to clock register values */
sahilmgandhi 18:6a4db94011d3 381 if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */
sahilmgandhi 18:6a4db94011d3 382 if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
sahilmgandhi 18:6a4db94011d3 383 SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F));
sahilmgandhi 18:6a4db94011d3 384 PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F));
sahilmgandhi 18:6a4db94011d3 385 EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
sahilmgandhi 18:6a4db94011d3 386 }
sahilmgandhi 18:6a4db94011d3 387 else { /* sysclk = osc_clk */
sahilmgandhi 18:6a4db94011d3 388 if ((LPC_SC->SCS & 0x40) == 0) {
sahilmgandhi 18:6a4db94011d3 389 SystemCoreClock = 0; /* this should never happen! */
sahilmgandhi 18:6a4db94011d3 390 PeripheralClock = 0;
sahilmgandhi 18:6a4db94011d3 391 EMCClock = 0;
sahilmgandhi 18:6a4db94011d3 392 }
sahilmgandhi 18:6a4db94011d3 393 else {
sahilmgandhi 18:6a4db94011d3 394 SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F));
sahilmgandhi 18:6a4db94011d3 395 PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F));
sahilmgandhi 18:6a4db94011d3 396 EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
sahilmgandhi 18:6a4db94011d3 397 }
sahilmgandhi 18:6a4db94011d3 398 }
sahilmgandhi 18:6a4db94011d3 399 }
sahilmgandhi 18:6a4db94011d3 400 else { /* cclk = pll_clk */
sahilmgandhi 18:6a4db94011d3 401 if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */
sahilmgandhi 18:6a4db94011d3 402 SystemCoreClock = 0; /* this should never happen! */
sahilmgandhi 18:6a4db94011d3 403 PeripheralClock = 0;
sahilmgandhi 18:6a4db94011d3 404 EMCClock = 0;
sahilmgandhi 18:6a4db94011d3 405 }
sahilmgandhi 18:6a4db94011d3 406 else {
sahilmgandhi 18:6a4db94011d3 407 if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
sahilmgandhi 18:6a4db94011d3 408 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
sahilmgandhi 18:6a4db94011d3 409 uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
sahilmgandhi 18:6a4db94011d3 410 uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
sahilmgandhi 18:6a4db94011d3 411 uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
sahilmgandhi 18:6a4db94011d3 412 SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div);
sahilmgandhi 18:6a4db94011d3 413 PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div);
sahilmgandhi 18:6a4db94011d3 414 EMCClock = SystemCoreClock / emc_div;
sahilmgandhi 18:6a4db94011d3 415 }
sahilmgandhi 18:6a4db94011d3 416 else { /* sysclk = osc_clk */
sahilmgandhi 18:6a4db94011d3 417 if ((LPC_SC->SCS & 0x40) == 0) {
sahilmgandhi 18:6a4db94011d3 418 SystemCoreClock = 0; /* this should never happen! */
sahilmgandhi 18:6a4db94011d3 419 PeripheralClock = 0;
sahilmgandhi 18:6a4db94011d3 420 EMCClock = 0;
sahilmgandhi 18:6a4db94011d3 421 }
sahilmgandhi 18:6a4db94011d3 422 else {
sahilmgandhi 18:6a4db94011d3 423 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
sahilmgandhi 18:6a4db94011d3 424 uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
sahilmgandhi 18:6a4db94011d3 425 uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
sahilmgandhi 18:6a4db94011d3 426 uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
sahilmgandhi 18:6a4db94011d3 427 SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div);
sahilmgandhi 18:6a4db94011d3 428 PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div);
sahilmgandhi 18:6a4db94011d3 429 EMCClock = SystemCoreClock / emc_div;
sahilmgandhi 18:6a4db94011d3 430 }
sahilmgandhi 18:6a4db94011d3 431 }
sahilmgandhi 18:6a4db94011d3 432 }
sahilmgandhi 18:6a4db94011d3 433 }
sahilmgandhi 18:6a4db94011d3 434 /* ---update USBClock------------------*/
sahilmgandhi 18:6a4db94011d3 435 if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
sahilmgandhi 18:6a4db94011d3 436 {
sahilmgandhi 18:6a4db94011d3 437 switch (LPC_SC->USBCLKSEL & 0x1F)
sahilmgandhi 18:6a4db94011d3 438 {
sahilmgandhi 18:6a4db94011d3 439 case 0:
sahilmgandhi 18:6a4db94011d3 440 USBClock = 0; //no clock will be provided to the USB subsystem
sahilmgandhi 18:6a4db94011d3 441 break;
sahilmgandhi 18:6a4db94011d3 442 case 4:
sahilmgandhi 18:6a4db94011d3 443 case 6:
sahilmgandhi 18:6a4db94011d3 444 {
sahilmgandhi 18:6a4db94011d3 445 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
sahilmgandhi 18:6a4db94011d3 446 uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F);
sahilmgandhi 18:6a4db94011d3 447 if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc
sahilmgandhi 18:6a4db94011d3 448 USBClock = OSC_CLK * mul / usb_div;
sahilmgandhi 18:6a4db94011d3 449 else //pll_clk_in = irc_clk
sahilmgandhi 18:6a4db94011d3 450 USBClock = IRC_OSC * mul / usb_div;
sahilmgandhi 18:6a4db94011d3 451 }
sahilmgandhi 18:6a4db94011d3 452 break;
sahilmgandhi 18:6a4db94011d3 453 default:
sahilmgandhi 18:6a4db94011d3 454 USBClock = 0; /* this should never happen! */
sahilmgandhi 18:6a4db94011d3 455 }
sahilmgandhi 18:6a4db94011d3 456 }
sahilmgandhi 18:6a4db94011d3 457 else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
sahilmgandhi 18:6a4db94011d3 458 {
sahilmgandhi 18:6a4db94011d3 459 if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc
sahilmgandhi 18:6a4db94011d3 460 USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
sahilmgandhi 18:6a4db94011d3 461 else //pll1_clk_in = irc_clk
sahilmgandhi 18:6a4db94011d3 462 USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
sahilmgandhi 18:6a4db94011d3 463 }
sahilmgandhi 18:6a4db94011d3 464 else
sahilmgandhi 18:6a4db94011d3 465 USBClock = 0; /* this should never happen! */
sahilmgandhi 18:6a4db94011d3 466 }
sahilmgandhi 18:6a4db94011d3 467
sahilmgandhi 18:6a4db94011d3 468 /* Determine clock frequency according to clock register values */
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 #ifdef CORE_M4
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 void fpu_init(void)
sahilmgandhi 18:6a4db94011d3 473 {
sahilmgandhi 18:6a4db94011d3 474 // from arm trm manual:
sahilmgandhi 18:6a4db94011d3 475 // ; CPACR is located at address 0xE000ED88
sahilmgandhi 18:6a4db94011d3 476 // LDR.W R0, =0xE000ED88
sahilmgandhi 18:6a4db94011d3 477 // ; Read CPACR
sahilmgandhi 18:6a4db94011d3 478 // LDR R1, [R0]
sahilmgandhi 18:6a4db94011d3 479 // ; Set bits 20-23 to enable CP10 and CP11 coprocessors
sahilmgandhi 18:6a4db94011d3 480 // ORR R1, R1, #(0xF << 20)
sahilmgandhi 18:6a4db94011d3 481 // ; Write back the modified value to the CPACR
sahilmgandhi 18:6a4db94011d3 482 // STR R1, [R0]
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484
sahilmgandhi 18:6a4db94011d3 485 volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;
sahilmgandhi 18:6a4db94011d3 486 volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;
sahilmgandhi 18:6a4db94011d3 487 volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;
sahilmgandhi 18:6a4db94011d3 488 volatile uint32_t Cpacr;
sahilmgandhi 18:6a4db94011d3 489 volatile uint32_t Mvfr0;
sahilmgandhi 18:6a4db94011d3 490 volatile uint32_t Mvfr1;
sahilmgandhi 18:6a4db94011d3 491 char vfpPresent = 0;
sahilmgandhi 18:6a4db94011d3 492
sahilmgandhi 18:6a4db94011d3 493 Mvfr0 = *regMvfr0;
sahilmgandhi 18:6a4db94011d3 494 Mvfr1 = *regMvfr1;
sahilmgandhi 18:6a4db94011d3 495
sahilmgandhi 18:6a4db94011d3 496 vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
sahilmgandhi 18:6a4db94011d3 497
sahilmgandhi 18:6a4db94011d3 498 if(vfpPresent)
sahilmgandhi 18:6a4db94011d3 499 {
sahilmgandhi 18:6a4db94011d3 500 Cpacr = *regCpacr;
sahilmgandhi 18:6a4db94011d3 501 Cpacr |= (0xF << 20);
sahilmgandhi 18:6a4db94011d3 502 *regCpacr = Cpacr; // enable CP10 and CP11 for full access
sahilmgandhi 18:6a4db94011d3 503 }
sahilmgandhi 18:6a4db94011d3 504
sahilmgandhi 18:6a4db94011d3 505 }
sahilmgandhi 18:6a4db94011d3 506 #endif
sahilmgandhi 18:6a4db94011d3 507
sahilmgandhi 18:6a4db94011d3 508 /**
sahilmgandhi 18:6a4db94011d3 509 * Initialize the system
sahilmgandhi 18:6a4db94011d3 510 *
sahilmgandhi 18:6a4db94011d3 511 * @param none
sahilmgandhi 18:6a4db94011d3 512 * @return none
sahilmgandhi 18:6a4db94011d3 513 *
sahilmgandhi 18:6a4db94011d3 514 * @brief Setup the microcontroller system.
sahilmgandhi 18:6a4db94011d3 515 * Initialize the System.
sahilmgandhi 18:6a4db94011d3 516 */
sahilmgandhi 18:6a4db94011d3 517 void SystemInit (void)
sahilmgandhi 18:6a4db94011d3 518 {
sahilmgandhi 18:6a4db94011d3 519 #ifndef __CODE_RED
sahilmgandhi 18:6a4db94011d3 520 #ifdef CORE_M4
sahilmgandhi 18:6a4db94011d3 521 fpu_init();
sahilmgandhi 18:6a4db94011d3 522 #endif
sahilmgandhi 18:6a4db94011d3 523 #endif
sahilmgandhi 18:6a4db94011d3 524
sahilmgandhi 18:6a4db94011d3 525 #if (CLOCK_SETUP) /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 526 LPC_SC->SCS = SCS_Val;
sahilmgandhi 18:6a4db94011d3 527 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
sahilmgandhi 18:6a4db94011d3 528 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
sahilmgandhi 18:6a4db94011d3 529 }
sahilmgandhi 18:6a4db94011d3 530
sahilmgandhi 18:6a4db94011d3 531 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 #if (PLL0_SETUP)
sahilmgandhi 18:6a4db94011d3 534 LPC_SC->PLL0CFG = PLL0CFG_Val;
sahilmgandhi 18:6a4db94011d3 535 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
sahilmgandhi 18:6a4db94011d3 536 LPC_SC->PLL0FEED = 0xAA;
sahilmgandhi 18:6a4db94011d3 537 LPC_SC->PLL0FEED = 0x55;
sahilmgandhi 18:6a4db94011d3 538 while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */
sahilmgandhi 18:6a4db94011d3 539 #endif
sahilmgandhi 18:6a4db94011d3 540
sahilmgandhi 18:6a4db94011d3 541 #if (PLL1_SETUP)
sahilmgandhi 18:6a4db94011d3 542 LPC_SC->PLL1CFG = PLL1CFG_Val;
sahilmgandhi 18:6a4db94011d3 543 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
sahilmgandhi 18:6a4db94011d3 544 LPC_SC->PLL1FEED = 0xAA;
sahilmgandhi 18:6a4db94011d3 545 LPC_SC->PLL1FEED = 0x55;
sahilmgandhi 18:6a4db94011d3 546 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
sahilmgandhi 18:6a4db94011d3 547 #endif
sahilmgandhi 18:6a4db94011d3 548
sahilmgandhi 18:6a4db94011d3 549 LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */
sahilmgandhi 18:6a4db94011d3 550 LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */
sahilmgandhi 18:6a4db94011d3 551 LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */
sahilmgandhi 18:6a4db94011d3 552 LPC_SC->SPIFICLKSEL = SPIFICLKSEL_Val; /* SPIFI Clock Selection */
sahilmgandhi 18:6a4db94011d3 553 LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */
sahilmgandhi 18:6a4db94011d3 554 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
sahilmgandhi 18:6a4db94011d3 555 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
sahilmgandhi 18:6a4db94011d3 556 #endif
sahilmgandhi 18:6a4db94011d3 557
sahilmgandhi 18:6a4db94011d3 558 LPC_SC->PBOOST |= 0x03; /* Power Boost control */
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
sahilmgandhi 18:6a4db94011d3 561 LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A;
sahilmgandhi 18:6a4db94011d3 562 #endif
sahilmgandhi 18:6a4db94011d3 563 #ifndef __CODE_RED
sahilmgandhi 18:6a4db94011d3 564 #ifdef __RAM_MODE__
sahilmgandhi 18:6a4db94011d3 565 SCB->VTOR = 0x10000000 & 0x3FFFFF80;
sahilmgandhi 18:6a4db94011d3 566 #else
sahilmgandhi 18:6a4db94011d3 567 SCB->VTOR = 0x00000000 & 0x3FFFFF80;
sahilmgandhi 18:6a4db94011d3 568 #endif
sahilmgandhi 18:6a4db94011d3 569 #endif
sahilmgandhi 18:6a4db94011d3 570
sahilmgandhi 18:6a4db94011d3 571 /* Must set ROM_LAT bit in the Matrix Arbitration Register otherwise SPIFI
sahilmgandhi 18:6a4db94011d3 572 * initialization will cause debugging to HardFault */
sahilmgandhi 18:6a4db94011d3 573 LPC_SC->MATRIXARB |= (1<<16);
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 /* Reset LCD Controller to prevent strange behavior when doing a partial
sahilmgandhi 18:6a4db94011d3 576 * reset (happens when debugging).
sahilmgandhi 18:6a4db94011d3 577 */
sahilmgandhi 18:6a4db94011d3 578 LPC_SC->RSTCON0 = 1;
sahilmgandhi 18:6a4db94011d3 579
sahilmgandhi 18:6a4db94011d3 580 SystemCoreClockUpdate();
sahilmgandhi 18:6a4db94011d3 581 }