MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC23XX/device/LPC23xx.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library - LPC23xx CMSIS-like structs
sahilmgandhi 18:6a4db94011d3 2 * Copyright (C) 2009 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
sahilmgandhi 18:6a4db94011d3 5 */
sahilmgandhi 18:6a4db94011d3 6
sahilmgandhi 18:6a4db94011d3 7 #ifndef __LPC23xx_H
sahilmgandhi 18:6a4db94011d3 8 #define __LPC23xx_H
sahilmgandhi 18:6a4db94011d3 9
sahilmgandhi 18:6a4db94011d3 10 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 11 extern "C" {
sahilmgandhi 18:6a4db94011d3 12 #endif
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14 /*
sahilmgandhi 18:6a4db94011d3 15 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 16 * ---------- Interrupt Number Definition -----------------------------------
sahilmgandhi 18:6a4db94011d3 17 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 18 */
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 typedef enum IRQn
sahilmgandhi 18:6a4db94011d3 21 {
sahilmgandhi 18:6a4db94011d3 22 /****** LPC23xx Specific Interrupt Numbers *******************************************************/
sahilmgandhi 18:6a4db94011d3 23 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
sahilmgandhi 18:6a4db94011d3 26 TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
sahilmgandhi 18:6a4db94011d3 27 UART0_IRQn = 6, /*!< UART0 Interrupt */
sahilmgandhi 18:6a4db94011d3 28 UART1_IRQn = 7, /*!< UART1 Interrupt */
sahilmgandhi 18:6a4db94011d3 29 PWM1_IRQn = 8, /*!< PWM1 Interrupt */
sahilmgandhi 18:6a4db94011d3 30 I2C0_IRQn = 9, /*!< I2C0 Interrupt */
sahilmgandhi 18:6a4db94011d3 31 SPI_IRQn = 10, /*!< SPI Interrupt */
sahilmgandhi 18:6a4db94011d3 32 SSP0_IRQn = 10, /*!< SSP0 Interrupt */
sahilmgandhi 18:6a4db94011d3 33 SSP1_IRQn = 11, /*!< SSP1 Interrupt */
sahilmgandhi 18:6a4db94011d3 34 PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
sahilmgandhi 18:6a4db94011d3 35 RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
sahilmgandhi 18:6a4db94011d3 36 EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
sahilmgandhi 18:6a4db94011d3 37 EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
sahilmgandhi 18:6a4db94011d3 38 EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
sahilmgandhi 18:6a4db94011d3 39 EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
sahilmgandhi 18:6a4db94011d3 40 ADC_IRQn = 18, /*!< A/D Converter Interrupt */
sahilmgandhi 18:6a4db94011d3 41 I2C1_IRQn = 19, /*!< I2C1 Interrupt */
sahilmgandhi 18:6a4db94011d3 42 BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
sahilmgandhi 18:6a4db94011d3 43 ENET_IRQn = 21, /*!< Ethernet Interrupt */
sahilmgandhi 18:6a4db94011d3 44 USB_IRQn = 22, /*!< USB Interrupt */
sahilmgandhi 18:6a4db94011d3 45 CAN_IRQn = 23, /*!< CAN Interrupt */
sahilmgandhi 18:6a4db94011d3 46 MIC_IRQn = 24, /*!< Multimedia Interface Controler */
sahilmgandhi 18:6a4db94011d3 47 DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
sahilmgandhi 18:6a4db94011d3 48 TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
sahilmgandhi 18:6a4db94011d3 49 TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
sahilmgandhi 18:6a4db94011d3 50 UART2_IRQn = 28, /*!< UART2 Interrupt */
sahilmgandhi 18:6a4db94011d3 51 UART3_IRQn = 29, /*!< UART3 Interrupt */
sahilmgandhi 18:6a4db94011d3 52 I2C2_IRQn = 30, /*!< I2C2 Interrupt */
sahilmgandhi 18:6a4db94011d3 53 I2S_IRQn = 31, /*!< I2S Interrupt */
sahilmgandhi 18:6a4db94011d3 54 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 /*
sahilmgandhi 18:6a4db94011d3 57 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 58 * ----------- Processor and Core Peripheral Section ------------------------
sahilmgandhi 18:6a4db94011d3 59 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 60 */
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 /* Configuration of the ARM7 Processor and Core Peripherals */
sahilmgandhi 18:6a4db94011d3 63 #define __MPU_PRESENT 0 /*!< MPU present or not */
sahilmgandhi 18:6a4db94011d3 64 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 65 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 #include <core_arm7.h>
sahilmgandhi 18:6a4db94011d3 69 #include "system_LPC23xx.h" /* System Header */
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 73 /* Device Specific Peripheral registers structures */
sahilmgandhi 18:6a4db94011d3 74 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 75 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 76 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 77 #endif
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 /*------------- Vector Interupt Controler (VIC) ------------------------------*/
sahilmgandhi 18:6a4db94011d3 80 typedef struct
sahilmgandhi 18:6a4db94011d3 81 {
sahilmgandhi 18:6a4db94011d3 82 __I uint32_t IRQStatus;
sahilmgandhi 18:6a4db94011d3 83 __I uint32_t FIQStatus;
sahilmgandhi 18:6a4db94011d3 84 __I uint32_t RawIntr;
sahilmgandhi 18:6a4db94011d3 85 __IO uint32_t IntSelect;
sahilmgandhi 18:6a4db94011d3 86 __IO uint32_t IntEnable;
sahilmgandhi 18:6a4db94011d3 87 __O uint32_t IntEnClr;
sahilmgandhi 18:6a4db94011d3 88 __IO uint32_t SoftInt;
sahilmgandhi 18:6a4db94011d3 89 __O uint32_t SoftIntClr;
sahilmgandhi 18:6a4db94011d3 90 __IO uint32_t Protection;
sahilmgandhi 18:6a4db94011d3 91 __IO uint32_t SWPriorityMask;
sahilmgandhi 18:6a4db94011d3 92 __IO uint32_t RESERVED0[54];
sahilmgandhi 18:6a4db94011d3 93 __IO uint32_t VectAddr[32];
sahilmgandhi 18:6a4db94011d3 94 __IO uint32_t RESERVED1[32];
sahilmgandhi 18:6a4db94011d3 95 __IO uint32_t VectPriority[32];
sahilmgandhi 18:6a4db94011d3 96 __IO uint32_t RESERVED2[800];
sahilmgandhi 18:6a4db94011d3 97 __IO uint32_t Address;
sahilmgandhi 18:6a4db94011d3 98 } LPC_VIC_TypeDef;
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 /*------------- System Control (SC) ------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 101 typedef struct
sahilmgandhi 18:6a4db94011d3 102 {
sahilmgandhi 18:6a4db94011d3 103 __IO uint32_t MAMCR;
sahilmgandhi 18:6a4db94011d3 104 __IO uint32_t MAMTIM;
sahilmgandhi 18:6a4db94011d3 105 uint32_t RESERVED0[14];
sahilmgandhi 18:6a4db94011d3 106 __IO uint32_t MEMMAP;
sahilmgandhi 18:6a4db94011d3 107 uint32_t RESERVED1[15];
sahilmgandhi 18:6a4db94011d3 108 __IO uint32_t PLL0CON; /* Clocking and Power Control */
sahilmgandhi 18:6a4db94011d3 109 __IO uint32_t PLL0CFG;
sahilmgandhi 18:6a4db94011d3 110 __I uint32_t PLL0STAT;
sahilmgandhi 18:6a4db94011d3 111 __O uint32_t PLL0FEED;
sahilmgandhi 18:6a4db94011d3 112 uint32_t RESERVED2[12];
sahilmgandhi 18:6a4db94011d3 113 __IO uint32_t PCON;
sahilmgandhi 18:6a4db94011d3 114 __IO uint32_t PCONP;
sahilmgandhi 18:6a4db94011d3 115 uint32_t RESERVED3[15];
sahilmgandhi 18:6a4db94011d3 116 __IO uint32_t CCLKCFG;
sahilmgandhi 18:6a4db94011d3 117 __IO uint32_t USBCLKCFG;
sahilmgandhi 18:6a4db94011d3 118 __IO uint32_t CLKSRCSEL;
sahilmgandhi 18:6a4db94011d3 119 uint32_t RESERVED4[12];
sahilmgandhi 18:6a4db94011d3 120 __IO uint32_t EXTINT; /* External Interrupts */
sahilmgandhi 18:6a4db94011d3 121 __IO uint32_t INTWAKE;
sahilmgandhi 18:6a4db94011d3 122 __IO uint32_t EXTMODE;
sahilmgandhi 18:6a4db94011d3 123 __IO uint32_t EXTPOLAR;
sahilmgandhi 18:6a4db94011d3 124 uint32_t RESERVED6[12];
sahilmgandhi 18:6a4db94011d3 125 __IO uint32_t RSID; /* Reset */
sahilmgandhi 18:6a4db94011d3 126 __IO uint32_t CSPR;
sahilmgandhi 18:6a4db94011d3 127 __IO uint32_t AHBCFG1;
sahilmgandhi 18:6a4db94011d3 128 __IO uint32_t AHBCFG2;
sahilmgandhi 18:6a4db94011d3 129 uint32_t RESERVED7[4];
sahilmgandhi 18:6a4db94011d3 130 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
sahilmgandhi 18:6a4db94011d3 131 __IO uint32_t IRCTRIM; /* Clock Dividers */
sahilmgandhi 18:6a4db94011d3 132 __IO uint32_t PCLKSEL0;
sahilmgandhi 18:6a4db94011d3 133 __IO uint32_t PCLKSEL1;
sahilmgandhi 18:6a4db94011d3 134 uint32_t RESERVED8[4];
sahilmgandhi 18:6a4db94011d3 135 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
sahilmgandhi 18:6a4db94011d3 136 uint32_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 137 // __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
sahilmgandhi 18:6a4db94011d3 138 } LPC_SC_TypeDef;
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
sahilmgandhi 18:6a4db94011d3 141 typedef struct
sahilmgandhi 18:6a4db94011d3 142 {
sahilmgandhi 18:6a4db94011d3 143 __IO uint32_t PINSEL0;
sahilmgandhi 18:6a4db94011d3 144 __IO uint32_t PINSEL1;
sahilmgandhi 18:6a4db94011d3 145 __IO uint32_t PINSEL2;
sahilmgandhi 18:6a4db94011d3 146 __IO uint32_t PINSEL3;
sahilmgandhi 18:6a4db94011d3 147 __IO uint32_t PINSEL4;
sahilmgandhi 18:6a4db94011d3 148 __IO uint32_t PINSEL5;
sahilmgandhi 18:6a4db94011d3 149 __IO uint32_t PINSEL6;
sahilmgandhi 18:6a4db94011d3 150 __IO uint32_t PINSEL7;
sahilmgandhi 18:6a4db94011d3 151 __IO uint32_t PINSEL8;
sahilmgandhi 18:6a4db94011d3 152 __IO uint32_t PINSEL9;
sahilmgandhi 18:6a4db94011d3 153 __IO uint32_t PINSEL10;
sahilmgandhi 18:6a4db94011d3 154 uint32_t RESERVED0[5];
sahilmgandhi 18:6a4db94011d3 155 __IO uint32_t PINMODE0;
sahilmgandhi 18:6a4db94011d3 156 __IO uint32_t PINMODE1;
sahilmgandhi 18:6a4db94011d3 157 __IO uint32_t PINMODE2;
sahilmgandhi 18:6a4db94011d3 158 __IO uint32_t PINMODE3;
sahilmgandhi 18:6a4db94011d3 159 __IO uint32_t PINMODE4;
sahilmgandhi 18:6a4db94011d3 160 __IO uint32_t PINMODE5;
sahilmgandhi 18:6a4db94011d3 161 __IO uint32_t PINMODE6;
sahilmgandhi 18:6a4db94011d3 162 __IO uint32_t PINMODE7;
sahilmgandhi 18:6a4db94011d3 163 __IO uint32_t PINMODE8;
sahilmgandhi 18:6a4db94011d3 164 __IO uint32_t PINMODE9;
sahilmgandhi 18:6a4db94011d3 165 __IO uint32_t PINMODE_OD0;
sahilmgandhi 18:6a4db94011d3 166 __IO uint32_t PINMODE_OD1;
sahilmgandhi 18:6a4db94011d3 167 __IO uint32_t PINMODE_OD2;
sahilmgandhi 18:6a4db94011d3 168 __IO uint32_t PINMODE_OD3;
sahilmgandhi 18:6a4db94011d3 169 __IO uint32_t PINMODE_OD4;
sahilmgandhi 18:6a4db94011d3 170 } LPC_PINCON_TypeDef;
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
sahilmgandhi 18:6a4db94011d3 173 typedef struct
sahilmgandhi 18:6a4db94011d3 174 {
sahilmgandhi 18:6a4db94011d3 175 __IO uint32_t FIODIR;
sahilmgandhi 18:6a4db94011d3 176 uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 177 __IO uint32_t FIOMASK;
sahilmgandhi 18:6a4db94011d3 178 __IO uint32_t FIOPIN;
sahilmgandhi 18:6a4db94011d3 179 __IO uint32_t FIOSET;
sahilmgandhi 18:6a4db94011d3 180 __O uint32_t FIOCLR;
sahilmgandhi 18:6a4db94011d3 181 } LPC_GPIO_TypeDef;
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 typedef struct
sahilmgandhi 18:6a4db94011d3 184 {
sahilmgandhi 18:6a4db94011d3 185 __I uint32_t IntStatus;
sahilmgandhi 18:6a4db94011d3 186 __I uint32_t IO0IntStatR;
sahilmgandhi 18:6a4db94011d3 187 __I uint32_t IO0IntStatF;
sahilmgandhi 18:6a4db94011d3 188 __O uint32_t IO0IntClr;
sahilmgandhi 18:6a4db94011d3 189 __IO uint32_t IO0IntEnR;
sahilmgandhi 18:6a4db94011d3 190 __IO uint32_t IO0IntEnF;
sahilmgandhi 18:6a4db94011d3 191 uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 192 __I uint32_t IO2IntStatR;
sahilmgandhi 18:6a4db94011d3 193 __I uint32_t IO2IntStatF;
sahilmgandhi 18:6a4db94011d3 194 __O uint32_t IO2IntClr;
sahilmgandhi 18:6a4db94011d3 195 __IO uint32_t IO2IntEnR;
sahilmgandhi 18:6a4db94011d3 196 __IO uint32_t IO2IntEnF;
sahilmgandhi 18:6a4db94011d3 197 } LPC_GPIOINT_TypeDef;
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 /*------------- Timer (TIM) --------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 200 typedef struct
sahilmgandhi 18:6a4db94011d3 201 {
sahilmgandhi 18:6a4db94011d3 202 __IO uint32_t IR;
sahilmgandhi 18:6a4db94011d3 203 __IO uint32_t TCR;
sahilmgandhi 18:6a4db94011d3 204 __IO uint32_t TC;
sahilmgandhi 18:6a4db94011d3 205 __IO uint32_t PR;
sahilmgandhi 18:6a4db94011d3 206 __IO uint32_t PC;
sahilmgandhi 18:6a4db94011d3 207 __IO uint32_t MCR;
sahilmgandhi 18:6a4db94011d3 208 __IO uint32_t MR0;
sahilmgandhi 18:6a4db94011d3 209 __IO uint32_t MR1;
sahilmgandhi 18:6a4db94011d3 210 __IO uint32_t MR2;
sahilmgandhi 18:6a4db94011d3 211 __IO uint32_t MR3;
sahilmgandhi 18:6a4db94011d3 212 __IO uint32_t CCR;
sahilmgandhi 18:6a4db94011d3 213 __I uint32_t CR0;
sahilmgandhi 18:6a4db94011d3 214 __I uint32_t CR1;
sahilmgandhi 18:6a4db94011d3 215 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 216 __IO uint32_t EMR;
sahilmgandhi 18:6a4db94011d3 217 uint32_t RESERVED1[12];
sahilmgandhi 18:6a4db94011d3 218 __IO uint32_t CTCR;
sahilmgandhi 18:6a4db94011d3 219 } LPC_TIM_TypeDef;
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
sahilmgandhi 18:6a4db94011d3 222 typedef struct
sahilmgandhi 18:6a4db94011d3 223 {
sahilmgandhi 18:6a4db94011d3 224 __IO uint32_t IR;
sahilmgandhi 18:6a4db94011d3 225 __IO uint32_t TCR;
sahilmgandhi 18:6a4db94011d3 226 __IO uint32_t TC;
sahilmgandhi 18:6a4db94011d3 227 __IO uint32_t PR;
sahilmgandhi 18:6a4db94011d3 228 __IO uint32_t PC;
sahilmgandhi 18:6a4db94011d3 229 __IO uint32_t MCR;
sahilmgandhi 18:6a4db94011d3 230 __IO uint32_t MR0;
sahilmgandhi 18:6a4db94011d3 231 __IO uint32_t MR1;
sahilmgandhi 18:6a4db94011d3 232 __IO uint32_t MR2;
sahilmgandhi 18:6a4db94011d3 233 __IO uint32_t MR3;
sahilmgandhi 18:6a4db94011d3 234 __IO uint32_t CCR;
sahilmgandhi 18:6a4db94011d3 235 __I uint32_t CR0;
sahilmgandhi 18:6a4db94011d3 236 __I uint32_t CR1;
sahilmgandhi 18:6a4db94011d3 237 __I uint32_t CR2;
sahilmgandhi 18:6a4db94011d3 238 __I uint32_t CR3;
sahilmgandhi 18:6a4db94011d3 239 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 240 __IO uint32_t MR4;
sahilmgandhi 18:6a4db94011d3 241 __IO uint32_t MR5;
sahilmgandhi 18:6a4db94011d3 242 __IO uint32_t MR6;
sahilmgandhi 18:6a4db94011d3 243 __IO uint32_t PCR;
sahilmgandhi 18:6a4db94011d3 244 __IO uint32_t LER;
sahilmgandhi 18:6a4db94011d3 245 uint32_t RESERVED1[7];
sahilmgandhi 18:6a4db94011d3 246 __IO uint32_t CTCR;
sahilmgandhi 18:6a4db94011d3 247 } LPC_PWM_TypeDef;
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
sahilmgandhi 18:6a4db94011d3 250 typedef struct
sahilmgandhi 18:6a4db94011d3 251 {
sahilmgandhi 18:6a4db94011d3 252 union {
sahilmgandhi 18:6a4db94011d3 253 __I uint8_t RBR;
sahilmgandhi 18:6a4db94011d3 254 __O uint8_t THR;
sahilmgandhi 18:6a4db94011d3 255 __IO uint8_t DLL;
sahilmgandhi 18:6a4db94011d3 256 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 257 };
sahilmgandhi 18:6a4db94011d3 258 union {
sahilmgandhi 18:6a4db94011d3 259 __IO uint8_t DLM;
sahilmgandhi 18:6a4db94011d3 260 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 261 };
sahilmgandhi 18:6a4db94011d3 262 union {
sahilmgandhi 18:6a4db94011d3 263 __I uint32_t IIR;
sahilmgandhi 18:6a4db94011d3 264 __O uint8_t FCR;
sahilmgandhi 18:6a4db94011d3 265 };
sahilmgandhi 18:6a4db94011d3 266 __IO uint8_t LCR;
sahilmgandhi 18:6a4db94011d3 267 uint8_t RESERVED1[7];
sahilmgandhi 18:6a4db94011d3 268 __IO uint8_t LSR;
sahilmgandhi 18:6a4db94011d3 269 uint8_t RESERVED2[7];
sahilmgandhi 18:6a4db94011d3 270 __IO uint8_t SCR;
sahilmgandhi 18:6a4db94011d3 271 uint8_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 272 __IO uint32_t ACR;
sahilmgandhi 18:6a4db94011d3 273 __IO uint8_t ICR;
sahilmgandhi 18:6a4db94011d3 274 uint8_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 275 __IO uint8_t FDR;
sahilmgandhi 18:6a4db94011d3 276 uint8_t RESERVED5[7];
sahilmgandhi 18:6a4db94011d3 277 __IO uint8_t TER;
sahilmgandhi 18:6a4db94011d3 278 uint8_t RESERVED6[27];
sahilmgandhi 18:6a4db94011d3 279 __IO uint8_t RS485CTRL;
sahilmgandhi 18:6a4db94011d3 280 uint8_t RESERVED7[3];
sahilmgandhi 18:6a4db94011d3 281 __IO uint8_t ADRMATCH;
sahilmgandhi 18:6a4db94011d3 282 } LPC_UART_TypeDef;
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 typedef struct
sahilmgandhi 18:6a4db94011d3 285 {
sahilmgandhi 18:6a4db94011d3 286 union {
sahilmgandhi 18:6a4db94011d3 287 __I uint8_t RBR;
sahilmgandhi 18:6a4db94011d3 288 __O uint8_t THR;
sahilmgandhi 18:6a4db94011d3 289 __IO uint8_t DLL;
sahilmgandhi 18:6a4db94011d3 290 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 291 };
sahilmgandhi 18:6a4db94011d3 292 union {
sahilmgandhi 18:6a4db94011d3 293 __IO uint8_t DLM;
sahilmgandhi 18:6a4db94011d3 294 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 295 };
sahilmgandhi 18:6a4db94011d3 296 union {
sahilmgandhi 18:6a4db94011d3 297 __I uint32_t IIR;
sahilmgandhi 18:6a4db94011d3 298 __O uint8_t FCR;
sahilmgandhi 18:6a4db94011d3 299 };
sahilmgandhi 18:6a4db94011d3 300 __IO uint8_t LCR;
sahilmgandhi 18:6a4db94011d3 301 uint8_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 302 __IO uint8_t MCR;
sahilmgandhi 18:6a4db94011d3 303 uint8_t RESERVED2[3];
sahilmgandhi 18:6a4db94011d3 304 __IO uint8_t LSR;
sahilmgandhi 18:6a4db94011d3 305 uint8_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 306 __IO uint8_t MSR;
sahilmgandhi 18:6a4db94011d3 307 uint8_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 308 __IO uint8_t SCR;
sahilmgandhi 18:6a4db94011d3 309 uint8_t RESERVED5[3];
sahilmgandhi 18:6a4db94011d3 310 __IO uint32_t ACR;
sahilmgandhi 18:6a4db94011d3 311 uint32_t RESERVED6;
sahilmgandhi 18:6a4db94011d3 312 __IO uint32_t FDR;
sahilmgandhi 18:6a4db94011d3 313 uint32_t RESERVED7;
sahilmgandhi 18:6a4db94011d3 314 __IO uint8_t TER;
sahilmgandhi 18:6a4db94011d3 315 uint8_t RESERVED8[27];
sahilmgandhi 18:6a4db94011d3 316 __IO uint8_t RS485CTRL;
sahilmgandhi 18:6a4db94011d3 317 uint8_t RESERVED9[3];
sahilmgandhi 18:6a4db94011d3 318 __IO uint8_t ADRMATCH;
sahilmgandhi 18:6a4db94011d3 319 uint8_t RESERVED10[3];
sahilmgandhi 18:6a4db94011d3 320 __IO uint8_t RS485DLY;
sahilmgandhi 18:6a4db94011d3 321 } LPC_UART1_TypeDef;
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
sahilmgandhi 18:6a4db94011d3 324 typedef struct
sahilmgandhi 18:6a4db94011d3 325 {
sahilmgandhi 18:6a4db94011d3 326 __IO uint32_t SPCR;
sahilmgandhi 18:6a4db94011d3 327 __I uint32_t SPSR;
sahilmgandhi 18:6a4db94011d3 328 __IO uint32_t SPDR;
sahilmgandhi 18:6a4db94011d3 329 __IO uint32_t SPCCR;
sahilmgandhi 18:6a4db94011d3 330 uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 331 __IO uint32_t SPINT;
sahilmgandhi 18:6a4db94011d3 332 } LPC_SPI_TypeDef;
sahilmgandhi 18:6a4db94011d3 333
sahilmgandhi 18:6a4db94011d3 334 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
sahilmgandhi 18:6a4db94011d3 335 typedef struct
sahilmgandhi 18:6a4db94011d3 336 {
sahilmgandhi 18:6a4db94011d3 337 __IO uint32_t CR0;
sahilmgandhi 18:6a4db94011d3 338 __IO uint32_t CR1;
sahilmgandhi 18:6a4db94011d3 339 __IO uint32_t DR;
sahilmgandhi 18:6a4db94011d3 340 __I uint32_t SR;
sahilmgandhi 18:6a4db94011d3 341 __IO uint32_t CPSR;
sahilmgandhi 18:6a4db94011d3 342 __IO uint32_t IMSC;
sahilmgandhi 18:6a4db94011d3 343 __IO uint32_t RIS;
sahilmgandhi 18:6a4db94011d3 344 __IO uint32_t MIS;
sahilmgandhi 18:6a4db94011d3 345 __IO uint32_t ICR;
sahilmgandhi 18:6a4db94011d3 346 __IO uint32_t DMACR;
sahilmgandhi 18:6a4db94011d3 347 } LPC_SSP_TypeDef;
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
sahilmgandhi 18:6a4db94011d3 350 typedef struct
sahilmgandhi 18:6a4db94011d3 351 {
sahilmgandhi 18:6a4db94011d3 352 __IO uint32_t I2CONSET;
sahilmgandhi 18:6a4db94011d3 353 __I uint32_t I2STAT;
sahilmgandhi 18:6a4db94011d3 354 __IO uint32_t I2DAT;
sahilmgandhi 18:6a4db94011d3 355 __IO uint32_t I2ADR0;
sahilmgandhi 18:6a4db94011d3 356 __IO uint32_t I2SCLH;
sahilmgandhi 18:6a4db94011d3 357 __IO uint32_t I2SCLL;
sahilmgandhi 18:6a4db94011d3 358 __O uint32_t I2CONCLR;
sahilmgandhi 18:6a4db94011d3 359 __IO uint32_t MMCTRL;
sahilmgandhi 18:6a4db94011d3 360 __IO uint32_t I2ADR1;
sahilmgandhi 18:6a4db94011d3 361 __IO uint32_t I2ADR2;
sahilmgandhi 18:6a4db94011d3 362 __IO uint32_t I2ADR3;
sahilmgandhi 18:6a4db94011d3 363 __I uint32_t I2DATA_BUFFER;
sahilmgandhi 18:6a4db94011d3 364 __IO uint32_t I2MASK0;
sahilmgandhi 18:6a4db94011d3 365 __IO uint32_t I2MASK1;
sahilmgandhi 18:6a4db94011d3 366 __IO uint32_t I2MASK2;
sahilmgandhi 18:6a4db94011d3 367 __IO uint32_t I2MASK3;
sahilmgandhi 18:6a4db94011d3 368 } LPC_I2C_TypeDef;
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 371 typedef struct
sahilmgandhi 18:6a4db94011d3 372 {
sahilmgandhi 18:6a4db94011d3 373 __IO uint32_t I2SDAO;
sahilmgandhi 18:6a4db94011d3 374 __I uint32_t I2SDAI;
sahilmgandhi 18:6a4db94011d3 375 __O uint32_t I2STXFIFO;
sahilmgandhi 18:6a4db94011d3 376 __I uint32_t I2SRXFIFO;
sahilmgandhi 18:6a4db94011d3 377 __I uint32_t I2SSTATE;
sahilmgandhi 18:6a4db94011d3 378 __IO uint32_t I2SDMA1;
sahilmgandhi 18:6a4db94011d3 379 __IO uint32_t I2SDMA2;
sahilmgandhi 18:6a4db94011d3 380 __IO uint32_t I2SIRQ;
sahilmgandhi 18:6a4db94011d3 381 __IO uint32_t I2STXRATE;
sahilmgandhi 18:6a4db94011d3 382 __IO uint32_t I2SRXRATE;
sahilmgandhi 18:6a4db94011d3 383 __IO uint32_t I2STXBITRATE;
sahilmgandhi 18:6a4db94011d3 384 __IO uint32_t I2SRXBITRATE;
sahilmgandhi 18:6a4db94011d3 385 __IO uint32_t I2STXMODE;
sahilmgandhi 18:6a4db94011d3 386 __IO uint32_t I2SRXMODE;
sahilmgandhi 18:6a4db94011d3 387 } LPC_I2S_TypeDef;
sahilmgandhi 18:6a4db94011d3 388
sahilmgandhi 18:6a4db94011d3 389 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 390 typedef struct
sahilmgandhi 18:6a4db94011d3 391 {
sahilmgandhi 18:6a4db94011d3 392 __IO uint8_t ILR;
sahilmgandhi 18:6a4db94011d3 393 uint8_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 394 __IO uint8_t CTC;
sahilmgandhi 18:6a4db94011d3 395 uint8_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 396 __IO uint8_t CCR;
sahilmgandhi 18:6a4db94011d3 397 uint8_t RESERVED2[3];
sahilmgandhi 18:6a4db94011d3 398 __IO uint8_t CIIR;
sahilmgandhi 18:6a4db94011d3 399 uint8_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 400 __IO uint8_t AMR;
sahilmgandhi 18:6a4db94011d3 401 uint8_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 402 __I uint32_t CTIME0;
sahilmgandhi 18:6a4db94011d3 403 __I uint32_t CTIME1;
sahilmgandhi 18:6a4db94011d3 404 __I uint32_t CTIME2;
sahilmgandhi 18:6a4db94011d3 405 __IO uint8_t SEC;
sahilmgandhi 18:6a4db94011d3 406 uint8_t RESERVED5[3];
sahilmgandhi 18:6a4db94011d3 407 __IO uint8_t MIN;
sahilmgandhi 18:6a4db94011d3 408 uint8_t RESERVED6[3];
sahilmgandhi 18:6a4db94011d3 409 __IO uint8_t HOUR;
sahilmgandhi 18:6a4db94011d3 410 uint8_t RESERVED7[3];
sahilmgandhi 18:6a4db94011d3 411 __IO uint8_t DOM;
sahilmgandhi 18:6a4db94011d3 412 uint8_t RESERVED8[3];
sahilmgandhi 18:6a4db94011d3 413 __IO uint8_t DOW;
sahilmgandhi 18:6a4db94011d3 414 uint8_t RESERVED9[3];
sahilmgandhi 18:6a4db94011d3 415 __IO uint16_t DOY;
sahilmgandhi 18:6a4db94011d3 416 uint16_t RESERVED10;
sahilmgandhi 18:6a4db94011d3 417 __IO uint8_t MONTH;
sahilmgandhi 18:6a4db94011d3 418 uint8_t RESERVED11[3];
sahilmgandhi 18:6a4db94011d3 419 __IO uint16_t YEAR;
sahilmgandhi 18:6a4db94011d3 420 uint16_t RESERVED12;
sahilmgandhi 18:6a4db94011d3 421 __IO uint32_t CALIBRATION;
sahilmgandhi 18:6a4db94011d3 422 __IO uint32_t GPREG0;
sahilmgandhi 18:6a4db94011d3 423 __IO uint32_t GPREG1;
sahilmgandhi 18:6a4db94011d3 424 __IO uint32_t GPREG2;
sahilmgandhi 18:6a4db94011d3 425 __IO uint32_t GPREG3;
sahilmgandhi 18:6a4db94011d3 426 __IO uint32_t GPREG4;
sahilmgandhi 18:6a4db94011d3 427 __IO uint8_t WAKEUPDIS;
sahilmgandhi 18:6a4db94011d3 428 uint8_t RESERVED13[3];
sahilmgandhi 18:6a4db94011d3 429 __IO uint8_t PWRCTRL;
sahilmgandhi 18:6a4db94011d3 430 uint8_t RESERVED14[3];
sahilmgandhi 18:6a4db94011d3 431 __IO uint8_t ALSEC;
sahilmgandhi 18:6a4db94011d3 432 uint8_t RESERVED15[3];
sahilmgandhi 18:6a4db94011d3 433 __IO uint8_t ALMIN;
sahilmgandhi 18:6a4db94011d3 434 uint8_t RESERVED16[3];
sahilmgandhi 18:6a4db94011d3 435 __IO uint8_t ALHOUR;
sahilmgandhi 18:6a4db94011d3 436 uint8_t RESERVED17[3];
sahilmgandhi 18:6a4db94011d3 437 __IO uint8_t ALDOM;
sahilmgandhi 18:6a4db94011d3 438 uint8_t RESERVED18[3];
sahilmgandhi 18:6a4db94011d3 439 __IO uint8_t ALDOW;
sahilmgandhi 18:6a4db94011d3 440 uint8_t RESERVED19[3];
sahilmgandhi 18:6a4db94011d3 441 __IO uint16_t ALDOY;
sahilmgandhi 18:6a4db94011d3 442 uint16_t RESERVED20;
sahilmgandhi 18:6a4db94011d3 443 __IO uint8_t ALMON;
sahilmgandhi 18:6a4db94011d3 444 uint8_t RESERVED21[3];
sahilmgandhi 18:6a4db94011d3 445 __IO uint16_t ALYEAR;
sahilmgandhi 18:6a4db94011d3 446 uint16_t RESERVED22;
sahilmgandhi 18:6a4db94011d3 447 } LPC_RTC_TypeDef;
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 450 typedef struct
sahilmgandhi 18:6a4db94011d3 451 {
sahilmgandhi 18:6a4db94011d3 452 __IO uint8_t WDMOD;
sahilmgandhi 18:6a4db94011d3 453 uint8_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 454 __IO uint32_t WDTC;
sahilmgandhi 18:6a4db94011d3 455 __O uint8_t WDFEED;
sahilmgandhi 18:6a4db94011d3 456 uint8_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 457 __I uint32_t WDTV;
sahilmgandhi 18:6a4db94011d3 458 __IO uint32_t WDCLKSEL;
sahilmgandhi 18:6a4db94011d3 459 } LPC_WDT_TypeDef;
sahilmgandhi 18:6a4db94011d3 460
sahilmgandhi 18:6a4db94011d3 461 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
sahilmgandhi 18:6a4db94011d3 462 typedef struct
sahilmgandhi 18:6a4db94011d3 463 {
sahilmgandhi 18:6a4db94011d3 464 __IO uint32_t ADCR;
sahilmgandhi 18:6a4db94011d3 465 __IO uint32_t ADGDR;
sahilmgandhi 18:6a4db94011d3 466 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 467 __IO uint32_t ADINTEN;
sahilmgandhi 18:6a4db94011d3 468 __I uint32_t ADDR0;
sahilmgandhi 18:6a4db94011d3 469 __I uint32_t ADDR1;
sahilmgandhi 18:6a4db94011d3 470 __I uint32_t ADDR2;
sahilmgandhi 18:6a4db94011d3 471 __I uint32_t ADDR3;
sahilmgandhi 18:6a4db94011d3 472 __I uint32_t ADDR4;
sahilmgandhi 18:6a4db94011d3 473 __I uint32_t ADDR5;
sahilmgandhi 18:6a4db94011d3 474 __I uint32_t ADDR6;
sahilmgandhi 18:6a4db94011d3 475 __I uint32_t ADDR7;
sahilmgandhi 18:6a4db94011d3 476 __I uint32_t ADSTAT;
sahilmgandhi 18:6a4db94011d3 477 __IO uint32_t ADTRM;
sahilmgandhi 18:6a4db94011d3 478 } LPC_ADC_TypeDef;
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
sahilmgandhi 18:6a4db94011d3 481 typedef struct
sahilmgandhi 18:6a4db94011d3 482 {
sahilmgandhi 18:6a4db94011d3 483 __IO uint32_t DACR;
sahilmgandhi 18:6a4db94011d3 484 __IO uint32_t DACCTRL;
sahilmgandhi 18:6a4db94011d3 485 __IO uint16_t DACCNTVAL;
sahilmgandhi 18:6a4db94011d3 486 } LPC_DAC_TypeDef;
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488 /*------------- Multimedia Card Interface (MCI) ------------------------------*/
sahilmgandhi 18:6a4db94011d3 489 typedef struct
sahilmgandhi 18:6a4db94011d3 490 {
sahilmgandhi 18:6a4db94011d3 491 __IO uint32_t MCIPower; /* Power control */
sahilmgandhi 18:6a4db94011d3 492 __IO uint32_t MCIClock; /* Clock control */
sahilmgandhi 18:6a4db94011d3 493 __IO uint32_t MCIArgument;
sahilmgandhi 18:6a4db94011d3 494 __IO uint32_t MMCCommand;
sahilmgandhi 18:6a4db94011d3 495 __I uint32_t MCIRespCmd;
sahilmgandhi 18:6a4db94011d3 496 __I uint32_t MCIResponse0;
sahilmgandhi 18:6a4db94011d3 497 __I uint32_t MCIResponse1;
sahilmgandhi 18:6a4db94011d3 498 __I uint32_t MCIResponse2;
sahilmgandhi 18:6a4db94011d3 499 __I uint32_t MCIResponse3;
sahilmgandhi 18:6a4db94011d3 500 __IO uint32_t MCIDataTimer;
sahilmgandhi 18:6a4db94011d3 501 __IO uint32_t MCIDataLength;
sahilmgandhi 18:6a4db94011d3 502 __IO uint32_t MCIDataCtrl;
sahilmgandhi 18:6a4db94011d3 503 __I uint32_t MCIDataCnt;
sahilmgandhi 18:6a4db94011d3 504 } LPC_MCI_TypeDef;
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 /*------------- Controller Area Network (CAN) --------------------------------*/
sahilmgandhi 18:6a4db94011d3 507 typedef struct
sahilmgandhi 18:6a4db94011d3 508 {
sahilmgandhi 18:6a4db94011d3 509 __IO uint32_t mask[512]; /* ID Masks */
sahilmgandhi 18:6a4db94011d3 510 } LPC_CANAF_RAM_TypeDef;
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 typedef struct /* Acceptance Filter Registers */
sahilmgandhi 18:6a4db94011d3 513 {
sahilmgandhi 18:6a4db94011d3 514 __IO uint32_t AFMR;
sahilmgandhi 18:6a4db94011d3 515 __IO uint32_t SFF_sa;
sahilmgandhi 18:6a4db94011d3 516 __IO uint32_t SFF_GRP_sa;
sahilmgandhi 18:6a4db94011d3 517 __IO uint32_t EFF_sa;
sahilmgandhi 18:6a4db94011d3 518 __IO uint32_t EFF_GRP_sa;
sahilmgandhi 18:6a4db94011d3 519 __IO uint32_t ENDofTable;
sahilmgandhi 18:6a4db94011d3 520 __I uint32_t LUTerrAd;
sahilmgandhi 18:6a4db94011d3 521 __I uint32_t LUTerr;
sahilmgandhi 18:6a4db94011d3 522 } LPC_CANAF_TypeDef;
sahilmgandhi 18:6a4db94011d3 523
sahilmgandhi 18:6a4db94011d3 524 typedef struct /* Central Registers */
sahilmgandhi 18:6a4db94011d3 525 {
sahilmgandhi 18:6a4db94011d3 526 __I uint32_t CANTxSR;
sahilmgandhi 18:6a4db94011d3 527 __I uint32_t CANRxSR;
sahilmgandhi 18:6a4db94011d3 528 __I uint32_t CANMSR;
sahilmgandhi 18:6a4db94011d3 529 } LPC_CANCR_TypeDef;
sahilmgandhi 18:6a4db94011d3 530
sahilmgandhi 18:6a4db94011d3 531 typedef struct /* Controller Registers */
sahilmgandhi 18:6a4db94011d3 532 {
sahilmgandhi 18:6a4db94011d3 533 __IO uint32_t MOD;
sahilmgandhi 18:6a4db94011d3 534 __O uint32_t CMR;
sahilmgandhi 18:6a4db94011d3 535 __IO uint32_t GSR;
sahilmgandhi 18:6a4db94011d3 536 __I uint32_t ICR;
sahilmgandhi 18:6a4db94011d3 537 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 538 __IO uint32_t BTR;
sahilmgandhi 18:6a4db94011d3 539 __IO uint32_t EWL;
sahilmgandhi 18:6a4db94011d3 540 __I uint32_t SR;
sahilmgandhi 18:6a4db94011d3 541 __IO uint32_t RFS;
sahilmgandhi 18:6a4db94011d3 542 __IO uint32_t RID;
sahilmgandhi 18:6a4db94011d3 543 __IO uint32_t RDA;
sahilmgandhi 18:6a4db94011d3 544 __IO uint32_t RDB;
sahilmgandhi 18:6a4db94011d3 545 __IO uint32_t TFI1;
sahilmgandhi 18:6a4db94011d3 546 __IO uint32_t TID1;
sahilmgandhi 18:6a4db94011d3 547 __IO uint32_t TDA1;
sahilmgandhi 18:6a4db94011d3 548 __IO uint32_t TDB1;
sahilmgandhi 18:6a4db94011d3 549 __IO uint32_t TFI2;
sahilmgandhi 18:6a4db94011d3 550 __IO uint32_t TID2;
sahilmgandhi 18:6a4db94011d3 551 __IO uint32_t TDA2;
sahilmgandhi 18:6a4db94011d3 552 __IO uint32_t TDB2;
sahilmgandhi 18:6a4db94011d3 553 __IO uint32_t TFI3;
sahilmgandhi 18:6a4db94011d3 554 __IO uint32_t TID3;
sahilmgandhi 18:6a4db94011d3 555 __IO uint32_t TDA3;
sahilmgandhi 18:6a4db94011d3 556 __IO uint32_t TDB3;
sahilmgandhi 18:6a4db94011d3 557 } LPC_CAN_TypeDef;
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
sahilmgandhi 18:6a4db94011d3 560 typedef struct /* Common Registers */
sahilmgandhi 18:6a4db94011d3 561 {
sahilmgandhi 18:6a4db94011d3 562 __I uint32_t DMACIntStat;
sahilmgandhi 18:6a4db94011d3 563 __I uint32_t DMACIntTCStat;
sahilmgandhi 18:6a4db94011d3 564 __O uint32_t DMACIntTCClear;
sahilmgandhi 18:6a4db94011d3 565 __I uint32_t DMACIntErrStat;
sahilmgandhi 18:6a4db94011d3 566 __O uint32_t DMACIntErrClr;
sahilmgandhi 18:6a4db94011d3 567 __I uint32_t DMACRawIntTCStat;
sahilmgandhi 18:6a4db94011d3 568 __I uint32_t DMACRawIntErrStat;
sahilmgandhi 18:6a4db94011d3 569 __I uint32_t DMACEnbldChns;
sahilmgandhi 18:6a4db94011d3 570 __IO uint32_t DMACSoftBReq;
sahilmgandhi 18:6a4db94011d3 571 __IO uint32_t DMACSoftSReq;
sahilmgandhi 18:6a4db94011d3 572 __IO uint32_t DMACSoftLBReq;
sahilmgandhi 18:6a4db94011d3 573 __IO uint32_t DMACSoftLSReq;
sahilmgandhi 18:6a4db94011d3 574 __IO uint32_t DMACConfig;
sahilmgandhi 18:6a4db94011d3 575 __IO uint32_t DMACSync;
sahilmgandhi 18:6a4db94011d3 576 } LPC_GPDMA_TypeDef;
sahilmgandhi 18:6a4db94011d3 577
sahilmgandhi 18:6a4db94011d3 578 typedef struct /* Channel Registers */
sahilmgandhi 18:6a4db94011d3 579 {
sahilmgandhi 18:6a4db94011d3 580 __IO uint32_t DMACCSrcAddr;
sahilmgandhi 18:6a4db94011d3 581 __IO uint32_t DMACCDestAddr;
sahilmgandhi 18:6a4db94011d3 582 __IO uint32_t DMACCLLI;
sahilmgandhi 18:6a4db94011d3 583 __IO uint32_t DMACCControl;
sahilmgandhi 18:6a4db94011d3 584 __IO uint32_t DMACCConfig;
sahilmgandhi 18:6a4db94011d3 585 } LPC_GPDMACH_TypeDef;
sahilmgandhi 18:6a4db94011d3 586
sahilmgandhi 18:6a4db94011d3 587 /*------------- Universal Serial Bus (USB) -----------------------------------*/
sahilmgandhi 18:6a4db94011d3 588 typedef struct
sahilmgandhi 18:6a4db94011d3 589 {
sahilmgandhi 18:6a4db94011d3 590 __I uint32_t HcRevision; /* USB Host Registers */
sahilmgandhi 18:6a4db94011d3 591 __IO uint32_t HcControl;
sahilmgandhi 18:6a4db94011d3 592 __IO uint32_t HcCommandStatus;
sahilmgandhi 18:6a4db94011d3 593 __IO uint32_t HcInterruptStatus;
sahilmgandhi 18:6a4db94011d3 594 __IO uint32_t HcInterruptEnable;
sahilmgandhi 18:6a4db94011d3 595 __IO uint32_t HcInterruptDisable;
sahilmgandhi 18:6a4db94011d3 596 __IO uint32_t HcHCCA;
sahilmgandhi 18:6a4db94011d3 597 __I uint32_t HcPeriodCurrentED;
sahilmgandhi 18:6a4db94011d3 598 __IO uint32_t HcControlHeadED;
sahilmgandhi 18:6a4db94011d3 599 __IO uint32_t HcControlCurrentED;
sahilmgandhi 18:6a4db94011d3 600 __IO uint32_t HcBulkHeadED;
sahilmgandhi 18:6a4db94011d3 601 __IO uint32_t HcBulkCurrentED;
sahilmgandhi 18:6a4db94011d3 602 __I uint32_t HcDoneHead;
sahilmgandhi 18:6a4db94011d3 603 __IO uint32_t HcFmInterval;
sahilmgandhi 18:6a4db94011d3 604 __I uint32_t HcFmRemaining;
sahilmgandhi 18:6a4db94011d3 605 __I uint32_t HcFmNumber;
sahilmgandhi 18:6a4db94011d3 606 __IO uint32_t HcPeriodicStart;
sahilmgandhi 18:6a4db94011d3 607 __IO uint32_t HcLSTreshold;
sahilmgandhi 18:6a4db94011d3 608 __IO uint32_t HcRhDescriptorA;
sahilmgandhi 18:6a4db94011d3 609 __IO uint32_t HcRhDescriptorB;
sahilmgandhi 18:6a4db94011d3 610 __IO uint32_t HcRhStatus;
sahilmgandhi 18:6a4db94011d3 611 __IO uint32_t HcRhPortStatus1;
sahilmgandhi 18:6a4db94011d3 612 __IO uint32_t HcRhPortStatus2;
sahilmgandhi 18:6a4db94011d3 613 uint32_t RESERVED0[40];
sahilmgandhi 18:6a4db94011d3 614 __I uint32_t Module_ID;
sahilmgandhi 18:6a4db94011d3 615
sahilmgandhi 18:6a4db94011d3 616 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
sahilmgandhi 18:6a4db94011d3 617 __IO uint32_t OTGIntEn;
sahilmgandhi 18:6a4db94011d3 618 __O uint32_t OTGIntSet;
sahilmgandhi 18:6a4db94011d3 619 __O uint32_t OTGIntClr;
sahilmgandhi 18:6a4db94011d3 620 __IO uint32_t OTGStCtrl;
sahilmgandhi 18:6a4db94011d3 621 __IO uint32_t OTGTmr;
sahilmgandhi 18:6a4db94011d3 622 uint32_t RESERVED1[58];
sahilmgandhi 18:6a4db94011d3 623
sahilmgandhi 18:6a4db94011d3 624 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
sahilmgandhi 18:6a4db94011d3 625 __IO uint32_t USBDevIntEn;
sahilmgandhi 18:6a4db94011d3 626 __O uint32_t USBDevIntClr;
sahilmgandhi 18:6a4db94011d3 627 __O uint32_t USBDevIntSet;
sahilmgandhi 18:6a4db94011d3 628
sahilmgandhi 18:6a4db94011d3 629 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
sahilmgandhi 18:6a4db94011d3 630 __I uint32_t USBCmdData;
sahilmgandhi 18:6a4db94011d3 631
sahilmgandhi 18:6a4db94011d3 632 __I uint32_t USBRxData; /* USB Device Transfer Registers */
sahilmgandhi 18:6a4db94011d3 633 __O uint32_t USBTxData;
sahilmgandhi 18:6a4db94011d3 634 __I uint32_t USBRxPLen;
sahilmgandhi 18:6a4db94011d3 635 __O uint32_t USBTxPLen;
sahilmgandhi 18:6a4db94011d3 636 __IO uint32_t USBCtrl;
sahilmgandhi 18:6a4db94011d3 637 __O uint32_t USBDevIntPri;
sahilmgandhi 18:6a4db94011d3 638
sahilmgandhi 18:6a4db94011d3 639 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
sahilmgandhi 18:6a4db94011d3 640 __IO uint32_t USBEpIntEn;
sahilmgandhi 18:6a4db94011d3 641 __O uint32_t USBEpIntClr;
sahilmgandhi 18:6a4db94011d3 642 __O uint32_t USBEpIntSet;
sahilmgandhi 18:6a4db94011d3 643 __O uint32_t USBEpIntPri;
sahilmgandhi 18:6a4db94011d3 644
sahilmgandhi 18:6a4db94011d3 645 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
sahilmgandhi 18:6a4db94011d3 646 __O uint32_t USBEpInd;
sahilmgandhi 18:6a4db94011d3 647 __IO uint32_t USBMaxPSize;
sahilmgandhi 18:6a4db94011d3 648
sahilmgandhi 18:6a4db94011d3 649 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
sahilmgandhi 18:6a4db94011d3 650 __O uint32_t USBDMARClr;
sahilmgandhi 18:6a4db94011d3 651 __O uint32_t USBDMARSet;
sahilmgandhi 18:6a4db94011d3 652 uint32_t RESERVED2[9];
sahilmgandhi 18:6a4db94011d3 653 __IO uint32_t USBUDCAH;
sahilmgandhi 18:6a4db94011d3 654 __I uint32_t USBEpDMASt;
sahilmgandhi 18:6a4db94011d3 655 __O uint32_t USBEpDMAEn;
sahilmgandhi 18:6a4db94011d3 656 __O uint32_t USBEpDMADis;
sahilmgandhi 18:6a4db94011d3 657 __I uint32_t USBDMAIntSt;
sahilmgandhi 18:6a4db94011d3 658 __IO uint32_t USBDMAIntEn;
sahilmgandhi 18:6a4db94011d3 659 uint32_t RESERVED3[2];
sahilmgandhi 18:6a4db94011d3 660 __I uint32_t USBEoTIntSt;
sahilmgandhi 18:6a4db94011d3 661 __O uint32_t USBEoTIntClr;
sahilmgandhi 18:6a4db94011d3 662 __O uint32_t USBEoTIntSet;
sahilmgandhi 18:6a4db94011d3 663 __I uint32_t USBNDDRIntSt;
sahilmgandhi 18:6a4db94011d3 664 __O uint32_t USBNDDRIntClr;
sahilmgandhi 18:6a4db94011d3 665 __O uint32_t USBNDDRIntSet;
sahilmgandhi 18:6a4db94011d3 666 __I uint32_t USBSysErrIntSt;
sahilmgandhi 18:6a4db94011d3 667 __O uint32_t USBSysErrIntClr;
sahilmgandhi 18:6a4db94011d3 668 __O uint32_t USBSysErrIntSet;
sahilmgandhi 18:6a4db94011d3 669 uint32_t RESERVED4[15];
sahilmgandhi 18:6a4db94011d3 670
sahilmgandhi 18:6a4db94011d3 671 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
sahilmgandhi 18:6a4db94011d3 672 __O uint32_t I2C_WO;
sahilmgandhi 18:6a4db94011d3 673 __I uint32_t I2C_STS;
sahilmgandhi 18:6a4db94011d3 674 __IO uint32_t I2C_CTL;
sahilmgandhi 18:6a4db94011d3 675 __IO uint32_t I2C_CLKHI;
sahilmgandhi 18:6a4db94011d3 676 __O uint32_t I2C_CLKLO;
sahilmgandhi 18:6a4db94011d3 677 uint32_t RESERVED5[823];
sahilmgandhi 18:6a4db94011d3 678
sahilmgandhi 18:6a4db94011d3 679 union {
sahilmgandhi 18:6a4db94011d3 680 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
sahilmgandhi 18:6a4db94011d3 681 __IO uint32_t OTGClkCtrl;
sahilmgandhi 18:6a4db94011d3 682 };
sahilmgandhi 18:6a4db94011d3 683 union {
sahilmgandhi 18:6a4db94011d3 684 __I uint32_t USBClkSt;
sahilmgandhi 18:6a4db94011d3 685 __I uint32_t OTGClkSt;
sahilmgandhi 18:6a4db94011d3 686 };
sahilmgandhi 18:6a4db94011d3 687 } LPC_USB_TypeDef;
sahilmgandhi 18:6a4db94011d3 688
sahilmgandhi 18:6a4db94011d3 689 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
sahilmgandhi 18:6a4db94011d3 690 typedef struct
sahilmgandhi 18:6a4db94011d3 691 {
sahilmgandhi 18:6a4db94011d3 692 __IO uint32_t MAC1; /* MAC Registers */
sahilmgandhi 18:6a4db94011d3 693 __IO uint32_t MAC2;
sahilmgandhi 18:6a4db94011d3 694 __IO uint32_t IPGT;
sahilmgandhi 18:6a4db94011d3 695 __IO uint32_t IPGR;
sahilmgandhi 18:6a4db94011d3 696 __IO uint32_t CLRT;
sahilmgandhi 18:6a4db94011d3 697 __IO uint32_t MAXF;
sahilmgandhi 18:6a4db94011d3 698 __IO uint32_t SUPP;
sahilmgandhi 18:6a4db94011d3 699 __IO uint32_t TEST;
sahilmgandhi 18:6a4db94011d3 700 __IO uint32_t MCFG;
sahilmgandhi 18:6a4db94011d3 701 __IO uint32_t MCMD;
sahilmgandhi 18:6a4db94011d3 702 __IO uint32_t MADR;
sahilmgandhi 18:6a4db94011d3 703 __O uint32_t MWTD;
sahilmgandhi 18:6a4db94011d3 704 __I uint32_t MRDD;
sahilmgandhi 18:6a4db94011d3 705 __I uint32_t MIND;
sahilmgandhi 18:6a4db94011d3 706 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 707 __IO uint32_t SA0;
sahilmgandhi 18:6a4db94011d3 708 __IO uint32_t SA1;
sahilmgandhi 18:6a4db94011d3 709 __IO uint32_t SA2;
sahilmgandhi 18:6a4db94011d3 710 uint32_t RESERVED1[45];
sahilmgandhi 18:6a4db94011d3 711 __IO uint32_t Command; /* Control Registers */
sahilmgandhi 18:6a4db94011d3 712 __I uint32_t Status;
sahilmgandhi 18:6a4db94011d3 713 __IO uint32_t RxDescriptor;
sahilmgandhi 18:6a4db94011d3 714 __IO uint32_t RxStatus;
sahilmgandhi 18:6a4db94011d3 715 __IO uint32_t RxDescriptorNumber;
sahilmgandhi 18:6a4db94011d3 716 __I uint32_t RxProduceIndex;
sahilmgandhi 18:6a4db94011d3 717 __IO uint32_t RxConsumeIndex;
sahilmgandhi 18:6a4db94011d3 718 __IO uint32_t TxDescriptor;
sahilmgandhi 18:6a4db94011d3 719 __IO uint32_t TxStatus;
sahilmgandhi 18:6a4db94011d3 720 __IO uint32_t TxDescriptorNumber;
sahilmgandhi 18:6a4db94011d3 721 __IO uint32_t TxProduceIndex;
sahilmgandhi 18:6a4db94011d3 722 __I uint32_t TxConsumeIndex;
sahilmgandhi 18:6a4db94011d3 723 uint32_t RESERVED2[10];
sahilmgandhi 18:6a4db94011d3 724 __I uint32_t TSV0;
sahilmgandhi 18:6a4db94011d3 725 __I uint32_t TSV1;
sahilmgandhi 18:6a4db94011d3 726 __I uint32_t RSV;
sahilmgandhi 18:6a4db94011d3 727 uint32_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 728 __IO uint32_t FlowControlCounter;
sahilmgandhi 18:6a4db94011d3 729 __I uint32_t FlowControlStatus;
sahilmgandhi 18:6a4db94011d3 730 uint32_t RESERVED4[34];
sahilmgandhi 18:6a4db94011d3 731 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
sahilmgandhi 18:6a4db94011d3 732 __IO uint32_t RxFilterWoLStatus;
sahilmgandhi 18:6a4db94011d3 733 __IO uint32_t RxFilterWoLClear;
sahilmgandhi 18:6a4db94011d3 734 uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 735 __IO uint32_t HashFilterL;
sahilmgandhi 18:6a4db94011d3 736 __IO uint32_t HashFilterH;
sahilmgandhi 18:6a4db94011d3 737 uint32_t RESERVED6[882];
sahilmgandhi 18:6a4db94011d3 738 __I uint32_t IntStatus; /* Module Control Registers */
sahilmgandhi 18:6a4db94011d3 739 __IO uint32_t IntEnable;
sahilmgandhi 18:6a4db94011d3 740 __O uint32_t IntClear;
sahilmgandhi 18:6a4db94011d3 741 __O uint32_t IntSet;
sahilmgandhi 18:6a4db94011d3 742 uint32_t RESERVED7;
sahilmgandhi 18:6a4db94011d3 743 __IO uint32_t PowerDown;
sahilmgandhi 18:6a4db94011d3 744 uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 745 __IO uint32_t Module_ID;
sahilmgandhi 18:6a4db94011d3 746 } LPC_EMAC_TypeDef;
sahilmgandhi 18:6a4db94011d3 747
sahilmgandhi 18:6a4db94011d3 748 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 749 #pragma no_anon_unions
sahilmgandhi 18:6a4db94011d3 750 #endif
sahilmgandhi 18:6a4db94011d3 751
sahilmgandhi 18:6a4db94011d3 752 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 753 /* Peripheral memory map */
sahilmgandhi 18:6a4db94011d3 754 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 755 /* Base addresses */
sahilmgandhi 18:6a4db94011d3 756
sahilmgandhi 18:6a4db94011d3 757 /* AHB Peripheral # 0 */
sahilmgandhi 18:6a4db94011d3 758
sahilmgandhi 18:6a4db94011d3 759 /*
sahilmgandhi 18:6a4db94011d3 760 #define FLASH_BASE (0x00000000UL)
sahilmgandhi 18:6a4db94011d3 761 #define RAM_BASE (0x10000000UL)
sahilmgandhi 18:6a4db94011d3 762 #define GPIO_BASE (0x2009C000UL)
sahilmgandhi 18:6a4db94011d3 763 #define APB0_BASE (0x40000000UL)
sahilmgandhi 18:6a4db94011d3 764 #define APB1_BASE (0x40080000UL)
sahilmgandhi 18:6a4db94011d3 765 #define AHB_BASE (0x50000000UL)
sahilmgandhi 18:6a4db94011d3 766 #define CM3_BASE (0xE0000000UL)
sahilmgandhi 18:6a4db94011d3 767 */
sahilmgandhi 18:6a4db94011d3 768
sahilmgandhi 18:6a4db94011d3 769 // TODO - #define VIC_BASE_ADDR 0xFFFFF000
sahilmgandhi 18:6a4db94011d3 770
sahilmgandhi 18:6a4db94011d3 771 #define LPC_WDT_BASE (0xE0000000)
sahilmgandhi 18:6a4db94011d3 772 #define LPC_TIM0_BASE (0xE0004000)
sahilmgandhi 18:6a4db94011d3 773 #define LPC_TIM1_BASE (0xE0008000)
sahilmgandhi 18:6a4db94011d3 774 #define LPC_UART0_BASE (0xE000C000)
sahilmgandhi 18:6a4db94011d3 775 #define LPC_UART1_BASE (0xE0010000)
sahilmgandhi 18:6a4db94011d3 776 #define LPC_PWM1_BASE (0xE0018000)
sahilmgandhi 18:6a4db94011d3 777 #define LPC_I2C0_BASE (0xE001C000)
sahilmgandhi 18:6a4db94011d3 778 #define LPC_SPI_BASE (0xE0020000)
sahilmgandhi 18:6a4db94011d3 779 #define LPC_RTC_BASE (0xE0024000)
sahilmgandhi 18:6a4db94011d3 780 #define LPC_GPIOINT_BASE (0xE0028080)
sahilmgandhi 18:6a4db94011d3 781 #define LPC_PINCON_BASE (0xE002C000)
sahilmgandhi 18:6a4db94011d3 782 #define LPC_SSP1_BASE (0xE0030000)
sahilmgandhi 18:6a4db94011d3 783 #define LPC_ADC_BASE (0xE0034000)
sahilmgandhi 18:6a4db94011d3 784 #define LPC_CANAF_RAM_BASE (0xE0038000)
sahilmgandhi 18:6a4db94011d3 785 #define LPC_CANAF_BASE (0xE003C000)
sahilmgandhi 18:6a4db94011d3 786 #define LPC_CANCR_BASE (0xE0040000)
sahilmgandhi 18:6a4db94011d3 787 #define LPC_CAN1_BASE (0xE0044000)
sahilmgandhi 18:6a4db94011d3 788 #define LPC_CAN2_BASE (0xE0048000)
sahilmgandhi 18:6a4db94011d3 789 #define LPC_I2C1_BASE (0xE005C000)
sahilmgandhi 18:6a4db94011d3 790 #define LPC_SSP0_BASE (0xE0068000)
sahilmgandhi 18:6a4db94011d3 791 #define LPC_DAC_BASE (0xE006C000)
sahilmgandhi 18:6a4db94011d3 792 #define LPC_TIM2_BASE (0xE0070000)
sahilmgandhi 18:6a4db94011d3 793 #define LPC_TIM3_BASE (0xE0074000)
sahilmgandhi 18:6a4db94011d3 794 #define LPC_UART2_BASE (0xE0078000)
sahilmgandhi 18:6a4db94011d3 795 #define LPC_UART3_BASE (0xE007C000)
sahilmgandhi 18:6a4db94011d3 796 #define LPC_I2C2_BASE (0xE0080000)
sahilmgandhi 18:6a4db94011d3 797 #define LPC_I2S_BASE (0xE0088000)
sahilmgandhi 18:6a4db94011d3 798 #define LPC_MCI_BASE (0xE008C000)
sahilmgandhi 18:6a4db94011d3 799 #define LPC_SC_BASE (0xE01FC000)
sahilmgandhi 18:6a4db94011d3 800 #define LPC_EMAC_BASE (0xFFE00000)
sahilmgandhi 18:6a4db94011d3 801 #define LPC_GPDMA_BASE (0xFFE04000)
sahilmgandhi 18:6a4db94011d3 802 #define LPC_GPDMACH0_BASE (0xFFE04100)
sahilmgandhi 18:6a4db94011d3 803 #define LPC_GPDMACH1_BASE (0xFFE04120)
sahilmgandhi 18:6a4db94011d3 804 #define LPC_USB_BASE (0xFFE0C000)
sahilmgandhi 18:6a4db94011d3 805 #define LPC_VIC_BASE (0xFFFFF000)
sahilmgandhi 18:6a4db94011d3 806
sahilmgandhi 18:6a4db94011d3 807 /* GPIOs */
sahilmgandhi 18:6a4db94011d3 808 #define LPC_GPIO0_BASE (0x3FFFC000)
sahilmgandhi 18:6a4db94011d3 809 #define LPC_GPIO1_BASE (0x3FFFC020)
sahilmgandhi 18:6a4db94011d3 810 #define LPC_GPIO2_BASE (0x3FFFC040)
sahilmgandhi 18:6a4db94011d3 811 #define LPC_GPIO3_BASE (0x3FFFC060)
sahilmgandhi 18:6a4db94011d3 812 #define LPC_GPIO4_BASE (0x3FFFC080)
sahilmgandhi 18:6a4db94011d3 813
sahilmgandhi 18:6a4db94011d3 814
sahilmgandhi 18:6a4db94011d3 815 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 816 /* Peripheral declaration */
sahilmgandhi 18:6a4db94011d3 817 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 818 #define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
sahilmgandhi 18:6a4db94011d3 819 #define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
sahilmgandhi 18:6a4db94011d3 820 #define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
sahilmgandhi 18:6a4db94011d3 821 #define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
sahilmgandhi 18:6a4db94011d3 822 #define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
sahilmgandhi 18:6a4db94011d3 823 #define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
sahilmgandhi 18:6a4db94011d3 824 #define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
sahilmgandhi 18:6a4db94011d3 825 #define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
sahilmgandhi 18:6a4db94011d3 826 #define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
sahilmgandhi 18:6a4db94011d3 827 #define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
sahilmgandhi 18:6a4db94011d3 828 #define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
sahilmgandhi 18:6a4db94011d3 829 #define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
sahilmgandhi 18:6a4db94011d3 830 #define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
sahilmgandhi 18:6a4db94011d3 831 #define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
sahilmgandhi 18:6a4db94011d3 832 #define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
sahilmgandhi 18:6a4db94011d3 833 #define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
sahilmgandhi 18:6a4db94011d3 834 #define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
sahilmgandhi 18:6a4db94011d3 835 #define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 836 #define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
sahilmgandhi 18:6a4db94011d3 837 #define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
sahilmgandhi 18:6a4db94011d3 838 #define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
sahilmgandhi 18:6a4db94011d3 839 #define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
sahilmgandhi 18:6a4db94011d3 840 #define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
sahilmgandhi 18:6a4db94011d3 841 #define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
sahilmgandhi 18:6a4db94011d3 842 #define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
sahilmgandhi 18:6a4db94011d3 843 #define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
sahilmgandhi 18:6a4db94011d3 844 #define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
sahilmgandhi 18:6a4db94011d3 845 #define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
sahilmgandhi 18:6a4db94011d3 846 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
sahilmgandhi 18:6a4db94011d3 847 #define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
sahilmgandhi 18:6a4db94011d3 848 #define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
sahilmgandhi 18:6a4db94011d3 849 #define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
sahilmgandhi 18:6a4db94011d3 850 #define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
sahilmgandhi 18:6a4db94011d3 851 #define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
sahilmgandhi 18:6a4db94011d3 852 #define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
sahilmgandhi 18:6a4db94011d3 853 #define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
sahilmgandhi 18:6a4db94011d3 854 #define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
sahilmgandhi 18:6a4db94011d3 855 #define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
sahilmgandhi 18:6a4db94011d3 856 #define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
sahilmgandhi 18:6a4db94011d3 857 #define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
sahilmgandhi 18:6a4db94011d3 858
sahilmgandhi 18:6a4db94011d3 859 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 860 }
sahilmgandhi 18:6a4db94011d3 861 #endif
sahilmgandhi 18:6a4db94011d3 862
sahilmgandhi 18:6a4db94011d3 863 #endif // __LPC23xx_H
sahilmgandhi 18:6a4db94011d3 864