MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC176X/device/system_LPC17xx.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file system_LPC17xx.c
sahilmgandhi 18:6a4db94011d3 3 * @brief CMSIS Cortex-M3 Device System Source File for
sahilmgandhi 18:6a4db94011d3 4 * NXP LPC17xx Device Series
sahilmgandhi 18:6a4db94011d3 5 * @version V1.11
sahilmgandhi 18:6a4db94011d3 6 * @date 21. June 2011
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * @par
sahilmgandhi 18:6a4db94011d3 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
sahilmgandhi 18:6a4db94011d3 13 * processor based microcontrollers. This file can be freely distributed
sahilmgandhi 18:6a4db94011d3 14 * within development tools that are supporting such ARM based processors.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * @par
sahilmgandhi 18:6a4db94011d3 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
sahilmgandhi 18:6a4db94011d3 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 22 *
sahilmgandhi 18:6a4db94011d3 23 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 27 #include "LPC17xx.h"
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 /** @addtogroup LPC17xx_System
sahilmgandhi 18:6a4db94011d3 31 * @{
sahilmgandhi 18:6a4db94011d3 32 */
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 /*
sahilmgandhi 18:6a4db94011d3 35 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /*--------------------- Clock Configuration ----------------------------------
sahilmgandhi 18:6a4db94011d3 39 //
sahilmgandhi 18:6a4db94011d3 40 // <e> Clock Configuration
sahilmgandhi 18:6a4db94011d3 41 // <h> System Controls and Status Register (SCS)
sahilmgandhi 18:6a4db94011d3 42 // <o1.4> OSCRANGE: Main Oscillator Range Select
sahilmgandhi 18:6a4db94011d3 43 // <0=> 1 MHz to 20 MHz
sahilmgandhi 18:6a4db94011d3 44 // <1=> 15 MHz to 25 MHz
sahilmgandhi 18:6a4db94011d3 45 // <e1.5> OSCEN: Main Oscillator Enable
sahilmgandhi 18:6a4db94011d3 46 // </e>
sahilmgandhi 18:6a4db94011d3 47 // </h>
sahilmgandhi 18:6a4db94011d3 48 //
sahilmgandhi 18:6a4db94011d3 49 // <h> Clock Source Select Register (CLKSRCSEL)
sahilmgandhi 18:6a4db94011d3 50 // <o2.0..1> CLKSRC: PLL Clock Source Selection
sahilmgandhi 18:6a4db94011d3 51 // <0=> Internal RC oscillator
sahilmgandhi 18:6a4db94011d3 52 // <1=> Main oscillator
sahilmgandhi 18:6a4db94011d3 53 // <2=> RTC oscillator
sahilmgandhi 18:6a4db94011d3 54 // </h>
sahilmgandhi 18:6a4db94011d3 55 //
sahilmgandhi 18:6a4db94011d3 56 // <e3> PLL0 Configuration (Main PLL)
sahilmgandhi 18:6a4db94011d3 57 // <h> PLL0 Configuration Register (PLL0CFG)
sahilmgandhi 18:6a4db94011d3 58 // <i> F_cco0 = (2 * M * F_in) / N
sahilmgandhi 18:6a4db94011d3 59 // <i> F_in must be in the range of 32 kHz to 50 MHz
sahilmgandhi 18:6a4db94011d3 60 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz
sahilmgandhi 18:6a4db94011d3 61 // <o4.0..14> MSEL: PLL Multiplier Selection
sahilmgandhi 18:6a4db94011d3 62 // <6-32768><#-1>
sahilmgandhi 18:6a4db94011d3 63 // <i> M Value
sahilmgandhi 18:6a4db94011d3 64 // <o4.16..23> NSEL: PLL Divider Selection
sahilmgandhi 18:6a4db94011d3 65 // <1-256><#-1>
sahilmgandhi 18:6a4db94011d3 66 // <i> N Value
sahilmgandhi 18:6a4db94011d3 67 // </h>
sahilmgandhi 18:6a4db94011d3 68 // </e>
sahilmgandhi 18:6a4db94011d3 69 //
sahilmgandhi 18:6a4db94011d3 70 // <e5> PLL1 Configuration (USB PLL)
sahilmgandhi 18:6a4db94011d3 71 // <h> PLL1 Configuration Register (PLL1CFG)
sahilmgandhi 18:6a4db94011d3 72 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
sahilmgandhi 18:6a4db94011d3 73 // <i> F_cco1 = F_osc * M * 2 * P
sahilmgandhi 18:6a4db94011d3 74 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz
sahilmgandhi 18:6a4db94011d3 75 // <o6.0..4> MSEL: PLL Multiplier Selection
sahilmgandhi 18:6a4db94011d3 76 // <1-32><#-1>
sahilmgandhi 18:6a4db94011d3 77 // <i> M Value (for USB maximum value is 4)
sahilmgandhi 18:6a4db94011d3 78 // <o6.5..6> PSEL: PLL Divider Selection
sahilmgandhi 18:6a4db94011d3 79 // <0=> 1
sahilmgandhi 18:6a4db94011d3 80 // <1=> 2
sahilmgandhi 18:6a4db94011d3 81 // <2=> 4
sahilmgandhi 18:6a4db94011d3 82 // <3=> 8
sahilmgandhi 18:6a4db94011d3 83 // <i> P Value
sahilmgandhi 18:6a4db94011d3 84 // </h>
sahilmgandhi 18:6a4db94011d3 85 // </e>
sahilmgandhi 18:6a4db94011d3 86 //
sahilmgandhi 18:6a4db94011d3 87 // <h> CPU Clock Configuration Register (CCLKCFG)
sahilmgandhi 18:6a4db94011d3 88 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
sahilmgandhi 18:6a4db94011d3 89 // <1-256><#-1>
sahilmgandhi 18:6a4db94011d3 90 // </h>
sahilmgandhi 18:6a4db94011d3 91 //
sahilmgandhi 18:6a4db94011d3 92 // <h> USB Clock Configuration Register (USBCLKCFG)
sahilmgandhi 18:6a4db94011d3 93 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
sahilmgandhi 18:6a4db94011d3 94 // <0-15>
sahilmgandhi 18:6a4db94011d3 95 // <i> Divide is USBSEL + 1
sahilmgandhi 18:6a4db94011d3 96 // </h>
sahilmgandhi 18:6a4db94011d3 97 //
sahilmgandhi 18:6a4db94011d3 98 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
sahilmgandhi 18:6a4db94011d3 99 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
sahilmgandhi 18:6a4db94011d3 100 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 101 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 102 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 103 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 104 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
sahilmgandhi 18:6a4db94011d3 105 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 106 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 107 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 108 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 109 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
sahilmgandhi 18:6a4db94011d3 110 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 111 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 112 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 113 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 114 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
sahilmgandhi 18:6a4db94011d3 115 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 116 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 117 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 118 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 119 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
sahilmgandhi 18:6a4db94011d3 120 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 121 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 122 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 123 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 124 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
sahilmgandhi 18:6a4db94011d3 125 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 126 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 127 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 128 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 129 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
sahilmgandhi 18:6a4db94011d3 130 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 131 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 132 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 133 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 134 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
sahilmgandhi 18:6a4db94011d3 135 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 136 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 137 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 138 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 139 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
sahilmgandhi 18:6a4db94011d3 140 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 141 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 142 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 143 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 144 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
sahilmgandhi 18:6a4db94011d3 145 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 146 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 147 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 148 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 149 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
sahilmgandhi 18:6a4db94011d3 150 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 151 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 152 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 153 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 154 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
sahilmgandhi 18:6a4db94011d3 155 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 156 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 157 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 158 // <3=> Pclk = Hclk / 6
sahilmgandhi 18:6a4db94011d3 159 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
sahilmgandhi 18:6a4db94011d3 160 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 161 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 162 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 163 // <3=> Pclk = Hclk / 6
sahilmgandhi 18:6a4db94011d3 164 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
sahilmgandhi 18:6a4db94011d3 165 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 166 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 167 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 168 // <3=> Pclk = Hclk / 6
sahilmgandhi 18:6a4db94011d3 169 // </h>
sahilmgandhi 18:6a4db94011d3 170 //
sahilmgandhi 18:6a4db94011d3 171 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
sahilmgandhi 18:6a4db94011d3 172 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
sahilmgandhi 18:6a4db94011d3 173 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 174 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 175 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 176 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 177 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
sahilmgandhi 18:6a4db94011d3 178 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 179 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 180 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 181 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 182 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
sahilmgandhi 18:6a4db94011d3 183 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 184 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 185 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 186 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 187 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
sahilmgandhi 18:6a4db94011d3 188 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 189 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 190 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 191 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 192 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
sahilmgandhi 18:6a4db94011d3 193 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 194 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 195 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 196 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 197 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
sahilmgandhi 18:6a4db94011d3 198 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 199 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 200 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 201 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 202 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
sahilmgandhi 18:6a4db94011d3 203 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 204 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 205 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 206 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 207 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
sahilmgandhi 18:6a4db94011d3 208 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 209 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 210 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 211 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 212 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
sahilmgandhi 18:6a4db94011d3 213 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 214 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 215 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 216 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 217 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
sahilmgandhi 18:6a4db94011d3 218 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 219 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 220 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 221 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 222 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
sahilmgandhi 18:6a4db94011d3 223 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 224 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 225 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 226 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 227 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
sahilmgandhi 18:6a4db94011d3 228 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 229 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 230 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 231 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 232 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
sahilmgandhi 18:6a4db94011d3 233 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 234 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 235 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 236 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 237 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
sahilmgandhi 18:6a4db94011d3 238 // <0=> Pclk = Cclk / 4
sahilmgandhi 18:6a4db94011d3 239 // <1=> Pclk = Cclk
sahilmgandhi 18:6a4db94011d3 240 // <2=> Pclk = Cclk / 2
sahilmgandhi 18:6a4db94011d3 241 // <3=> Pclk = Hclk / 8
sahilmgandhi 18:6a4db94011d3 242 // </h>
sahilmgandhi 18:6a4db94011d3 243 //
sahilmgandhi 18:6a4db94011d3 244 // <h> Power Control for Peripherals Register (PCONP)
sahilmgandhi 18:6a4db94011d3 245 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
sahilmgandhi 18:6a4db94011d3 246 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
sahilmgandhi 18:6a4db94011d3 247 // <o11.3> PCUART0: UART 0 power/clock enable
sahilmgandhi 18:6a4db94011d3 248 // <o11.4> PCUART1: UART 1 power/clock enable
sahilmgandhi 18:6a4db94011d3 249 // <o11.6> PCPWM1: PWM 1 power/clock enable
sahilmgandhi 18:6a4db94011d3 250 // <o11.7> PCI2C0: I2C interface 0 power/clock enable
sahilmgandhi 18:6a4db94011d3 251 // <o11.8> PCSPI: SPI interface power/clock enable
sahilmgandhi 18:6a4db94011d3 252 // <o11.9> PCRTC: RTC power/clock enable
sahilmgandhi 18:6a4db94011d3 253 // <o11.10> PCSSP1: SSP interface 1 power/clock enable
sahilmgandhi 18:6a4db94011d3 254 // <o11.12> PCAD: A/D converter power/clock enable
sahilmgandhi 18:6a4db94011d3 255 // <o11.13> PCCAN1: CAN controller 1 power/clock enable
sahilmgandhi 18:6a4db94011d3 256 // <o11.14> PCCAN2: CAN controller 2 power/clock enable
sahilmgandhi 18:6a4db94011d3 257 // <o11.15> PCGPIO: GPIOs power/clock enable
sahilmgandhi 18:6a4db94011d3 258 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
sahilmgandhi 18:6a4db94011d3 259 // <o11.17> PCMC: Motor control PWM power/clock enable
sahilmgandhi 18:6a4db94011d3 260 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable
sahilmgandhi 18:6a4db94011d3 261 // <o11.19> PCI2C1: I2C interface 1 power/clock enable
sahilmgandhi 18:6a4db94011d3 262 // <o11.21> PCSSP0: SSP interface 0 power/clock enable
sahilmgandhi 18:6a4db94011d3 263 // <o11.22> PCTIM2: Timer 2 power/clock enable
sahilmgandhi 18:6a4db94011d3 264 // <o11.23> PCTIM3: Timer 3 power/clock enable
sahilmgandhi 18:6a4db94011d3 265 // <o11.24> PCUART2: UART 2 power/clock enable
sahilmgandhi 18:6a4db94011d3 266 // <o11.25> PCUART3: UART 3 power/clock enable
sahilmgandhi 18:6a4db94011d3 267 // <o11.26> PCI2C2: I2C interface 2 power/clock enable
sahilmgandhi 18:6a4db94011d3 268 // <o11.27> PCI2S: I2S interface power/clock enable
sahilmgandhi 18:6a4db94011d3 269 // <o11.29> PCGPDMA: GP DMA function power/clock enable
sahilmgandhi 18:6a4db94011d3 270 // <o11.30> PCENET: Ethernet block power/clock enable
sahilmgandhi 18:6a4db94011d3 271 // <o11.31> PCUSB: USB interface power/clock enable
sahilmgandhi 18:6a4db94011d3 272 // </h>
sahilmgandhi 18:6a4db94011d3 273 //
sahilmgandhi 18:6a4db94011d3 274 // <h> Clock Output Configuration Register (CLKOUTCFG)
sahilmgandhi 18:6a4db94011d3 275 // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
sahilmgandhi 18:6a4db94011d3 276 // <0=> CPU clock
sahilmgandhi 18:6a4db94011d3 277 // <1=> Main oscillator
sahilmgandhi 18:6a4db94011d3 278 // <2=> Internal RC oscillator
sahilmgandhi 18:6a4db94011d3 279 // <3=> USB clock
sahilmgandhi 18:6a4db94011d3 280 // <4=> RTC oscillator
sahilmgandhi 18:6a4db94011d3 281 // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
sahilmgandhi 18:6a4db94011d3 282 // <1-16><#-1>
sahilmgandhi 18:6a4db94011d3 283 // <o12.8> CLKOUT_EN: CLKOUT enable control
sahilmgandhi 18:6a4db94011d3 284 // </h>
sahilmgandhi 18:6a4db94011d3 285 //
sahilmgandhi 18:6a4db94011d3 286 // </e>
sahilmgandhi 18:6a4db94011d3 287 */
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 /** @addtogroup LPC17xx_System_Defines LPC17xx System Defines
sahilmgandhi 18:6a4db94011d3 292 @{
sahilmgandhi 18:6a4db94011d3 293 */
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 #define CLOCK_SETUP 1
sahilmgandhi 18:6a4db94011d3 296 #define SCS_Val 0x00000020
sahilmgandhi 18:6a4db94011d3 297 #define CLKSRCSEL_Val 0x00000001
sahilmgandhi 18:6a4db94011d3 298 #define PLL0_SETUP 1
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 #ifdef MCB1700
sahilmgandhi 18:6a4db94011d3 301 # define PLL0CFG_Val 0x00050063
sahilmgandhi 18:6a4db94011d3 302 # define PLL1_SETUP 1
sahilmgandhi 18:6a4db94011d3 303 # define PLL1CFG_Val 0x00000023
sahilmgandhi 18:6a4db94011d3 304 # define CCLKCFG_Val 0x00000003
sahilmgandhi 18:6a4db94011d3 305 # define USBCLKCFG_Val 0x00000000
sahilmgandhi 18:6a4db94011d3 306 #else
sahilmgandhi 18:6a4db94011d3 307 # define PLL0CFG_Val 0x0000000B
sahilmgandhi 18:6a4db94011d3 308 # define PLL1_SETUP 0
sahilmgandhi 18:6a4db94011d3 309 # define PLL1CFG_Val 0x00000000
sahilmgandhi 18:6a4db94011d3 310 # define CCLKCFG_Val 0x00000002
sahilmgandhi 18:6a4db94011d3 311 # define USBCLKCFG_Val 0x00000005
sahilmgandhi 18:6a4db94011d3 312 #endif
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 #define PCLKSEL0_Val 0x00000000
sahilmgandhi 18:6a4db94011d3 315 #define PCLKSEL1_Val 0x00000000
sahilmgandhi 18:6a4db94011d3 316 #define PCONP_Val 0x042887DE
sahilmgandhi 18:6a4db94011d3 317 #define CLKOUTCFG_Val 0x00000000
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 /*--------------------- Flash Accelerator Configuration ----------------------
sahilmgandhi 18:6a4db94011d3 321 //
sahilmgandhi 18:6a4db94011d3 322 // <e> Flash Accelerator Configuration
sahilmgandhi 18:6a4db94011d3 323 // <o1.12..15> FLASHTIM: Flash Access Time
sahilmgandhi 18:6a4db94011d3 324 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
sahilmgandhi 18:6a4db94011d3 325 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
sahilmgandhi 18:6a4db94011d3 326 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
sahilmgandhi 18:6a4db94011d3 327 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
sahilmgandhi 18:6a4db94011d3 328 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
sahilmgandhi 18:6a4db94011d3 329 // <5=> 6 CPU clocks (for any CPU clock)
sahilmgandhi 18:6a4db94011d3 330 // </e>
sahilmgandhi 18:6a4db94011d3 331 */
sahilmgandhi 18:6a4db94011d3 332 #define FLASH_SETUP 1
sahilmgandhi 18:6a4db94011d3 333 #define FLASHCFG_Val 0x0000303A
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 /*
sahilmgandhi 18:6a4db94011d3 336 //-------- <<< end of configuration section >>> ------------------------------
sahilmgandhi 18:6a4db94011d3 337 */
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 340 Check the register settings
sahilmgandhi 18:6a4db94011d3 341 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 342 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
sahilmgandhi 18:6a4db94011d3 343 #define CHECK_RSVD(val, mask) (val & mask)
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 /* Clock Configuration -------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 346 #if (CHECK_RSVD((SCS_Val), ~0x00000030))
sahilmgandhi 18:6a4db94011d3 347 #error "SCS: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 348 #endif
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
sahilmgandhi 18:6a4db94011d3 351 #error "CLKSRCSEL: Value out of range!"
sahilmgandhi 18:6a4db94011d3 352 #endif
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
sahilmgandhi 18:6a4db94011d3 355 #error "PLL0CFG: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 356 #endif
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
sahilmgandhi 18:6a4db94011d3 359 #error "PLL1CFG: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 360 #endif
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 #if (PLL0_SETUP) /* if PLL0 is used */
sahilmgandhi 18:6a4db94011d3 363 #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */
sahilmgandhi 18:6a4db94011d3 364 #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
sahilmgandhi 18:6a4db94011d3 365 #endif
sahilmgandhi 18:6a4db94011d3 366 #endif
sahilmgandhi 18:6a4db94011d3 367
sahilmgandhi 18:6a4db94011d3 368 #if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
sahilmgandhi 18:6a4db94011d3 369 #error "CCLKCFG: Value out of range!"
sahilmgandhi 18:6a4db94011d3 370 #endif
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
sahilmgandhi 18:6a4db94011d3 373 #error "USBCLKCFG: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 374 #endif
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
sahilmgandhi 18:6a4db94011d3 377 #error "PCLKSEL0: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 378 #endif
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
sahilmgandhi 18:6a4db94011d3 381 #error "PCLKSEL1: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 382 #endif
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 #if (CHECK_RSVD((PCONP_Val), 0x10100821))
sahilmgandhi 18:6a4db94011d3 385 #error "PCONP: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 386 #endif
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
sahilmgandhi 18:6a4db94011d3 389 #error "CLKOUTCFG: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 390 #endif
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 /* Flash Accelerator Configuration -------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 393 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
sahilmgandhi 18:6a4db94011d3 394 #error "FLASHCFG: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 395 #endif
sahilmgandhi 18:6a4db94011d3 396
sahilmgandhi 18:6a4db94011d3 397
sahilmgandhi 18:6a4db94011d3 398 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 399 DEFINES
sahilmgandhi 18:6a4db94011d3 400 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 401
sahilmgandhi 18:6a4db94011d3 402 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 403 Define clocks
sahilmgandhi 18:6a4db94011d3 404 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 405 #define XTAL (12000000UL) /* Oscillator frequency */
sahilmgandhi 18:6a4db94011d3 406 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
sahilmgandhi 18:6a4db94011d3 407 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
sahilmgandhi 18:6a4db94011d3 408 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410
sahilmgandhi 18:6a4db94011d3 411 /* F_cco0 = (2 * M * F_in) / N */
sahilmgandhi 18:6a4db94011d3 412 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
sahilmgandhi 18:6a4db94011d3 413 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
sahilmgandhi 18:6a4db94011d3 414 #define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
sahilmgandhi 18:6a4db94011d3 415 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
sahilmgandhi 18:6a4db94011d3 416
sahilmgandhi 18:6a4db94011d3 417 /* Determine core clock frequency according to settings */
sahilmgandhi 18:6a4db94011d3 418 #if (PLL0_SETUP)
sahilmgandhi 18:6a4db94011d3 419 #if ((CLKSRCSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 420 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
sahilmgandhi 18:6a4db94011d3 421 #elif ((CLKSRCSEL_Val & 0x03) == 2)
sahilmgandhi 18:6a4db94011d3 422 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
sahilmgandhi 18:6a4db94011d3 423 #else
sahilmgandhi 18:6a4db94011d3 424 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
sahilmgandhi 18:6a4db94011d3 425 #endif
sahilmgandhi 18:6a4db94011d3 426 #else
sahilmgandhi 18:6a4db94011d3 427 #if ((CLKSRCSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 428 #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
sahilmgandhi 18:6a4db94011d3 429 #elif ((CLKSRCSEL_Val & 0x03) == 2)
sahilmgandhi 18:6a4db94011d3 430 #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
sahilmgandhi 18:6a4db94011d3 431 #else
sahilmgandhi 18:6a4db94011d3 432 #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
sahilmgandhi 18:6a4db94011d3 433 #endif
sahilmgandhi 18:6a4db94011d3 434 #endif
sahilmgandhi 18:6a4db94011d3 435
sahilmgandhi 18:6a4db94011d3 436 /**
sahilmgandhi 18:6a4db94011d3 437 * @}
sahilmgandhi 18:6a4db94011d3 438 */
sahilmgandhi 18:6a4db94011d3 439
sahilmgandhi 18:6a4db94011d3 440
sahilmgandhi 18:6a4db94011d3 441 /** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables
sahilmgandhi 18:6a4db94011d3 442 @{
sahilmgandhi 18:6a4db94011d3 443 */
sahilmgandhi 18:6a4db94011d3 444 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 445 Clock Variable definitions
sahilmgandhi 18:6a4db94011d3 446 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 447 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 /**
sahilmgandhi 18:6a4db94011d3 450 * @}
sahilmgandhi 18:6a4db94011d3 451 */
sahilmgandhi 18:6a4db94011d3 452
sahilmgandhi 18:6a4db94011d3 453
sahilmgandhi 18:6a4db94011d3 454 /** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions
sahilmgandhi 18:6a4db94011d3 455 @{
sahilmgandhi 18:6a4db94011d3 456 */
sahilmgandhi 18:6a4db94011d3 457
sahilmgandhi 18:6a4db94011d3 458 /**
sahilmgandhi 18:6a4db94011d3 459 * Update SystemCoreClock variable
sahilmgandhi 18:6a4db94011d3 460 *
sahilmgandhi 18:6a4db94011d3 461 * @param none
sahilmgandhi 18:6a4db94011d3 462 * @return none
sahilmgandhi 18:6a4db94011d3 463 *
sahilmgandhi 18:6a4db94011d3 464 * @brief Updates the SystemCoreClock with current core Clock
sahilmgandhi 18:6a4db94011d3 465 * retrieved from cpu registers.
sahilmgandhi 18:6a4db94011d3 466 */void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
sahilmgandhi 18:6a4db94011d3 467 {
sahilmgandhi 18:6a4db94011d3 468 /* Determine clock frequency according to clock register values */
sahilmgandhi 18:6a4db94011d3 469 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
sahilmgandhi 18:6a4db94011d3 470 switch (LPC_SC->CLKSRCSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 471 case 0: /* Int. RC oscillator => PLL0 */
sahilmgandhi 18:6a4db94011d3 472 case 3: /* Reserved, default to Int. RC */
sahilmgandhi 18:6a4db94011d3 473 SystemCoreClock = (IRC_OSC *
sahilmgandhi 18:6a4db94011d3 474 ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
sahilmgandhi 18:6a4db94011d3 475 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
sahilmgandhi 18:6a4db94011d3 476 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
sahilmgandhi 18:6a4db94011d3 477 break;
sahilmgandhi 18:6a4db94011d3 478 case 1: /* Main oscillator => PLL0 */
sahilmgandhi 18:6a4db94011d3 479 SystemCoreClock = (OSC_CLK *
sahilmgandhi 18:6a4db94011d3 480 ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
sahilmgandhi 18:6a4db94011d3 481 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
sahilmgandhi 18:6a4db94011d3 482 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
sahilmgandhi 18:6a4db94011d3 483 break;
sahilmgandhi 18:6a4db94011d3 484 case 2: /* RTC oscillator => PLL0 */
sahilmgandhi 18:6a4db94011d3 485 SystemCoreClock = (RTC_CLK *
sahilmgandhi 18:6a4db94011d3 486 ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
sahilmgandhi 18:6a4db94011d3 487 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
sahilmgandhi 18:6a4db94011d3 488 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
sahilmgandhi 18:6a4db94011d3 489 break;
sahilmgandhi 18:6a4db94011d3 490 }
sahilmgandhi 18:6a4db94011d3 491 } else {
sahilmgandhi 18:6a4db94011d3 492 switch (LPC_SC->CLKSRCSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 493 case 0: /* Int. RC oscillator => PLL0 */
sahilmgandhi 18:6a4db94011d3 494 case 3: /* Reserved, default to Int. RC */
sahilmgandhi 18:6a4db94011d3 495 SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
sahilmgandhi 18:6a4db94011d3 496 break;
sahilmgandhi 18:6a4db94011d3 497 case 1: /* Main oscillator => PLL0 */
sahilmgandhi 18:6a4db94011d3 498 SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
sahilmgandhi 18:6a4db94011d3 499 break;
sahilmgandhi 18:6a4db94011d3 500 case 2: /* RTC oscillator => PLL0 */
sahilmgandhi 18:6a4db94011d3 501 SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
sahilmgandhi 18:6a4db94011d3 502 break;
sahilmgandhi 18:6a4db94011d3 503 }
sahilmgandhi 18:6a4db94011d3 504 }
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 }
sahilmgandhi 18:6a4db94011d3 507
sahilmgandhi 18:6a4db94011d3 508 /**
sahilmgandhi 18:6a4db94011d3 509 * Initialize the system
sahilmgandhi 18:6a4db94011d3 510 *
sahilmgandhi 18:6a4db94011d3 511 * @param none
sahilmgandhi 18:6a4db94011d3 512 * @return none
sahilmgandhi 18:6a4db94011d3 513 *
sahilmgandhi 18:6a4db94011d3 514 * @brief Setup the microcontroller system.
sahilmgandhi 18:6a4db94011d3 515 * Initialize the System.
sahilmgandhi 18:6a4db94011d3 516 */
sahilmgandhi 18:6a4db94011d3 517 void SystemInit (void)
sahilmgandhi 18:6a4db94011d3 518 {
sahilmgandhi 18:6a4db94011d3 519 #if (CLOCK_SETUP) /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 520 LPC_SC->SCS = SCS_Val;
sahilmgandhi 18:6a4db94011d3 521 if (LPC_SC->SCS & (1 << 5)) { /* If Main Oscillator is enabled */
sahilmgandhi 18:6a4db94011d3 522 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
sahilmgandhi 18:6a4db94011d3 523 }
sahilmgandhi 18:6a4db94011d3 524
sahilmgandhi 18:6a4db94011d3 525 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
sahilmgandhi 18:6a4db94011d3 526 /* Periphral clock must be selected before PLL0 enabling and connecting
sahilmgandhi 18:6a4db94011d3 527 * - according errata.lpc1768-16.March.2010 -
sahilmgandhi 18:6a4db94011d3 528 */
sahilmgandhi 18:6a4db94011d3 529 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
sahilmgandhi 18:6a4db94011d3 530 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 #if (PLL0_SETUP)
sahilmgandhi 18:6a4db94011d3 533 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
sahilmgandhi 18:6a4db94011d3 534
sahilmgandhi 18:6a4db94011d3 535 LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
sahilmgandhi 18:6a4db94011d3 536 LPC_SC->PLL0FEED = 0xAA;
sahilmgandhi 18:6a4db94011d3 537 LPC_SC->PLL0FEED = 0x55;
sahilmgandhi 18:6a4db94011d3 538
sahilmgandhi 18:6a4db94011d3 539 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
sahilmgandhi 18:6a4db94011d3 540 LPC_SC->PLL0FEED = 0xAA;
sahilmgandhi 18:6a4db94011d3 541 LPC_SC->PLL0FEED = 0x55;
sahilmgandhi 18:6a4db94011d3 542 while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
sahilmgandhi 18:6a4db94011d3 543
sahilmgandhi 18:6a4db94011d3 544 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
sahilmgandhi 18:6a4db94011d3 545 LPC_SC->PLL0FEED = 0xAA;
sahilmgandhi 18:6a4db94011d3 546 LPC_SC->PLL0FEED = 0x55;
sahilmgandhi 18:6a4db94011d3 547 while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
sahilmgandhi 18:6a4db94011d3 548 #endif
sahilmgandhi 18:6a4db94011d3 549
sahilmgandhi 18:6a4db94011d3 550 #if (PLL1_SETUP)
sahilmgandhi 18:6a4db94011d3 551 LPC_SC->PLL1CFG = PLL1CFG_Val;
sahilmgandhi 18:6a4db94011d3 552 LPC_SC->PLL1FEED = 0xAA;
sahilmgandhi 18:6a4db94011d3 553 LPC_SC->PLL1FEED = 0x55;
sahilmgandhi 18:6a4db94011d3 554
sahilmgandhi 18:6a4db94011d3 555 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
sahilmgandhi 18:6a4db94011d3 556 LPC_SC->PLL1FEED = 0xAA;
sahilmgandhi 18:6a4db94011d3 557 LPC_SC->PLL1FEED = 0x55;
sahilmgandhi 18:6a4db94011d3 558 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
sahilmgandhi 18:6a4db94011d3 561 LPC_SC->PLL1FEED = 0xAA;
sahilmgandhi 18:6a4db94011d3 562 LPC_SC->PLL1FEED = 0x55;
sahilmgandhi 18:6a4db94011d3 563 while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
sahilmgandhi 18:6a4db94011d3 564 #else
sahilmgandhi 18:6a4db94011d3 565 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
sahilmgandhi 18:6a4db94011d3 566 #endif
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
sahilmgandhi 18:6a4db94011d3 571 #endif
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
sahilmgandhi 18:6a4db94011d3 574 LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
sahilmgandhi 18:6a4db94011d3 575 #endif
sahilmgandhi 18:6a4db94011d3 576 }
sahilmgandhi 18:6a4db94011d3 577
sahilmgandhi 18:6a4db94011d3 578 /**
sahilmgandhi 18:6a4db94011d3 579 * @}
sahilmgandhi 18:6a4db94011d3 580 */
sahilmgandhi 18:6a4db94011d3 581
sahilmgandhi 18:6a4db94011d3 582 /**
sahilmgandhi 18:6a4db94011d3 583 * @}
sahilmgandhi 18:6a4db94011d3 584 */