MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC176X/device/LPC17xx.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file LPC17xx.h
sahilmgandhi 18:6a4db94011d3 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
sahilmgandhi 18:6a4db94011d3 4 * NXP LPC17xx Device Series
sahilmgandhi 18:6a4db94011d3 5 * @version: V1.09
sahilmgandhi 18:6a4db94011d3 6 * @date: 17. March 2010
sahilmgandhi 18:6a4db94011d3 7
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * @note
sahilmgandhi 18:6a4db94011d3 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * @par
sahilmgandhi 18:6a4db94011d3 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
sahilmgandhi 18:6a4db94011d3 14 * processor based microcontrollers. This file can be freely distributed
sahilmgandhi 18:6a4db94011d3 15 * within development tools that are supporting such ARM based processors.
sahilmgandhi 18:6a4db94011d3 16 *
sahilmgandhi 18:6a4db94011d3 17 * @par
sahilmgandhi 18:6a4db94011d3 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
sahilmgandhi 18:6a4db94011d3 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 #ifndef __LPC17xx_H__
sahilmgandhi 18:6a4db94011d3 28 #define __LPC17xx_H__
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 /*
sahilmgandhi 18:6a4db94011d3 31 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 32 * ---------- Interrupt Number Definition -----------------------------------
sahilmgandhi 18:6a4db94011d3 33 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 34 */
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 typedef enum IRQn
sahilmgandhi 18:6a4db94011d3 37 {
sahilmgandhi 18:6a4db94011d3 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
sahilmgandhi 18:6a4db94011d3 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
sahilmgandhi 18:6a4db94011d3 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
sahilmgandhi 18:6a4db94011d3 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
sahilmgandhi 18:6a4db94011d3 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
sahilmgandhi 18:6a4db94011d3 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
sahilmgandhi 18:6a4db94011d3 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
sahilmgandhi 18:6a4db94011d3 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
sahilmgandhi 18:6a4db94011d3 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
sahilmgandhi 18:6a4db94011d3 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
sahilmgandhi 18:6a4db94011d3 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
sahilmgandhi 18:6a4db94011d3 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
sahilmgandhi 18:6a4db94011d3 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
sahilmgandhi 18:6a4db94011d3 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
sahilmgandhi 18:6a4db94011d3 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
sahilmgandhi 18:6a4db94011d3 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
sahilmgandhi 18:6a4db94011d3 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
sahilmgandhi 18:6a4db94011d3 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
sahilmgandhi 18:6a4db94011d3 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
sahilmgandhi 18:6a4db94011d3 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
sahilmgandhi 18:6a4db94011d3 62 SPI_IRQn = 13, /*!< SPI Interrupt */
sahilmgandhi 18:6a4db94011d3 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
sahilmgandhi 18:6a4db94011d3 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
sahilmgandhi 18:6a4db94011d3 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
sahilmgandhi 18:6a4db94011d3 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
sahilmgandhi 18:6a4db94011d3 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
sahilmgandhi 18:6a4db94011d3 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
sahilmgandhi 18:6a4db94011d3 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
sahilmgandhi 18:6a4db94011d3 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
sahilmgandhi 18:6a4db94011d3 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
sahilmgandhi 18:6a4db94011d3 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
sahilmgandhi 18:6a4db94011d3 73 USB_IRQn = 24, /*!< USB Interrupt */
sahilmgandhi 18:6a4db94011d3 74 CAN_IRQn = 25, /*!< CAN Interrupt */
sahilmgandhi 18:6a4db94011d3 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
sahilmgandhi 18:6a4db94011d3 76 I2S_IRQn = 27, /*!< I2S Interrupt */
sahilmgandhi 18:6a4db94011d3 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
sahilmgandhi 18:6a4db94011d3 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
sahilmgandhi 18:6a4db94011d3 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
sahilmgandhi 18:6a4db94011d3 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
sahilmgandhi 18:6a4db94011d3 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
sahilmgandhi 18:6a4db94011d3 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
sahilmgandhi 18:6a4db94011d3 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
sahilmgandhi 18:6a4db94011d3 84 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 /*
sahilmgandhi 18:6a4db94011d3 88 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 89 * ----------- Processor and Core Peripheral Section ------------------------
sahilmgandhi 18:6a4db94011d3 90 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 91 */
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
sahilmgandhi 18:6a4db94011d3 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
sahilmgandhi 18:6a4db94011d3 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 100 #include "system_LPC17xx.h" /* System Header */
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 104 /* Device Specific Peripheral registers structures */
sahilmgandhi 18:6a4db94011d3 105 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 108 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 109 #endif
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /*------------- System Control (SC) ------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 112 typedef struct
sahilmgandhi 18:6a4db94011d3 113 {
sahilmgandhi 18:6a4db94011d3 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
sahilmgandhi 18:6a4db94011d3 115 uint32_t RESERVED0[31];
sahilmgandhi 18:6a4db94011d3 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
sahilmgandhi 18:6a4db94011d3 117 __IO uint32_t PLL0CFG;
sahilmgandhi 18:6a4db94011d3 118 __I uint32_t PLL0STAT;
sahilmgandhi 18:6a4db94011d3 119 __O uint32_t PLL0FEED;
sahilmgandhi 18:6a4db94011d3 120 uint32_t RESERVED1[4];
sahilmgandhi 18:6a4db94011d3 121 __IO uint32_t PLL1CON;
sahilmgandhi 18:6a4db94011d3 122 __IO uint32_t PLL1CFG;
sahilmgandhi 18:6a4db94011d3 123 __I uint32_t PLL1STAT;
sahilmgandhi 18:6a4db94011d3 124 __O uint32_t PLL1FEED;
sahilmgandhi 18:6a4db94011d3 125 uint32_t RESERVED2[4];
sahilmgandhi 18:6a4db94011d3 126 __IO uint32_t PCON;
sahilmgandhi 18:6a4db94011d3 127 __IO uint32_t PCONP;
sahilmgandhi 18:6a4db94011d3 128 uint32_t RESERVED3[15];
sahilmgandhi 18:6a4db94011d3 129 __IO uint32_t CCLKCFG;
sahilmgandhi 18:6a4db94011d3 130 __IO uint32_t USBCLKCFG;
sahilmgandhi 18:6a4db94011d3 131 __IO uint32_t CLKSRCSEL;
sahilmgandhi 18:6a4db94011d3 132 __IO uint32_t CANSLEEPCLR;
sahilmgandhi 18:6a4db94011d3 133 __IO uint32_t CANWAKEFLAGS;
sahilmgandhi 18:6a4db94011d3 134 uint32_t RESERVED4[10];
sahilmgandhi 18:6a4db94011d3 135 __IO uint32_t EXTINT; /* External Interrupts */
sahilmgandhi 18:6a4db94011d3 136 uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 137 __IO uint32_t EXTMODE;
sahilmgandhi 18:6a4db94011d3 138 __IO uint32_t EXTPOLAR;
sahilmgandhi 18:6a4db94011d3 139 uint32_t RESERVED6[12];
sahilmgandhi 18:6a4db94011d3 140 __IO uint32_t RSID; /* Reset */
sahilmgandhi 18:6a4db94011d3 141 uint32_t RESERVED7[7];
sahilmgandhi 18:6a4db94011d3 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
sahilmgandhi 18:6a4db94011d3 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
sahilmgandhi 18:6a4db94011d3 144 __IO uint32_t PCLKSEL0;
sahilmgandhi 18:6a4db94011d3 145 __IO uint32_t PCLKSEL1;
sahilmgandhi 18:6a4db94011d3 146 uint32_t RESERVED8[4];
sahilmgandhi 18:6a4db94011d3 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
sahilmgandhi 18:6a4db94011d3 148 __IO uint32_t DMAREQSEL;
sahilmgandhi 18:6a4db94011d3 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
sahilmgandhi 18:6a4db94011d3 150 } LPC_SC_TypeDef;
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
sahilmgandhi 18:6a4db94011d3 153 typedef struct
sahilmgandhi 18:6a4db94011d3 154 {
sahilmgandhi 18:6a4db94011d3 155 __IO uint32_t PINSEL0;
sahilmgandhi 18:6a4db94011d3 156 __IO uint32_t PINSEL1;
sahilmgandhi 18:6a4db94011d3 157 __IO uint32_t PINSEL2;
sahilmgandhi 18:6a4db94011d3 158 __IO uint32_t PINSEL3;
sahilmgandhi 18:6a4db94011d3 159 __IO uint32_t PINSEL4;
sahilmgandhi 18:6a4db94011d3 160 __IO uint32_t PINSEL5;
sahilmgandhi 18:6a4db94011d3 161 __IO uint32_t PINSEL6;
sahilmgandhi 18:6a4db94011d3 162 __IO uint32_t PINSEL7;
sahilmgandhi 18:6a4db94011d3 163 __IO uint32_t PINSEL8;
sahilmgandhi 18:6a4db94011d3 164 __IO uint32_t PINSEL9;
sahilmgandhi 18:6a4db94011d3 165 __IO uint32_t PINSEL10;
sahilmgandhi 18:6a4db94011d3 166 uint32_t RESERVED0[5];
sahilmgandhi 18:6a4db94011d3 167 __IO uint32_t PINMODE0;
sahilmgandhi 18:6a4db94011d3 168 __IO uint32_t PINMODE1;
sahilmgandhi 18:6a4db94011d3 169 __IO uint32_t PINMODE2;
sahilmgandhi 18:6a4db94011d3 170 __IO uint32_t PINMODE3;
sahilmgandhi 18:6a4db94011d3 171 __IO uint32_t PINMODE4;
sahilmgandhi 18:6a4db94011d3 172 __IO uint32_t PINMODE5;
sahilmgandhi 18:6a4db94011d3 173 __IO uint32_t PINMODE6;
sahilmgandhi 18:6a4db94011d3 174 __IO uint32_t PINMODE7;
sahilmgandhi 18:6a4db94011d3 175 __IO uint32_t PINMODE8;
sahilmgandhi 18:6a4db94011d3 176 __IO uint32_t PINMODE9;
sahilmgandhi 18:6a4db94011d3 177 __IO uint32_t PINMODE_OD0;
sahilmgandhi 18:6a4db94011d3 178 __IO uint32_t PINMODE_OD1;
sahilmgandhi 18:6a4db94011d3 179 __IO uint32_t PINMODE_OD2;
sahilmgandhi 18:6a4db94011d3 180 __IO uint32_t PINMODE_OD3;
sahilmgandhi 18:6a4db94011d3 181 __IO uint32_t PINMODE_OD4;
sahilmgandhi 18:6a4db94011d3 182 __IO uint32_t I2CPADCFG;
sahilmgandhi 18:6a4db94011d3 183 } LPC_PINCON_TypeDef;
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
sahilmgandhi 18:6a4db94011d3 186 typedef struct
sahilmgandhi 18:6a4db94011d3 187 {
sahilmgandhi 18:6a4db94011d3 188 union {
sahilmgandhi 18:6a4db94011d3 189 __IO uint32_t FIODIR;
sahilmgandhi 18:6a4db94011d3 190 struct {
sahilmgandhi 18:6a4db94011d3 191 __IO uint16_t FIODIRL;
sahilmgandhi 18:6a4db94011d3 192 __IO uint16_t FIODIRH;
sahilmgandhi 18:6a4db94011d3 193 };
sahilmgandhi 18:6a4db94011d3 194 struct {
sahilmgandhi 18:6a4db94011d3 195 __IO uint8_t FIODIR0;
sahilmgandhi 18:6a4db94011d3 196 __IO uint8_t FIODIR1;
sahilmgandhi 18:6a4db94011d3 197 __IO uint8_t FIODIR2;
sahilmgandhi 18:6a4db94011d3 198 __IO uint8_t FIODIR3;
sahilmgandhi 18:6a4db94011d3 199 };
sahilmgandhi 18:6a4db94011d3 200 };
sahilmgandhi 18:6a4db94011d3 201 uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 202 union {
sahilmgandhi 18:6a4db94011d3 203 __IO uint32_t FIOMASK;
sahilmgandhi 18:6a4db94011d3 204 struct {
sahilmgandhi 18:6a4db94011d3 205 __IO uint16_t FIOMASKL;
sahilmgandhi 18:6a4db94011d3 206 __IO uint16_t FIOMASKH;
sahilmgandhi 18:6a4db94011d3 207 };
sahilmgandhi 18:6a4db94011d3 208 struct {
sahilmgandhi 18:6a4db94011d3 209 __IO uint8_t FIOMASK0;
sahilmgandhi 18:6a4db94011d3 210 __IO uint8_t FIOMASK1;
sahilmgandhi 18:6a4db94011d3 211 __IO uint8_t FIOMASK2;
sahilmgandhi 18:6a4db94011d3 212 __IO uint8_t FIOMASK3;
sahilmgandhi 18:6a4db94011d3 213 };
sahilmgandhi 18:6a4db94011d3 214 };
sahilmgandhi 18:6a4db94011d3 215 union {
sahilmgandhi 18:6a4db94011d3 216 __IO uint32_t FIOPIN;
sahilmgandhi 18:6a4db94011d3 217 struct {
sahilmgandhi 18:6a4db94011d3 218 __IO uint16_t FIOPINL;
sahilmgandhi 18:6a4db94011d3 219 __IO uint16_t FIOPINH;
sahilmgandhi 18:6a4db94011d3 220 };
sahilmgandhi 18:6a4db94011d3 221 struct {
sahilmgandhi 18:6a4db94011d3 222 __IO uint8_t FIOPIN0;
sahilmgandhi 18:6a4db94011d3 223 __IO uint8_t FIOPIN1;
sahilmgandhi 18:6a4db94011d3 224 __IO uint8_t FIOPIN2;
sahilmgandhi 18:6a4db94011d3 225 __IO uint8_t FIOPIN3;
sahilmgandhi 18:6a4db94011d3 226 };
sahilmgandhi 18:6a4db94011d3 227 };
sahilmgandhi 18:6a4db94011d3 228 union {
sahilmgandhi 18:6a4db94011d3 229 __IO uint32_t FIOSET;
sahilmgandhi 18:6a4db94011d3 230 struct {
sahilmgandhi 18:6a4db94011d3 231 __IO uint16_t FIOSETL;
sahilmgandhi 18:6a4db94011d3 232 __IO uint16_t FIOSETH;
sahilmgandhi 18:6a4db94011d3 233 };
sahilmgandhi 18:6a4db94011d3 234 struct {
sahilmgandhi 18:6a4db94011d3 235 __IO uint8_t FIOSET0;
sahilmgandhi 18:6a4db94011d3 236 __IO uint8_t FIOSET1;
sahilmgandhi 18:6a4db94011d3 237 __IO uint8_t FIOSET2;
sahilmgandhi 18:6a4db94011d3 238 __IO uint8_t FIOSET3;
sahilmgandhi 18:6a4db94011d3 239 };
sahilmgandhi 18:6a4db94011d3 240 };
sahilmgandhi 18:6a4db94011d3 241 union {
sahilmgandhi 18:6a4db94011d3 242 __O uint32_t FIOCLR;
sahilmgandhi 18:6a4db94011d3 243 struct {
sahilmgandhi 18:6a4db94011d3 244 __O uint16_t FIOCLRL;
sahilmgandhi 18:6a4db94011d3 245 __O uint16_t FIOCLRH;
sahilmgandhi 18:6a4db94011d3 246 };
sahilmgandhi 18:6a4db94011d3 247 struct {
sahilmgandhi 18:6a4db94011d3 248 __O uint8_t FIOCLR0;
sahilmgandhi 18:6a4db94011d3 249 __O uint8_t FIOCLR1;
sahilmgandhi 18:6a4db94011d3 250 __O uint8_t FIOCLR2;
sahilmgandhi 18:6a4db94011d3 251 __O uint8_t FIOCLR3;
sahilmgandhi 18:6a4db94011d3 252 };
sahilmgandhi 18:6a4db94011d3 253 };
sahilmgandhi 18:6a4db94011d3 254 } LPC_GPIO_TypeDef;
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 typedef struct
sahilmgandhi 18:6a4db94011d3 257 {
sahilmgandhi 18:6a4db94011d3 258 __I uint32_t IntStatus;
sahilmgandhi 18:6a4db94011d3 259 __I uint32_t IO0IntStatR;
sahilmgandhi 18:6a4db94011d3 260 __I uint32_t IO0IntStatF;
sahilmgandhi 18:6a4db94011d3 261 __O uint32_t IO0IntClr;
sahilmgandhi 18:6a4db94011d3 262 __IO uint32_t IO0IntEnR;
sahilmgandhi 18:6a4db94011d3 263 __IO uint32_t IO0IntEnF;
sahilmgandhi 18:6a4db94011d3 264 uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 265 __I uint32_t IO2IntStatR;
sahilmgandhi 18:6a4db94011d3 266 __I uint32_t IO2IntStatF;
sahilmgandhi 18:6a4db94011d3 267 __O uint32_t IO2IntClr;
sahilmgandhi 18:6a4db94011d3 268 __IO uint32_t IO2IntEnR;
sahilmgandhi 18:6a4db94011d3 269 __IO uint32_t IO2IntEnF;
sahilmgandhi 18:6a4db94011d3 270 } LPC_GPIOINT_TypeDef;
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 /*------------- Timer (TIM) --------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 273 typedef struct
sahilmgandhi 18:6a4db94011d3 274 {
sahilmgandhi 18:6a4db94011d3 275 __IO uint32_t IR;
sahilmgandhi 18:6a4db94011d3 276 __IO uint32_t TCR;
sahilmgandhi 18:6a4db94011d3 277 __IO uint32_t TC;
sahilmgandhi 18:6a4db94011d3 278 __IO uint32_t PR;
sahilmgandhi 18:6a4db94011d3 279 __IO uint32_t PC;
sahilmgandhi 18:6a4db94011d3 280 __IO uint32_t MCR;
sahilmgandhi 18:6a4db94011d3 281 __IO uint32_t MR0;
sahilmgandhi 18:6a4db94011d3 282 __IO uint32_t MR1;
sahilmgandhi 18:6a4db94011d3 283 __IO uint32_t MR2;
sahilmgandhi 18:6a4db94011d3 284 __IO uint32_t MR3;
sahilmgandhi 18:6a4db94011d3 285 __IO uint32_t CCR;
sahilmgandhi 18:6a4db94011d3 286 __I uint32_t CR0;
sahilmgandhi 18:6a4db94011d3 287 __I uint32_t CR1;
sahilmgandhi 18:6a4db94011d3 288 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 289 __IO uint32_t EMR;
sahilmgandhi 18:6a4db94011d3 290 uint32_t RESERVED1[12];
sahilmgandhi 18:6a4db94011d3 291 __IO uint32_t CTCR;
sahilmgandhi 18:6a4db94011d3 292 } LPC_TIM_TypeDef;
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
sahilmgandhi 18:6a4db94011d3 295 typedef struct
sahilmgandhi 18:6a4db94011d3 296 {
sahilmgandhi 18:6a4db94011d3 297 __IO uint32_t IR;
sahilmgandhi 18:6a4db94011d3 298 __IO uint32_t TCR;
sahilmgandhi 18:6a4db94011d3 299 __IO uint32_t TC;
sahilmgandhi 18:6a4db94011d3 300 __IO uint32_t PR;
sahilmgandhi 18:6a4db94011d3 301 __IO uint32_t PC;
sahilmgandhi 18:6a4db94011d3 302 __IO uint32_t MCR;
sahilmgandhi 18:6a4db94011d3 303 __IO uint32_t MR0;
sahilmgandhi 18:6a4db94011d3 304 __IO uint32_t MR1;
sahilmgandhi 18:6a4db94011d3 305 __IO uint32_t MR2;
sahilmgandhi 18:6a4db94011d3 306 __IO uint32_t MR3;
sahilmgandhi 18:6a4db94011d3 307 __IO uint32_t CCR;
sahilmgandhi 18:6a4db94011d3 308 __I uint32_t CR0;
sahilmgandhi 18:6a4db94011d3 309 __I uint32_t CR1;
sahilmgandhi 18:6a4db94011d3 310 __I uint32_t CR2;
sahilmgandhi 18:6a4db94011d3 311 __I uint32_t CR3;
sahilmgandhi 18:6a4db94011d3 312 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 313 __IO uint32_t MR4;
sahilmgandhi 18:6a4db94011d3 314 __IO uint32_t MR5;
sahilmgandhi 18:6a4db94011d3 315 __IO uint32_t MR6;
sahilmgandhi 18:6a4db94011d3 316 __IO uint32_t PCR;
sahilmgandhi 18:6a4db94011d3 317 __IO uint32_t LER;
sahilmgandhi 18:6a4db94011d3 318 uint32_t RESERVED1[7];
sahilmgandhi 18:6a4db94011d3 319 __IO uint32_t CTCR;
sahilmgandhi 18:6a4db94011d3 320 } LPC_PWM_TypeDef;
sahilmgandhi 18:6a4db94011d3 321
sahilmgandhi 18:6a4db94011d3 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
sahilmgandhi 18:6a4db94011d3 323 typedef struct
sahilmgandhi 18:6a4db94011d3 324 {
sahilmgandhi 18:6a4db94011d3 325 union {
sahilmgandhi 18:6a4db94011d3 326 __I uint8_t RBR;
sahilmgandhi 18:6a4db94011d3 327 __O uint8_t THR;
sahilmgandhi 18:6a4db94011d3 328 __IO uint8_t DLL;
sahilmgandhi 18:6a4db94011d3 329 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 330 };
sahilmgandhi 18:6a4db94011d3 331 union {
sahilmgandhi 18:6a4db94011d3 332 __IO uint8_t DLM;
sahilmgandhi 18:6a4db94011d3 333 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 334 };
sahilmgandhi 18:6a4db94011d3 335 union {
sahilmgandhi 18:6a4db94011d3 336 __I uint32_t IIR;
sahilmgandhi 18:6a4db94011d3 337 __O uint8_t FCR;
sahilmgandhi 18:6a4db94011d3 338 };
sahilmgandhi 18:6a4db94011d3 339 __IO uint8_t LCR;
sahilmgandhi 18:6a4db94011d3 340 uint8_t RESERVED1[7];
sahilmgandhi 18:6a4db94011d3 341 __I uint8_t LSR;
sahilmgandhi 18:6a4db94011d3 342 uint8_t RESERVED2[7];
sahilmgandhi 18:6a4db94011d3 343 __IO uint8_t SCR;
sahilmgandhi 18:6a4db94011d3 344 uint8_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 345 __IO uint32_t ACR;
sahilmgandhi 18:6a4db94011d3 346 __IO uint8_t ICR;
sahilmgandhi 18:6a4db94011d3 347 uint8_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 348 __IO uint8_t FDR;
sahilmgandhi 18:6a4db94011d3 349 uint8_t RESERVED5[7];
sahilmgandhi 18:6a4db94011d3 350 __IO uint8_t TER;
sahilmgandhi 18:6a4db94011d3 351 uint8_t RESERVED6[39];
sahilmgandhi 18:6a4db94011d3 352 __IO uint32_t FIFOLVL;
sahilmgandhi 18:6a4db94011d3 353 } LPC_UART_TypeDef;
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 typedef struct
sahilmgandhi 18:6a4db94011d3 356 {
sahilmgandhi 18:6a4db94011d3 357 union {
sahilmgandhi 18:6a4db94011d3 358 __I uint8_t RBR;
sahilmgandhi 18:6a4db94011d3 359 __O uint8_t THR;
sahilmgandhi 18:6a4db94011d3 360 __IO uint8_t DLL;
sahilmgandhi 18:6a4db94011d3 361 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 362 };
sahilmgandhi 18:6a4db94011d3 363 union {
sahilmgandhi 18:6a4db94011d3 364 __IO uint8_t DLM;
sahilmgandhi 18:6a4db94011d3 365 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 366 };
sahilmgandhi 18:6a4db94011d3 367 union {
sahilmgandhi 18:6a4db94011d3 368 __I uint32_t IIR;
sahilmgandhi 18:6a4db94011d3 369 __O uint8_t FCR;
sahilmgandhi 18:6a4db94011d3 370 };
sahilmgandhi 18:6a4db94011d3 371 __IO uint8_t LCR;
sahilmgandhi 18:6a4db94011d3 372 uint8_t RESERVED1[7];
sahilmgandhi 18:6a4db94011d3 373 __I uint8_t LSR;
sahilmgandhi 18:6a4db94011d3 374 uint8_t RESERVED2[7];
sahilmgandhi 18:6a4db94011d3 375 __IO uint8_t SCR;
sahilmgandhi 18:6a4db94011d3 376 uint8_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 377 __IO uint32_t ACR;
sahilmgandhi 18:6a4db94011d3 378 __IO uint8_t ICR;
sahilmgandhi 18:6a4db94011d3 379 uint8_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 380 __IO uint8_t FDR;
sahilmgandhi 18:6a4db94011d3 381 uint8_t RESERVED5[7];
sahilmgandhi 18:6a4db94011d3 382 __IO uint8_t TER;
sahilmgandhi 18:6a4db94011d3 383 uint8_t RESERVED6[39];
sahilmgandhi 18:6a4db94011d3 384 __IO uint32_t FIFOLVL;
sahilmgandhi 18:6a4db94011d3 385 } LPC_UART0_TypeDef;
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 typedef struct
sahilmgandhi 18:6a4db94011d3 388 {
sahilmgandhi 18:6a4db94011d3 389 union {
sahilmgandhi 18:6a4db94011d3 390 __I uint8_t RBR;
sahilmgandhi 18:6a4db94011d3 391 __O uint8_t THR;
sahilmgandhi 18:6a4db94011d3 392 __IO uint8_t DLL;
sahilmgandhi 18:6a4db94011d3 393 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 394 };
sahilmgandhi 18:6a4db94011d3 395 union {
sahilmgandhi 18:6a4db94011d3 396 __IO uint8_t DLM;
sahilmgandhi 18:6a4db94011d3 397 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 398 };
sahilmgandhi 18:6a4db94011d3 399 union {
sahilmgandhi 18:6a4db94011d3 400 __I uint32_t IIR;
sahilmgandhi 18:6a4db94011d3 401 __O uint8_t FCR;
sahilmgandhi 18:6a4db94011d3 402 };
sahilmgandhi 18:6a4db94011d3 403 __IO uint8_t LCR;
sahilmgandhi 18:6a4db94011d3 404 uint8_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 405 __IO uint8_t MCR;
sahilmgandhi 18:6a4db94011d3 406 uint8_t RESERVED2[3];
sahilmgandhi 18:6a4db94011d3 407 __I uint8_t LSR;
sahilmgandhi 18:6a4db94011d3 408 uint8_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 409 __I uint8_t MSR;
sahilmgandhi 18:6a4db94011d3 410 uint8_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 411 __IO uint8_t SCR;
sahilmgandhi 18:6a4db94011d3 412 uint8_t RESERVED5[3];
sahilmgandhi 18:6a4db94011d3 413 __IO uint32_t ACR;
sahilmgandhi 18:6a4db94011d3 414 uint32_t RESERVED6;
sahilmgandhi 18:6a4db94011d3 415 __IO uint32_t FDR;
sahilmgandhi 18:6a4db94011d3 416 uint32_t RESERVED7;
sahilmgandhi 18:6a4db94011d3 417 __IO uint8_t TER;
sahilmgandhi 18:6a4db94011d3 418 uint8_t RESERVED8[27];
sahilmgandhi 18:6a4db94011d3 419 __IO uint8_t RS485CTRL;
sahilmgandhi 18:6a4db94011d3 420 uint8_t RESERVED9[3];
sahilmgandhi 18:6a4db94011d3 421 __IO uint8_t ADRMATCH;
sahilmgandhi 18:6a4db94011d3 422 uint8_t RESERVED10[3];
sahilmgandhi 18:6a4db94011d3 423 __IO uint8_t RS485DLY;
sahilmgandhi 18:6a4db94011d3 424 uint8_t RESERVED11[3];
sahilmgandhi 18:6a4db94011d3 425 __IO uint32_t FIFOLVL;
sahilmgandhi 18:6a4db94011d3 426 } LPC_UART1_TypeDef;
sahilmgandhi 18:6a4db94011d3 427
sahilmgandhi 18:6a4db94011d3 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
sahilmgandhi 18:6a4db94011d3 429 typedef struct
sahilmgandhi 18:6a4db94011d3 430 {
sahilmgandhi 18:6a4db94011d3 431 __IO uint32_t SPCR;
sahilmgandhi 18:6a4db94011d3 432 __I uint32_t SPSR;
sahilmgandhi 18:6a4db94011d3 433 __IO uint32_t SPDR;
sahilmgandhi 18:6a4db94011d3 434 __IO uint32_t SPCCR;
sahilmgandhi 18:6a4db94011d3 435 uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 436 __IO uint32_t SPINT;
sahilmgandhi 18:6a4db94011d3 437 } LPC_SPI_TypeDef;
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
sahilmgandhi 18:6a4db94011d3 440 typedef struct
sahilmgandhi 18:6a4db94011d3 441 {
sahilmgandhi 18:6a4db94011d3 442 __IO uint32_t CR0;
sahilmgandhi 18:6a4db94011d3 443 __IO uint32_t CR1;
sahilmgandhi 18:6a4db94011d3 444 __IO uint32_t DR;
sahilmgandhi 18:6a4db94011d3 445 __I uint32_t SR;
sahilmgandhi 18:6a4db94011d3 446 __IO uint32_t CPSR;
sahilmgandhi 18:6a4db94011d3 447 __IO uint32_t IMSC;
sahilmgandhi 18:6a4db94011d3 448 __IO uint32_t RIS;
sahilmgandhi 18:6a4db94011d3 449 __IO uint32_t MIS;
sahilmgandhi 18:6a4db94011d3 450 __IO uint32_t ICR;
sahilmgandhi 18:6a4db94011d3 451 __IO uint32_t DMACR;
sahilmgandhi 18:6a4db94011d3 452 } LPC_SSP_TypeDef;
sahilmgandhi 18:6a4db94011d3 453
sahilmgandhi 18:6a4db94011d3 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
sahilmgandhi 18:6a4db94011d3 455 typedef struct
sahilmgandhi 18:6a4db94011d3 456 {
sahilmgandhi 18:6a4db94011d3 457 __IO uint32_t I2CONSET;
sahilmgandhi 18:6a4db94011d3 458 __I uint32_t I2STAT;
sahilmgandhi 18:6a4db94011d3 459 __IO uint32_t I2DAT;
sahilmgandhi 18:6a4db94011d3 460 __IO uint32_t I2ADR0;
sahilmgandhi 18:6a4db94011d3 461 __IO uint32_t I2SCLH;
sahilmgandhi 18:6a4db94011d3 462 __IO uint32_t I2SCLL;
sahilmgandhi 18:6a4db94011d3 463 __O uint32_t I2CONCLR;
sahilmgandhi 18:6a4db94011d3 464 __IO uint32_t MMCTRL;
sahilmgandhi 18:6a4db94011d3 465 __IO uint32_t I2ADR1;
sahilmgandhi 18:6a4db94011d3 466 __IO uint32_t I2ADR2;
sahilmgandhi 18:6a4db94011d3 467 __IO uint32_t I2ADR3;
sahilmgandhi 18:6a4db94011d3 468 __I uint32_t I2DATA_BUFFER;
sahilmgandhi 18:6a4db94011d3 469 __IO uint32_t I2MASK0;
sahilmgandhi 18:6a4db94011d3 470 __IO uint32_t I2MASK1;
sahilmgandhi 18:6a4db94011d3 471 __IO uint32_t I2MASK2;
sahilmgandhi 18:6a4db94011d3 472 __IO uint32_t I2MASK3;
sahilmgandhi 18:6a4db94011d3 473 } LPC_I2C_TypeDef;
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 476 typedef struct
sahilmgandhi 18:6a4db94011d3 477 {
sahilmgandhi 18:6a4db94011d3 478 __IO uint32_t I2SDAO;
sahilmgandhi 18:6a4db94011d3 479 __IO uint32_t I2SDAI;
sahilmgandhi 18:6a4db94011d3 480 __O uint32_t I2STXFIFO;
sahilmgandhi 18:6a4db94011d3 481 __I uint32_t I2SRXFIFO;
sahilmgandhi 18:6a4db94011d3 482 __I uint32_t I2SSTATE;
sahilmgandhi 18:6a4db94011d3 483 __IO uint32_t I2SDMA1;
sahilmgandhi 18:6a4db94011d3 484 __IO uint32_t I2SDMA2;
sahilmgandhi 18:6a4db94011d3 485 __IO uint32_t I2SIRQ;
sahilmgandhi 18:6a4db94011d3 486 __IO uint32_t I2STXRATE;
sahilmgandhi 18:6a4db94011d3 487 __IO uint32_t I2SRXRATE;
sahilmgandhi 18:6a4db94011d3 488 __IO uint32_t I2STXBITRATE;
sahilmgandhi 18:6a4db94011d3 489 __IO uint32_t I2SRXBITRATE;
sahilmgandhi 18:6a4db94011d3 490 __IO uint32_t I2STXMODE;
sahilmgandhi 18:6a4db94011d3 491 __IO uint32_t I2SRXMODE;
sahilmgandhi 18:6a4db94011d3 492 } LPC_I2S_TypeDef;
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
sahilmgandhi 18:6a4db94011d3 495 typedef struct
sahilmgandhi 18:6a4db94011d3 496 {
sahilmgandhi 18:6a4db94011d3 497 __IO uint32_t RICOMPVAL;
sahilmgandhi 18:6a4db94011d3 498 __IO uint32_t RIMASK;
sahilmgandhi 18:6a4db94011d3 499 __IO uint8_t RICTRL;
sahilmgandhi 18:6a4db94011d3 500 uint8_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 501 __IO uint32_t RICOUNTER;
sahilmgandhi 18:6a4db94011d3 502 } LPC_RIT_TypeDef;
sahilmgandhi 18:6a4db94011d3 503
sahilmgandhi 18:6a4db94011d3 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 505 typedef struct
sahilmgandhi 18:6a4db94011d3 506 {
sahilmgandhi 18:6a4db94011d3 507 __IO uint8_t ILR;
sahilmgandhi 18:6a4db94011d3 508 uint8_t RESERVED0[7];
sahilmgandhi 18:6a4db94011d3 509 __IO uint8_t CCR;
sahilmgandhi 18:6a4db94011d3 510 uint8_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 511 __IO uint8_t CIIR;
sahilmgandhi 18:6a4db94011d3 512 uint8_t RESERVED2[3];
sahilmgandhi 18:6a4db94011d3 513 __IO uint8_t AMR;
sahilmgandhi 18:6a4db94011d3 514 uint8_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 515 __I uint32_t CTIME0;
sahilmgandhi 18:6a4db94011d3 516 __I uint32_t CTIME1;
sahilmgandhi 18:6a4db94011d3 517 __I uint32_t CTIME2;
sahilmgandhi 18:6a4db94011d3 518 __IO uint8_t SEC;
sahilmgandhi 18:6a4db94011d3 519 uint8_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 520 __IO uint8_t MIN;
sahilmgandhi 18:6a4db94011d3 521 uint8_t RESERVED5[3];
sahilmgandhi 18:6a4db94011d3 522 __IO uint8_t HOUR;
sahilmgandhi 18:6a4db94011d3 523 uint8_t RESERVED6[3];
sahilmgandhi 18:6a4db94011d3 524 __IO uint8_t DOM;
sahilmgandhi 18:6a4db94011d3 525 uint8_t RESERVED7[3];
sahilmgandhi 18:6a4db94011d3 526 __IO uint8_t DOW;
sahilmgandhi 18:6a4db94011d3 527 uint8_t RESERVED8[3];
sahilmgandhi 18:6a4db94011d3 528 __IO uint16_t DOY;
sahilmgandhi 18:6a4db94011d3 529 uint16_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 530 __IO uint8_t MONTH;
sahilmgandhi 18:6a4db94011d3 531 uint8_t RESERVED10[3];
sahilmgandhi 18:6a4db94011d3 532 __IO uint16_t YEAR;
sahilmgandhi 18:6a4db94011d3 533 uint16_t RESERVED11;
sahilmgandhi 18:6a4db94011d3 534 __IO uint32_t CALIBRATION;
sahilmgandhi 18:6a4db94011d3 535 __IO uint32_t GPREG0;
sahilmgandhi 18:6a4db94011d3 536 __IO uint32_t GPREG1;
sahilmgandhi 18:6a4db94011d3 537 __IO uint32_t GPREG2;
sahilmgandhi 18:6a4db94011d3 538 __IO uint32_t GPREG3;
sahilmgandhi 18:6a4db94011d3 539 __IO uint32_t GPREG4;
sahilmgandhi 18:6a4db94011d3 540 __IO uint8_t RTC_AUXEN;
sahilmgandhi 18:6a4db94011d3 541 uint8_t RESERVED12[3];
sahilmgandhi 18:6a4db94011d3 542 __IO uint8_t RTC_AUX;
sahilmgandhi 18:6a4db94011d3 543 uint8_t RESERVED13[3];
sahilmgandhi 18:6a4db94011d3 544 __IO uint8_t ALSEC;
sahilmgandhi 18:6a4db94011d3 545 uint8_t RESERVED14[3];
sahilmgandhi 18:6a4db94011d3 546 __IO uint8_t ALMIN;
sahilmgandhi 18:6a4db94011d3 547 uint8_t RESERVED15[3];
sahilmgandhi 18:6a4db94011d3 548 __IO uint8_t ALHOUR;
sahilmgandhi 18:6a4db94011d3 549 uint8_t RESERVED16[3];
sahilmgandhi 18:6a4db94011d3 550 __IO uint8_t ALDOM;
sahilmgandhi 18:6a4db94011d3 551 uint8_t RESERVED17[3];
sahilmgandhi 18:6a4db94011d3 552 __IO uint8_t ALDOW;
sahilmgandhi 18:6a4db94011d3 553 uint8_t RESERVED18[3];
sahilmgandhi 18:6a4db94011d3 554 __IO uint16_t ALDOY;
sahilmgandhi 18:6a4db94011d3 555 uint16_t RESERVED19;
sahilmgandhi 18:6a4db94011d3 556 __IO uint8_t ALMON;
sahilmgandhi 18:6a4db94011d3 557 uint8_t RESERVED20[3];
sahilmgandhi 18:6a4db94011d3 558 __IO uint16_t ALYEAR;
sahilmgandhi 18:6a4db94011d3 559 uint16_t RESERVED21;
sahilmgandhi 18:6a4db94011d3 560 } LPC_RTC_TypeDef;
sahilmgandhi 18:6a4db94011d3 561
sahilmgandhi 18:6a4db94011d3 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 563 typedef struct
sahilmgandhi 18:6a4db94011d3 564 {
sahilmgandhi 18:6a4db94011d3 565 __IO uint8_t WDMOD;
sahilmgandhi 18:6a4db94011d3 566 uint8_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 567 __IO uint32_t WDTC;
sahilmgandhi 18:6a4db94011d3 568 __O uint8_t WDFEED;
sahilmgandhi 18:6a4db94011d3 569 uint8_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 570 __I uint32_t WDTV;
sahilmgandhi 18:6a4db94011d3 571 __IO uint32_t WDCLKSEL;
sahilmgandhi 18:6a4db94011d3 572 } LPC_WDT_TypeDef;
sahilmgandhi 18:6a4db94011d3 573
sahilmgandhi 18:6a4db94011d3 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
sahilmgandhi 18:6a4db94011d3 575 typedef struct
sahilmgandhi 18:6a4db94011d3 576 {
sahilmgandhi 18:6a4db94011d3 577 __IO uint32_t ADCR;
sahilmgandhi 18:6a4db94011d3 578 __IO uint32_t ADGDR;
sahilmgandhi 18:6a4db94011d3 579 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 580 __IO uint32_t ADINTEN;
sahilmgandhi 18:6a4db94011d3 581 __I uint32_t ADDR0;
sahilmgandhi 18:6a4db94011d3 582 __I uint32_t ADDR1;
sahilmgandhi 18:6a4db94011d3 583 __I uint32_t ADDR2;
sahilmgandhi 18:6a4db94011d3 584 __I uint32_t ADDR3;
sahilmgandhi 18:6a4db94011d3 585 __I uint32_t ADDR4;
sahilmgandhi 18:6a4db94011d3 586 __I uint32_t ADDR5;
sahilmgandhi 18:6a4db94011d3 587 __I uint32_t ADDR6;
sahilmgandhi 18:6a4db94011d3 588 __I uint32_t ADDR7;
sahilmgandhi 18:6a4db94011d3 589 __I uint32_t ADSTAT;
sahilmgandhi 18:6a4db94011d3 590 __IO uint32_t ADTRM;
sahilmgandhi 18:6a4db94011d3 591 } LPC_ADC_TypeDef;
sahilmgandhi 18:6a4db94011d3 592
sahilmgandhi 18:6a4db94011d3 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
sahilmgandhi 18:6a4db94011d3 594 typedef struct
sahilmgandhi 18:6a4db94011d3 595 {
sahilmgandhi 18:6a4db94011d3 596 __IO uint32_t DACR;
sahilmgandhi 18:6a4db94011d3 597 __IO uint32_t DACCTRL;
sahilmgandhi 18:6a4db94011d3 598 __IO uint16_t DACCNTVAL;
sahilmgandhi 18:6a4db94011d3 599 } LPC_DAC_TypeDef;
sahilmgandhi 18:6a4db94011d3 600
sahilmgandhi 18:6a4db94011d3 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
sahilmgandhi 18:6a4db94011d3 602 typedef struct
sahilmgandhi 18:6a4db94011d3 603 {
sahilmgandhi 18:6a4db94011d3 604 __I uint32_t MCCON;
sahilmgandhi 18:6a4db94011d3 605 __O uint32_t MCCON_SET;
sahilmgandhi 18:6a4db94011d3 606 __O uint32_t MCCON_CLR;
sahilmgandhi 18:6a4db94011d3 607 __I uint32_t MCCAPCON;
sahilmgandhi 18:6a4db94011d3 608 __O uint32_t MCCAPCON_SET;
sahilmgandhi 18:6a4db94011d3 609 __O uint32_t MCCAPCON_CLR;
sahilmgandhi 18:6a4db94011d3 610 __IO uint32_t MCTIM0;
sahilmgandhi 18:6a4db94011d3 611 __IO uint32_t MCTIM1;
sahilmgandhi 18:6a4db94011d3 612 __IO uint32_t MCTIM2;
sahilmgandhi 18:6a4db94011d3 613 __IO uint32_t MCPER0;
sahilmgandhi 18:6a4db94011d3 614 __IO uint32_t MCPER1;
sahilmgandhi 18:6a4db94011d3 615 __IO uint32_t MCPER2;
sahilmgandhi 18:6a4db94011d3 616 __IO uint32_t MCPW0;
sahilmgandhi 18:6a4db94011d3 617 __IO uint32_t MCPW1;
sahilmgandhi 18:6a4db94011d3 618 __IO uint32_t MCPW2;
sahilmgandhi 18:6a4db94011d3 619 __IO uint32_t MCDEADTIME;
sahilmgandhi 18:6a4db94011d3 620 __IO uint32_t MCCCP;
sahilmgandhi 18:6a4db94011d3 621 __IO uint32_t MCCR0;
sahilmgandhi 18:6a4db94011d3 622 __IO uint32_t MCCR1;
sahilmgandhi 18:6a4db94011d3 623 __IO uint32_t MCCR2;
sahilmgandhi 18:6a4db94011d3 624 __I uint32_t MCINTEN;
sahilmgandhi 18:6a4db94011d3 625 __O uint32_t MCINTEN_SET;
sahilmgandhi 18:6a4db94011d3 626 __O uint32_t MCINTEN_CLR;
sahilmgandhi 18:6a4db94011d3 627 __I uint32_t MCCNTCON;
sahilmgandhi 18:6a4db94011d3 628 __O uint32_t MCCNTCON_SET;
sahilmgandhi 18:6a4db94011d3 629 __O uint32_t MCCNTCON_CLR;
sahilmgandhi 18:6a4db94011d3 630 __I uint32_t MCINTFLAG;
sahilmgandhi 18:6a4db94011d3 631 __O uint32_t MCINTFLAG_SET;
sahilmgandhi 18:6a4db94011d3 632 __O uint32_t MCINTFLAG_CLR;
sahilmgandhi 18:6a4db94011d3 633 __O uint32_t MCCAP_CLR;
sahilmgandhi 18:6a4db94011d3 634 } LPC_MCPWM_TypeDef;
sahilmgandhi 18:6a4db94011d3 635
sahilmgandhi 18:6a4db94011d3 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
sahilmgandhi 18:6a4db94011d3 637 typedef struct
sahilmgandhi 18:6a4db94011d3 638 {
sahilmgandhi 18:6a4db94011d3 639 __O uint32_t QEICON;
sahilmgandhi 18:6a4db94011d3 640 __I uint32_t QEISTAT;
sahilmgandhi 18:6a4db94011d3 641 __IO uint32_t QEICONF;
sahilmgandhi 18:6a4db94011d3 642 __I uint32_t QEIPOS;
sahilmgandhi 18:6a4db94011d3 643 __IO uint32_t QEIMAXPOS;
sahilmgandhi 18:6a4db94011d3 644 __IO uint32_t CMPOS0;
sahilmgandhi 18:6a4db94011d3 645 __IO uint32_t CMPOS1;
sahilmgandhi 18:6a4db94011d3 646 __IO uint32_t CMPOS2;
sahilmgandhi 18:6a4db94011d3 647 __I uint32_t INXCNT;
sahilmgandhi 18:6a4db94011d3 648 __IO uint32_t INXCMP;
sahilmgandhi 18:6a4db94011d3 649 __IO uint32_t QEILOAD;
sahilmgandhi 18:6a4db94011d3 650 __I uint32_t QEITIME;
sahilmgandhi 18:6a4db94011d3 651 __I uint32_t QEIVEL;
sahilmgandhi 18:6a4db94011d3 652 __I uint32_t QEICAP;
sahilmgandhi 18:6a4db94011d3 653 __IO uint32_t VELCOMP;
sahilmgandhi 18:6a4db94011d3 654 __IO uint32_t FILTER;
sahilmgandhi 18:6a4db94011d3 655 uint32_t RESERVED0[998];
sahilmgandhi 18:6a4db94011d3 656 __O uint32_t QEIIEC;
sahilmgandhi 18:6a4db94011d3 657 __O uint32_t QEIIES;
sahilmgandhi 18:6a4db94011d3 658 __I uint32_t QEIINTSTAT;
sahilmgandhi 18:6a4db94011d3 659 __I uint32_t QEIIE;
sahilmgandhi 18:6a4db94011d3 660 __O uint32_t QEICLR;
sahilmgandhi 18:6a4db94011d3 661 __O uint32_t QEISET;
sahilmgandhi 18:6a4db94011d3 662 } LPC_QEI_TypeDef;
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 /*------------- Controller Area Network (CAN) --------------------------------*/
sahilmgandhi 18:6a4db94011d3 665 typedef struct
sahilmgandhi 18:6a4db94011d3 666 {
sahilmgandhi 18:6a4db94011d3 667 __IO uint32_t mask[512]; /* ID Masks */
sahilmgandhi 18:6a4db94011d3 668 } LPC_CANAF_RAM_TypeDef;
sahilmgandhi 18:6a4db94011d3 669
sahilmgandhi 18:6a4db94011d3 670 typedef struct /* Acceptance Filter Registers */
sahilmgandhi 18:6a4db94011d3 671 {
sahilmgandhi 18:6a4db94011d3 672 __IO uint32_t AFMR;
sahilmgandhi 18:6a4db94011d3 673 __IO uint32_t SFF_sa;
sahilmgandhi 18:6a4db94011d3 674 __IO uint32_t SFF_GRP_sa;
sahilmgandhi 18:6a4db94011d3 675 __IO uint32_t EFF_sa;
sahilmgandhi 18:6a4db94011d3 676 __IO uint32_t EFF_GRP_sa;
sahilmgandhi 18:6a4db94011d3 677 __IO uint32_t ENDofTable;
sahilmgandhi 18:6a4db94011d3 678 __I uint32_t LUTerrAd;
sahilmgandhi 18:6a4db94011d3 679 __I uint32_t LUTerr;
sahilmgandhi 18:6a4db94011d3 680 __IO uint32_t FCANIE;
sahilmgandhi 18:6a4db94011d3 681 __IO uint32_t FCANIC0;
sahilmgandhi 18:6a4db94011d3 682 __IO uint32_t FCANIC1;
sahilmgandhi 18:6a4db94011d3 683 } LPC_CANAF_TypeDef;
sahilmgandhi 18:6a4db94011d3 684
sahilmgandhi 18:6a4db94011d3 685 typedef struct /* Central Registers */
sahilmgandhi 18:6a4db94011d3 686 {
sahilmgandhi 18:6a4db94011d3 687 __I uint32_t CANTxSR;
sahilmgandhi 18:6a4db94011d3 688 __I uint32_t CANRxSR;
sahilmgandhi 18:6a4db94011d3 689 __I uint32_t CANMSR;
sahilmgandhi 18:6a4db94011d3 690 } LPC_CANCR_TypeDef;
sahilmgandhi 18:6a4db94011d3 691
sahilmgandhi 18:6a4db94011d3 692 typedef struct /* Controller Registers */
sahilmgandhi 18:6a4db94011d3 693 {
sahilmgandhi 18:6a4db94011d3 694 __IO uint32_t MOD;
sahilmgandhi 18:6a4db94011d3 695 __O uint32_t CMR;
sahilmgandhi 18:6a4db94011d3 696 __IO uint32_t GSR;
sahilmgandhi 18:6a4db94011d3 697 __I uint32_t ICR;
sahilmgandhi 18:6a4db94011d3 698 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 699 __IO uint32_t BTR;
sahilmgandhi 18:6a4db94011d3 700 __IO uint32_t EWL;
sahilmgandhi 18:6a4db94011d3 701 __I uint32_t SR;
sahilmgandhi 18:6a4db94011d3 702 __IO uint32_t RFS;
sahilmgandhi 18:6a4db94011d3 703 __IO uint32_t RID;
sahilmgandhi 18:6a4db94011d3 704 __IO uint32_t RDA;
sahilmgandhi 18:6a4db94011d3 705 __IO uint32_t RDB;
sahilmgandhi 18:6a4db94011d3 706 __IO uint32_t TFI1;
sahilmgandhi 18:6a4db94011d3 707 __IO uint32_t TID1;
sahilmgandhi 18:6a4db94011d3 708 __IO uint32_t TDA1;
sahilmgandhi 18:6a4db94011d3 709 __IO uint32_t TDB1;
sahilmgandhi 18:6a4db94011d3 710 __IO uint32_t TFI2;
sahilmgandhi 18:6a4db94011d3 711 __IO uint32_t TID2;
sahilmgandhi 18:6a4db94011d3 712 __IO uint32_t TDA2;
sahilmgandhi 18:6a4db94011d3 713 __IO uint32_t TDB2;
sahilmgandhi 18:6a4db94011d3 714 __IO uint32_t TFI3;
sahilmgandhi 18:6a4db94011d3 715 __IO uint32_t TID3;
sahilmgandhi 18:6a4db94011d3 716 __IO uint32_t TDA3;
sahilmgandhi 18:6a4db94011d3 717 __IO uint32_t TDB3;
sahilmgandhi 18:6a4db94011d3 718 } LPC_CAN_TypeDef;
sahilmgandhi 18:6a4db94011d3 719
sahilmgandhi 18:6a4db94011d3 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
sahilmgandhi 18:6a4db94011d3 721 typedef struct /* Common Registers */
sahilmgandhi 18:6a4db94011d3 722 {
sahilmgandhi 18:6a4db94011d3 723 __I uint32_t DMACIntStat;
sahilmgandhi 18:6a4db94011d3 724 __I uint32_t DMACIntTCStat;
sahilmgandhi 18:6a4db94011d3 725 __O uint32_t DMACIntTCClear;
sahilmgandhi 18:6a4db94011d3 726 __I uint32_t DMACIntErrStat;
sahilmgandhi 18:6a4db94011d3 727 __O uint32_t DMACIntErrClr;
sahilmgandhi 18:6a4db94011d3 728 __I uint32_t DMACRawIntTCStat;
sahilmgandhi 18:6a4db94011d3 729 __I uint32_t DMACRawIntErrStat;
sahilmgandhi 18:6a4db94011d3 730 __I uint32_t DMACEnbldChns;
sahilmgandhi 18:6a4db94011d3 731 __IO uint32_t DMACSoftBReq;
sahilmgandhi 18:6a4db94011d3 732 __IO uint32_t DMACSoftSReq;
sahilmgandhi 18:6a4db94011d3 733 __IO uint32_t DMACSoftLBReq;
sahilmgandhi 18:6a4db94011d3 734 __IO uint32_t DMACSoftLSReq;
sahilmgandhi 18:6a4db94011d3 735 __IO uint32_t DMACConfig;
sahilmgandhi 18:6a4db94011d3 736 __IO uint32_t DMACSync;
sahilmgandhi 18:6a4db94011d3 737 } LPC_GPDMA_TypeDef;
sahilmgandhi 18:6a4db94011d3 738
sahilmgandhi 18:6a4db94011d3 739 typedef struct /* Channel Registers */
sahilmgandhi 18:6a4db94011d3 740 {
sahilmgandhi 18:6a4db94011d3 741 __IO uint32_t DMACCSrcAddr;
sahilmgandhi 18:6a4db94011d3 742 __IO uint32_t DMACCDestAddr;
sahilmgandhi 18:6a4db94011d3 743 __IO uint32_t DMACCLLI;
sahilmgandhi 18:6a4db94011d3 744 __IO uint32_t DMACCControl;
sahilmgandhi 18:6a4db94011d3 745 __IO uint32_t DMACCConfig;
sahilmgandhi 18:6a4db94011d3 746 } LPC_GPDMACH_TypeDef;
sahilmgandhi 18:6a4db94011d3 747
sahilmgandhi 18:6a4db94011d3 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
sahilmgandhi 18:6a4db94011d3 749 typedef struct
sahilmgandhi 18:6a4db94011d3 750 {
sahilmgandhi 18:6a4db94011d3 751 __I uint32_t HcRevision; /* USB Host Registers */
sahilmgandhi 18:6a4db94011d3 752 __IO uint32_t HcControl;
sahilmgandhi 18:6a4db94011d3 753 __IO uint32_t HcCommandStatus;
sahilmgandhi 18:6a4db94011d3 754 __IO uint32_t HcInterruptStatus;
sahilmgandhi 18:6a4db94011d3 755 __IO uint32_t HcInterruptEnable;
sahilmgandhi 18:6a4db94011d3 756 __IO uint32_t HcInterruptDisable;
sahilmgandhi 18:6a4db94011d3 757 __IO uint32_t HcHCCA;
sahilmgandhi 18:6a4db94011d3 758 __I uint32_t HcPeriodCurrentED;
sahilmgandhi 18:6a4db94011d3 759 __IO uint32_t HcControlHeadED;
sahilmgandhi 18:6a4db94011d3 760 __IO uint32_t HcControlCurrentED;
sahilmgandhi 18:6a4db94011d3 761 __IO uint32_t HcBulkHeadED;
sahilmgandhi 18:6a4db94011d3 762 __IO uint32_t HcBulkCurrentED;
sahilmgandhi 18:6a4db94011d3 763 __I uint32_t HcDoneHead;
sahilmgandhi 18:6a4db94011d3 764 __IO uint32_t HcFmInterval;
sahilmgandhi 18:6a4db94011d3 765 __I uint32_t HcFmRemaining;
sahilmgandhi 18:6a4db94011d3 766 __I uint32_t HcFmNumber;
sahilmgandhi 18:6a4db94011d3 767 __IO uint32_t HcPeriodicStart;
sahilmgandhi 18:6a4db94011d3 768 __IO uint32_t HcLSTreshold;
sahilmgandhi 18:6a4db94011d3 769 __IO uint32_t HcRhDescriptorA;
sahilmgandhi 18:6a4db94011d3 770 __IO uint32_t HcRhDescriptorB;
sahilmgandhi 18:6a4db94011d3 771 __IO uint32_t HcRhStatus;
sahilmgandhi 18:6a4db94011d3 772 __IO uint32_t HcRhPortStatus1;
sahilmgandhi 18:6a4db94011d3 773 __IO uint32_t HcRhPortStatus2;
sahilmgandhi 18:6a4db94011d3 774 uint32_t RESERVED0[40];
sahilmgandhi 18:6a4db94011d3 775 __I uint32_t Module_ID;
sahilmgandhi 18:6a4db94011d3 776
sahilmgandhi 18:6a4db94011d3 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
sahilmgandhi 18:6a4db94011d3 778 __IO uint32_t OTGIntEn;
sahilmgandhi 18:6a4db94011d3 779 __O uint32_t OTGIntSet;
sahilmgandhi 18:6a4db94011d3 780 __O uint32_t OTGIntClr;
sahilmgandhi 18:6a4db94011d3 781 __IO uint32_t OTGStCtrl;
sahilmgandhi 18:6a4db94011d3 782 __IO uint32_t OTGTmr;
sahilmgandhi 18:6a4db94011d3 783 uint32_t RESERVED1[58];
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
sahilmgandhi 18:6a4db94011d3 786 __IO uint32_t USBDevIntEn;
sahilmgandhi 18:6a4db94011d3 787 __O uint32_t USBDevIntClr;
sahilmgandhi 18:6a4db94011d3 788 __O uint32_t USBDevIntSet;
sahilmgandhi 18:6a4db94011d3 789
sahilmgandhi 18:6a4db94011d3 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
sahilmgandhi 18:6a4db94011d3 791 __I uint32_t USBCmdData;
sahilmgandhi 18:6a4db94011d3 792
sahilmgandhi 18:6a4db94011d3 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
sahilmgandhi 18:6a4db94011d3 794 __O uint32_t USBTxData;
sahilmgandhi 18:6a4db94011d3 795 __I uint32_t USBRxPLen;
sahilmgandhi 18:6a4db94011d3 796 __O uint32_t USBTxPLen;
sahilmgandhi 18:6a4db94011d3 797 __IO uint32_t USBCtrl;
sahilmgandhi 18:6a4db94011d3 798 __O uint32_t USBDevIntPri;
sahilmgandhi 18:6a4db94011d3 799
sahilmgandhi 18:6a4db94011d3 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
sahilmgandhi 18:6a4db94011d3 801 __IO uint32_t USBEpIntEn;
sahilmgandhi 18:6a4db94011d3 802 __O uint32_t USBEpIntClr;
sahilmgandhi 18:6a4db94011d3 803 __O uint32_t USBEpIntSet;
sahilmgandhi 18:6a4db94011d3 804 __O uint32_t USBEpIntPri;
sahilmgandhi 18:6a4db94011d3 805
sahilmgandhi 18:6a4db94011d3 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
sahilmgandhi 18:6a4db94011d3 807 __O uint32_t USBEpInd;
sahilmgandhi 18:6a4db94011d3 808 __IO uint32_t USBMaxPSize;
sahilmgandhi 18:6a4db94011d3 809
sahilmgandhi 18:6a4db94011d3 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
sahilmgandhi 18:6a4db94011d3 811 __O uint32_t USBDMARClr;
sahilmgandhi 18:6a4db94011d3 812 __O uint32_t USBDMARSet;
sahilmgandhi 18:6a4db94011d3 813 uint32_t RESERVED2[9];
sahilmgandhi 18:6a4db94011d3 814 __IO uint32_t USBUDCAH;
sahilmgandhi 18:6a4db94011d3 815 __I uint32_t USBEpDMASt;
sahilmgandhi 18:6a4db94011d3 816 __O uint32_t USBEpDMAEn;
sahilmgandhi 18:6a4db94011d3 817 __O uint32_t USBEpDMADis;
sahilmgandhi 18:6a4db94011d3 818 __I uint32_t USBDMAIntSt;
sahilmgandhi 18:6a4db94011d3 819 __IO uint32_t USBDMAIntEn;
sahilmgandhi 18:6a4db94011d3 820 uint32_t RESERVED3[2];
sahilmgandhi 18:6a4db94011d3 821 __I uint32_t USBEoTIntSt;
sahilmgandhi 18:6a4db94011d3 822 __O uint32_t USBEoTIntClr;
sahilmgandhi 18:6a4db94011d3 823 __O uint32_t USBEoTIntSet;
sahilmgandhi 18:6a4db94011d3 824 __I uint32_t USBNDDRIntSt;
sahilmgandhi 18:6a4db94011d3 825 __O uint32_t USBNDDRIntClr;
sahilmgandhi 18:6a4db94011d3 826 __O uint32_t USBNDDRIntSet;
sahilmgandhi 18:6a4db94011d3 827 __I uint32_t USBSysErrIntSt;
sahilmgandhi 18:6a4db94011d3 828 __O uint32_t USBSysErrIntClr;
sahilmgandhi 18:6a4db94011d3 829 __O uint32_t USBSysErrIntSet;
sahilmgandhi 18:6a4db94011d3 830 uint32_t RESERVED4[15];
sahilmgandhi 18:6a4db94011d3 831
sahilmgandhi 18:6a4db94011d3 832 union {
sahilmgandhi 18:6a4db94011d3 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
sahilmgandhi 18:6a4db94011d3 834 __O uint32_t I2C_TX;
sahilmgandhi 18:6a4db94011d3 835 };
sahilmgandhi 18:6a4db94011d3 836 __I uint32_t I2C_STS;
sahilmgandhi 18:6a4db94011d3 837 __IO uint32_t I2C_CTL;
sahilmgandhi 18:6a4db94011d3 838 __IO uint32_t I2C_CLKHI;
sahilmgandhi 18:6a4db94011d3 839 __O uint32_t I2C_CLKLO;
sahilmgandhi 18:6a4db94011d3 840 uint32_t RESERVED5[824];
sahilmgandhi 18:6a4db94011d3 841
sahilmgandhi 18:6a4db94011d3 842 union {
sahilmgandhi 18:6a4db94011d3 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
sahilmgandhi 18:6a4db94011d3 844 __IO uint32_t OTGClkCtrl;
sahilmgandhi 18:6a4db94011d3 845 };
sahilmgandhi 18:6a4db94011d3 846 union {
sahilmgandhi 18:6a4db94011d3 847 __I uint32_t USBClkSt;
sahilmgandhi 18:6a4db94011d3 848 __I uint32_t OTGClkSt;
sahilmgandhi 18:6a4db94011d3 849 };
sahilmgandhi 18:6a4db94011d3 850 } LPC_USB_TypeDef;
sahilmgandhi 18:6a4db94011d3 851
sahilmgandhi 18:6a4db94011d3 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
sahilmgandhi 18:6a4db94011d3 853 typedef struct
sahilmgandhi 18:6a4db94011d3 854 {
sahilmgandhi 18:6a4db94011d3 855 __IO uint32_t MAC1; /* MAC Registers */
sahilmgandhi 18:6a4db94011d3 856 __IO uint32_t MAC2;
sahilmgandhi 18:6a4db94011d3 857 __IO uint32_t IPGT;
sahilmgandhi 18:6a4db94011d3 858 __IO uint32_t IPGR;
sahilmgandhi 18:6a4db94011d3 859 __IO uint32_t CLRT;
sahilmgandhi 18:6a4db94011d3 860 __IO uint32_t MAXF;
sahilmgandhi 18:6a4db94011d3 861 __IO uint32_t SUPP;
sahilmgandhi 18:6a4db94011d3 862 __IO uint32_t TEST;
sahilmgandhi 18:6a4db94011d3 863 __IO uint32_t MCFG;
sahilmgandhi 18:6a4db94011d3 864 __IO uint32_t MCMD;
sahilmgandhi 18:6a4db94011d3 865 __IO uint32_t MADR;
sahilmgandhi 18:6a4db94011d3 866 __O uint32_t MWTD;
sahilmgandhi 18:6a4db94011d3 867 __I uint32_t MRDD;
sahilmgandhi 18:6a4db94011d3 868 __I uint32_t MIND;
sahilmgandhi 18:6a4db94011d3 869 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 870 __IO uint32_t SA0;
sahilmgandhi 18:6a4db94011d3 871 __IO uint32_t SA1;
sahilmgandhi 18:6a4db94011d3 872 __IO uint32_t SA2;
sahilmgandhi 18:6a4db94011d3 873 uint32_t RESERVED1[45];
sahilmgandhi 18:6a4db94011d3 874 __IO uint32_t Command; /* Control Registers */
sahilmgandhi 18:6a4db94011d3 875 __I uint32_t Status;
sahilmgandhi 18:6a4db94011d3 876 __IO uint32_t RxDescriptor;
sahilmgandhi 18:6a4db94011d3 877 __IO uint32_t RxStatus;
sahilmgandhi 18:6a4db94011d3 878 __IO uint32_t RxDescriptorNumber;
sahilmgandhi 18:6a4db94011d3 879 __I uint32_t RxProduceIndex;
sahilmgandhi 18:6a4db94011d3 880 __IO uint32_t RxConsumeIndex;
sahilmgandhi 18:6a4db94011d3 881 __IO uint32_t TxDescriptor;
sahilmgandhi 18:6a4db94011d3 882 __IO uint32_t TxStatus;
sahilmgandhi 18:6a4db94011d3 883 __IO uint32_t TxDescriptorNumber;
sahilmgandhi 18:6a4db94011d3 884 __IO uint32_t TxProduceIndex;
sahilmgandhi 18:6a4db94011d3 885 __I uint32_t TxConsumeIndex;
sahilmgandhi 18:6a4db94011d3 886 uint32_t RESERVED2[10];
sahilmgandhi 18:6a4db94011d3 887 __I uint32_t TSV0;
sahilmgandhi 18:6a4db94011d3 888 __I uint32_t TSV1;
sahilmgandhi 18:6a4db94011d3 889 __I uint32_t RSV;
sahilmgandhi 18:6a4db94011d3 890 uint32_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 891 __IO uint32_t FlowControlCounter;
sahilmgandhi 18:6a4db94011d3 892 __I uint32_t FlowControlStatus;
sahilmgandhi 18:6a4db94011d3 893 uint32_t RESERVED4[34];
sahilmgandhi 18:6a4db94011d3 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
sahilmgandhi 18:6a4db94011d3 895 __IO uint32_t RxFilterWoLStatus;
sahilmgandhi 18:6a4db94011d3 896 __IO uint32_t RxFilterWoLClear;
sahilmgandhi 18:6a4db94011d3 897 uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 898 __IO uint32_t HashFilterL;
sahilmgandhi 18:6a4db94011d3 899 __IO uint32_t HashFilterH;
sahilmgandhi 18:6a4db94011d3 900 uint32_t RESERVED6[882];
sahilmgandhi 18:6a4db94011d3 901 __I uint32_t IntStatus; /* Module Control Registers */
sahilmgandhi 18:6a4db94011d3 902 __IO uint32_t IntEnable;
sahilmgandhi 18:6a4db94011d3 903 __O uint32_t IntClear;
sahilmgandhi 18:6a4db94011d3 904 __O uint32_t IntSet;
sahilmgandhi 18:6a4db94011d3 905 uint32_t RESERVED7;
sahilmgandhi 18:6a4db94011d3 906 __IO uint32_t PowerDown;
sahilmgandhi 18:6a4db94011d3 907 uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 908 __IO uint32_t Module_ID;
sahilmgandhi 18:6a4db94011d3 909 } LPC_EMAC_TypeDef;
sahilmgandhi 18:6a4db94011d3 910
sahilmgandhi 18:6a4db94011d3 911 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 912 #pragma no_anon_unions
sahilmgandhi 18:6a4db94011d3 913 #endif
sahilmgandhi 18:6a4db94011d3 914
sahilmgandhi 18:6a4db94011d3 915
sahilmgandhi 18:6a4db94011d3 916 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 917 /* Peripheral memory map */
sahilmgandhi 18:6a4db94011d3 918 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 919 /* Base addresses */
sahilmgandhi 18:6a4db94011d3 920 #define LPC_FLASH_BASE (0x00000000UL)
sahilmgandhi 18:6a4db94011d3 921 #define LPC_RAM_BASE (0x10000000UL)
sahilmgandhi 18:6a4db94011d3 922 #define LPC_GPIO_BASE (0x2009C000UL)
sahilmgandhi 18:6a4db94011d3 923 #define LPC_APB0_BASE (0x40000000UL)
sahilmgandhi 18:6a4db94011d3 924 #define LPC_APB1_BASE (0x40080000UL)
sahilmgandhi 18:6a4db94011d3 925 #define LPC_AHB_BASE (0x50000000UL)
sahilmgandhi 18:6a4db94011d3 926 #define LPC_CM3_BASE (0xE0000000UL)
sahilmgandhi 18:6a4db94011d3 927
sahilmgandhi 18:6a4db94011d3 928 /* APB0 peripherals */
sahilmgandhi 18:6a4db94011d3 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
sahilmgandhi 18:6a4db94011d3 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
sahilmgandhi 18:6a4db94011d3 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
sahilmgandhi 18:6a4db94011d3 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
sahilmgandhi 18:6a4db94011d3 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
sahilmgandhi 18:6a4db94011d3 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
sahilmgandhi 18:6a4db94011d3 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
sahilmgandhi 18:6a4db94011d3 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
sahilmgandhi 18:6a4db94011d3 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
sahilmgandhi 18:6a4db94011d3 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
sahilmgandhi 18:6a4db94011d3 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
sahilmgandhi 18:6a4db94011d3 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
sahilmgandhi 18:6a4db94011d3 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
sahilmgandhi 18:6a4db94011d3 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
sahilmgandhi 18:6a4db94011d3 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
sahilmgandhi 18:6a4db94011d3 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
sahilmgandhi 18:6a4db94011d3 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
sahilmgandhi 18:6a4db94011d3 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
sahilmgandhi 18:6a4db94011d3 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
sahilmgandhi 18:6a4db94011d3 948
sahilmgandhi 18:6a4db94011d3 949 /* APB1 peripherals */
sahilmgandhi 18:6a4db94011d3 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
sahilmgandhi 18:6a4db94011d3 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
sahilmgandhi 18:6a4db94011d3 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
sahilmgandhi 18:6a4db94011d3 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
sahilmgandhi 18:6a4db94011d3 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
sahilmgandhi 18:6a4db94011d3 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
sahilmgandhi 18:6a4db94011d3 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
sahilmgandhi 18:6a4db94011d3 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
sahilmgandhi 18:6a4db94011d3 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
sahilmgandhi 18:6a4db94011d3 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
sahilmgandhi 18:6a4db94011d3 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
sahilmgandhi 18:6a4db94011d3 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
sahilmgandhi 18:6a4db94011d3 962
sahilmgandhi 18:6a4db94011d3 963 /* AHB peripherals */
sahilmgandhi 18:6a4db94011d3 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
sahilmgandhi 18:6a4db94011d3 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
sahilmgandhi 18:6a4db94011d3 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
sahilmgandhi 18:6a4db94011d3 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
sahilmgandhi 18:6a4db94011d3 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
sahilmgandhi 18:6a4db94011d3 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
sahilmgandhi 18:6a4db94011d3 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
sahilmgandhi 18:6a4db94011d3 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
sahilmgandhi 18:6a4db94011d3 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
sahilmgandhi 18:6a4db94011d3 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
sahilmgandhi 18:6a4db94011d3 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
sahilmgandhi 18:6a4db94011d3 975
sahilmgandhi 18:6a4db94011d3 976 /* GPIOs */
sahilmgandhi 18:6a4db94011d3 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
sahilmgandhi 18:6a4db94011d3 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
sahilmgandhi 18:6a4db94011d3 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
sahilmgandhi 18:6a4db94011d3 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
sahilmgandhi 18:6a4db94011d3 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
sahilmgandhi 18:6a4db94011d3 982
sahilmgandhi 18:6a4db94011d3 983
sahilmgandhi 18:6a4db94011d3 984 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 985 /* Peripheral declaration */
sahilmgandhi 18:6a4db94011d3 986 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
sahilmgandhi 18:6a4db94011d3 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
sahilmgandhi 18:6a4db94011d3 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
sahilmgandhi 18:6a4db94011d3 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
sahilmgandhi 18:6a4db94011d3 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
sahilmgandhi 18:6a4db94011d3 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
sahilmgandhi 18:6a4db94011d3 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
sahilmgandhi 18:6a4db94011d3 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
sahilmgandhi 18:6a4db94011d3 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
sahilmgandhi 18:6a4db94011d3 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
sahilmgandhi 18:6a4db94011d3 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
sahilmgandhi 18:6a4db94011d3 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
sahilmgandhi 18:6a4db94011d3 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
sahilmgandhi 18:6a4db94011d3 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
sahilmgandhi 18:6a4db94011d3 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
sahilmgandhi 18:6a4db94011d3 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
sahilmgandhi 18:6a4db94011d3 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
sahilmgandhi 18:6a4db94011d3 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
sahilmgandhi 18:6a4db94011d3 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
sahilmgandhi 18:6a4db94011d3 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
sahilmgandhi 18:6a4db94011d3 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
sahilmgandhi 18:6a4db94011d3 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
sahilmgandhi 18:6a4db94011d3 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
sahilmgandhi 18:6a4db94011d3 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
sahilmgandhi 18:6a4db94011d3 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
sahilmgandhi 18:6a4db94011d3 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
sahilmgandhi 18:6a4db94011d3 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
sahilmgandhi 18:6a4db94011d3 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
sahilmgandhi 18:6a4db94011d3 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
sahilmgandhi 18:6a4db94011d3 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
sahilmgandhi 18:6a4db94011d3 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
sahilmgandhi 18:6a4db94011d3 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
sahilmgandhi 18:6a4db94011d3 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
sahilmgandhi 18:6a4db94011d3 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
sahilmgandhi 18:6a4db94011d3 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
sahilmgandhi 18:6a4db94011d3 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
sahilmgandhi 18:6a4db94011d3 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
sahilmgandhi 18:6a4db94011d3 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
sahilmgandhi 18:6a4db94011d3 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
sahilmgandhi 18:6a4db94011d3 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
sahilmgandhi 18:6a4db94011d3 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
sahilmgandhi 18:6a4db94011d3 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
sahilmgandhi 18:6a4db94011d3 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
sahilmgandhi 18:6a4db94011d3 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
sahilmgandhi 18:6a4db94011d3 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
sahilmgandhi 18:6a4db94011d3 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
sahilmgandhi 18:6a4db94011d3 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
sahilmgandhi 18:6a4db94011d3 1034
sahilmgandhi 18:6a4db94011d3 1035 #endif // __LPC17xx_H__