MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC176X/can_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 17 #include "can_api.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 20 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 #include <math.h>
sahilmgandhi 18:6a4db94011d3 23 #include <string.h>
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 #define CAN_NUM 2
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 /* Acceptance filter mode in AFMR register */
sahilmgandhi 18:6a4db94011d3 28 #define ACCF_OFF 0x01
sahilmgandhi 18:6a4db94011d3 29 #define ACCF_BYPASS 0x02
sahilmgandhi 18:6a4db94011d3 30 #define ACCF_ON 0x00
sahilmgandhi 18:6a4db94011d3 31 #define ACCF_FULLCAN 0x04
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 /* There are several bit timing calculators on the internet.
sahilmgandhi 18:6a4db94011d3 34 http://www.port.de/engl/canprod/sv_req_form.html
sahilmgandhi 18:6a4db94011d3 35 http://www.kvaser.com/can/index.htm
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 static const PinMap PinMap_CAN_RD[] = {
sahilmgandhi 18:6a4db94011d3 39 {P0_0 , CAN_1, 1},
sahilmgandhi 18:6a4db94011d3 40 {P0_4 , CAN_2, 2},
sahilmgandhi 18:6a4db94011d3 41 {P0_21, CAN_1, 3},
sahilmgandhi 18:6a4db94011d3 42 {P2_7 , CAN_2, 1},
sahilmgandhi 18:6a4db94011d3 43 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 44 };
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 static const PinMap PinMap_CAN_TD[] = {
sahilmgandhi 18:6a4db94011d3 47 {P0_1 , CAN_1, 1},
sahilmgandhi 18:6a4db94011d3 48 {P0_5 , CAN_2, 2},
sahilmgandhi 18:6a4db94011d3 49 {P0_22, CAN_1, 3},
sahilmgandhi 18:6a4db94011d3 50 {P2_8 , CAN_2, 1},
sahilmgandhi 18:6a4db94011d3 51 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 52 };
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 // Type definition to hold a CAN message
sahilmgandhi 18:6a4db94011d3 55 struct CANMsg {
sahilmgandhi 18:6a4db94011d3 56 unsigned int reserved1 : 16;
sahilmgandhi 18:6a4db94011d3 57 unsigned int dlc : 4; // Bits 16..19: DLC - Data Length Counter
sahilmgandhi 18:6a4db94011d3 58 unsigned int reserved0 : 10;
sahilmgandhi 18:6a4db94011d3 59 unsigned int rtr : 1; // Bit 30: Set if this is a RTR message
sahilmgandhi 18:6a4db94011d3 60 unsigned int type : 1; // Bit 31: Set if this is a 29-bit ID message
sahilmgandhi 18:6a4db94011d3 61 unsigned int id; // CAN Message ID (11-bit or 29-bit)
sahilmgandhi 18:6a4db94011d3 62 unsigned char data[8]; // CAN Message Data Bytes 0-7
sahilmgandhi 18:6a4db94011d3 63 };
sahilmgandhi 18:6a4db94011d3 64 typedef struct CANMsg CANMsg;
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 static uint32_t can_irq_ids[CAN_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 67 static can_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 static uint32_t can_disable(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 70 uint32_t sm = obj->dev->MOD;
sahilmgandhi 18:6a4db94011d3 71 obj->dev->MOD |= 1;
sahilmgandhi 18:6a4db94011d3 72 return sm;
sahilmgandhi 18:6a4db94011d3 73 }
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 static inline void can_enable(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 76 if (obj->dev->MOD & 1) {
sahilmgandhi 18:6a4db94011d3 77 obj->dev->MOD &= ~(1);
sahilmgandhi 18:6a4db94011d3 78 }
sahilmgandhi 18:6a4db94011d3 79 }
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 int can_mode(can_t *obj, CanMode mode) {
sahilmgandhi 18:6a4db94011d3 82 int success = 0;
sahilmgandhi 18:6a4db94011d3 83 switch (mode) {
sahilmgandhi 18:6a4db94011d3 84 case MODE_RESET:
sahilmgandhi 18:6a4db94011d3 85 // Clear all special modes
sahilmgandhi 18:6a4db94011d3 86 can_reset(obj);
sahilmgandhi 18:6a4db94011d3 87 obj->dev->MOD &=~ 0x06;
sahilmgandhi 18:6a4db94011d3 88 success = 1;
sahilmgandhi 18:6a4db94011d3 89 break;
sahilmgandhi 18:6a4db94011d3 90 case MODE_NORMAL:
sahilmgandhi 18:6a4db94011d3 91 // Clear all special modes
sahilmgandhi 18:6a4db94011d3 92 can_disable(obj);
sahilmgandhi 18:6a4db94011d3 93 obj->dev->MOD &=~ 0x06;
sahilmgandhi 18:6a4db94011d3 94 can_enable(obj);
sahilmgandhi 18:6a4db94011d3 95 success = 1;
sahilmgandhi 18:6a4db94011d3 96 break;
sahilmgandhi 18:6a4db94011d3 97 case MODE_SILENT:
sahilmgandhi 18:6a4db94011d3 98 // Set listen-only mode and clear self-test mode
sahilmgandhi 18:6a4db94011d3 99 can_disable(obj);
sahilmgandhi 18:6a4db94011d3 100 obj->dev->MOD |= 0x02;
sahilmgandhi 18:6a4db94011d3 101 obj->dev->MOD &=~ 0x04;
sahilmgandhi 18:6a4db94011d3 102 can_enable(obj);
sahilmgandhi 18:6a4db94011d3 103 success = 1;
sahilmgandhi 18:6a4db94011d3 104 break;
sahilmgandhi 18:6a4db94011d3 105 case MODE_TEST_LOCAL:
sahilmgandhi 18:6a4db94011d3 106 // Set self-test mode and clear listen-only mode
sahilmgandhi 18:6a4db94011d3 107 can_disable(obj);
sahilmgandhi 18:6a4db94011d3 108 obj->dev->MOD |= 0x04;
sahilmgandhi 18:6a4db94011d3 109 obj->dev->MOD &=~ 0x02;
sahilmgandhi 18:6a4db94011d3 110 can_enable(obj);
sahilmgandhi 18:6a4db94011d3 111 success = 1;
sahilmgandhi 18:6a4db94011d3 112 break;
sahilmgandhi 18:6a4db94011d3 113 case MODE_TEST_SILENT:
sahilmgandhi 18:6a4db94011d3 114 case MODE_TEST_GLOBAL:
sahilmgandhi 18:6a4db94011d3 115 default:
sahilmgandhi 18:6a4db94011d3 116 success = 0;
sahilmgandhi 18:6a4db94011d3 117 break;
sahilmgandhi 18:6a4db94011d3 118 }
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 return success;
sahilmgandhi 18:6a4db94011d3 121 }
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
sahilmgandhi 18:6a4db94011d3 124 return 0; // not implemented
sahilmgandhi 18:6a4db94011d3 125 }
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 static inline void can_irq(uint32_t icr, uint32_t index) {
sahilmgandhi 18:6a4db94011d3 128 uint32_t i;
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 for(i = 0; i < 8; i++)
sahilmgandhi 18:6a4db94011d3 131 {
sahilmgandhi 18:6a4db94011d3 132 if((can_irq_ids[index] != 0) && (icr & (1 << i)))
sahilmgandhi 18:6a4db94011d3 133 {
sahilmgandhi 18:6a4db94011d3 134 switch (i) {
sahilmgandhi 18:6a4db94011d3 135 case 0: irq_handler(can_irq_ids[index], IRQ_RX); break;
sahilmgandhi 18:6a4db94011d3 136 case 1: irq_handler(can_irq_ids[index], IRQ_TX); break;
sahilmgandhi 18:6a4db94011d3 137 case 2: irq_handler(can_irq_ids[index], IRQ_ERROR); break;
sahilmgandhi 18:6a4db94011d3 138 case 3: irq_handler(can_irq_ids[index], IRQ_OVERRUN); break;
sahilmgandhi 18:6a4db94011d3 139 case 4: irq_handler(can_irq_ids[index], IRQ_WAKEUP); break;
sahilmgandhi 18:6a4db94011d3 140 case 5: irq_handler(can_irq_ids[index], IRQ_PASSIVE); break;
sahilmgandhi 18:6a4db94011d3 141 case 6: irq_handler(can_irq_ids[index], IRQ_ARB); break;
sahilmgandhi 18:6a4db94011d3 142 case 7: irq_handler(can_irq_ids[index], IRQ_BUS); break;
sahilmgandhi 18:6a4db94011d3 143 case 8: irq_handler(can_irq_ids[index], IRQ_READY); break;
sahilmgandhi 18:6a4db94011d3 144 }
sahilmgandhi 18:6a4db94011d3 145 }
sahilmgandhi 18:6a4db94011d3 146 }
sahilmgandhi 18:6a4db94011d3 147 }
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 // Have to check that the CAN block is active before reading the Interrupt
sahilmgandhi 18:6a4db94011d3 150 // Control Register, or the mbed hangs
sahilmgandhi 18:6a4db94011d3 151 void can_irq_n() {
sahilmgandhi 18:6a4db94011d3 152 uint32_t icr;
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 if(LPC_SC->PCONP & (1 << 13)) {
sahilmgandhi 18:6a4db94011d3 155 icr = LPC_CAN1->ICR & 0x1FF;
sahilmgandhi 18:6a4db94011d3 156 can_irq(icr, 0);
sahilmgandhi 18:6a4db94011d3 157 }
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 if(LPC_SC->PCONP & (1 << 14)) {
sahilmgandhi 18:6a4db94011d3 160 icr = LPC_CAN2->ICR & 0x1FF;
sahilmgandhi 18:6a4db94011d3 161 can_irq(icr, 1);
sahilmgandhi 18:6a4db94011d3 162 }
sahilmgandhi 18:6a4db94011d3 163 }
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 // Register CAN object's irq handler
sahilmgandhi 18:6a4db94011d3 166 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
sahilmgandhi 18:6a4db94011d3 167 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 168 can_irq_ids[obj->index] = id;
sahilmgandhi 18:6a4db94011d3 169 }
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 // Unregister CAN object's irq handler
sahilmgandhi 18:6a4db94011d3 172 void can_irq_free(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 173 obj->dev->IER &= ~(1);
sahilmgandhi 18:6a4db94011d3 174 can_irq_ids[obj->index] = 0;
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 if ((can_irq_ids[0] == 0) && (can_irq_ids[1] == 0)) {
sahilmgandhi 18:6a4db94011d3 177 NVIC_DisableIRQ(CAN_IRQn);
sahilmgandhi 18:6a4db94011d3 178 }
sahilmgandhi 18:6a4db94011d3 179 }
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 // Clear or set a irq
sahilmgandhi 18:6a4db94011d3 182 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
sahilmgandhi 18:6a4db94011d3 183 uint32_t ier;
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 switch (type) {
sahilmgandhi 18:6a4db94011d3 186 case IRQ_RX: ier = (1 << 0); break;
sahilmgandhi 18:6a4db94011d3 187 case IRQ_TX: ier = (1 << 1); break;
sahilmgandhi 18:6a4db94011d3 188 case IRQ_ERROR: ier = (1 << 2); break;
sahilmgandhi 18:6a4db94011d3 189 case IRQ_OVERRUN: ier = (1 << 3); break;
sahilmgandhi 18:6a4db94011d3 190 case IRQ_WAKEUP: ier = (1 << 4); break;
sahilmgandhi 18:6a4db94011d3 191 case IRQ_PASSIVE: ier = (1 << 5); break;
sahilmgandhi 18:6a4db94011d3 192 case IRQ_ARB: ier = (1 << 6); break;
sahilmgandhi 18:6a4db94011d3 193 case IRQ_BUS: ier = (1 << 7); break;
sahilmgandhi 18:6a4db94011d3 194 case IRQ_READY: ier = (1 << 8); break;
sahilmgandhi 18:6a4db94011d3 195 default: return;
sahilmgandhi 18:6a4db94011d3 196 }
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 obj->dev->MOD |= 1;
sahilmgandhi 18:6a4db94011d3 199 if(enable == 0) {
sahilmgandhi 18:6a4db94011d3 200 obj->dev->IER &= ~ier;
sahilmgandhi 18:6a4db94011d3 201 }
sahilmgandhi 18:6a4db94011d3 202 else {
sahilmgandhi 18:6a4db94011d3 203 obj->dev->IER |= ier;
sahilmgandhi 18:6a4db94011d3 204 }
sahilmgandhi 18:6a4db94011d3 205 obj->dev->MOD &= ~(1);
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 // Enable NVIC if at least 1 interrupt is active
sahilmgandhi 18:6a4db94011d3 208 if(((LPC_SC->PCONP & (1 << 13)) && LPC_CAN1->IER) || ((LPC_SC->PCONP & (1 << 14)) && LPC_CAN2->IER)) {
sahilmgandhi 18:6a4db94011d3 209 NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n);
sahilmgandhi 18:6a4db94011d3 210 NVIC_EnableIRQ(CAN_IRQn);
sahilmgandhi 18:6a4db94011d3 211 }
sahilmgandhi 18:6a4db94011d3 212 else {
sahilmgandhi 18:6a4db94011d3 213 NVIC_DisableIRQ(CAN_IRQn);
sahilmgandhi 18:6a4db94011d3 214 }
sahilmgandhi 18:6a4db94011d3 215 }
sahilmgandhi 18:6a4db94011d3 216
sahilmgandhi 18:6a4db94011d3 217 static int can_pclk(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 218 int value = 0;
sahilmgandhi 18:6a4db94011d3 219 switch ((int)obj->dev) {
sahilmgandhi 18:6a4db94011d3 220 case CAN_1: value = (LPC_SC->PCLKSEL0 & (0x3 << 26)) >> 26; break;
sahilmgandhi 18:6a4db94011d3 221 case CAN_2: value = (LPC_SC->PCLKSEL0 & (0x3 << 28)) >> 28; break;
sahilmgandhi 18:6a4db94011d3 222 }
sahilmgandhi 18:6a4db94011d3 223
sahilmgandhi 18:6a4db94011d3 224 switch (value) {
sahilmgandhi 18:6a4db94011d3 225 case 1: return 1;
sahilmgandhi 18:6a4db94011d3 226 case 2: return 2;
sahilmgandhi 18:6a4db94011d3 227 case 3: return 6;
sahilmgandhi 18:6a4db94011d3 228 default: return 4;
sahilmgandhi 18:6a4db94011d3 229 }
sahilmgandhi 18:6a4db94011d3 230 }
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 // This table has the sampling points as close to 75% as possible. The first
sahilmgandhi 18:6a4db94011d3 233 // value is TSEG1, the second TSEG2.
sahilmgandhi 18:6a4db94011d3 234 static const int timing_pts[23][2] = {
sahilmgandhi 18:6a4db94011d3 235 {0x0, 0x0}, // 2, 50%
sahilmgandhi 18:6a4db94011d3 236 {0x1, 0x0}, // 3, 67%
sahilmgandhi 18:6a4db94011d3 237 {0x2, 0x0}, // 4, 75%
sahilmgandhi 18:6a4db94011d3 238 {0x3, 0x0}, // 5, 80%
sahilmgandhi 18:6a4db94011d3 239 {0x3, 0x1}, // 6, 67%
sahilmgandhi 18:6a4db94011d3 240 {0x4, 0x1}, // 7, 71%
sahilmgandhi 18:6a4db94011d3 241 {0x5, 0x1}, // 8, 75%
sahilmgandhi 18:6a4db94011d3 242 {0x6, 0x1}, // 9, 78%
sahilmgandhi 18:6a4db94011d3 243 {0x6, 0x2}, // 10, 70%
sahilmgandhi 18:6a4db94011d3 244 {0x7, 0x2}, // 11, 73%
sahilmgandhi 18:6a4db94011d3 245 {0x8, 0x2}, // 12, 75%
sahilmgandhi 18:6a4db94011d3 246 {0x9, 0x2}, // 13, 77%
sahilmgandhi 18:6a4db94011d3 247 {0x9, 0x3}, // 14, 71%
sahilmgandhi 18:6a4db94011d3 248 {0xA, 0x3}, // 15, 73%
sahilmgandhi 18:6a4db94011d3 249 {0xB, 0x3}, // 16, 75%
sahilmgandhi 18:6a4db94011d3 250 {0xC, 0x3}, // 17, 76%
sahilmgandhi 18:6a4db94011d3 251 {0xD, 0x3}, // 18, 78%
sahilmgandhi 18:6a4db94011d3 252 {0xD, 0x4}, // 19, 74%
sahilmgandhi 18:6a4db94011d3 253 {0xE, 0x4}, // 20, 75%
sahilmgandhi 18:6a4db94011d3 254 {0xF, 0x4}, // 21, 76%
sahilmgandhi 18:6a4db94011d3 255 {0xF, 0x5}, // 22, 73%
sahilmgandhi 18:6a4db94011d3 256 {0xF, 0x6}, // 23, 70%
sahilmgandhi 18:6a4db94011d3 257 {0xF, 0x7}, // 24, 67%
sahilmgandhi 18:6a4db94011d3 258 };
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 static unsigned int can_speed(unsigned int sclk, unsigned int pclk, unsigned int cclk, unsigned char psjw) {
sahilmgandhi 18:6a4db94011d3 261 uint32_t btr;
sahilmgandhi 18:6a4db94011d3 262 uint16_t brp = 0;
sahilmgandhi 18:6a4db94011d3 263 uint32_t calcbit;
sahilmgandhi 18:6a4db94011d3 264 uint32_t bitwidth;
sahilmgandhi 18:6a4db94011d3 265 int hit = 0;
sahilmgandhi 18:6a4db94011d3 266 int bits;
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 bitwidth = sclk / (pclk * cclk);
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 brp = bitwidth / 0x18;
sahilmgandhi 18:6a4db94011d3 271 while ((!hit) && (brp < bitwidth / 4)) {
sahilmgandhi 18:6a4db94011d3 272 brp++;
sahilmgandhi 18:6a4db94011d3 273 for (bits = 22; bits > 0; bits--) {
sahilmgandhi 18:6a4db94011d3 274 calcbit = (bits + 3) * (brp + 1);
sahilmgandhi 18:6a4db94011d3 275 if (calcbit == bitwidth) {
sahilmgandhi 18:6a4db94011d3 276 hit = 1;
sahilmgandhi 18:6a4db94011d3 277 break;
sahilmgandhi 18:6a4db94011d3 278 }
sahilmgandhi 18:6a4db94011d3 279 }
sahilmgandhi 18:6a4db94011d3 280 }
sahilmgandhi 18:6a4db94011d3 281
sahilmgandhi 18:6a4db94011d3 282 if (hit) {
sahilmgandhi 18:6a4db94011d3 283 btr = ((timing_pts[bits][1] << 20) & 0x00700000)
sahilmgandhi 18:6a4db94011d3 284 | ((timing_pts[bits][0] << 16) & 0x000F0000)
sahilmgandhi 18:6a4db94011d3 285 | ((psjw << 14) & 0x0000C000)
sahilmgandhi 18:6a4db94011d3 286 | ((brp << 0) & 0x000003FF);
sahilmgandhi 18:6a4db94011d3 287 } else {
sahilmgandhi 18:6a4db94011d3 288 btr = 0xFFFFFFFF;
sahilmgandhi 18:6a4db94011d3 289 }
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 return btr;
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 }
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 void can_init(can_t *obj, PinName rd, PinName td) {
sahilmgandhi 18:6a4db94011d3 296 CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
sahilmgandhi 18:6a4db94011d3 297 CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
sahilmgandhi 18:6a4db94011d3 298 obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
sahilmgandhi 18:6a4db94011d3 299 MBED_ASSERT((int)obj->dev != NC);
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 switch ((int)obj->dev) {
sahilmgandhi 18:6a4db94011d3 302 case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
sahilmgandhi 18:6a4db94011d3 303 case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
sahilmgandhi 18:6a4db94011d3 304 }
sahilmgandhi 18:6a4db94011d3 305
sahilmgandhi 18:6a4db94011d3 306 pinmap_pinout(rd, PinMap_CAN_RD);
sahilmgandhi 18:6a4db94011d3 307 pinmap_pinout(td, PinMap_CAN_TD);
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 switch ((int)obj->dev) {
sahilmgandhi 18:6a4db94011d3 310 case CAN_1: obj->index = 0; break;
sahilmgandhi 18:6a4db94011d3 311 case CAN_2: obj->index = 1; break;
sahilmgandhi 18:6a4db94011d3 312 }
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 can_reset(obj);
sahilmgandhi 18:6a4db94011d3 315 obj->dev->IER = 0; // Disable Interrupts
sahilmgandhi 18:6a4db94011d3 316 can_frequency(obj, 100000);
sahilmgandhi 18:6a4db94011d3 317
sahilmgandhi 18:6a4db94011d3 318 LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
sahilmgandhi 18:6a4db94011d3 319 }
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 void can_free(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 322 switch ((int)obj->dev) {
sahilmgandhi 18:6a4db94011d3 323 case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
sahilmgandhi 18:6a4db94011d3 324 case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
sahilmgandhi 18:6a4db94011d3 325 }
sahilmgandhi 18:6a4db94011d3 326 }
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 int can_frequency(can_t *obj, int f) {
sahilmgandhi 18:6a4db94011d3 329 int pclk = can_pclk(obj);
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 int btr = can_speed(SystemCoreClock, pclk, (unsigned int)f, 1);
sahilmgandhi 18:6a4db94011d3 332
sahilmgandhi 18:6a4db94011d3 333 if (btr > 0) {
sahilmgandhi 18:6a4db94011d3 334 uint32_t modmask = can_disable(obj);
sahilmgandhi 18:6a4db94011d3 335 obj->dev->BTR = btr;
sahilmgandhi 18:6a4db94011d3 336 obj->dev->MOD = modmask;
sahilmgandhi 18:6a4db94011d3 337 return 1;
sahilmgandhi 18:6a4db94011d3 338 } else {
sahilmgandhi 18:6a4db94011d3 339 return 0;
sahilmgandhi 18:6a4db94011d3 340 }
sahilmgandhi 18:6a4db94011d3 341 }
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 int can_write(can_t *obj, CAN_Message msg, int cc) {
sahilmgandhi 18:6a4db94011d3 344 unsigned int CANStatus;
sahilmgandhi 18:6a4db94011d3 345 CANMsg m;
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 can_enable(obj);
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 m.id = msg.id ;
sahilmgandhi 18:6a4db94011d3 350 m.dlc = msg.len & 0xF;
sahilmgandhi 18:6a4db94011d3 351 m.rtr = msg.type;
sahilmgandhi 18:6a4db94011d3 352 m.type = msg.format;
sahilmgandhi 18:6a4db94011d3 353 memcpy(m.data, msg.data, msg.len);
sahilmgandhi 18:6a4db94011d3 354 const unsigned int *buf = (const unsigned int *)&m;
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 CANStatus = obj->dev->SR;
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 // Send the message to ourself if in a test mode
sahilmgandhi 18:6a4db94011d3 359 if (obj->dev->MOD & 0x04) {
sahilmgandhi 18:6a4db94011d3 360 cc = 1;
sahilmgandhi 18:6a4db94011d3 361 }
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 if (CANStatus & 0x00000004) {
sahilmgandhi 18:6a4db94011d3 364 obj->dev->TFI1 = buf[0] & 0xC00F0000;
sahilmgandhi 18:6a4db94011d3 365 obj->dev->TID1 = buf[1];
sahilmgandhi 18:6a4db94011d3 366 obj->dev->TDA1 = buf[2];
sahilmgandhi 18:6a4db94011d3 367 obj->dev->TDB1 = buf[3];
sahilmgandhi 18:6a4db94011d3 368 if(cc) {
sahilmgandhi 18:6a4db94011d3 369 obj->dev->CMR = 0x30;
sahilmgandhi 18:6a4db94011d3 370 } else {
sahilmgandhi 18:6a4db94011d3 371 obj->dev->CMR = 0x21;
sahilmgandhi 18:6a4db94011d3 372 }
sahilmgandhi 18:6a4db94011d3 373 return 1;
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375 } else if (CANStatus & 0x00000400) {
sahilmgandhi 18:6a4db94011d3 376 obj->dev->TFI2 = buf[0] & 0xC00F0000;
sahilmgandhi 18:6a4db94011d3 377 obj->dev->TID2 = buf[1];
sahilmgandhi 18:6a4db94011d3 378 obj->dev->TDA2 = buf[2];
sahilmgandhi 18:6a4db94011d3 379 obj->dev->TDB2 = buf[3];
sahilmgandhi 18:6a4db94011d3 380 if (cc) {
sahilmgandhi 18:6a4db94011d3 381 obj->dev->CMR = 0x50;
sahilmgandhi 18:6a4db94011d3 382 } else {
sahilmgandhi 18:6a4db94011d3 383 obj->dev->CMR = 0x41;
sahilmgandhi 18:6a4db94011d3 384 }
sahilmgandhi 18:6a4db94011d3 385 return 1;
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 } else if (CANStatus & 0x00040000) {
sahilmgandhi 18:6a4db94011d3 388 obj->dev->TFI3 = buf[0] & 0xC00F0000;
sahilmgandhi 18:6a4db94011d3 389 obj->dev->TID3 = buf[1];
sahilmgandhi 18:6a4db94011d3 390 obj->dev->TDA3 = buf[2];
sahilmgandhi 18:6a4db94011d3 391 obj->dev->TDB3 = buf[3];
sahilmgandhi 18:6a4db94011d3 392 if (cc) {
sahilmgandhi 18:6a4db94011d3 393 obj->dev->CMR = 0x90;
sahilmgandhi 18:6a4db94011d3 394 } else {
sahilmgandhi 18:6a4db94011d3 395 obj->dev->CMR = 0x81;
sahilmgandhi 18:6a4db94011d3 396 }
sahilmgandhi 18:6a4db94011d3 397 return 1;
sahilmgandhi 18:6a4db94011d3 398 }
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 return 0;
sahilmgandhi 18:6a4db94011d3 401 }
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 int can_read(can_t *obj, CAN_Message *msg, int handle) {
sahilmgandhi 18:6a4db94011d3 404 CANMsg x;
sahilmgandhi 18:6a4db94011d3 405 unsigned int *i = (unsigned int *)&x;
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 can_enable(obj);
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 if (obj->dev->GSR & 0x1) {
sahilmgandhi 18:6a4db94011d3 410 *i++ = obj->dev->RFS; // Frame
sahilmgandhi 18:6a4db94011d3 411 *i++ = obj->dev->RID; // ID
sahilmgandhi 18:6a4db94011d3 412 *i++ = obj->dev->RDA; // Data A
sahilmgandhi 18:6a4db94011d3 413 *i++ = obj->dev->RDB; // Data B
sahilmgandhi 18:6a4db94011d3 414 obj->dev->CMR = 0x04; // release receive buffer
sahilmgandhi 18:6a4db94011d3 415
sahilmgandhi 18:6a4db94011d3 416 msg->id = x.id;
sahilmgandhi 18:6a4db94011d3 417 msg->len = x.dlc;
sahilmgandhi 18:6a4db94011d3 418 msg->format = (x.type)? CANExtended : CANStandard;
sahilmgandhi 18:6a4db94011d3 419 msg->type = (x.rtr)? CANRemote: CANData;
sahilmgandhi 18:6a4db94011d3 420 memcpy(msg->data,x.data,x.dlc);
sahilmgandhi 18:6a4db94011d3 421 return 1;
sahilmgandhi 18:6a4db94011d3 422 }
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 return 0;
sahilmgandhi 18:6a4db94011d3 425 }
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 void can_reset(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 428 can_disable(obj);
sahilmgandhi 18:6a4db94011d3 429 obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
sahilmgandhi 18:6a4db94011d3 430 }
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 unsigned char can_rderror(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 433 return (obj->dev->GSR >> 16) & 0xFF;
sahilmgandhi 18:6a4db94011d3 434 }
sahilmgandhi 18:6a4db94011d3 435
sahilmgandhi 18:6a4db94011d3 436 unsigned char can_tderror(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 437 return (obj->dev->GSR >> 24) & 0xFF;
sahilmgandhi 18:6a4db94011d3 438 }
sahilmgandhi 18:6a4db94011d3 439
sahilmgandhi 18:6a4db94011d3 440 void can_monitor(can_t *obj, int silent) {
sahilmgandhi 18:6a4db94011d3 441 uint32_t mod_mask = can_disable(obj);
sahilmgandhi 18:6a4db94011d3 442 if (silent) {
sahilmgandhi 18:6a4db94011d3 443 obj->dev->MOD |= (1 << 1);
sahilmgandhi 18:6a4db94011d3 444 } else {
sahilmgandhi 18:6a4db94011d3 445 obj->dev->MOD &= ~(1 << 1);
sahilmgandhi 18:6a4db94011d3 446 }
sahilmgandhi 18:6a4db94011d3 447 if (!(mod_mask & 1)) {
sahilmgandhi 18:6a4db94011d3 448 can_enable(obj);
sahilmgandhi 18:6a4db94011d3 449 }
sahilmgandhi 18:6a4db94011d3 450 }