MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC15XX/can_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 #include "can_api.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 20 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 #include <math.h>
sahilmgandhi 18:6a4db94011d3 23 #include <string.h>
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 /* Handy defines */
sahilmgandhi 18:6a4db94011d3 26 #define RX_MSG_OBJ_COUNT 31
sahilmgandhi 18:6a4db94011d3 27 #define TX_MSG_OBJ_COUNT 1
sahilmgandhi 18:6a4db94011d3 28 #define DLC_MAX 8
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 #define ID_STD_MASK 0x07FF
sahilmgandhi 18:6a4db94011d3 31 #define ID_EXT_MASK 0x1FFFFFFF
sahilmgandhi 18:6a4db94011d3 32 #define DLC_MASK 0x0F
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 #define CANIFn_ARB2_DIR (1UL << 13)
sahilmgandhi 18:6a4db94011d3 35 #define CANIFn_ARB2_XTD (1UL << 14)
sahilmgandhi 18:6a4db94011d3 36 #define CANIFn_ARB2_MSGVAL (1UL << 15)
sahilmgandhi 18:6a4db94011d3 37 #define CANIFn_MSK2_MXTD (1UL << 15)
sahilmgandhi 18:6a4db94011d3 38 #define CANIFn_MSK2_MDIR (1UL << 14)
sahilmgandhi 18:6a4db94011d3 39 #define CANIFn_MCTRL_EOB (1UL << 7)
sahilmgandhi 18:6a4db94011d3 40 #define CANIFn_MCTRL_TXRQST (1UL << 8)
sahilmgandhi 18:6a4db94011d3 41 #define CANIFn_MCTRL_RMTEN (1UL << 9)
sahilmgandhi 18:6a4db94011d3 42 #define CANIFn_MCTRL_RXIE (1UL << 10)
sahilmgandhi 18:6a4db94011d3 43 #define CANIFn_MCTRL_TXIE (1UL << 11)
sahilmgandhi 18:6a4db94011d3 44 #define CANIFn_MCTRL_UMASK (1UL << 12)
sahilmgandhi 18:6a4db94011d3 45 #define CANIFn_MCTRL_INTPND (1UL << 13)
sahilmgandhi 18:6a4db94011d3 46 #define CANIFn_MCTRL_MSGLST (1UL << 14)
sahilmgandhi 18:6a4db94011d3 47 #define CANIFn_MCTRL_NEWDAT (1UL << 15)
sahilmgandhi 18:6a4db94011d3 48 #define CANIFn_CMDMSK_DATA_B (1UL << 0)
sahilmgandhi 18:6a4db94011d3 49 #define CANIFn_CMDMSK_DATA_A (1UL << 1)
sahilmgandhi 18:6a4db94011d3 50 #define CANIFn_CMDMSK_TXRQST (1UL << 2)
sahilmgandhi 18:6a4db94011d3 51 #define CANIFn_CMDMSK_NEWDAT (1UL << 2)
sahilmgandhi 18:6a4db94011d3 52 #define CANIFn_CMDMSK_CLRINTPND (1UL << 3)
sahilmgandhi 18:6a4db94011d3 53 #define CANIFn_CMDMSK_CTRL (1UL << 4)
sahilmgandhi 18:6a4db94011d3 54 #define CANIFn_CMDMSK_ARB (1UL << 5)
sahilmgandhi 18:6a4db94011d3 55 #define CANIFn_CMDMSK_MASK (1UL << 6)
sahilmgandhi 18:6a4db94011d3 56 #define CANIFn_CMDMSK_WR (1UL << 7)
sahilmgandhi 18:6a4db94011d3 57 #define CANIFn_CMDMSK_RD (0UL << 7)
sahilmgandhi 18:6a4db94011d3 58 #define CANIFn_CMDREQ_BUSY (1UL << 15)
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 #define CANSTAT_TXOK (1 << 3) // Transmitted a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
sahilmgandhi 18:6a4db94011d3 61 #define CANSTAT_RXOK (1 << 4) // Received a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
sahilmgandhi 18:6a4db94011d3 62 #define CANSTAT_EPASS (1 << 5) // Error passive
sahilmgandhi 18:6a4db94011d3 63 #define CANSTAT_EWARN (1 << 6) // Warning status
sahilmgandhi 18:6a4db94011d3 64 #define CANSTAT_BOFF (1 << 7) // Busoff status
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 #define CANCNTL_INIT (1 << 0) // Initialization
sahilmgandhi 18:6a4db94011d3 67 #define CANCNTL_IE (1 << 1) // Module interrupt enable
sahilmgandhi 18:6a4db94011d3 68 #define CANCNTL_SIE (1 << 2) // Status change interrupt enable
sahilmgandhi 18:6a4db94011d3 69 #define CANCNTL_EIE (1 << 3) // Error interrupt enable
sahilmgandhi 18:6a4db94011d3 70 #define CANCNTL_DAR (1 << 5) // Disable automatic retransmission
sahilmgandhi 18:6a4db94011d3 71 #define CANCNTL_CCE (1 << 6) // Configuration change enable
sahilmgandhi 18:6a4db94011d3 72 #define CANCNTL_TEST (1 << 7) // Test mode enable
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 #define CANTEST_BASIC (1 << 2) // Basic mode
sahilmgandhi 18:6a4db94011d3 75 #define CANTEST_SILENT (1 << 3) // Silent mode
sahilmgandhi 18:6a4db94011d3 76 #define CANTEST_LBACK (1 << 4) // Loop back mode
sahilmgandhi 18:6a4db94011d3 77 #define CANTEST_TX_MASK 0x0060 // Control of CAN_TXD pins
sahilmgandhi 18:6a4db94011d3 78 #define CANTEST_TX_SHIFT 5
sahilmgandhi 18:6a4db94011d3 79 #define CANTEST_RX (1 << 7) // Monitors the actual value of the CAN_RXD pin.
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 static uint32_t can_irq_id = 0;
sahilmgandhi 18:6a4db94011d3 82 static can_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 #define IRQ_ENABLE_TX (1 << 0)
sahilmgandhi 18:6a4db94011d3 85 #define IRQ_ENABLE_RX (1 << 1)
sahilmgandhi 18:6a4db94011d3 86 #define IRQ_ENABLE_EW (1 << 2)
sahilmgandhi 18:6a4db94011d3 87 #define IRQ_ENABLE_EP (1 << 3)
sahilmgandhi 18:6a4db94011d3 88 #define IRQ_ENABLE_BE (1 << 4)
sahilmgandhi 18:6a4db94011d3 89 #define IRQ_ENABLE_STATUS (IRQ_ENABLE_TX | IRQ_ENABLE_RX)
sahilmgandhi 18:6a4db94011d3 90 #define IRQ_ENABLE_ERROR (IRQ_ENABLE_EW | IRQ_ENABLE_EP | IRQ_ENABLE_BE)
sahilmgandhi 18:6a4db94011d3 91 #define IRQ_ENABLE_ANY (IRQ_ENABLE_STATUS | IRQ_ENABLE_ERROR)
sahilmgandhi 18:6a4db94011d3 92 static uint32_t enabled_irqs = 0;
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 static inline void can_disable(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 95 LPC_C_CAN0->CANCNTL |= 0x1;
sahilmgandhi 18:6a4db94011d3 96 }
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 static inline void can_enable(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 99 if (LPC_C_CAN0->CANCNTL & 0x1) {
sahilmgandhi 18:6a4db94011d3 100 LPC_C_CAN0->CANCNTL &= ~(0x1);
sahilmgandhi 18:6a4db94011d3 101 }
sahilmgandhi 18:6a4db94011d3 102 }
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 int can_mode(can_t *obj, CanMode mode) {
sahilmgandhi 18:6a4db94011d3 105 int success = 0;
sahilmgandhi 18:6a4db94011d3 106 switch (mode) {
sahilmgandhi 18:6a4db94011d3 107 case MODE_RESET:
sahilmgandhi 18:6a4db94011d3 108 LPC_C_CAN0->CANCNTL &=~CANCNTL_TEST;
sahilmgandhi 18:6a4db94011d3 109 can_disable(obj);
sahilmgandhi 18:6a4db94011d3 110 success = 1;
sahilmgandhi 18:6a4db94011d3 111 break;
sahilmgandhi 18:6a4db94011d3 112 case MODE_NORMAL:
sahilmgandhi 18:6a4db94011d3 113 LPC_C_CAN0->CANCNTL &=~CANCNTL_TEST;
sahilmgandhi 18:6a4db94011d3 114 can_enable(obj);
sahilmgandhi 18:6a4db94011d3 115 success = 1;
sahilmgandhi 18:6a4db94011d3 116 break;
sahilmgandhi 18:6a4db94011d3 117 case MODE_SILENT:
sahilmgandhi 18:6a4db94011d3 118 LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
sahilmgandhi 18:6a4db94011d3 119 LPC_C_CAN0->CANTEST |= CANTEST_SILENT;
sahilmgandhi 18:6a4db94011d3 120 LPC_C_CAN0->CANTEST &=~ CANTEST_LBACK;
sahilmgandhi 18:6a4db94011d3 121 success = 1;
sahilmgandhi 18:6a4db94011d3 122 break;
sahilmgandhi 18:6a4db94011d3 123 case MODE_TEST_LOCAL:
sahilmgandhi 18:6a4db94011d3 124 LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
sahilmgandhi 18:6a4db94011d3 125 LPC_C_CAN0->CANTEST &=~CANTEST_SILENT;
sahilmgandhi 18:6a4db94011d3 126 LPC_C_CAN0->CANTEST |= CANTEST_LBACK;
sahilmgandhi 18:6a4db94011d3 127 success = 1;
sahilmgandhi 18:6a4db94011d3 128 break;
sahilmgandhi 18:6a4db94011d3 129 case MODE_TEST_SILENT:
sahilmgandhi 18:6a4db94011d3 130 LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
sahilmgandhi 18:6a4db94011d3 131 LPC_C_CAN0->CANTEST |= (CANTEST_LBACK | CANTEST_SILENT);
sahilmgandhi 18:6a4db94011d3 132 success = 1;
sahilmgandhi 18:6a4db94011d3 133 break;
sahilmgandhi 18:6a4db94011d3 134 case MODE_TEST_GLOBAL:
sahilmgandhi 18:6a4db94011d3 135 default:
sahilmgandhi 18:6a4db94011d3 136 success = 0;
sahilmgandhi 18:6a4db94011d3 137 break;
sahilmgandhi 18:6a4db94011d3 138 }
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 return success;
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
sahilmgandhi 18:6a4db94011d3 144 uint16_t i;
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 // Find first free message object
sahilmgandhi 18:6a4db94011d3 147 if (handle == 0) {
sahilmgandhi 18:6a4db94011d3 148 uint32_t msgval = LPC_C_CAN0->CANMSGV1 | (LPC_C_CAN0->CANMSGV2 << 16);
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150 // Find first free messagebox
sahilmgandhi 18:6a4db94011d3 151 for (i = 0; i < 32; i++) {
sahilmgandhi 18:6a4db94011d3 152 if ((msgval & (1 << i)) == 0) {
sahilmgandhi 18:6a4db94011d3 153 handle = i+1;
sahilmgandhi 18:6a4db94011d3 154 break;
sahilmgandhi 18:6a4db94011d3 155 }
sahilmgandhi 18:6a4db94011d3 156 }
sahilmgandhi 18:6a4db94011d3 157 }
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 if (handle > 0 && handle <= 32) {
sahilmgandhi 18:6a4db94011d3 160 if (format == CANExtended) {
sahilmgandhi 18:6a4db94011d3 161 // Mark message valid, Direction = TX, Extended Frame, Set Identifier and mask everything
sahilmgandhi 18:6a4db94011d3 162 LPC_C_CAN0->CANIF1_ARB1 = (id & 0xFFFF);
sahilmgandhi 18:6a4db94011d3 163 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | ((id >> 16) & 0x1FFF);
sahilmgandhi 18:6a4db94011d3 164 LPC_C_CAN0->CANIF1_MSK1 = (mask & 0xFFFF);
sahilmgandhi 18:6a4db94011d3 165 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD /*| CANIFn_MSK2_MDIR*/ | ((mask >> 16) & 0x1FFF);
sahilmgandhi 18:6a4db94011d3 166 } else {
sahilmgandhi 18:6a4db94011d3 167 // Mark message valid, Direction = TX, Set Identifier and mask everything
sahilmgandhi 18:6a4db94011d3 168 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | ((id << 2) & 0x1FFF);
sahilmgandhi 18:6a4db94011d3 169 LPC_C_CAN0->CANIF1_MSK2 = /*CANIFn_MSK2_MDIR |*/ ((mask << 2) & 0x1FFF);
sahilmgandhi 18:6a4db94011d3 170 }
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 // Use mask, single message object and set DLC
sahilmgandhi 18:6a4db94011d3 173 LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_EOB | (DLC_MAX & 0xF);
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 // Transfer all fields to message object
sahilmgandhi 18:6a4db94011d3 176 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 // Start Transfer to given message number
sahilmgandhi 18:6a4db94011d3 179 LPC_C_CAN0->CANIF1_CMDREQ = (handle & 0x3F);
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 // Wait until transfer to message ram complete - TODO: maybe not block??
sahilmgandhi 18:6a4db94011d3 182 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
sahilmgandhi 18:6a4db94011d3 183 }
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 return handle;
sahilmgandhi 18:6a4db94011d3 186 }
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 static inline void can_irq() {
sahilmgandhi 18:6a4db94011d3 189 uint32_t intid = LPC_C_CAN0->CANINT & 0xFFFF;
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 if (intid == 0x8000) {
sahilmgandhi 18:6a4db94011d3 192 uint32_t status = LPC_C_CAN0->CANSTAT;
sahilmgandhi 18:6a4db94011d3 193 // Note that since it's impossible to tell which specific status caused
sahilmgandhi 18:6a4db94011d3 194 // the interrupt to fire, this just fires them all.
sahilmgandhi 18:6a4db94011d3 195 // In particular, EWARN is not mutually exclusive with the others and
sahilmgandhi 18:6a4db94011d3 196 // may fire multiple times with other status transitions, including
sahilmgandhi 18:6a4db94011d3 197 // transmit and receive completion (if enabled). Ignoring EWARN with a
sahilmgandhi 18:6a4db94011d3 198 // priority system (i.e. blocking EWARN interrupts if EPASS or BOFF is
sahilmgandhi 18:6a4db94011d3 199 // set) may discard some EWARN interrupts.
sahilmgandhi 18:6a4db94011d3 200 if (status & CANSTAT_BOFF) {
sahilmgandhi 18:6a4db94011d3 201 if (enabled_irqs & IRQ_ENABLE_BE) {
sahilmgandhi 18:6a4db94011d3 202 irq_handler(can_irq_id, IRQ_BUS);
sahilmgandhi 18:6a4db94011d3 203 }
sahilmgandhi 18:6a4db94011d3 204 }
sahilmgandhi 18:6a4db94011d3 205 if (status & CANSTAT_EPASS) {
sahilmgandhi 18:6a4db94011d3 206 if (enabled_irqs & IRQ_ENABLE_EP) {
sahilmgandhi 18:6a4db94011d3 207 irq_handler(can_irq_id, IRQ_PASSIVE);
sahilmgandhi 18:6a4db94011d3 208 }
sahilmgandhi 18:6a4db94011d3 209 }
sahilmgandhi 18:6a4db94011d3 210 if (status & CANSTAT_EWARN) {
sahilmgandhi 18:6a4db94011d3 211 if (enabled_irqs & IRQ_ENABLE_EW) {
sahilmgandhi 18:6a4db94011d3 212 irq_handler(can_irq_id, IRQ_ERROR);
sahilmgandhi 18:6a4db94011d3 213 }
sahilmgandhi 18:6a4db94011d3 214 }
sahilmgandhi 18:6a4db94011d3 215 if ((status & CANSTAT_RXOK) != 0) {
sahilmgandhi 18:6a4db94011d3 216 LPC_C_CAN0->CANSTAT &= ~CANSTAT_RXOK;
sahilmgandhi 18:6a4db94011d3 217 irq_handler(can_irq_id, IRQ_RX);
sahilmgandhi 18:6a4db94011d3 218 }
sahilmgandhi 18:6a4db94011d3 219 if ((status & CANSTAT_TXOK) != 0) {
sahilmgandhi 18:6a4db94011d3 220 LPC_C_CAN0->CANSTAT &= ~CANSTAT_TXOK;
sahilmgandhi 18:6a4db94011d3 221 irq_handler(can_irq_id, IRQ_TX);
sahilmgandhi 18:6a4db94011d3 222 }
sahilmgandhi 18:6a4db94011d3 223 }
sahilmgandhi 18:6a4db94011d3 224 }
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 // Register CAN object's irq handler
sahilmgandhi 18:6a4db94011d3 227 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
sahilmgandhi 18:6a4db94011d3 228 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 229 can_irq_id = id;
sahilmgandhi 18:6a4db94011d3 230 }
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 // Unregister CAN object's irq handler
sahilmgandhi 18:6a4db94011d3 233 void can_irq_free(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 234 LPC_C_CAN0->CANCNTL &= ~(1UL << 1); // Disable Interrupts :)
sahilmgandhi 18:6a4db94011d3 235 can_irq_id = 0;
sahilmgandhi 18:6a4db94011d3 236 NVIC_DisableIRQ(C_CAN0_IRQn);
sahilmgandhi 18:6a4db94011d3 237 }
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 // Clear or set a irq
sahilmgandhi 18:6a4db94011d3 240 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
sahilmgandhi 18:6a4db94011d3 241 uint32_t mask_enable;
sahilmgandhi 18:6a4db94011d3 242 switch (type) {
sahilmgandhi 18:6a4db94011d3 243 case IRQ_RX:
sahilmgandhi 18:6a4db94011d3 244 mask_enable = IRQ_ENABLE_RX;
sahilmgandhi 18:6a4db94011d3 245 break;
sahilmgandhi 18:6a4db94011d3 246 case IRQ_TX:
sahilmgandhi 18:6a4db94011d3 247 mask_enable = IRQ_ENABLE_TX;
sahilmgandhi 18:6a4db94011d3 248 break;
sahilmgandhi 18:6a4db94011d3 249 case IRQ_BUS:
sahilmgandhi 18:6a4db94011d3 250 mask_enable = IRQ_ENABLE_BE;
sahilmgandhi 18:6a4db94011d3 251 break;
sahilmgandhi 18:6a4db94011d3 252 case IRQ_PASSIVE:
sahilmgandhi 18:6a4db94011d3 253 mask_enable = IRQ_ENABLE_EP;
sahilmgandhi 18:6a4db94011d3 254 break;
sahilmgandhi 18:6a4db94011d3 255 case IRQ_ERROR:
sahilmgandhi 18:6a4db94011d3 256 mask_enable = IRQ_ENABLE_EW;
sahilmgandhi 18:6a4db94011d3 257 break;
sahilmgandhi 18:6a4db94011d3 258 default:
sahilmgandhi 18:6a4db94011d3 259 return;
sahilmgandhi 18:6a4db94011d3 260 }
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 if (enable) {
sahilmgandhi 18:6a4db94011d3 263 enabled_irqs = enabled_irqs | mask_enable;
sahilmgandhi 18:6a4db94011d3 264 } else {
sahilmgandhi 18:6a4db94011d3 265 enabled_irqs = enabled_irqs & ~mask_enable;
sahilmgandhi 18:6a4db94011d3 266 }
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 // Put CAN in Reset Mode and enable interrupt
sahilmgandhi 18:6a4db94011d3 269 can_disable(obj);
sahilmgandhi 18:6a4db94011d3 270 if (!(enabled_irqs & IRQ_ENABLE_ANY)) {
sahilmgandhi 18:6a4db94011d3 271 LPC_C_CAN0->CANCNTL &= ~(1UL << 1 | 1UL << 2 | 1UL << 3);
sahilmgandhi 18:6a4db94011d3 272 } else {
sahilmgandhi 18:6a4db94011d3 273 LPC_C_CAN0->CANCNTL |= 1UL << 1;
sahilmgandhi 18:6a4db94011d3 274 // Use status interrupts instead of message interrupts to avoid
sahilmgandhi 18:6a4db94011d3 275 // stomping over potential filter configurations.
sahilmgandhi 18:6a4db94011d3 276 if (enabled_irqs & IRQ_ENABLE_STATUS) {
sahilmgandhi 18:6a4db94011d3 277 LPC_C_CAN0->CANCNTL |= 1UL << 2;
sahilmgandhi 18:6a4db94011d3 278 } else {
sahilmgandhi 18:6a4db94011d3 279 LPC_C_CAN0->CANCNTL &= ~(1UL << 2);
sahilmgandhi 18:6a4db94011d3 280 }
sahilmgandhi 18:6a4db94011d3 281 if (enabled_irqs & IRQ_ENABLE_ERROR) {
sahilmgandhi 18:6a4db94011d3 282 LPC_C_CAN0->CANCNTL |= 1UL << 3;
sahilmgandhi 18:6a4db94011d3 283 } else {
sahilmgandhi 18:6a4db94011d3 284 LPC_C_CAN0->CANCNTL &= ~(1UL << 3);
sahilmgandhi 18:6a4db94011d3 285 }
sahilmgandhi 18:6a4db94011d3 286 }
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 // Take it out of reset...
sahilmgandhi 18:6a4db94011d3 289 can_enable(obj);
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 // Enable NVIC if at least 1 interrupt is active
sahilmgandhi 18:6a4db94011d3 292 NVIC_SetVector(C_CAN0_IRQn, (uint32_t) &can_irq);
sahilmgandhi 18:6a4db94011d3 293 NVIC_EnableIRQ(C_CAN0_IRQn);
sahilmgandhi 18:6a4db94011d3 294 }
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 // This table has the sampling points as close to 75% as possible. The first
sahilmgandhi 18:6a4db94011d3 297 // value is TSEG1, the second TSEG2.
sahilmgandhi 18:6a4db94011d3 298 static const int timing_pts[23][2] = {
sahilmgandhi 18:6a4db94011d3 299 {0x0, 0x0}, // 2, 50%
sahilmgandhi 18:6a4db94011d3 300 {0x1, 0x0}, // 3, 67%
sahilmgandhi 18:6a4db94011d3 301 {0x2, 0x0}, // 4, 75%
sahilmgandhi 18:6a4db94011d3 302 {0x3, 0x0}, // 5, 80%
sahilmgandhi 18:6a4db94011d3 303 {0x3, 0x1}, // 6, 67%
sahilmgandhi 18:6a4db94011d3 304 {0x4, 0x1}, // 7, 71%
sahilmgandhi 18:6a4db94011d3 305 {0x5, 0x1}, // 8, 75%
sahilmgandhi 18:6a4db94011d3 306 {0x6, 0x1}, // 9, 78%
sahilmgandhi 18:6a4db94011d3 307 {0x6, 0x2}, // 10, 70%
sahilmgandhi 18:6a4db94011d3 308 {0x7, 0x2}, // 11, 73%
sahilmgandhi 18:6a4db94011d3 309 {0x8, 0x2}, // 12, 75%
sahilmgandhi 18:6a4db94011d3 310 {0x9, 0x2}, // 13, 77%
sahilmgandhi 18:6a4db94011d3 311 {0x9, 0x3}, // 14, 71%
sahilmgandhi 18:6a4db94011d3 312 {0xA, 0x3}, // 15, 73%
sahilmgandhi 18:6a4db94011d3 313 {0xB, 0x3}, // 16, 75%
sahilmgandhi 18:6a4db94011d3 314 {0xC, 0x3}, // 17, 76%
sahilmgandhi 18:6a4db94011d3 315 {0xD, 0x3}, // 18, 78%
sahilmgandhi 18:6a4db94011d3 316 {0xD, 0x4}, // 19, 74%
sahilmgandhi 18:6a4db94011d3 317 {0xE, 0x4}, // 20, 75%
sahilmgandhi 18:6a4db94011d3 318 {0xF, 0x4}, // 21, 76%
sahilmgandhi 18:6a4db94011d3 319 {0xF, 0x5}, // 22, 73%
sahilmgandhi 18:6a4db94011d3 320 {0xF, 0x6}, // 23, 70%
sahilmgandhi 18:6a4db94011d3 321 {0xF, 0x7}, // 24, 67%
sahilmgandhi 18:6a4db94011d3 322 };
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 static unsigned int can_speed(unsigned int sclk, unsigned int cclk, unsigned char psjw) {
sahilmgandhi 18:6a4db94011d3 325 uint32_t btr;
sahilmgandhi 18:6a4db94011d3 326 uint32_t clkdiv = 1;
sahilmgandhi 18:6a4db94011d3 327 uint16_t brp = 0;
sahilmgandhi 18:6a4db94011d3 328 uint32_t calcbit;
sahilmgandhi 18:6a4db94011d3 329 uint32_t bitwidth;
sahilmgandhi 18:6a4db94011d3 330 int hit = 0;
sahilmgandhi 18:6a4db94011d3 331 int bits = 0;
sahilmgandhi 18:6a4db94011d3 332
sahilmgandhi 18:6a4db94011d3 333 bitwidth = sclk / cclk;
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 brp = bitwidth / 0x18;
sahilmgandhi 18:6a4db94011d3 336 while ((!hit) && (brp < bitwidth / 4)) {
sahilmgandhi 18:6a4db94011d3 337 brp++;
sahilmgandhi 18:6a4db94011d3 338 for (bits = 22; bits > 0; bits--) {
sahilmgandhi 18:6a4db94011d3 339 calcbit = (bits + 3) * (brp + 1);
sahilmgandhi 18:6a4db94011d3 340 if (calcbit == bitwidth) {
sahilmgandhi 18:6a4db94011d3 341 hit = 1;
sahilmgandhi 18:6a4db94011d3 342 break;
sahilmgandhi 18:6a4db94011d3 343 }
sahilmgandhi 18:6a4db94011d3 344 }
sahilmgandhi 18:6a4db94011d3 345 }
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 clkdiv = clkdiv - 1;
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 if (hit) {
sahilmgandhi 18:6a4db94011d3 350 btr = (timing_pts[bits][1] & 0x7) << 12
sahilmgandhi 18:6a4db94011d3 351 | (timing_pts[bits][0] & 0xf) << 8
sahilmgandhi 18:6a4db94011d3 352 | (psjw & 0x3) << 6
sahilmgandhi 18:6a4db94011d3 353 | (brp & 0x3F);
sahilmgandhi 18:6a4db94011d3 354 btr = btr | (clkdiv << 16);
sahilmgandhi 18:6a4db94011d3 355 } else {
sahilmgandhi 18:6a4db94011d3 356 btr = 0;
sahilmgandhi 18:6a4db94011d3 357 }
sahilmgandhi 18:6a4db94011d3 358
sahilmgandhi 18:6a4db94011d3 359 return btr;
sahilmgandhi 18:6a4db94011d3 360 }
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 int can_config_rxmsgobj(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 364 uint16_t i = 0;
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 // Make sure the interface is available
sahilmgandhi 18:6a4db94011d3 367 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
sahilmgandhi 18:6a4db94011d3 368
sahilmgandhi 18:6a4db94011d3 369 // Mark message valid, Direction = RX, Don't care about anything else
sahilmgandhi 18:6a4db94011d3 370 LPC_C_CAN0->CANIF1_ARB1 = 0;
sahilmgandhi 18:6a4db94011d3 371 LPC_C_CAN0->CANIF1_ARB2 = 0;
sahilmgandhi 18:6a4db94011d3 372 LPC_C_CAN0->CANIF1_MCTRL = 0;
sahilmgandhi 18:6a4db94011d3 373
sahilmgandhi 18:6a4db94011d3 374 for ( i = 1; i <= RX_MSG_OBJ_COUNT; i++ ) {
sahilmgandhi 18:6a4db94011d3 375 // Transfer arb and control fields to message object
sahilmgandhi 18:6a4db94011d3 376 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378 // Start Transfer to given message number
sahilmgandhi 18:6a4db94011d3 379 LPC_C_CAN0->CANIF1_CMDREQ = (i & 0x3F);
sahilmgandhi 18:6a4db94011d3 380
sahilmgandhi 18:6a4db94011d3 381 // Wait until transfer to message ram complete - TODO: maybe not block??
sahilmgandhi 18:6a4db94011d3 382 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
sahilmgandhi 18:6a4db94011d3 383 }
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 // Accept all messages
sahilmgandhi 18:6a4db94011d3 386 can_filter(obj, 0, 0, CANStandard, 1);
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 return 1;
sahilmgandhi 18:6a4db94011d3 389 }
sahilmgandhi 18:6a4db94011d3 390
sahilmgandhi 18:6a4db94011d3 391 int can_config_txmsgobj(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 392 uint16_t i = 0;
sahilmgandhi 18:6a4db94011d3 393
sahilmgandhi 18:6a4db94011d3 394 // Make sure the interface is available
sahilmgandhi 18:6a4db94011d3 395 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
sahilmgandhi 18:6a4db94011d3 396
sahilmgandhi 18:6a4db94011d3 397 // Mark message valid, Direction = TX, Don't care about anything else
sahilmgandhi 18:6a4db94011d3 398 LPC_C_CAN0->CANIF1_ARB1 = 0;
sahilmgandhi 18:6a4db94011d3 399 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_DIR;
sahilmgandhi 18:6a4db94011d3 400 LPC_C_CAN0->CANIF1_MCTRL = 0;
sahilmgandhi 18:6a4db94011d3 401
sahilmgandhi 18:6a4db94011d3 402 for ( i = RX_MSG_OBJ_COUNT + 1; i <= (TX_MSG_OBJ_COUNT + RX_MSG_OBJ_COUNT); i++ )
sahilmgandhi 18:6a4db94011d3 403 {
sahilmgandhi 18:6a4db94011d3 404 // Transfer arb and control fields to message object
sahilmgandhi 18:6a4db94011d3 405 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
sahilmgandhi 18:6a4db94011d3 406 // In a union with CANIF1_CMDMSK_R
sahilmgandhi 18:6a4db94011d3 407
sahilmgandhi 18:6a4db94011d3 408 // Start Transfer to given message number
sahilmgandhi 18:6a4db94011d3 409 LPC_C_CAN0->CANIF1_CMDREQ = i & 0x3F;
sahilmgandhi 18:6a4db94011d3 410
sahilmgandhi 18:6a4db94011d3 411 // Wait until transfer to message ram complete - TODO: maybe not block??
sahilmgandhi 18:6a4db94011d3 412 while( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
sahilmgandhi 18:6a4db94011d3 413 }
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 return 1;
sahilmgandhi 18:6a4db94011d3 416 }
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 void can_init(can_t *obj, PinName rd, PinName td) {
sahilmgandhi 18:6a4db94011d3 420 // Enable power and clock
sahilmgandhi 18:6a4db94011d3 421 LPC_SYSCON->SYSAHBCLKCTRL1 |= (1UL << 7);
sahilmgandhi 18:6a4db94011d3 422 LPC_SYSCON->PRESETCTRL1 |= (1UL << 7);
sahilmgandhi 18:6a4db94011d3 423 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 // Enable Initialization mode
sahilmgandhi 18:6a4db94011d3 426 if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
sahilmgandhi 18:6a4db94011d3 427 LPC_C_CAN0->CANCNTL |= (1UL << 0);
sahilmgandhi 18:6a4db94011d3 428 }
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 LPC_SWM->PINASSIGN[6] &= ~(0x00FFFF00L);
sahilmgandhi 18:6a4db94011d3 431 LPC_SWM->PINASSIGN[6] |= (rd << 16) | (td << 8);
sahilmgandhi 18:6a4db94011d3 432
sahilmgandhi 18:6a4db94011d3 433 can_frequency(obj, 100000);
sahilmgandhi 18:6a4db94011d3 434
sahilmgandhi 18:6a4db94011d3 435 // Resume operation
sahilmgandhi 18:6a4db94011d3 436 LPC_C_CAN0->CANCNTL &= ~(1UL << 0);
sahilmgandhi 18:6a4db94011d3 437 while ( LPC_C_CAN0->CANCNTL & (1UL << 0) );
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 // Initialize RX message object
sahilmgandhi 18:6a4db94011d3 440 can_config_rxmsgobj(obj);
sahilmgandhi 18:6a4db94011d3 441 // Initialize TX message object
sahilmgandhi 18:6a4db94011d3 442 can_config_txmsgobj(obj);
sahilmgandhi 18:6a4db94011d3 443 }
sahilmgandhi 18:6a4db94011d3 444
sahilmgandhi 18:6a4db94011d3 445 void can_free(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 446 LPC_SYSCON->SYSAHBCLKCTRL1 &= ~(1UL << 7);
sahilmgandhi 18:6a4db94011d3 447 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
sahilmgandhi 18:6a4db94011d3 448 }
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450 int can_frequency(can_t *obj, int f) {
sahilmgandhi 18:6a4db94011d3 451 int btr = can_speed(SystemCoreClock, (unsigned int)f, 1);
sahilmgandhi 18:6a4db94011d3 452 int clkdiv = (btr >> 16) & 0x0F;
sahilmgandhi 18:6a4db94011d3 453 btr = btr & 0xFFFF;
sahilmgandhi 18:6a4db94011d3 454
sahilmgandhi 18:6a4db94011d3 455 if (btr > 0) {
sahilmgandhi 18:6a4db94011d3 456 // Set the bit clock
sahilmgandhi 18:6a4db94011d3 457 LPC_C_CAN0->CANCNTL |= (1UL << 6 | 1UL << 0); // set CCE and INIT
sahilmgandhi 18:6a4db94011d3 458 LPC_C_CAN0->CANCLKDIV = clkdiv;
sahilmgandhi 18:6a4db94011d3 459 LPC_C_CAN0->CANBT = btr;
sahilmgandhi 18:6a4db94011d3 460 LPC_C_CAN0->CANBRPE = 0x0000;
sahilmgandhi 18:6a4db94011d3 461 LPC_C_CAN0->CANCNTL &= ~(1UL << 6 | 1UL << 0); // clear CCE and INIT
sahilmgandhi 18:6a4db94011d3 462 return 1;
sahilmgandhi 18:6a4db94011d3 463 }
sahilmgandhi 18:6a4db94011d3 464 return 0;
sahilmgandhi 18:6a4db94011d3 465 }
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 int can_write(can_t *obj, CAN_Message msg, int cc) {
sahilmgandhi 18:6a4db94011d3 468
sahilmgandhi 18:6a4db94011d3 469 // Make sure controller is enabled
sahilmgandhi 18:6a4db94011d3 470 can_enable(obj);
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 // Find first message object that isn't pending to send
sahilmgandhi 18:6a4db94011d3 473 uint16_t msgnum = 0;
sahilmgandhi 18:6a4db94011d3 474 uint32_t txPending = (LPC_C_CAN0->CANTXREQ1 & 0xFF) | (LPC_C_CAN0->CANTXREQ2 << 16);
sahilmgandhi 18:6a4db94011d3 475 uint16_t i = 0;
sahilmgandhi 18:6a4db94011d3 476 for(i = RX_MSG_OBJ_COUNT; i < 32; i++) {
sahilmgandhi 18:6a4db94011d3 477 if ((txPending & (1 << i)) == 0) {
sahilmgandhi 18:6a4db94011d3 478 msgnum = i+1;
sahilmgandhi 18:6a4db94011d3 479 break;
sahilmgandhi 18:6a4db94011d3 480 }
sahilmgandhi 18:6a4db94011d3 481 }
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 // If no messageboxes are available, stop and return failure
sahilmgandhi 18:6a4db94011d3 484 if (msgnum == 0) {
sahilmgandhi 18:6a4db94011d3 485 return 0;
sahilmgandhi 18:6a4db94011d3 486 }
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488 // Make sure the interface is available
sahilmgandhi 18:6a4db94011d3 489 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
sahilmgandhi 18:6a4db94011d3 490
sahilmgandhi 18:6a4db94011d3 491 // Set the direction bit based on the message type
sahilmgandhi 18:6a4db94011d3 492 uint32_t direction = 0;
sahilmgandhi 18:6a4db94011d3 493 if (msg.type == CANData) {
sahilmgandhi 18:6a4db94011d3 494 direction = CANIFn_ARB2_DIR;
sahilmgandhi 18:6a4db94011d3 495 }
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 if (msg.format == CANExtended) {
sahilmgandhi 18:6a4db94011d3 498 // Mark message valid, Extended Frame, Set Identifier and mask everything
sahilmgandhi 18:6a4db94011d3 499 LPC_C_CAN0->CANIF1_ARB1 = (msg.id & 0xFFFF);
sahilmgandhi 18:6a4db94011d3 500 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | direction | ((msg.id >> 16) & 0x1FFFF);
sahilmgandhi 18:6a4db94011d3 501 LPC_C_CAN0->CANIF1_MSK1 = (ID_EXT_MASK & 0xFFFF);
sahilmgandhi 18:6a4db94011d3 502 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD | CANIFn_MSK2_MDIR | ((ID_EXT_MASK >> 16) & 0x1FFF);
sahilmgandhi 18:6a4db94011d3 503 } else {
sahilmgandhi 18:6a4db94011d3 504 // Mark message valid, Set Identifier and mask everything
sahilmgandhi 18:6a4db94011d3 505 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | direction | ((msg.id << 2) & 0x1FFF);
sahilmgandhi 18:6a4db94011d3 506 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MDIR | ((ID_STD_MASK << 2) & 0x1FFF);
sahilmgandhi 18:6a4db94011d3 507 }
sahilmgandhi 18:6a4db94011d3 508
sahilmgandhi 18:6a4db94011d3 509 // Use mask, request transmission, single message object and set DLC
sahilmgandhi 18:6a4db94011d3 510 LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_TXRQST | CANIFn_MCTRL_EOB | (msg.len & 0xF);
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 LPC_C_CAN0->CANIF1_DA1 = ((msg.data[1] & 0xFF) << 8) | (msg.data[0] & 0xFF);
sahilmgandhi 18:6a4db94011d3 513 LPC_C_CAN0->CANIF1_DA2 = ((msg.data[3] & 0xFF) << 8) | (msg.data[2] & 0xFF);
sahilmgandhi 18:6a4db94011d3 514 LPC_C_CAN0->CANIF1_DB1 = ((msg.data[5] & 0xFF) << 8) | (msg.data[4] & 0xFF);
sahilmgandhi 18:6a4db94011d3 515 LPC_C_CAN0->CANIF1_DB2 = ((msg.data[7] & 0xFF) << 8) | (msg.data[6] & 0xFF);
sahilmgandhi 18:6a4db94011d3 516
sahilmgandhi 18:6a4db94011d3 517 // Transfer all fields to message object
sahilmgandhi 18:6a4db94011d3 518 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
sahilmgandhi 18:6a4db94011d3 519
sahilmgandhi 18:6a4db94011d3 520 // Start Transfer to given message number
sahilmgandhi 18:6a4db94011d3 521 LPC_C_CAN0->CANIF1_CMDREQ = (msgnum & 0x3F);
sahilmgandhi 18:6a4db94011d3 522
sahilmgandhi 18:6a4db94011d3 523 // Wait until transfer to message ram complete - TODO: maybe not block??
sahilmgandhi 18:6a4db94011d3 524 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY);
sahilmgandhi 18:6a4db94011d3 525
sahilmgandhi 18:6a4db94011d3 526 // Wait until TXOK is set, then clear it - TODO: maybe not block
sahilmgandhi 18:6a4db94011d3 527 //while ( !(LPC_C_CAN0->STAT & CANSTAT_TXOK) );
sahilmgandhi 18:6a4db94011d3 528 LPC_C_CAN0->CANSTAT &= ~(1UL << 3);
sahilmgandhi 18:6a4db94011d3 529
sahilmgandhi 18:6a4db94011d3 530 return 1;
sahilmgandhi 18:6a4db94011d3 531 }
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 int can_read(can_t *obj, CAN_Message *msg, int handle) {
sahilmgandhi 18:6a4db94011d3 534 uint16_t i;
sahilmgandhi 18:6a4db94011d3 535
sahilmgandhi 18:6a4db94011d3 536 // Make sure controller is enabled
sahilmgandhi 18:6a4db94011d3 537 can_enable(obj);
sahilmgandhi 18:6a4db94011d3 538
sahilmgandhi 18:6a4db94011d3 539 // Find first message object with new data
sahilmgandhi 18:6a4db94011d3 540 if (handle == 0) {
sahilmgandhi 18:6a4db94011d3 541 uint32_t newdata = LPC_C_CAN0->CANND1 | (LPC_C_CAN0->CANND2 << 16);
sahilmgandhi 18:6a4db94011d3 542 // Find first free messagebox
sahilmgandhi 18:6a4db94011d3 543 for (i = 0; i < RX_MSG_OBJ_COUNT; i++) {
sahilmgandhi 18:6a4db94011d3 544 if (newdata & (1 << i)) {
sahilmgandhi 18:6a4db94011d3 545 handle = i+1;
sahilmgandhi 18:6a4db94011d3 546 break;
sahilmgandhi 18:6a4db94011d3 547 }
sahilmgandhi 18:6a4db94011d3 548 }
sahilmgandhi 18:6a4db94011d3 549 }
sahilmgandhi 18:6a4db94011d3 550
sahilmgandhi 18:6a4db94011d3 551 if (handle > 0 && handle <= 32) {
sahilmgandhi 18:6a4db94011d3 552 // Wait until message interface is free
sahilmgandhi 18:6a4db94011d3 553 while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
sahilmgandhi 18:6a4db94011d3 554
sahilmgandhi 18:6a4db94011d3 555 // Transfer all fields to message object
sahilmgandhi 18:6a4db94011d3 556 LPC_C_CAN0->CANIF2_CMDMSK_W = CANIFn_CMDMSK_RD | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_CLRINTPND | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
sahilmgandhi 18:6a4db94011d3 557
sahilmgandhi 18:6a4db94011d3 558 // Start Transfer from given message number
sahilmgandhi 18:6a4db94011d3 559 LPC_C_CAN0->CANIF2_CMDREQ = (handle & 0x3F);
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 // Wait until transfer to message ram complete
sahilmgandhi 18:6a4db94011d3 562 while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
sahilmgandhi 18:6a4db94011d3 563
sahilmgandhi 18:6a4db94011d3 564 if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_XTD) {
sahilmgandhi 18:6a4db94011d3 565 msg->format = CANExtended;
sahilmgandhi 18:6a4db94011d3 566 msg->id = (LPC_C_CAN0->CANIF2_ARB1 & 0x1FFF) << 16;
sahilmgandhi 18:6a4db94011d3 567 msg->id |= (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF);
sahilmgandhi 18:6a4db94011d3 568 } else {
sahilmgandhi 18:6a4db94011d3 569 msg->format = CANStandard;
sahilmgandhi 18:6a4db94011d3 570 msg->id = (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF) >> 2;
sahilmgandhi 18:6a4db94011d3 571 }
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_DIR) {
sahilmgandhi 18:6a4db94011d3 574 msg->type = CANRemote;
sahilmgandhi 18:6a4db94011d3 575 }
sahilmgandhi 18:6a4db94011d3 576 else {
sahilmgandhi 18:6a4db94011d3 577 msg->type = CANData;
sahilmgandhi 18:6a4db94011d3 578 }
sahilmgandhi 18:6a4db94011d3 579
sahilmgandhi 18:6a4db94011d3 580 msg->len = (LPC_C_CAN0->CANIF2_MCTRL & 0xF); // TODO: If > 8, len = 8
sahilmgandhi 18:6a4db94011d3 581 msg->data[0] = ((LPC_C_CAN0->CANIF2_DA1 >> 0) & 0xFF);
sahilmgandhi 18:6a4db94011d3 582 msg->data[1] = ((LPC_C_CAN0->CANIF2_DA1 >> 8) & 0xFF);
sahilmgandhi 18:6a4db94011d3 583 msg->data[2] = ((LPC_C_CAN0->CANIF2_DA2 >> 0) & 0xFF);
sahilmgandhi 18:6a4db94011d3 584 msg->data[3] = ((LPC_C_CAN0->CANIF2_DA2 >> 8) & 0xFF);
sahilmgandhi 18:6a4db94011d3 585 msg->data[4] = ((LPC_C_CAN0->CANIF2_DB1 >> 0) & 0xFF);
sahilmgandhi 18:6a4db94011d3 586 msg->data[5] = ((LPC_C_CAN0->CANIF2_DB1 >> 8) & 0xFF);
sahilmgandhi 18:6a4db94011d3 587 msg->data[6] = ((LPC_C_CAN0->CANIF2_DB2 >> 0) & 0xFF);
sahilmgandhi 18:6a4db94011d3 588 msg->data[7] = ((LPC_C_CAN0->CANIF2_DB2 >> 8) & 0xFF);
sahilmgandhi 18:6a4db94011d3 589
sahilmgandhi 18:6a4db94011d3 590 LPC_C_CAN0->CANSTAT &= ~(1UL << 4);
sahilmgandhi 18:6a4db94011d3 591 return 1;
sahilmgandhi 18:6a4db94011d3 592 }
sahilmgandhi 18:6a4db94011d3 593 return 0;
sahilmgandhi 18:6a4db94011d3 594 }
sahilmgandhi 18:6a4db94011d3 595
sahilmgandhi 18:6a4db94011d3 596 void can_reset(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 597 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
sahilmgandhi 18:6a4db94011d3 598 LPC_C_CAN0->CANSTAT = 0;
sahilmgandhi 18:6a4db94011d3 599 can_config_rxmsgobj(obj);
sahilmgandhi 18:6a4db94011d3 600 can_config_txmsgobj(obj);
sahilmgandhi 18:6a4db94011d3 601
sahilmgandhi 18:6a4db94011d3 602 can_enable(obj); // clears a bus-off condition if necessary
sahilmgandhi 18:6a4db94011d3 603 }
sahilmgandhi 18:6a4db94011d3 604
sahilmgandhi 18:6a4db94011d3 605 unsigned char can_rderror(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 606 return ((LPC_C_CAN0->CANEC >> 8) & 0x7F);
sahilmgandhi 18:6a4db94011d3 607 }
sahilmgandhi 18:6a4db94011d3 608
sahilmgandhi 18:6a4db94011d3 609 unsigned char can_tderror(can_t *obj) {
sahilmgandhi 18:6a4db94011d3 610 return (LPC_C_CAN0->CANEC & 0xFF);
sahilmgandhi 18:6a4db94011d3 611 }
sahilmgandhi 18:6a4db94011d3 612
sahilmgandhi 18:6a4db94011d3 613 void can_monitor(can_t *obj, int silent) {
sahilmgandhi 18:6a4db94011d3 614 if (silent) {
sahilmgandhi 18:6a4db94011d3 615 LPC_C_CAN0->CANCNTL |= (1UL << 7);
sahilmgandhi 18:6a4db94011d3 616 LPC_C_CAN0->CANTEST |= (1UL << 3);
sahilmgandhi 18:6a4db94011d3 617 } else {
sahilmgandhi 18:6a4db94011d3 618 LPC_C_CAN0->CANCNTL &= ~(1UL << 7);
sahilmgandhi 18:6a4db94011d3 619 LPC_C_CAN0->CANTEST &= ~(1UL << 3);
sahilmgandhi 18:6a4db94011d3 620 }
sahilmgandhi 18:6a4db94011d3 621
sahilmgandhi 18:6a4db94011d3 622 if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
sahilmgandhi 18:6a4db94011d3 623 LPC_C_CAN0->CANCNTL |= (1UL << 0);
sahilmgandhi 18:6a4db94011d3 624 }
sahilmgandhi 18:6a4db94011d3 625 }