MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pdma.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file pdma.h
sahilmgandhi 18:6a4db94011d3 3 * @version V1.00
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 8 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 14/06/05 5:16p $
sahilmgandhi 18:6a4db94011d3 6 * @brief NUC472/NUC442 PDMA driver header file
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11 #ifndef __PDMA_H__
sahilmgandhi 18:6a4db94011d3 12 #define __PDMA_H__
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 15 extern "C"
sahilmgandhi 18:6a4db94011d3 16 {
sahilmgandhi 18:6a4db94011d3 17 #endif
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
sahilmgandhi 18:6a4db94011d3 21 @{
sahilmgandhi 18:6a4db94011d3 22 */
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 /** @addtogroup NUC472_442_PDMA_Driver PDMA Driver
sahilmgandhi 18:6a4db94011d3 25 @{
sahilmgandhi 18:6a4db94011d3 26 */
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 /** @addtogroup NUC472_442_PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
sahilmgandhi 18:6a4db94011d3 29 @{
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31 #define PDMA_CH_MAX 16 /*!< Specify Maximum Channels of PDMA \hideinitializer */
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 34 /* operation Mode Constant Definitions */
sahilmgandhi 18:6a4db94011d3 35 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 36 #define PDMA_OP_STOP 0x00000000UL /*!<DMA Stop Mode \hideinitializer */
sahilmgandhi 18:6a4db94011d3 37 #define PDMA_OP_BASIC 0x00000001UL /*!<DMA Basic Mode \hideinitializer */
sahilmgandhi 18:6a4db94011d3 38 #define PDMA_OP_SCATTER 0x00000002UL /*!<DMA Scatter-gather Mode \hideinitializer */
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 41 /* Data Width Constant Definitions */
sahilmgandhi 18:6a4db94011d3 42 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 43 #define PDMA_WIDTH_8 0x00000000UL /*!<DMA Transfer Width 8-bit \hideinitializer */
sahilmgandhi 18:6a4db94011d3 44 #define PDMA_WIDTH_16 0x00001000UL /*!<DMA Transfer Width 16-bit \hideinitializer */
sahilmgandhi 18:6a4db94011d3 45 #define PDMA_WIDTH_32 0x00002000UL /*!<DMA Transfer Width 32-bit \hideinitializer */
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 48 /* Address Attribute Constant Definitions */
sahilmgandhi 18:6a4db94011d3 49 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 50 #define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment \hideinitializer */
sahilmgandhi 18:6a4db94011d3 51 #define PDMA_SAR_FIX 0x00000300UL /*!<DMA SAR fix address \hideinitializer */
sahilmgandhi 18:6a4db94011d3 52 #define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment \hideinitializer */
sahilmgandhi 18:6a4db94011d3 53 #define PDMA_DAR_FIX 0x00000C00UL /*!<DMA DAR fix address \hideinitializer */
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 56 /* Burst Mode Constant Definitions */
sahilmgandhi 18:6a4db94011d3 57 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 58 #define PDMA_REQ_SINGLE 0x00000004UL /*!<DMA Single Request \hideinitializer */
sahilmgandhi 18:6a4db94011d3 59 #define PDMA_REQ_BURST 0x00000000UL /*!<DMA Burst Request \hideinitializer */
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 #define PDMA_BURST_128 0x00000000UL /*!<DMA Burst 128 Transfers \hideinitializer */
sahilmgandhi 18:6a4db94011d3 62 #define PDMA_BURST_64 0x00000010UL /*!<DMA Burst 64 Transfers \hideinitializer */
sahilmgandhi 18:6a4db94011d3 63 #define PDMA_BURST_32 0x00000020UL /*!<DMA Burst 32 Transfers \hideinitializer */
sahilmgandhi 18:6a4db94011d3 64 #define PDMA_BURST_16 0x00000030UL /*!<DMA Burst 16 Transfers \hideinitializer */
sahilmgandhi 18:6a4db94011d3 65 #define PDMA_BURST_8 0x00000040UL /*!<DMA Burst 8 Transfers \hideinitializer */
sahilmgandhi 18:6a4db94011d3 66 #define PDMA_BURST_4 0x00000050UL /*!<DMA Burst 4 Transfers \hideinitializer */
sahilmgandhi 18:6a4db94011d3 67 #define PDMA_BURST_2 0x00000060UL /*!<DMA Burst 2 Transfers \hideinitializer */
sahilmgandhi 18:6a4db94011d3 68 #define PDMA_BURST_1 0x00000070UL /*!<DMA Burst 1 Transfers \hideinitializer */
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 71 /* Peripheral Transfer Mode Constant Definitions */
sahilmgandhi 18:6a4db94011d3 72 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 73 #define PDMA_SPI0_TX 0x00000000UL /*!<DMA Connect to SPI0 TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 74 #define PDMA_SPI1_TX 0x00000001UL /*!<DMA Connect to SPI1 TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 75 #define PDMA_SPI2_TX 0x00000002UL /*!<DMA Connect to SPI2 TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 76 #define PDMA_SPI3_TX 0x00000003UL /*!<DMA Connect to SPI3 TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 77 #define PDMA_UART0_TX 0x00000004UL /*!<DMA Connect to UART0 TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 78 #define PDMA_UART1_TX 0x00000005UL /*!<DMA Connect to UART1 TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 79 #define PDMA_UART2_TX 0x00000006UL /*!<DMA Connect to UART2 TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 80 #define PDMA_UART3_TX 0x00000007UL /*!<DMA Connect to UART3 TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 81 #define PDMA_UART4_TX 0x00000008UL /*!<DMA Connect to UART4 TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 82 #define PDMA_UART5_TX 0x00000009UL /*!<DMA Connect to UART5 TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 83 #define PDMA_I2S0_TX 0x0000000BUL /*!<DMA Connect to I2S TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 84 #define PDMA_I2S1_TX 0x0000000CUL /*!<DMA Connect to I2S1 TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 85 #define PDMA_SPI0_RX 0x0000000DUL /*!<DMA Connect to SPI0 RX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 86 #define PDMA_SPI1_RX 0x0000000EUL /*!<DMA Connect to SPI1 RX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 87 #define PDMA_SPI2_RX 0x0000000FUL /*!<DMA Connect to SPI2 RX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 88 #define PDMA_SPI3_RX 0x00000010UL /*!<DMA Connect to SPI3 RX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 89 #define PDMA_UART0_RX 0x00000011UL /*!<DMA Connect to UART0 RX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 90 #define PDMA_UART1_RX 0x00000012UL /*!<DMA Connect to UART1 RX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 91 #define PDMA_UART2_RX 0x00000013UL /*!<DMA Connect to UART2 RX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 92 #define PDMA_UART3_RX 0x00000014UL /*!<DMA Connect to UART3 RX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 93 #define PDMA_UART4_RX 0x00000015UL /*!<DMA Connect to UART4 RX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 94 #define PDMA_UART5_RX 0x00000016UL /*!<DMA Connect to UART5 RX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 95 #define PDMA_ADC 0x00000018UL /*!<DMA Connect to ADC \hideinitializer */
sahilmgandhi 18:6a4db94011d3 96 #define PDMA_I2S0_RX 0x00000019UL /*!<DMA Connect to I2S TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 97 #define PDMA_I2S1_RX 0x0000001AUL /*!<DMA Connect to I2S1 TX \hideinitializer */
sahilmgandhi 18:6a4db94011d3 98 #define PDMA_MEM 0x0000001FUL /*!<DMA Connect to Memory \hideinitializer */
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 /*@}*/ /* end of group NUC472_442_PDMA_EXPORTED_CONSTANTS */
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 /** @addtogroup NUC472_442_PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
sahilmgandhi 18:6a4db94011d3 103 @{
sahilmgandhi 18:6a4db94011d3 104 */
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 /**
sahilmgandhi 18:6a4db94011d3 107 * @brief Get PDMA Interrupt Status
sahilmgandhi 18:6a4db94011d3 108 *
sahilmgandhi 18:6a4db94011d3 109 * @param[in] None
sahilmgandhi 18:6a4db94011d3 110 *
sahilmgandhi 18:6a4db94011d3 111 * @return None
sahilmgandhi 18:6a4db94011d3 112 *
sahilmgandhi 18:6a4db94011d3 113 * @details This macro gets the interrupt status.
sahilmgandhi 18:6a4db94011d3 114 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 115 */
sahilmgandhi 18:6a4db94011d3 116 #define PDMA_GET_INT_STATUS() ((uint32_t)(PDMA->INTSTS))
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 /**
sahilmgandhi 18:6a4db94011d3 119 * @brief Get Transfer Done Interrupt Status
sahilmgandhi 18:6a4db94011d3 120 *
sahilmgandhi 18:6a4db94011d3 121 * @param[in] None
sahilmgandhi 18:6a4db94011d3 122 *
sahilmgandhi 18:6a4db94011d3 123 * @return None
sahilmgandhi 18:6a4db94011d3 124 *
sahilmgandhi 18:6a4db94011d3 125 * @details Get the transfer done Interrupt status.
sahilmgandhi 18:6a4db94011d3 126 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 127 */
sahilmgandhi 18:6a4db94011d3 128 #define PDMA_GET_TD_STS() ((uint32_t)(PDMA->TDSTS))
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 /**
sahilmgandhi 18:6a4db94011d3 131 * @brief Clear Transfer Done Interrupt Status
sahilmgandhi 18:6a4db94011d3 132 *
sahilmgandhi 18:6a4db94011d3 133 * @param[in] u32Mask The channel mask
sahilmgandhi 18:6a4db94011d3 134 *
sahilmgandhi 18:6a4db94011d3 135 * @return None
sahilmgandhi 18:6a4db94011d3 136 *
sahilmgandhi 18:6a4db94011d3 137 * @details Clear the transfer done Interrupt status.
sahilmgandhi 18:6a4db94011d3 138 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 139 */
sahilmgandhi 18:6a4db94011d3 140 #define PDMA_CLR_TD_FLAG(u32Mask) ((uint32_t)(PDMA->TDSTS = u32Mask))
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 /**
sahilmgandhi 18:6a4db94011d3 143 * @brief Get Target Abort Interrupt Status
sahilmgandhi 18:6a4db94011d3 144 *
sahilmgandhi 18:6a4db94011d3 145 * @param[in] None
sahilmgandhi 18:6a4db94011d3 146 *
sahilmgandhi 18:6a4db94011d3 147 * @return None
sahilmgandhi 18:6a4db94011d3 148 *
sahilmgandhi 18:6a4db94011d3 149 * @details Get the target abort Interrupt status.
sahilmgandhi 18:6a4db94011d3 150 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 151 */
sahilmgandhi 18:6a4db94011d3 152 #define PDMA_GET_ABORT_STS() ((uint32_t)(PDMA->ABTSTS))
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 /**
sahilmgandhi 18:6a4db94011d3 155 * @brief Clear Target Abort Interrupt Status
sahilmgandhi 18:6a4db94011d3 156 *
sahilmgandhi 18:6a4db94011d3 157 * @param[in] u32Mask The channel mask
sahilmgandhi 18:6a4db94011d3 158 *
sahilmgandhi 18:6a4db94011d3 159 * @return None
sahilmgandhi 18:6a4db94011d3 160 *
sahilmgandhi 18:6a4db94011d3 161 * @details Clear the target abort Interrupt status.
sahilmgandhi 18:6a4db94011d3 162 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 163 */
sahilmgandhi 18:6a4db94011d3 164 #define PDMA_CLR_ABORT_FLAG(u32Mask) ((uint32_t)(PDMA->ABTSTS = u32Mask))
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 /**
sahilmgandhi 18:6a4db94011d3 167 * @brief Get Scatter-Gather Table Empty Interrupt Status
sahilmgandhi 18:6a4db94011d3 168 *
sahilmgandhi 18:6a4db94011d3 169 * @param[in] None
sahilmgandhi 18:6a4db94011d3 170 *
sahilmgandhi 18:6a4db94011d3 171 * @return None
sahilmgandhi 18:6a4db94011d3 172 *
sahilmgandhi 18:6a4db94011d3 173 * @details Get the scatter-gather table empty Interrupt status.
sahilmgandhi 18:6a4db94011d3 174 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 175 */
sahilmgandhi 18:6a4db94011d3 176 #define PDMA_GET_EMPTY_STS() ((uint32_t)(PDMA->SCATSTS))
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 /**
sahilmgandhi 18:6a4db94011d3 179 * @brief Clear Scatter-Gather Table Empty Interrupt Status
sahilmgandhi 18:6a4db94011d3 180 *
sahilmgandhi 18:6a4db94011d3 181 * @param[in] u32Mask The channel mask
sahilmgandhi 18:6a4db94011d3 182 *
sahilmgandhi 18:6a4db94011d3 183 * @return None
sahilmgandhi 18:6a4db94011d3 184 *
sahilmgandhi 18:6a4db94011d3 185 * @details Clear the scatter-gather table empty Interrupt status.
sahilmgandhi 18:6a4db94011d3 186 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 187 */
sahilmgandhi 18:6a4db94011d3 188 #define PDMA_CLR_EMPTY_FLAG(u32Mask) ((uint32_t)(PDMA->SCATSTS = u32Mask))
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 /**
sahilmgandhi 18:6a4db94011d3 191 * @brief Clear Timeout Interrupt Status
sahilmgandhi 18:6a4db94011d3 192 *
sahilmgandhi 18:6a4db94011d3 193 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 194 *
sahilmgandhi 18:6a4db94011d3 195 * @return None
sahilmgandhi 18:6a4db94011d3 196 *
sahilmgandhi 18:6a4db94011d3 197 * @details Clear the selected channel timeout interrupt status.
sahilmgandhi 18:6a4db94011d3 198 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 199 */
sahilmgandhi 18:6a4db94011d3 200 #define PDMA_CLR_TMOUT_FLAG(u32Ch) ((uint32_t)(PDMA->INTSTS = (1 << (u32Ch + 8))))
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 /**
sahilmgandhi 18:6a4db94011d3 203 * @brief Check Channel Status
sahilmgandhi 18:6a4db94011d3 204 *
sahilmgandhi 18:6a4db94011d3 205 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 206 *
sahilmgandhi 18:6a4db94011d3 207 * @return 0 = idle; 1 = busy
sahilmgandhi 18:6a4db94011d3 208 *
sahilmgandhi 18:6a4db94011d3 209 * @details Check the selected channel is busy or not.
sahilmgandhi 18:6a4db94011d3 210 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 211 */
sahilmgandhi 18:6a4db94011d3 212 #define PDMA_IS_CH_BUSY(u32Ch) ((uint32_t)(PDMA->TRGSTS & (1 << u32Ch))? 1 : 0)
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 /**
sahilmgandhi 18:6a4db94011d3 215 * @brief Set Source Address
sahilmgandhi 18:6a4db94011d3 216 *
sahilmgandhi 18:6a4db94011d3 217 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 218 * @param[in] u32Addr The selected address
sahilmgandhi 18:6a4db94011d3 219 *
sahilmgandhi 18:6a4db94011d3 220 * @return None
sahilmgandhi 18:6a4db94011d3 221 *
sahilmgandhi 18:6a4db94011d3 222 * @details This macro set the selected channel source address.
sahilmgandhi 18:6a4db94011d3 223 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 224 */
sahilmgandhi 18:6a4db94011d3 225 #define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[u32Ch].ENDSA = u32Addr))
sahilmgandhi 18:6a4db94011d3 226
sahilmgandhi 18:6a4db94011d3 227 /**
sahilmgandhi 18:6a4db94011d3 228 * @brief Set Destination Address
sahilmgandhi 18:6a4db94011d3 229 *
sahilmgandhi 18:6a4db94011d3 230 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 231 * @param[in] u32Addr The selected address
sahilmgandhi 18:6a4db94011d3 232 *
sahilmgandhi 18:6a4db94011d3 233 * @return None
sahilmgandhi 18:6a4db94011d3 234 *
sahilmgandhi 18:6a4db94011d3 235 * @details This macro set the selected channel destination address.
sahilmgandhi 18:6a4db94011d3 236 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 237 */
sahilmgandhi 18:6a4db94011d3 238 #define PDMA_SET_DST_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[u32Ch].ENDDA = u32Addr))
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 /**
sahilmgandhi 18:6a4db94011d3 241 * @brief Set Transfer Count
sahilmgandhi 18:6a4db94011d3 242 *
sahilmgandhi 18:6a4db94011d3 243 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 244 * @param[in] u32Count Transfer Count
sahilmgandhi 18:6a4db94011d3 245 *
sahilmgandhi 18:6a4db94011d3 246 * @return None
sahilmgandhi 18:6a4db94011d3 247 *
sahilmgandhi 18:6a4db94011d3 248 * @details This macro set the selected channel transfer count.
sahilmgandhi 18:6a4db94011d3 249 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 250 */
sahilmgandhi 18:6a4db94011d3 251 #define PDMA_SET_TRANS_CNT(u32Ch, u32Count) ((uint32_t)(PDMA->DSCT[u32Ch].CTL=(PDMA->DSCT[u32Ch].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|((u32Count-1) << PDMA_DSCT_CTL_TXCNT_Pos))
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 /**
sahilmgandhi 18:6a4db94011d3 254 * @brief Set Scatter-gather descriptor Address
sahilmgandhi 18:6a4db94011d3 255 *
sahilmgandhi 18:6a4db94011d3 256 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 257 * @param[in] u32Addr The descriptor address
sahilmgandhi 18:6a4db94011d3 258 *
sahilmgandhi 18:6a4db94011d3 259 * @return None
sahilmgandhi 18:6a4db94011d3 260 *
sahilmgandhi 18:6a4db94011d3 261 * @details This macro set the selected channel scatter-gather descriptor address.
sahilmgandhi 18:6a4db94011d3 262 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 263 */
sahilmgandhi 18:6a4db94011d3 264 #define PDMA_SET_SCATTER_DESC(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[u32Ch].NEXT = u32Addr - (PDMA->SCATBA)))
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 /**
sahilmgandhi 18:6a4db94011d3 267 * @brief Stop the channel
sahilmgandhi 18:6a4db94011d3 268 *
sahilmgandhi 18:6a4db94011d3 269 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 270 *
sahilmgandhi 18:6a4db94011d3 271 * @return None
sahilmgandhi 18:6a4db94011d3 272 *
sahilmgandhi 18:6a4db94011d3 273 * @details This macro stop the selected channel.
sahilmgandhi 18:6a4db94011d3 274 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 275 */
sahilmgandhi 18:6a4db94011d3 276 #define PDMA_STOP(u32Ch) ((uint32_t)(PDMA->STOP = (1 << u32Ch)))
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 void PDMA_Open(uint32_t u32Mask);
sahilmgandhi 18:6a4db94011d3 281 void PDMA_Close(void);
sahilmgandhi 18:6a4db94011d3 282 void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
sahilmgandhi 18:6a4db94011d3 283 void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
sahilmgandhi 18:6a4db94011d3 284 void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
sahilmgandhi 18:6a4db94011d3 285 void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);
sahilmgandhi 18:6a4db94011d3 286 void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
sahilmgandhi 18:6a4db94011d3 287 void PDMA_Trigger(uint32_t u32Ch);
sahilmgandhi 18:6a4db94011d3 288 void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask);
sahilmgandhi 18:6a4db94011d3 289 void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask);
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 /*@}*/ /* end of group NUC472_442_PDMA_EXPORTED_FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 /*@}*/ /* end of group NUC472_442_PDMA_Driver */
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 /*@}*/ /* end of group NUC472_442_Device_Driver */
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 300 }
sahilmgandhi 18:6a4db94011d3 301 #endif
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 #endif //__PDMA_H__
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/