MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015-2016 Nuvoton
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #if DEVICE_INTERRUPTIN
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #include "gpio_api.h"
sahilmgandhi 18:6a4db94011d3 22 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 23 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 24 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 25 #include "nu_bitutil.h"
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 #define NU_MAX_PIN_PER_PORT 16
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 struct nu_gpio_irq_var {
sahilmgandhi 18:6a4db94011d3 30 gpio_irq_t * obj_arr[NU_MAX_PIN_PER_PORT];
sahilmgandhi 18:6a4db94011d3 31 IRQn_Type irq_n;
sahilmgandhi 18:6a4db94011d3 32 void (*vec)(void);
sahilmgandhi 18:6a4db94011d3 33 };
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 static void gpio_irq_0_vec(void);
sahilmgandhi 18:6a4db94011d3 36 static void gpio_irq_1_vec(void);
sahilmgandhi 18:6a4db94011d3 37 static void gpio_irq_2_vec(void);
sahilmgandhi 18:6a4db94011d3 38 static void gpio_irq_3_vec(void);
sahilmgandhi 18:6a4db94011d3 39 static void gpio_irq_4_vec(void);
sahilmgandhi 18:6a4db94011d3 40 static void gpio_irq_5_vec(void);
sahilmgandhi 18:6a4db94011d3 41 static void gpio_irq(struct nu_gpio_irq_var *var);
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 //EINT0_IRQn
sahilmgandhi 18:6a4db94011d3 44 static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
sahilmgandhi 18:6a4db94011d3 45 {{NULL}, GPA_IRQn, gpio_irq_0_vec},
sahilmgandhi 18:6a4db94011d3 46 {{NULL}, GPB_IRQn, gpio_irq_1_vec},
sahilmgandhi 18:6a4db94011d3 47 {{NULL}, GPC_IRQn, gpio_irq_2_vec},
sahilmgandhi 18:6a4db94011d3 48 {{NULL}, GPD_IRQn, gpio_irq_3_vec},
sahilmgandhi 18:6a4db94011d3 49 {{NULL}, GPE_IRQn, gpio_irq_4_vec},
sahilmgandhi 18:6a4db94011d3 50 {{NULL}, GPF_IRQn, gpio_irq_5_vec}
sahilmgandhi 18:6a4db94011d3 51 };
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 #define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 #ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
sahilmgandhi 18:6a4db94011d3 56 #define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE 0
sahilmgandhi 18:6a4db94011d3 57 #endif
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 #ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
sahilmgandhi 18:6a4db94011d3 60 #define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
sahilmgandhi 18:6a4db94011d3 61 #endif
sahilmgandhi 18:6a4db94011d3 62 static PinName gpio_irq_debounce_arr[] = {
sahilmgandhi 18:6a4db94011d3 63 MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
sahilmgandhi 18:6a4db94011d3 64 };
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 #ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
sahilmgandhi 18:6a4db94011d3 67 #define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
sahilmgandhi 18:6a4db94011d3 68 #endif
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 #ifndef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
sahilmgandhi 18:6a4db94011d3 71 #define MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
sahilmgandhi 18:6a4db94011d3 72 #endif
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
sahilmgandhi 18:6a4db94011d3 75 {
sahilmgandhi 18:6a4db94011d3 76 if (pin == NC) {
sahilmgandhi 18:6a4db94011d3 77 return -1;
sahilmgandhi 18:6a4db94011d3 78 }
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
sahilmgandhi 18:6a4db94011d3 81 uint32_t port_index = NU_PINNAME_TO_PORT(pin);
sahilmgandhi 18:6a4db94011d3 82 if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) {
sahilmgandhi 18:6a4db94011d3 83 return -1;
sahilmgandhi 18:6a4db94011d3 84 }
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 obj->pin = pin;
sahilmgandhi 18:6a4db94011d3 87 obj->irq_handler = (uint32_t) handler;
sahilmgandhi 18:6a4db94011d3 88 obj->irq_id = id;
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
sahilmgandhi 18:6a4db94011d3 91 //gpio_set(pin);
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 {
sahilmgandhi 18:6a4db94011d3 94 #if MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
sahilmgandhi 18:6a4db94011d3 95 // Suppress compiler warning
sahilmgandhi 18:6a4db94011d3 96 (void) gpio_irq_debounce_arr;
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 // Configure de-bounce clock source and sampling cycle time
sahilmgandhi 18:6a4db94011d3 99 GPIO_SET_DEBOUNCE_TIME(MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
sahilmgandhi 18:6a4db94011d3 100 GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
sahilmgandhi 18:6a4db94011d3 101 #else
sahilmgandhi 18:6a4db94011d3 102 // Enable de-bounce if the pin is in the de-bounce enable list
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 // De-bounce defaults to disabled.
sahilmgandhi 18:6a4db94011d3 105 GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 PinName *debounce_pos = gpio_irq_debounce_arr;
sahilmgandhi 18:6a4db94011d3 108 PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]);
sahilmgandhi 18:6a4db94011d3 109 for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) {
sahilmgandhi 18:6a4db94011d3 110 uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos);
sahilmgandhi 18:6a4db94011d3 111 uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos);
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 if (pin_index == pin_index_debunce &&
sahilmgandhi 18:6a4db94011d3 114 port_index == port_index_debounce) {
sahilmgandhi 18:6a4db94011d3 115 // Configure de-bounce clock source and sampling cycle time
sahilmgandhi 18:6a4db94011d3 116 GPIO_SET_DEBOUNCE_TIME(MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
sahilmgandhi 18:6a4db94011d3 117 GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
sahilmgandhi 18:6a4db94011d3 118 break;
sahilmgandhi 18:6a4db94011d3 119 }
sahilmgandhi 18:6a4db94011d3 120 }
sahilmgandhi 18:6a4db94011d3 121 #endif
sahilmgandhi 18:6a4db94011d3 122 }
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 var->obj_arr[pin_index] = obj;
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 // NOTE: InterruptIn requires IRQ enabled by default.
sahilmgandhi 18:6a4db94011d3 129 gpio_irq_enable(obj);
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 return 0;
sahilmgandhi 18:6a4db94011d3 132 }
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 void gpio_irq_free(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 135 {
sahilmgandhi 18:6a4db94011d3 136 uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
sahilmgandhi 18:6a4db94011d3 137 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
sahilmgandhi 18:6a4db94011d3 138 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 NVIC_DisableIRQ(var->irq_n);
sahilmgandhi 18:6a4db94011d3 141 NU_PORT_BASE(port_index)->INTEN = 0;
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
sahilmgandhi 18:6a4db94011d3 144 var->obj_arr[pin_index] = NULL;
sahilmgandhi 18:6a4db94011d3 145 }
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
sahilmgandhi 18:6a4db94011d3 148 {
sahilmgandhi 18:6a4db94011d3 149 uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
sahilmgandhi 18:6a4db94011d3 150 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
sahilmgandhi 18:6a4db94011d3 151 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 switch (event) {
sahilmgandhi 18:6a4db94011d3 154 case IRQ_RISE:
sahilmgandhi 18:6a4db94011d3 155 if (enable) {
sahilmgandhi 18:6a4db94011d3 156 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
sahilmgandhi 18:6a4db94011d3 157 }
sahilmgandhi 18:6a4db94011d3 158 else {
sahilmgandhi 18:6a4db94011d3 159 gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index);
sahilmgandhi 18:6a4db94011d3 160 }
sahilmgandhi 18:6a4db94011d3 161 break;
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 case IRQ_FALL:
sahilmgandhi 18:6a4db94011d3 164 if (enable) {
sahilmgandhi 18:6a4db94011d3 165 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
sahilmgandhi 18:6a4db94011d3 166 }
sahilmgandhi 18:6a4db94011d3 167 else {
sahilmgandhi 18:6a4db94011d3 168 gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index);
sahilmgandhi 18:6a4db94011d3 169 }
sahilmgandhi 18:6a4db94011d3 170 break;
sahilmgandhi 18:6a4db94011d3 171 }
sahilmgandhi 18:6a4db94011d3 172 }
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 void gpio_irq_enable(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 175 {
sahilmgandhi 18:6a4db94011d3 176 //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
sahilmgandhi 18:6a4db94011d3 177 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
sahilmgandhi 18:6a4db94011d3 178 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 NVIC_SetVector(var->irq_n, (uint32_t) var->vec);
sahilmgandhi 18:6a4db94011d3 181 NVIC_EnableIRQ(var->irq_n);
sahilmgandhi 18:6a4db94011d3 182 }
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 void gpio_irq_disable(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 185 {
sahilmgandhi 18:6a4db94011d3 186 //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
sahilmgandhi 18:6a4db94011d3 187 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
sahilmgandhi 18:6a4db94011d3 188 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 NVIC_DisableIRQ(var->irq_n);
sahilmgandhi 18:6a4db94011d3 191 }
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 static void gpio_irq_0_vec(void)
sahilmgandhi 18:6a4db94011d3 194 {
sahilmgandhi 18:6a4db94011d3 195 gpio_irq(gpio_irq_var_arr + 0);
sahilmgandhi 18:6a4db94011d3 196 }
sahilmgandhi 18:6a4db94011d3 197 static void gpio_irq_1_vec(void)
sahilmgandhi 18:6a4db94011d3 198 {
sahilmgandhi 18:6a4db94011d3 199 gpio_irq(gpio_irq_var_arr + 1);
sahilmgandhi 18:6a4db94011d3 200 }
sahilmgandhi 18:6a4db94011d3 201 static void gpio_irq_2_vec(void)
sahilmgandhi 18:6a4db94011d3 202 {
sahilmgandhi 18:6a4db94011d3 203 gpio_irq(gpio_irq_var_arr + 2);
sahilmgandhi 18:6a4db94011d3 204 }
sahilmgandhi 18:6a4db94011d3 205 static void gpio_irq_3_vec(void)
sahilmgandhi 18:6a4db94011d3 206 {
sahilmgandhi 18:6a4db94011d3 207 gpio_irq(gpio_irq_var_arr + 3);
sahilmgandhi 18:6a4db94011d3 208 }
sahilmgandhi 18:6a4db94011d3 209 static void gpio_irq_4_vec(void)
sahilmgandhi 18:6a4db94011d3 210 {
sahilmgandhi 18:6a4db94011d3 211 gpio_irq(gpio_irq_var_arr + 4);
sahilmgandhi 18:6a4db94011d3 212 }
sahilmgandhi 18:6a4db94011d3 213 static void gpio_irq_5_vec(void)
sahilmgandhi 18:6a4db94011d3 214 {
sahilmgandhi 18:6a4db94011d3 215 gpio_irq(gpio_irq_var_arr + 5);
sahilmgandhi 18:6a4db94011d3 216 }
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 static void gpio_irq(struct nu_gpio_irq_var *var)
sahilmgandhi 18:6a4db94011d3 219 {
sahilmgandhi 18:6a4db94011d3 220 uint32_t port_index = var->irq_n - GPA_IRQn;
sahilmgandhi 18:6a4db94011d3 221 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 uint32_t intsrc = gpio_base->INTSRC;
sahilmgandhi 18:6a4db94011d3 224 uint32_t inten = gpio_base->INTEN;
sahilmgandhi 18:6a4db94011d3 225 while (intsrc) {
sahilmgandhi 18:6a4db94011d3 226 int pin_index = nu_ctz(intsrc);
sahilmgandhi 18:6a4db94011d3 227 gpio_irq_t *obj = var->obj_arr[pin_index];
sahilmgandhi 18:6a4db94011d3 228 if (inten & (GPIO_INT_RISING << pin_index)) {
sahilmgandhi 18:6a4db94011d3 229 if (GPIO_PIN_DATA(port_index, pin_index)) {
sahilmgandhi 18:6a4db94011d3 230 if (obj->irq_handler) {
sahilmgandhi 18:6a4db94011d3 231 ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE);
sahilmgandhi 18:6a4db94011d3 232 }
sahilmgandhi 18:6a4db94011d3 233 }
sahilmgandhi 18:6a4db94011d3 234 }
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 if (inten & (GPIO_INT_FALLING << pin_index)) {
sahilmgandhi 18:6a4db94011d3 237 if (! GPIO_PIN_DATA(port_index, pin_index)) {
sahilmgandhi 18:6a4db94011d3 238 if (obj->irq_handler) {
sahilmgandhi 18:6a4db94011d3 239 ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 240 }
sahilmgandhi 18:6a4db94011d3 241 }
sahilmgandhi 18:6a4db94011d3 242 }
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 intsrc &= ~(1 << pin_index);
sahilmgandhi 18:6a4db94011d3 245 }
sahilmgandhi 18:6a4db94011d3 246 // Clear all interrupt flags
sahilmgandhi 18:6a4db94011d3 247 gpio_base->INTSRC = gpio_base->INTSRC;
sahilmgandhi 18:6a4db94011d3 248 }
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 #endif