MacroRat
Mouse code for the MacroRat
mbed-dev/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_to_nrf52.h@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| sahilmgandhi | 18:6a4db94011d3 | 1 | /* |
| sahilmgandhi | 18:6a4db94011d3 | 2 | * Copyright (c) 2015 Nordic Semiconductor ASA |
| sahilmgandhi | 18:6a4db94011d3 | 3 | * All rights reserved. |
| sahilmgandhi | 18:6a4db94011d3 | 4 | * |
| sahilmgandhi | 18:6a4db94011d3 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
| sahilmgandhi | 18:6a4db94011d3 | 6 | * are permitted provided that the following conditions are met: |
| sahilmgandhi | 18:6a4db94011d3 | 7 | * |
| sahilmgandhi | 18:6a4db94011d3 | 8 | * 1. Redistributions of source code must retain the above copyright notice, this list |
| sahilmgandhi | 18:6a4db94011d3 | 9 | * of conditions and the following disclaimer. |
| sahilmgandhi | 18:6a4db94011d3 | 10 | * |
| sahilmgandhi | 18:6a4db94011d3 | 11 | * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA |
| sahilmgandhi | 18:6a4db94011d3 | 12 | * integrated circuit in a product or a software update for such product, must reproduce |
| sahilmgandhi | 18:6a4db94011d3 | 13 | * the above copyright notice, this list of conditions and the following disclaimer in |
| sahilmgandhi | 18:6a4db94011d3 | 14 | * the documentation and/or other materials provided with the distribution. |
| sahilmgandhi | 18:6a4db94011d3 | 15 | * |
| sahilmgandhi | 18:6a4db94011d3 | 16 | * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be |
| sahilmgandhi | 18:6a4db94011d3 | 17 | * used to endorse or promote products derived from this software without specific prior |
| sahilmgandhi | 18:6a4db94011d3 | 18 | * written permission. |
| sahilmgandhi | 18:6a4db94011d3 | 19 | * |
| sahilmgandhi | 18:6a4db94011d3 | 20 | * 4. This software, with or without modification, must only be used with a |
| sahilmgandhi | 18:6a4db94011d3 | 21 | * Nordic Semiconductor ASA integrated circuit. |
| sahilmgandhi | 18:6a4db94011d3 | 22 | * |
| sahilmgandhi | 18:6a4db94011d3 | 23 | * 5. Any software provided in binary or object form under this license must not be reverse |
| sahilmgandhi | 18:6a4db94011d3 | 24 | * engineered, decompiled, modified and/or disassembled. |
| sahilmgandhi | 18:6a4db94011d3 | 25 | * |
| sahilmgandhi | 18:6a4db94011d3 | 26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| sahilmgandhi | 18:6a4db94011d3 | 27 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| sahilmgandhi | 18:6a4db94011d3 | 28 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| sahilmgandhi | 18:6a4db94011d3 | 29 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| sahilmgandhi | 18:6a4db94011d3 | 30 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| sahilmgandhi | 18:6a4db94011d3 | 31 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| sahilmgandhi | 18:6a4db94011d3 | 32 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| sahilmgandhi | 18:6a4db94011d3 | 33 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| sahilmgandhi | 18:6a4db94011d3 | 34 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| sahilmgandhi | 18:6a4db94011d3 | 35 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| sahilmgandhi | 18:6a4db94011d3 | 36 | * |
| sahilmgandhi | 18:6a4db94011d3 | 37 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 38 | |
| sahilmgandhi | 18:6a4db94011d3 | 39 | |
| sahilmgandhi | 18:6a4db94011d3 | 40 | #ifndef NRF51_TO_NRF52_H |
| sahilmgandhi | 18:6a4db94011d3 | 41 | #define NRF51_TO_NRF52_H |
| sahilmgandhi | 18:6a4db94011d3 | 42 | |
| sahilmgandhi | 18:6a4db94011d3 | 43 | /*lint ++flb "Enter library region */ |
| sahilmgandhi | 18:6a4db94011d3 | 44 | |
| sahilmgandhi | 18:6a4db94011d3 | 45 | /* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices. |
| sahilmgandhi | 18:6a4db94011d3 | 46 | * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the |
| sahilmgandhi | 18:6a4db94011d3 | 47 | * functionality is gone, there old names are not define, so compilation will fail. Note that also includes macros |
| sahilmgandhi | 18:6a4db94011d3 | 48 | * from the nrf51_deprecated.h file. */ |
| sahilmgandhi | 18:6a4db94011d3 | 49 | |
| sahilmgandhi | 18:6a4db94011d3 | 50 | |
| sahilmgandhi | 18:6a4db94011d3 | 51 | /* IRQ */ |
| sahilmgandhi | 18:6a4db94011d3 | 52 | /* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ |
| sahilmgandhi | 18:6a4db94011d3 | 53 | #define UART0_IRQHandler UARTE0_UART0_IRQHandler |
| sahilmgandhi | 18:6a4db94011d3 | 54 | #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler |
| sahilmgandhi | 18:6a4db94011d3 | 55 | #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler |
| sahilmgandhi | 18:6a4db94011d3 | 56 | #define ADC_IRQHandler SAADC_IRQHandler |
| sahilmgandhi | 18:6a4db94011d3 | 57 | #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler |
| sahilmgandhi | 18:6a4db94011d3 | 58 | #define SWI0_IRQHandler SWI0_EGU0_IRQHandler |
| sahilmgandhi | 18:6a4db94011d3 | 59 | #define SWI1_IRQHandler SWI1_EGU1_IRQHandler |
| sahilmgandhi | 18:6a4db94011d3 | 60 | #define SWI2_IRQHandler SWI2_EGU2_IRQHandler |
| sahilmgandhi | 18:6a4db94011d3 | 61 | #define SWI3_IRQHandler SWI3_EGU3_IRQHandler |
| sahilmgandhi | 18:6a4db94011d3 | 62 | #define SWI4_IRQHandler SWI4_EGU4_IRQHandler |
| sahilmgandhi | 18:6a4db94011d3 | 63 | #define SWI5_IRQHandler SWI5_EGU5_IRQHandler |
| sahilmgandhi | 18:6a4db94011d3 | 64 | |
| sahilmgandhi | 18:6a4db94011d3 | 65 | #define UART0_IRQn UARTE0_UART0_IRQn |
| sahilmgandhi | 18:6a4db94011d3 | 66 | #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn |
| sahilmgandhi | 18:6a4db94011d3 | 67 | #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn |
| sahilmgandhi | 18:6a4db94011d3 | 68 | #define ADC_IRQn SAADC_IRQn |
| sahilmgandhi | 18:6a4db94011d3 | 69 | #define LPCOMP_IRQn COMP_LPCOMP_IRQn |
| sahilmgandhi | 18:6a4db94011d3 | 70 | #define SWI0_IRQn SWI0_EGU0_IRQn |
| sahilmgandhi | 18:6a4db94011d3 | 71 | #define SWI1_IRQn SWI1_EGU1_IRQn |
| sahilmgandhi | 18:6a4db94011d3 | 72 | #define SWI2_IRQn SWI2_EGU2_IRQn |
| sahilmgandhi | 18:6a4db94011d3 | 73 | #define SWI3_IRQn SWI3_EGU3_IRQn |
| sahilmgandhi | 18:6a4db94011d3 | 74 | #define SWI4_IRQn SWI4_EGU4_IRQn |
| sahilmgandhi | 18:6a4db94011d3 | 75 | #define SWI5_IRQn SWI5_EGU5_IRQn |
| sahilmgandhi | 18:6a4db94011d3 | 76 | |
| sahilmgandhi | 18:6a4db94011d3 | 77 | |
| sahilmgandhi | 18:6a4db94011d3 | 78 | /* UICR */ |
| sahilmgandhi | 18:6a4db94011d3 | 79 | /* Register RBPCONF was renamed to APPROTECT. */ |
| sahilmgandhi | 18:6a4db94011d3 | 80 | #define RBPCONF APPROTECT |
| sahilmgandhi | 18:6a4db94011d3 | 81 | |
| sahilmgandhi | 18:6a4db94011d3 | 82 | #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 83 | #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 84 | #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 85 | #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 86 | |
| sahilmgandhi | 18:6a4db94011d3 | 87 | |
| sahilmgandhi | 18:6a4db94011d3 | 88 | /* GPIO */ |
| sahilmgandhi | 18:6a4db94011d3 | 89 | /* GPIO port was renamed to P0. */ |
| sahilmgandhi | 18:6a4db94011d3 | 90 | #define NRF_GPIO NRF_P0 |
| sahilmgandhi | 18:6a4db94011d3 | 91 | #define NRF_GPIO_BASE NRF_P0_BASE |
| sahilmgandhi | 18:6a4db94011d3 | 92 | |
| sahilmgandhi | 18:6a4db94011d3 | 93 | |
| sahilmgandhi | 18:6a4db94011d3 | 94 | /* SPIS */ |
| sahilmgandhi | 18:6a4db94011d3 | 95 | /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ |
| sahilmgandhi | 18:6a4db94011d3 | 96 | #define PSELSCK PSEL.SCK |
| sahilmgandhi | 18:6a4db94011d3 | 97 | #define PSELMISO PSEL.MISO |
| sahilmgandhi | 18:6a4db94011d3 | 98 | #define PSELMOSI PSEL.MOSI |
| sahilmgandhi | 18:6a4db94011d3 | 99 | #define PSELCSN PSEL.CSN |
| sahilmgandhi | 18:6a4db94011d3 | 100 | |
| sahilmgandhi | 18:6a4db94011d3 | 101 | /* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ |
| sahilmgandhi | 18:6a4db94011d3 | 102 | #define RXDPTR RXD.PTR |
| sahilmgandhi | 18:6a4db94011d3 | 103 | #define MAXRX RXD.MAXCNT |
| sahilmgandhi | 18:6a4db94011d3 | 104 | #define AMOUNTRX RXD.AMOUNT |
| sahilmgandhi | 18:6a4db94011d3 | 105 | |
| sahilmgandhi | 18:6a4db94011d3 | 106 | #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 107 | #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 108 | |
| sahilmgandhi | 18:6a4db94011d3 | 109 | #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 110 | #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 111 | |
| sahilmgandhi | 18:6a4db94011d3 | 112 | /* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ |
| sahilmgandhi | 18:6a4db94011d3 | 113 | #define TXDPTR TXD.PTR |
| sahilmgandhi | 18:6a4db94011d3 | 114 | #define MAXTX TXD.MAXCNT |
| sahilmgandhi | 18:6a4db94011d3 | 115 | #define AMOUNTTX TXD.AMOUNT |
| sahilmgandhi | 18:6a4db94011d3 | 116 | |
| sahilmgandhi | 18:6a4db94011d3 | 117 | #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 118 | #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 119 | |
| sahilmgandhi | 18:6a4db94011d3 | 120 | #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 121 | #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 122 | |
| sahilmgandhi | 18:6a4db94011d3 | 123 | |
| sahilmgandhi | 18:6a4db94011d3 | 124 | /* MPU */ |
| sahilmgandhi | 18:6a4db94011d3 | 125 | /* Part of MPU module was renamed BPROT, while the rest was eliminated. */ |
| sahilmgandhi | 18:6a4db94011d3 | 126 | #define NRF_MPU NRF_BPROT |
| sahilmgandhi | 18:6a4db94011d3 | 127 | |
| sahilmgandhi | 18:6a4db94011d3 | 128 | /* Register DISABLEINDEBUG macros were affected. */ |
| sahilmgandhi | 18:6a4db94011d3 | 129 | #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 130 | #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 131 | #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 132 | #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 133 | |
| sahilmgandhi | 18:6a4db94011d3 | 134 | /* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */ |
| sahilmgandhi | 18:6a4db94011d3 | 135 | #define PROTENSET0 CONFIG0 |
| sahilmgandhi | 18:6a4db94011d3 | 136 | #define PROTENSET1 CONFIG1 |
| sahilmgandhi | 18:6a4db94011d3 | 137 | |
| sahilmgandhi | 18:6a4db94011d3 | 138 | #define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 139 | #define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 140 | #define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 141 | #define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 142 | #define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 143 | |
| sahilmgandhi | 18:6a4db94011d3 | 144 | #define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 145 | #define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 146 | #define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 147 | #define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 148 | #define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 149 | |
| sahilmgandhi | 18:6a4db94011d3 | 150 | #define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 151 | #define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 152 | #define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 153 | #define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 154 | #define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 155 | |
| sahilmgandhi | 18:6a4db94011d3 | 156 | #define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 157 | #define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 158 | #define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 159 | #define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 160 | #define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 161 | |
| sahilmgandhi | 18:6a4db94011d3 | 162 | #define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 163 | #define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 164 | #define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 165 | #define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 166 | #define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 167 | |
| sahilmgandhi | 18:6a4db94011d3 | 168 | #define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 169 | #define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 170 | #define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 171 | #define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 172 | #define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 173 | |
| sahilmgandhi | 18:6a4db94011d3 | 174 | #define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 175 | #define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 176 | #define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 177 | #define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 178 | #define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 179 | |
| sahilmgandhi | 18:6a4db94011d3 | 180 | #define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 181 | #define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 182 | #define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 183 | #define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 184 | #define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 185 | |
| sahilmgandhi | 18:6a4db94011d3 | 186 | #define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 187 | #define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 188 | #define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 189 | #define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 190 | #define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 191 | |
| sahilmgandhi | 18:6a4db94011d3 | 192 | #define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 193 | #define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 194 | #define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 195 | #define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 196 | #define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 197 | |
| sahilmgandhi | 18:6a4db94011d3 | 198 | #define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 199 | #define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 200 | #define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 201 | #define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 202 | #define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 203 | |
| sahilmgandhi | 18:6a4db94011d3 | 204 | #define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 205 | #define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 206 | #define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 207 | #define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 208 | #define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 209 | |
| sahilmgandhi | 18:6a4db94011d3 | 210 | #define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 211 | #define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 212 | #define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 213 | #define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 214 | #define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 215 | |
| sahilmgandhi | 18:6a4db94011d3 | 216 | #define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 217 | #define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 218 | #define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 219 | #define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 220 | #define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 221 | |
| sahilmgandhi | 18:6a4db94011d3 | 222 | #define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 223 | #define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 224 | #define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 225 | #define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 226 | #define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 227 | |
| sahilmgandhi | 18:6a4db94011d3 | 228 | #define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 229 | #define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 230 | #define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 231 | #define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 232 | #define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 233 | |
| sahilmgandhi | 18:6a4db94011d3 | 234 | #define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 235 | #define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 236 | #define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 237 | #define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 238 | #define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 239 | |
| sahilmgandhi | 18:6a4db94011d3 | 240 | #define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 241 | #define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 242 | #define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 243 | #define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 244 | #define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 245 | |
| sahilmgandhi | 18:6a4db94011d3 | 246 | #define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 247 | #define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 248 | #define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 249 | #define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 250 | #define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 251 | |
| sahilmgandhi | 18:6a4db94011d3 | 252 | #define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 253 | #define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 254 | #define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 255 | #define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 256 | #define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 257 | |
| sahilmgandhi | 18:6a4db94011d3 | 258 | #define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 259 | #define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 260 | #define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 261 | #define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 262 | #define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 263 | |
| sahilmgandhi | 18:6a4db94011d3 | 264 | #define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 265 | #define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 266 | #define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 267 | #define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 268 | #define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 269 | |
| sahilmgandhi | 18:6a4db94011d3 | 270 | #define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 271 | #define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 272 | #define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 273 | #define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 274 | #define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 275 | |
| sahilmgandhi | 18:6a4db94011d3 | 276 | #define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 277 | #define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 278 | #define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 279 | #define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 280 | #define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 281 | |
| sahilmgandhi | 18:6a4db94011d3 | 282 | #define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 283 | #define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 284 | #define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 285 | #define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 286 | #define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 287 | |
| sahilmgandhi | 18:6a4db94011d3 | 288 | #define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 289 | #define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 290 | #define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 291 | #define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 292 | #define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 293 | |
| sahilmgandhi | 18:6a4db94011d3 | 294 | #define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 295 | #define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 296 | #define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 297 | #define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 298 | #define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 299 | |
| sahilmgandhi | 18:6a4db94011d3 | 300 | #define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 301 | #define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 302 | #define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 303 | #define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 304 | #define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 305 | |
| sahilmgandhi | 18:6a4db94011d3 | 306 | #define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 307 | #define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 308 | #define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 309 | #define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 310 | #define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 311 | |
| sahilmgandhi | 18:6a4db94011d3 | 312 | #define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 313 | #define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 314 | #define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 315 | #define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 316 | #define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 317 | |
| sahilmgandhi | 18:6a4db94011d3 | 318 | #define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 319 | #define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 320 | #define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 321 | #define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 322 | #define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 323 | |
| sahilmgandhi | 18:6a4db94011d3 | 324 | #define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 325 | #define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 326 | #define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 327 | #define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 328 | #define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 329 | |
| sahilmgandhi | 18:6a4db94011d3 | 330 | #define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 331 | #define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 332 | #define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 333 | #define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 334 | #define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 335 | |
| sahilmgandhi | 18:6a4db94011d3 | 336 | #define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 337 | #define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 338 | #define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 339 | #define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 340 | #define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 341 | |
| sahilmgandhi | 18:6a4db94011d3 | 342 | #define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 343 | #define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 344 | #define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 345 | #define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 346 | #define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 347 | |
| sahilmgandhi | 18:6a4db94011d3 | 348 | #define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 349 | #define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 350 | #define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 351 | #define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 352 | #define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 353 | |
| sahilmgandhi | 18:6a4db94011d3 | 354 | #define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 355 | #define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 356 | #define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 357 | #define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 358 | #define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 359 | |
| sahilmgandhi | 18:6a4db94011d3 | 360 | #define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 361 | #define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 362 | #define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 363 | #define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 364 | #define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 365 | |
| sahilmgandhi | 18:6a4db94011d3 | 366 | #define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 367 | #define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 368 | #define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 369 | #define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 370 | #define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 371 | |
| sahilmgandhi | 18:6a4db94011d3 | 372 | #define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 373 | #define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 374 | #define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 375 | #define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 376 | #define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 377 | |
| sahilmgandhi | 18:6a4db94011d3 | 378 | #define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 379 | #define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 380 | #define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 381 | #define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 382 | #define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 383 | |
| sahilmgandhi | 18:6a4db94011d3 | 384 | #define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 385 | #define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 386 | #define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 387 | #define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 388 | #define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 389 | |
| sahilmgandhi | 18:6a4db94011d3 | 390 | #define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 391 | #define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 392 | #define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 393 | #define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 394 | #define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 395 | |
| sahilmgandhi | 18:6a4db94011d3 | 396 | #define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 397 | #define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 398 | #define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 399 | #define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 400 | #define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 401 | |
| sahilmgandhi | 18:6a4db94011d3 | 402 | #define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 403 | #define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 404 | #define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 405 | #define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 406 | #define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 407 | |
| sahilmgandhi | 18:6a4db94011d3 | 408 | #define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 409 | #define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 410 | #define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 411 | #define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 412 | #define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 413 | |
| sahilmgandhi | 18:6a4db94011d3 | 414 | #define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 415 | #define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 416 | #define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 417 | #define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 418 | #define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 419 | |
| sahilmgandhi | 18:6a4db94011d3 | 420 | #define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 421 | #define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 422 | #define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 423 | #define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 424 | #define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 425 | |
| sahilmgandhi | 18:6a4db94011d3 | 426 | #define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 427 | #define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 428 | #define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 429 | #define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 430 | #define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 431 | |
| sahilmgandhi | 18:6a4db94011d3 | 432 | #define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 433 | #define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 434 | #define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 435 | #define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 436 | #define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 437 | |
| sahilmgandhi | 18:6a4db94011d3 | 438 | #define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 439 | #define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 440 | #define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 441 | #define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 442 | #define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 443 | |
| sahilmgandhi | 18:6a4db94011d3 | 444 | #define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 445 | #define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 446 | #define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 447 | #define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 448 | #define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 449 | |
| sahilmgandhi | 18:6a4db94011d3 | 450 | #define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 451 | #define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 452 | #define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 453 | #define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 454 | #define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 455 | |
| sahilmgandhi | 18:6a4db94011d3 | 456 | #define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 457 | #define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 458 | #define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 459 | #define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 460 | #define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 461 | |
| sahilmgandhi | 18:6a4db94011d3 | 462 | #define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 463 | #define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 464 | #define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 465 | #define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 466 | #define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 467 | |
| sahilmgandhi | 18:6a4db94011d3 | 468 | #define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 469 | #define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 470 | #define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 471 | #define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 472 | #define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 473 | |
| sahilmgandhi | 18:6a4db94011d3 | 474 | #define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 475 | #define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 476 | #define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 477 | #define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 478 | #define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 479 | |
| sahilmgandhi | 18:6a4db94011d3 | 480 | #define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 481 | #define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 482 | #define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 483 | #define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 484 | #define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 485 | |
| sahilmgandhi | 18:6a4db94011d3 | 486 | #define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 487 | #define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 488 | #define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 489 | #define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 490 | #define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 491 | |
| sahilmgandhi | 18:6a4db94011d3 | 492 | #define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 493 | #define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 494 | #define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 495 | #define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 496 | #define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 497 | |
| sahilmgandhi | 18:6a4db94011d3 | 498 | #define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 499 | #define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 500 | #define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 501 | #define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 502 | #define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 503 | |
| sahilmgandhi | 18:6a4db94011d3 | 504 | #define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 505 | #define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 506 | #define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 507 | #define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 508 | #define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 509 | |
| sahilmgandhi | 18:6a4db94011d3 | 510 | #define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 511 | #define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 512 | #define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 513 | #define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 514 | #define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 515 | |
| sahilmgandhi | 18:6a4db94011d3 | 516 | #define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 517 | #define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 518 | #define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled |
| sahilmgandhi | 18:6a4db94011d3 | 519 | #define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 520 | #define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled |
| sahilmgandhi | 18:6a4db94011d3 | 521 | |
| sahilmgandhi | 18:6a4db94011d3 | 522 | |
| sahilmgandhi | 18:6a4db94011d3 | 523 | /* From nrf51_deprecated.h */ |
| sahilmgandhi | 18:6a4db94011d3 | 524 | |
| sahilmgandhi | 18:6a4db94011d3 | 525 | /* NVMC */ |
| sahilmgandhi | 18:6a4db94011d3 | 526 | /* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ |
| sahilmgandhi | 18:6a4db94011d3 | 527 | #define ERASEPROTECTEDPAGE ERASEPCR0 |
| sahilmgandhi | 18:6a4db94011d3 | 528 | |
| sahilmgandhi | 18:6a4db94011d3 | 529 | |
| sahilmgandhi | 18:6a4db94011d3 | 530 | /* IRQ */ |
| sahilmgandhi | 18:6a4db94011d3 | 531 | /* COMP module was eliminated. Adapted to nrf52 headers. */ |
| sahilmgandhi | 18:6a4db94011d3 | 532 | #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler |
| sahilmgandhi | 18:6a4db94011d3 | 533 | #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn |
| sahilmgandhi | 18:6a4db94011d3 | 534 | |
| sahilmgandhi | 18:6a4db94011d3 | 535 | |
| sahilmgandhi | 18:6a4db94011d3 | 536 | /* RADIO */ |
| sahilmgandhi | 18:6a4db94011d3 | 537 | /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ |
| sahilmgandhi | 18:6a4db94011d3 | 538 | #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 539 | #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 540 | #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include |
| sahilmgandhi | 18:6a4db94011d3 | 541 | #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip |
| sahilmgandhi | 18:6a4db94011d3 | 542 | |
| sahilmgandhi | 18:6a4db94011d3 | 543 | |
| sahilmgandhi | 18:6a4db94011d3 | 544 | /* FICR */ |
| sahilmgandhi | 18:6a4db94011d3 | 545 | /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ |
| sahilmgandhi | 18:6a4db94011d3 | 546 | #define DEVICEID0 DEVICEID[0] |
| sahilmgandhi | 18:6a4db94011d3 | 547 | #define DEVICEID1 DEVICEID[1] |
| sahilmgandhi | 18:6a4db94011d3 | 548 | |
| sahilmgandhi | 18:6a4db94011d3 | 549 | /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ |
| sahilmgandhi | 18:6a4db94011d3 | 550 | #define ER0 ER[0] |
| sahilmgandhi | 18:6a4db94011d3 | 551 | #define ER1 ER[1] |
| sahilmgandhi | 18:6a4db94011d3 | 552 | #define ER2 ER[2] |
| sahilmgandhi | 18:6a4db94011d3 | 553 | #define ER3 ER[3] |
| sahilmgandhi | 18:6a4db94011d3 | 554 | |
| sahilmgandhi | 18:6a4db94011d3 | 555 | /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ |
| sahilmgandhi | 18:6a4db94011d3 | 556 | #define IR0 IR[0] |
| sahilmgandhi | 18:6a4db94011d3 | 557 | #define IR1 IR[1] |
| sahilmgandhi | 18:6a4db94011d3 | 558 | #define IR2 IR[2] |
| sahilmgandhi | 18:6a4db94011d3 | 559 | #define IR3 IR[3] |
| sahilmgandhi | 18:6a4db94011d3 | 560 | |
| sahilmgandhi | 18:6a4db94011d3 | 561 | /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ |
| sahilmgandhi | 18:6a4db94011d3 | 562 | #define DEVICEADDR0 DEVICEADDR[0] |
| sahilmgandhi | 18:6a4db94011d3 | 563 | #define DEVICEADDR1 DEVICEADDR[1] |
| sahilmgandhi | 18:6a4db94011d3 | 564 | |
| sahilmgandhi | 18:6a4db94011d3 | 565 | |
| sahilmgandhi | 18:6a4db94011d3 | 566 | /* PPI */ |
| sahilmgandhi | 18:6a4db94011d3 | 567 | /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ |
| sahilmgandhi | 18:6a4db94011d3 | 568 | #define TASKS_CHG0EN TASKS_CHG[0].EN |
| sahilmgandhi | 18:6a4db94011d3 | 569 | #define TASKS_CHG0DIS TASKS_CHG[0].DIS |
| sahilmgandhi | 18:6a4db94011d3 | 570 | #define TASKS_CHG1EN TASKS_CHG[1].EN |
| sahilmgandhi | 18:6a4db94011d3 | 571 | #define TASKS_CHG1DIS TASKS_CHG[1].DIS |
| sahilmgandhi | 18:6a4db94011d3 | 572 | #define TASKS_CHG2EN TASKS_CHG[2].EN |
| sahilmgandhi | 18:6a4db94011d3 | 573 | #define TASKS_CHG2DIS TASKS_CHG[2].DIS |
| sahilmgandhi | 18:6a4db94011d3 | 574 | #define TASKS_CHG3EN TASKS_CHG[3].EN |
| sahilmgandhi | 18:6a4db94011d3 | 575 | #define TASKS_CHG3DIS TASKS_CHG[3].DIS |
| sahilmgandhi | 18:6a4db94011d3 | 576 | |
| sahilmgandhi | 18:6a4db94011d3 | 577 | /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ |
| sahilmgandhi | 18:6a4db94011d3 | 578 | #define CH0_EEP CH[0].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 579 | #define CH0_TEP CH[0].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 580 | #define CH1_EEP CH[1].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 581 | #define CH1_TEP CH[1].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 582 | #define CH2_EEP CH[2].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 583 | #define CH2_TEP CH[2].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 584 | #define CH3_EEP CH[3].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 585 | #define CH3_TEP CH[3].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 586 | #define CH4_EEP CH[4].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 587 | #define CH4_TEP CH[4].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 588 | #define CH5_EEP CH[5].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 589 | #define CH5_TEP CH[5].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 590 | #define CH6_EEP CH[6].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 591 | #define CH6_TEP CH[6].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 592 | #define CH7_EEP CH[7].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 593 | #define CH7_TEP CH[7].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 594 | #define CH8_EEP CH[8].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 595 | #define CH8_TEP CH[8].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 596 | #define CH9_EEP CH[9].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 597 | #define CH9_TEP CH[9].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 598 | #define CH10_EEP CH[10].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 599 | #define CH10_TEP CH[10].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 600 | #define CH11_EEP CH[11].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 601 | #define CH11_TEP CH[11].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 602 | #define CH12_EEP CH[12].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 603 | #define CH12_TEP CH[12].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 604 | #define CH13_EEP CH[13].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 605 | #define CH13_TEP CH[13].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 606 | #define CH14_EEP CH[14].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 607 | #define CH14_TEP CH[14].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 608 | #define CH15_EEP CH[15].EEP |
| sahilmgandhi | 18:6a4db94011d3 | 609 | #define CH15_TEP CH[15].TEP |
| sahilmgandhi | 18:6a4db94011d3 | 610 | |
| sahilmgandhi | 18:6a4db94011d3 | 611 | /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ |
| sahilmgandhi | 18:6a4db94011d3 | 612 | #define CHG0 CHG[0] |
| sahilmgandhi | 18:6a4db94011d3 | 613 | #define CHG1 CHG[1] |
| sahilmgandhi | 18:6a4db94011d3 | 614 | #define CHG2 CHG[2] |
| sahilmgandhi | 18:6a4db94011d3 | 615 | #define CHG3 CHG[3] |
| sahilmgandhi | 18:6a4db94011d3 | 616 | |
| sahilmgandhi | 18:6a4db94011d3 | 617 | /* All bitfield macros for the CHGx registers therefore changed name. */ |
| sahilmgandhi | 18:6a4db94011d3 | 618 | #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 619 | #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 620 | #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 621 | #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included |
| sahilmgandhi | 18:6a4db94011d3 | 622 | |
| sahilmgandhi | 18:6a4db94011d3 | 623 | #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 624 | #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 625 | #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 626 | #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included |
| sahilmgandhi | 18:6a4db94011d3 | 627 | |
| sahilmgandhi | 18:6a4db94011d3 | 628 | #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 629 | #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 630 | #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 631 | #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included |
| sahilmgandhi | 18:6a4db94011d3 | 632 | |
| sahilmgandhi | 18:6a4db94011d3 | 633 | #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 634 | #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 635 | #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 636 | #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included |
| sahilmgandhi | 18:6a4db94011d3 | 637 | |
| sahilmgandhi | 18:6a4db94011d3 | 638 | #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 639 | #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 640 | #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 641 | #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included |
| sahilmgandhi | 18:6a4db94011d3 | 642 | |
| sahilmgandhi | 18:6a4db94011d3 | 643 | #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 644 | #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 645 | #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 646 | #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included |
| sahilmgandhi | 18:6a4db94011d3 | 647 | |
| sahilmgandhi | 18:6a4db94011d3 | 648 | #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 649 | #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 650 | #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 651 | #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included |
| sahilmgandhi | 18:6a4db94011d3 | 652 | |
| sahilmgandhi | 18:6a4db94011d3 | 653 | #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 654 | #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 655 | #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 656 | #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included |
| sahilmgandhi | 18:6a4db94011d3 | 657 | |
| sahilmgandhi | 18:6a4db94011d3 | 658 | #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 659 | #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 660 | #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 661 | #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included |
| sahilmgandhi | 18:6a4db94011d3 | 662 | |
| sahilmgandhi | 18:6a4db94011d3 | 663 | #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 664 | #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 665 | #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 666 | #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included |
| sahilmgandhi | 18:6a4db94011d3 | 667 | |
| sahilmgandhi | 18:6a4db94011d3 | 668 | #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 669 | #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 670 | #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 671 | #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included |
| sahilmgandhi | 18:6a4db94011d3 | 672 | |
| sahilmgandhi | 18:6a4db94011d3 | 673 | #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 674 | #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 675 | #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 676 | #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included |
| sahilmgandhi | 18:6a4db94011d3 | 677 | |
| sahilmgandhi | 18:6a4db94011d3 | 678 | #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 679 | #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 680 | #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 681 | #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included |
| sahilmgandhi | 18:6a4db94011d3 | 682 | |
| sahilmgandhi | 18:6a4db94011d3 | 683 | #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 684 | #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 685 | #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 686 | #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included |
| sahilmgandhi | 18:6a4db94011d3 | 687 | |
| sahilmgandhi | 18:6a4db94011d3 | 688 | #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 689 | #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 690 | #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 691 | #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included |
| sahilmgandhi | 18:6a4db94011d3 | 692 | |
| sahilmgandhi | 18:6a4db94011d3 | 693 | #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 694 | #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 695 | #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 696 | #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included |
| sahilmgandhi | 18:6a4db94011d3 | 697 | |
| sahilmgandhi | 18:6a4db94011d3 | 698 | #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 699 | #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 700 | #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 701 | #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included |
| sahilmgandhi | 18:6a4db94011d3 | 702 | |
| sahilmgandhi | 18:6a4db94011d3 | 703 | #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 704 | #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 705 | #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 706 | #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included |
| sahilmgandhi | 18:6a4db94011d3 | 707 | |
| sahilmgandhi | 18:6a4db94011d3 | 708 | #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 709 | #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 710 | #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 711 | #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included |
| sahilmgandhi | 18:6a4db94011d3 | 712 | |
| sahilmgandhi | 18:6a4db94011d3 | 713 | #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 714 | #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 715 | #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 716 | #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included |
| sahilmgandhi | 18:6a4db94011d3 | 717 | |
| sahilmgandhi | 18:6a4db94011d3 | 718 | #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 719 | #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 720 | #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 721 | #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included |
| sahilmgandhi | 18:6a4db94011d3 | 722 | |
| sahilmgandhi | 18:6a4db94011d3 | 723 | #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 724 | #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 725 | #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 726 | #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included |
| sahilmgandhi | 18:6a4db94011d3 | 727 | |
| sahilmgandhi | 18:6a4db94011d3 | 728 | #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 729 | #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 730 | #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 731 | #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included |
| sahilmgandhi | 18:6a4db94011d3 | 732 | |
| sahilmgandhi | 18:6a4db94011d3 | 733 | #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 734 | #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 735 | #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 736 | #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included |
| sahilmgandhi | 18:6a4db94011d3 | 737 | |
| sahilmgandhi | 18:6a4db94011d3 | 738 | #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 739 | #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 740 | #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 741 | #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included |
| sahilmgandhi | 18:6a4db94011d3 | 742 | |
| sahilmgandhi | 18:6a4db94011d3 | 743 | #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 744 | #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 745 | #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 746 | #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included |
| sahilmgandhi | 18:6a4db94011d3 | 747 | |
| sahilmgandhi | 18:6a4db94011d3 | 748 | #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 749 | #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 750 | #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 751 | #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included |
| sahilmgandhi | 18:6a4db94011d3 | 752 | |
| sahilmgandhi | 18:6a4db94011d3 | 753 | #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 754 | #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 755 | #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 756 | #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included |
| sahilmgandhi | 18:6a4db94011d3 | 757 | |
| sahilmgandhi | 18:6a4db94011d3 | 758 | #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 759 | #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 760 | #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 761 | #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included |
| sahilmgandhi | 18:6a4db94011d3 | 762 | |
| sahilmgandhi | 18:6a4db94011d3 | 763 | #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 764 | #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 765 | #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 766 | #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included |
| sahilmgandhi | 18:6a4db94011d3 | 767 | |
| sahilmgandhi | 18:6a4db94011d3 | 768 | #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 769 | #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 770 | #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 771 | #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included |
| sahilmgandhi | 18:6a4db94011d3 | 772 | |
| sahilmgandhi | 18:6a4db94011d3 | 773 | #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 774 | #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 775 | #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 776 | #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included |
| sahilmgandhi | 18:6a4db94011d3 | 777 | |
| sahilmgandhi | 18:6a4db94011d3 | 778 | #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 779 | #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 780 | #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 781 | #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included |
| sahilmgandhi | 18:6a4db94011d3 | 782 | |
| sahilmgandhi | 18:6a4db94011d3 | 783 | #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 784 | #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 785 | #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 786 | #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included |
| sahilmgandhi | 18:6a4db94011d3 | 787 | |
| sahilmgandhi | 18:6a4db94011d3 | 788 | #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 789 | #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 790 | #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 791 | #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included |
| sahilmgandhi | 18:6a4db94011d3 | 792 | |
| sahilmgandhi | 18:6a4db94011d3 | 793 | #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 794 | #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 795 | #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 796 | #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included |
| sahilmgandhi | 18:6a4db94011d3 | 797 | |
| sahilmgandhi | 18:6a4db94011d3 | 798 | #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 799 | #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 800 | #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 801 | #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included |
| sahilmgandhi | 18:6a4db94011d3 | 802 | |
| sahilmgandhi | 18:6a4db94011d3 | 803 | #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 804 | #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 805 | #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 806 | #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included |
| sahilmgandhi | 18:6a4db94011d3 | 807 | |
| sahilmgandhi | 18:6a4db94011d3 | 808 | #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 809 | #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 810 | #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 811 | #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included |
| sahilmgandhi | 18:6a4db94011d3 | 812 | |
| sahilmgandhi | 18:6a4db94011d3 | 813 | #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 814 | #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 815 | #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 816 | #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included |
| sahilmgandhi | 18:6a4db94011d3 | 817 | |
| sahilmgandhi | 18:6a4db94011d3 | 818 | #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 819 | #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 820 | #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 821 | #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included |
| sahilmgandhi | 18:6a4db94011d3 | 822 | |
| sahilmgandhi | 18:6a4db94011d3 | 823 | #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 824 | #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 825 | #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 826 | #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included |
| sahilmgandhi | 18:6a4db94011d3 | 827 | |
| sahilmgandhi | 18:6a4db94011d3 | 828 | #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 829 | #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 830 | #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 831 | #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included |
| sahilmgandhi | 18:6a4db94011d3 | 832 | |
| sahilmgandhi | 18:6a4db94011d3 | 833 | #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 834 | #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 835 | #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 836 | #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included |
| sahilmgandhi | 18:6a4db94011d3 | 837 | |
| sahilmgandhi | 18:6a4db94011d3 | 838 | #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 839 | #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 840 | #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 841 | #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included |
| sahilmgandhi | 18:6a4db94011d3 | 842 | |
| sahilmgandhi | 18:6a4db94011d3 | 843 | #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 844 | #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 845 | #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 846 | #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included |
| sahilmgandhi | 18:6a4db94011d3 | 847 | |
| sahilmgandhi | 18:6a4db94011d3 | 848 | #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 849 | #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 850 | #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 851 | #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included |
| sahilmgandhi | 18:6a4db94011d3 | 852 | |
| sahilmgandhi | 18:6a4db94011d3 | 853 | #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 854 | #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 855 | #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 856 | #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included |
| sahilmgandhi | 18:6a4db94011d3 | 857 | |
| sahilmgandhi | 18:6a4db94011d3 | 858 | #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 859 | #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 860 | #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 861 | #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included |
| sahilmgandhi | 18:6a4db94011d3 | 862 | |
| sahilmgandhi | 18:6a4db94011d3 | 863 | #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 864 | #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 865 | #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 866 | #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included |
| sahilmgandhi | 18:6a4db94011d3 | 867 | |
| sahilmgandhi | 18:6a4db94011d3 | 868 | #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 869 | #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 870 | #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 871 | #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included |
| sahilmgandhi | 18:6a4db94011d3 | 872 | |
| sahilmgandhi | 18:6a4db94011d3 | 873 | #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 874 | #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 875 | #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 876 | #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included |
| sahilmgandhi | 18:6a4db94011d3 | 877 | |
| sahilmgandhi | 18:6a4db94011d3 | 878 | #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 879 | #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 880 | #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 881 | #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included |
| sahilmgandhi | 18:6a4db94011d3 | 882 | |
| sahilmgandhi | 18:6a4db94011d3 | 883 | #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 884 | #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 885 | #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 886 | #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included |
| sahilmgandhi | 18:6a4db94011d3 | 887 | |
| sahilmgandhi | 18:6a4db94011d3 | 888 | #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 889 | #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 890 | #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 891 | #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included |
| sahilmgandhi | 18:6a4db94011d3 | 892 | |
| sahilmgandhi | 18:6a4db94011d3 | 893 | #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 894 | #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 895 | #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 896 | #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included |
| sahilmgandhi | 18:6a4db94011d3 | 897 | |
| sahilmgandhi | 18:6a4db94011d3 | 898 | #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 899 | #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 900 | #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 901 | #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included |
| sahilmgandhi | 18:6a4db94011d3 | 902 | |
| sahilmgandhi | 18:6a4db94011d3 | 903 | #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 904 | #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 905 | #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 906 | #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included |
| sahilmgandhi | 18:6a4db94011d3 | 907 | |
| sahilmgandhi | 18:6a4db94011d3 | 908 | #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 909 | #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 910 | #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 911 | #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included |
| sahilmgandhi | 18:6a4db94011d3 | 912 | |
| sahilmgandhi | 18:6a4db94011d3 | 913 | #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 914 | #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 915 | #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 916 | #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included |
| sahilmgandhi | 18:6a4db94011d3 | 917 | |
| sahilmgandhi | 18:6a4db94011d3 | 918 | #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 919 | #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 920 | #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 921 | #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included |
| sahilmgandhi | 18:6a4db94011d3 | 922 | |
| sahilmgandhi | 18:6a4db94011d3 | 923 | #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 924 | #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 925 | #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 926 | #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included |
| sahilmgandhi | 18:6a4db94011d3 | 927 | |
| sahilmgandhi | 18:6a4db94011d3 | 928 | #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 929 | #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 930 | #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 931 | #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included |
| sahilmgandhi | 18:6a4db94011d3 | 932 | |
| sahilmgandhi | 18:6a4db94011d3 | 933 | #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos |
| sahilmgandhi | 18:6a4db94011d3 | 934 | #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 935 | #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded |
| sahilmgandhi | 18:6a4db94011d3 | 936 | #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included |
| sahilmgandhi | 18:6a4db94011d3 | 937 | |
| sahilmgandhi | 18:6a4db94011d3 | 938 | |
| sahilmgandhi | 18:6a4db94011d3 | 939 | |
| sahilmgandhi | 18:6a4db94011d3 | 940 | |
| sahilmgandhi | 18:6a4db94011d3 | 941 | /*lint --flb "Leave library region" */ |
| sahilmgandhi | 18:6a4db94011d3 | 942 | |
| sahilmgandhi | 18:6a4db94011d3 | 943 | #endif /* NRF51_TO_NRF52_H */ |
| sahilmgandhi | 18:6a4db94011d3 | 944 |